drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
   4  * Copyright (C) STMicroelectronics SA 2017
   5  *
   6  * Modified by Philippe Cornu <philippe.cornu@st.com>
   7  * This generic Synopsys DesignWare MIPI DSI host driver is based on the
   8  * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/component.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/module.h>
  15 #include <linux/of_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/reset.h>
  18 #include <drm/drmP.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_bridge.h>
  21 #include <drm/drm_crtc.h>
  22 #include <drm/drm_crtc_helper.h>
  23 #include <drm/drm_mipi_dsi.h>
  24 #include <drm/drm_of.h>
  25 #include <drm/bridge/dw_mipi_dsi.h>
  26 #include <video/mipi_display.h>
  27
  28 #define HWVER_131                       0x31333100      /* IP version 1.31 */
  29
  30 #define DSI_VERSION                     0x00
  31 #define VERSION                         GENMASK(31, 8)
  32
  33 #define DSI_PWR_UP                      0x04
  34 #define RESET                           0
  35 #define POWERUP                         BIT(0)
  36
  37 #define DSI_CLKMGR_CFG                  0x08
  38 #define TO_CLK_DIVISION(div)            (((div) & 0xff) << 8)
  39 #define TX_ESC_CLK_DIVISION(div)        ((div) & 0xff)
  40
  41 #define DSI_DPI_VCID                    0x0c
  42 #define DPI_VCID(vcid)                  ((vcid) & 0x3)
  43
  44 #define DSI_DPI_COLOR_CODING            0x10
  45 #define LOOSELY18_EN                    BIT(8)
  46 #define DPI_COLOR_CODING_16BIT_1        0x0
  47 #define DPI_COLOR_CODING_16BIT_2        0x1
  48 #define DPI_COLOR_CODING_16BIT_3        0x2
  49 #define DPI_COLOR_CODING_18BIT_1        0x3
  50 #define DPI_COLOR_CODING_18BIT_2        0x4
  51 #define DPI_COLOR_CODING_24BIT          0x5
  52
  53 #define DSI_DPI_CFG_POL                 0x14
  54 #define COLORM_ACTIVE_LOW               BIT(4)
  55 #define SHUTD_ACTIVE_LOW                BIT(3)
  56 #define HSYNC_ACTIVE_LOW                BIT(2)
  57 #define VSYNC_ACTIVE_LOW                BIT(1)
  58 #define DATAEN_ACTIVE_LOW               BIT(0)
  59
  60 #define DSI_DPI_LP_CMD_TIM              0x18
  61 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  62 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  63
  64 #define DSI_DBI_VCID                    0x1c
  65 #define DSI_DBI_CFG                     0x20
  66 #define DSI_DBI_PARTITIONING_EN         0x24
  67 #define DSI_DBI_CMDSIZE                 0x28
  68
  69 #define DSI_PCKHDL_CFG                  0x2c
  70 #define CRC_RX_EN                       BIT(4)
  71 #define ECC_RX_EN                       BIT(3)
  72 #define BTA_EN                          BIT(2)
  73 #define EOTP_RX_EN                      BIT(1)
  74 #define EOTP_TX_EN                      BIT(0)
  75
  76 #define DSI_GEN_VCID                    0x30
  77
  78 #define DSI_MODE_CFG                    0x34
  79 #define ENABLE_VIDEO_MODE               0
  80 #define ENABLE_CMD_MODE                 BIT(0)
  81
  82 #define DSI_VID_MODE_CFG                0x38
  83 #define ENABLE_LOW_POWER                (0x3f << 8)
  84 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
  85 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES     0x0
  86 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS     0x1
  87 #define VID_MODE_TYPE_BURST                     0x2
  88 #define VID_MODE_TYPE_MASK                      0x3
  89
  90 #define DSI_VID_PKT_SIZE                0x3c
  91 #define VID_PKT_SIZE(p)                 ((p) & 0x3fff)
  92
  93 #define DSI_VID_NUM_CHUNKS              0x40
  94 #define VID_NUM_CHUNKS(c)               ((c) & 0x1fff)
  95
  96 #define DSI_VID_NULL_SIZE               0x44
  97 #define VID_NULL_SIZE(b)                ((b) & 0x1fff)
  98
  99 #define DSI_VID_HSA_TIME                0x48
 100 #define DSI_VID_HBP_TIME                0x4c
 101 #define DSI_VID_HLINE_TIME              0x50
 102 #define DSI_VID_VSA_LINES               0x54
 103 #define DSI_VID_VBP_LINES               0x58
 104 #define DSI_VID_VFP_LINES               0x5c
 105 #define DSI_VID_VACTIVE_LINES           0x60
 106 #define DSI_EDPI_CMD_SIZE               0x64
 107
 108 #define DSI_CMD_MODE_CFG                0x68
 109 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 110 #define DCS_LW_TX_LP                    BIT(19)
 111 #define DCS_SR_0P_TX_LP                 BIT(18)
 112 #define DCS_SW_1P_TX_LP                 BIT(17)
 113 #define DCS_SW_0P_TX_LP                 BIT(16)
 114 #define GEN_LW_TX_LP                    BIT(14)
 115 #define GEN_SR_2P_TX_LP                 BIT(13)
 116 #define GEN_SR_1P_TX_LP                 BIT(12)
 117 #define GEN_SR_0P_TX_LP                 BIT(11)
 118 #define GEN_SW_2P_TX_LP                 BIT(10)
 119 #define GEN_SW_1P_TX_LP                 BIT(9)
 120 #define GEN_SW_0P_TX_LP                 BIT(8)
 121 #define ACK_RQST_EN                     BIT(1)
 122 #define TEAR_FX_EN                      BIT(0)
 123
 124 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 125                                          DCS_LW_TX_LP | \
 126                                          DCS_SR_0P_TX_LP | \
 127                                          DCS_SW_1P_TX_LP | \
 128                                          DCS_SW_0P_TX_LP | \
 129                                          GEN_LW_TX_LP | \
 130                                          GEN_SR_2P_TX_LP | \
 131                                          GEN_SR_1P_TX_LP | \
 132                                          GEN_SR_0P_TX_LP | \
 133                                          GEN_SW_2P_TX_LP | \
 134                                          GEN_SW_1P_TX_LP | \
 135                                          GEN_SW_0P_TX_LP)
 136
 137 #define DSI_GEN_HDR                     0x6c
 138 #define DSI_GEN_PLD_DATA                0x70
 139
 140 #define DSI_CMD_PKT_STATUS              0x74
 141 #define GEN_RD_CMD_BUSY                 BIT(6)
 142 #define GEN_PLD_R_FULL                  BIT(5)
 143 #define GEN_PLD_R_EMPTY                 BIT(4)
 144 #define GEN_PLD_W_FULL                  BIT(3)
 145 #define GEN_PLD_W_EMPTY                 BIT(2)
 146 #define GEN_CMD_FULL                    BIT(1)
 147 #define GEN_CMD_EMPTY                   BIT(0)
 148
 149 #define DSI_TO_CNT_CFG                  0x78
 150 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 151 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 152
 153 #define DSI_HS_RD_TO_CNT                0x7c
 154 #define DSI_LP_RD_TO_CNT                0x80
 155 #define DSI_HS_WR_TO_CNT                0x84
 156 #define DSI_LP_WR_TO_CNT                0x88
 157 #define DSI_BTA_TO_CNT                  0x8c
 158
 159 #define DSI_LPCLK_CTRL                  0x94
 160 #define AUTO_CLKLANE_CTRL               BIT(1)
 161 #define PHY_TXREQUESTCLKHS              BIT(0)
 162
 163 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 164 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 165 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 166
 167 #define DSI_PHY_TMR_CFG                 0x9c
 168 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 169 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 170 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 171 #define PHY_HS2LP_TIME_V131(lbcc)       (((lbcc) & 0x3ff) << 16)
 172 #define PHY_LP2HS_TIME_V131(lbcc)       ((lbcc) & 0x3ff)
 173
 174 #define DSI_PHY_RSTZ                    0xa0
 175 #define PHY_DISFORCEPLL                 0
 176 #define PHY_ENFORCEPLL                  BIT(3)
 177 #define PHY_DISABLECLK                  0
 178 #define PHY_ENABLECLK                   BIT(2)
 179 #define PHY_RSTZ                        0
 180 #define PHY_UNRSTZ                      BIT(1)
 181 #define PHY_SHUTDOWNZ                   0
 182 #define PHY_UNSHUTDOWNZ                 BIT(0)
 183
 184 #define DSI_PHY_IF_CFG                  0xa4
 185 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 186 #define N_LANES(n)                      (((n) - 1) & 0x3)
 187
 188 #define DSI_PHY_ULPS_CTRL               0xa8
 189 #define DSI_PHY_TX_TRIGGERS             0xac
 190
 191 #define DSI_PHY_STATUS                  0xb0
 192 #define PHY_STOP_STATE_CLK_LANE         BIT(2)
 193 #define PHY_LOCK                        BIT(0)
 194
 195 #define DSI_PHY_TST_CTRL0               0xb4
 196 #define PHY_TESTCLK                     BIT(1)
 197 #define PHY_UNTESTCLK                   0
 198 #define PHY_TESTCLR                     BIT(0)
 199 #define PHY_UNTESTCLR                   0
 200
 201 #define DSI_PHY_TST_CTRL1               0xb8
 202 #define PHY_TESTEN                      BIT(16)
 203 #define PHY_UNTESTEN                    0
 204 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 205 #define PHY_TESTDIN(n)                  ((n) & 0xff)
 206
 207 #define DSI_INT_ST0                     0xbc
 208 #define DSI_INT_ST1                     0xc0
 209 #define DSI_INT_MSK0                    0xc4
 210 #define DSI_INT_MSK1                    0xc8
 211
 212 #define DSI_PHY_TMR_RD_CFG              0xf4
 213 #define MAX_RD_TIME_V131(lbcc)          ((lbcc) & 0x7fff)
 214
 215 #define PHY_STATUS_TIMEOUT_US           10000
 216 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 217
 218 struct dw_mipi_dsi {
 219         struct drm_bridge bridge;
 220         struct mipi_dsi_host dsi_host;
 221         struct drm_bridge *panel_bridge;
 222         struct device *dev;
 223         void __iomem *base;
 224
 225         struct clk *pclk;
 226
 227         unsigned int lane_mbps; /* per lane */
 228         u32 channel;
 229         u32 lanes;
 230         u32 format;
 231         unsigned long mode_flags;
 232
 233         const struct dw_mipi_dsi_plat_data *plat_data;
 234 };
 235
 236 /*
 237  * The controller should generate 2 frames before
 238  * preparing the peripheral.
 239  */
 240 static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode)
 241 {
 242         int refresh, two_frames;
 243
 244         refresh = drm_mode_vrefresh(mode);
 245         two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
 246         msleep(two_frames);
 247 }
 248
 249 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 250 {
 251         return container_of(host, struct dw_mipi_dsi, dsi_host);
 252 }
 253
 254 static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
 255 {
 256         return container_of(bridge, struct dw_mipi_dsi, bridge);
 257 }
 258
 259 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 260 {
 261         writel(val, dsi->base + reg);
 262 }
 263
 264 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 265 {
 266         return readl(dsi->base + reg);
 267 }
 268
 269 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 270                                    struct mipi_dsi_device *device)
 271 {
 272         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 273         struct drm_bridge *bridge;
 274         struct drm_panel *panel;
 275         int ret;
 276
 277         if (device->lanes > dsi->plat_data->max_data_lanes) {
 278                 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
 279                         device->lanes);
 280                 return -EINVAL;
 281         }
 282
 283         dsi->lanes = device->lanes;
 284         dsi->channel = device->channel;
 285         dsi->format = device->format;
 286         dsi->mode_flags = device->mode_flags;
 287
 288         ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
 289                                           &panel, &bridge);
 290         if (ret)
 291                 return ret;
 292
 293         if (panel) {
 294                 bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI);
 295                 if (IS_ERR(bridge))
 296                         return PTR_ERR(bridge);
 297         }
 298
 299         dsi->panel_bridge = bridge;
 300
 301         drm_bridge_add(&dsi->bridge);
 302
 303         return 0;
 304 }
 305
 306 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
 307                                    struct mipi_dsi_device *device)
 308 {
 309         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 310
 311         drm_of_panel_bridge_remove(host->dev->of_node, 1, 0);
 312
 313         drm_bridge_remove(&dsi->bridge);
 314
 315         return 0;
 316 }
 317
 318 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
 319                                    const struct mipi_dsi_msg *msg)
 320 {
 321         bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
 322         u32 val = 0;
 323
 324         if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
 325                 val |= ACK_RQST_EN;
 326         if (lpm)
 327                 val |= CMD_MODE_ALL_LP;
 328
 329         dsi_write(dsi, DSI_CMD_MODE_CFG, val);
 330 }
 331
 332 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 333 {
 334         int ret;
 335         u32 val, mask;
 336
 337         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 338                                  val, !(val & GEN_CMD_FULL), 1000,
 339                                  CMD_PKT_STATUS_TIMEOUT_US);
 340         if (ret) {
 341                 dev_err(dsi->dev, "failed to get available command FIFO\n");
 342                 return ret;
 343         }
 344
 345         dsi_write(dsi, DSI_GEN_HDR, hdr_val);
 346
 347         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
 348         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 349                                  val, (val & mask) == mask,
 350                                  1000, CMD_PKT_STATUS_TIMEOUT_US);
 351         if (ret) {
 352                 dev_err(dsi->dev, "failed to write command FIFO\n");
 353                 return ret;
 354         }
 355
 356         return 0;
 357 }
 358
 359 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
 360                              const struct mipi_dsi_packet *packet)
 361 {
 362         const u8 *tx_buf = packet->payload;
 363         int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
 364         __le32 word;
 365         u32 val;
 366
 367         while (len) {
 368                 if (len < pld_data_bytes) {
 369                         word = 0;
 370                         memcpy(&word, tx_buf, len);
 371                         dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
 372                         len = 0;
 373                 } else {
 374                         memcpy(&word, tx_buf, pld_data_bytes);
 375                         dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
 376                         tx_buf += pld_data_bytes;
 377                         len -= pld_data_bytes;
 378                 }
 379
 380                 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 381                                          val, !(val & GEN_PLD_W_FULL), 1000,
 382                                          CMD_PKT_STATUS_TIMEOUT_US);
 383                 if (ret) {
 384                         dev_err(dsi->dev,
 385                                 "failed to get available write payload FIFO\n");
 386                         return ret;
 387                 }
 388         }
 389
 390         word = 0;
 391         memcpy(&word, packet->header, sizeof(packet->header));
 392         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
 393 }
 394
 395 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
 396                             const struct mipi_dsi_msg *msg)
 397 {
 398         int i, j, ret, len = msg->rx_len;
 399         u8 *buf = msg->rx_buf;
 400         u32 val;
 401
 402         /* Wait end of the read operation */
 403         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 404                                  val, !(val & GEN_RD_CMD_BUSY),
 405                                  1000, CMD_PKT_STATUS_TIMEOUT_US);
 406         if (ret) {
 407                 dev_err(dsi->dev, "Timeout during read operation\n");
 408                 return ret;
 409         }
 410
 411         for (i = 0; i < len; i += 4) {
 412                 /* Read fifo must not be empty before all bytes are read */
 413                 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 414                                          val, !(val & GEN_PLD_R_EMPTY),
 415                                          1000, CMD_PKT_STATUS_TIMEOUT_US);
 416                 if (ret) {
 417                         dev_err(dsi->dev, "Read payload FIFO is empty\n");
 418                         return ret;
 419                 }
 420
 421                 val = dsi_read(dsi, DSI_GEN_PLD_DATA);
 422                 for (j = 0; j < 4 && j + i < len; j++)
 423                         buf[i + j] = val >> (8 * j);
 424         }
 425
 426         return ret;
 427 }
 428
 429 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 430                                          const struct mipi_dsi_msg *msg)
 431 {
 432         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 433         struct mipi_dsi_packet packet;
 434         int ret, nb_bytes;
 435
 436         ret = mipi_dsi_create_packet(&packet, msg);
 437         if (ret) {
 438                 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
 439                 return ret;
 440         }
 441
 442         dw_mipi_message_config(dsi, msg);
 443
 444         ret = dw_mipi_dsi_write(dsi, &packet);
 445         if (ret)
 446                 return ret;
 447
 448         if (msg->rx_buf && msg->rx_len) {
 449                 ret = dw_mipi_dsi_read(dsi, msg);
 450                 if (ret)
 451                         return ret;
 452                 nb_bytes = msg->rx_len;
 453         } else {
 454                 nb_bytes = packet.size;
 455         }
 456
 457         return nb_bytes;
 458 }
 459
 460 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 461         .attach = dw_mipi_dsi_host_attach,
 462         .detach = dw_mipi_dsi_host_detach,
 463         .transfer = dw_mipi_dsi_host_transfer,
 464 };
 465
 466 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 467 {
 468         u32 val;
 469
 470         /*
 471          * TODO dw drv improvements
 472          * enabling low power is panel-dependent, we should use the
 473          * panel configuration here...
 474          */
 475         val = ENABLE_LOW_POWER;
 476
 477         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 478                 val |= VID_MODE_TYPE_BURST;
 479         else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 480                 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
 481         else
 482                 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
 483
 484         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 485 }
 486
 487 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 488                                  unsigned long mode_flags)
 489 {
 490         u32 val;
 491
 492         dsi_write(dsi, DSI_PWR_UP, RESET);
 493
 494         if (mode_flags & MIPI_DSI_MODE_VIDEO) {
 495                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 496                 dw_mipi_dsi_video_mode_config(dsi);
 497         } else {
 498                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 499         }
 500
 501         val = PHY_TXREQUESTCLKHS;
 502         if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
 503                 val |= AUTO_CLKLANE_CTRL;
 504         dsi_write(dsi, DSI_LPCLK_CTRL, val);
 505
 506         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 507 }
 508
 509 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
 510 {
 511         dsi_write(dsi, DSI_PWR_UP, RESET);
 512         dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
 513 }
 514
 515 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
 516 {
 517         /*
 518          * The maximum permitted escape clock is 20MHz and it is derived from
 519          * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
 520          *
 521          *     (lane_mbps >> 3) / esc_clk_division < 20
 522          * which is:
 523          *     (lane_mbps >> 3) / 20 > esc_clk_division
 524          */
 525         u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
 526
 527         dsi_write(dsi, DSI_PWR_UP, RESET);
 528
 529         /*
 530          * TODO dw drv improvements
 531          * timeout clock division should be computed with the
 532          * high speed transmission counter timeout and byte lane...
 533          */
 534         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
 535                   TX_ESC_CLK_DIVISION(esc_clk_division));
 536 }
 537
 538 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 539                                    struct drm_display_mode *mode)
 540 {
 541         u32 val = 0, color = 0;
 542
 543         switch (dsi->format) {
 544         case MIPI_DSI_FMT_RGB888:
 545                 color = DPI_COLOR_CODING_24BIT;
 546                 break;
 547         case MIPI_DSI_FMT_RGB666:
 548                 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
 549                 break;
 550         case MIPI_DSI_FMT_RGB666_PACKED:
 551                 color = DPI_COLOR_CODING_18BIT_1;
 552                 break;
 553         case MIPI_DSI_FMT_RGB565:
 554                 color = DPI_COLOR_CODING_16BIT_1;
 555                 break;
 556         }
 557
 558         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 559                 val |= VSYNC_ACTIVE_LOW;
 560         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 561                 val |= HSYNC_ACTIVE_LOW;
 562
 563         dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
 564         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 565         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 566         /*
 567          * TODO dw drv improvements
 568          * largest packet sizes during hfp or during vsa/vpb/vfp
 569          * should be computed according to byte lane, lane number and only
 570          * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
 571          */
 572         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 573                   | INVACT_LPCMD_TIME(4));
 574 }
 575
 576 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 577 {
 578         dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
 579 }
 580
 581 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 582                                             struct drm_display_mode *mode)
 583 {
 584         /*
 585          * TODO dw drv improvements
 586          * only burst mode is supported here. For non-burst video modes,
 587          * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
 588          * DSI_VNPCR.NPSIZE... especially because this driver supports
 589          * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
 590          */
 591         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
 592 }
 593
 594 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 595 {
 596         /*
 597          * TODO dw drv improvements
 598          * compute high speed transmission counter timeout according
 599          * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
 600          */
 601         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 602         /*
 603          * TODO dw drv improvements
 604          * the Bus-Turn-Around Timeout Counter should be computed
 605          * according to byte lane...
 606          */
 607         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 608         dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 609 }
 610
 611 /* Get lane byte clock cycles. */
 612 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 613                                            struct drm_display_mode *mode,
 614                                            u32 hcomponent)
 615 {
 616         u32 frac, lbcc;
 617
 618         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 619
 620         frac = lbcc % mode->clock;
 621         lbcc = lbcc / mode->clock;
 622         if (frac)
 623                 lbcc++;
 624
 625         return lbcc;
 626 }
 627
 628 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
 629                                           struct drm_display_mode *mode)
 630 {
 631         u32 htotal, hsa, hbp, lbcc;
 632
 633         htotal = mode->htotal;
 634         hsa = mode->hsync_end - mode->hsync_start;
 635         hbp = mode->htotal - mode->hsync_end;
 636
 637         /*
 638          * TODO dw drv improvements
 639          * computations below may be improved...
 640          */
 641         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
 642         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 643
 644         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
 645         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 646
 647         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
 648         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 649 }
 650
 651 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
 652                                                struct drm_display_mode *mode)
 653 {
 654         u32 vactive, vsa, vfp, vbp;
 655
 656         vactive = mode->vdisplay;
 657         vsa = mode->vsync_end - mode->vsync_start;
 658         vfp = mode->vsync_start - mode->vdisplay;
 659         vbp = mode->vtotal - mode->vsync_end;
 660
 661         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 662         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 663         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 664         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 665 }
 666
 667 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 668 {
 669         u32 hw_version;
 670
 671         /*
 672          * TODO dw drv improvements
 673          * data & clock lane timers should be computed according to panel
 674          * blankings and to the automatic clock lane control mode...
 675          * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
 676          * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
 677          */
 678
 679         hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
 680
 681         if (hw_version >= HWVER_131) {
 682                 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) |
 683                           PHY_LP2HS_TIME_V131(0x40));
 684                 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
 685         } else {
 686                 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) |
 687                           PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
 688         }
 689
 690         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 691                   | PHY_CLKLP2HS_TIME(0x40));
 692 }
 693
 694 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 695 {
 696         /*
 697          * TODO dw drv improvements
 698          * stop wait time should be the maximum between host dsi
 699          * and panel stop wait times
 700          */
 701         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 702                   N_LANES(dsi->lanes));
 703 }
 704
 705 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
 706 {
 707         /* Clear PHY state */
 708         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 709                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 710         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 711         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
 712         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 713 }
 714
 715 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
 716 {
 717         u32 val;
 718         int ret;
 719
 720         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 721                   PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 722
 723         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
 724                                  val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
 725         if (ret)
 726                 DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
 727
 728         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 729                                  val, val & PHY_STOP_STATE_CLK_LANE, 1000,
 730                                  PHY_STATUS_TIMEOUT_US);
 731         if (ret)
 732                 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
 733 }
 734
 735 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 736 {
 737         dsi_read(dsi, DSI_INT_ST0);
 738         dsi_read(dsi, DSI_INT_ST1);
 739         dsi_write(dsi, DSI_INT_MSK0, 0);
 740         dsi_write(dsi, DSI_INT_MSK1, 0);
 741 }
 742
 743 static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
 744 {
 745         struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
 746
 747         /*
 748          * Switch to command mode before panel-bridge post_disable &
 749          * panel unprepare.
 750          * Note: panel-bridge disable & panel disable has been called
 751          * before by the drm framework.
 752          */
 753         dw_mipi_dsi_set_mode(dsi, 0);
 754
 755         /*
 756          * TODO Only way found to call panel-bridge post_disable &
 757          * panel unprepare before the dsi "final" disable...
 758          * This needs to be fixed in the drm_bridge framework and the API
 759          * needs to be updated to manage our own call chains...
 760          */
 761         dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
 762
 763         dw_mipi_dsi_disable(dsi);
 764         clk_disable_unprepare(dsi->pclk);
 765         pm_runtime_put(dsi->dev);
 766 }
 767
 768 static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
 769                                         struct drm_display_mode *mode,
 770                                         struct drm_display_mode *adjusted_mode)
 771 {
 772         struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
 773         const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
 774         void *priv_data = dsi->plat_data->priv_data;
 775         int ret;
 776
 777         clk_prepare_enable(dsi->pclk);
 778
 779         ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags,
 780                                      dsi->lanes, dsi->format, &dsi->lane_mbps);
 781         if (ret)
 782                 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
 783
 784         pm_runtime_get_sync(dsi->dev);
 785         dw_mipi_dsi_init(dsi);
 786         dw_mipi_dsi_dpi_config(dsi, adjusted_mode);
 787         dw_mipi_dsi_packet_handler_config(dsi);
 788         dw_mipi_dsi_video_mode_config(dsi);
 789         dw_mipi_dsi_video_packet_config(dsi, adjusted_mode);
 790         dw_mipi_dsi_command_mode_config(dsi);
 791         dw_mipi_dsi_line_timer_config(dsi, adjusted_mode);
 792         dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode);
 793
 794         dw_mipi_dsi_dphy_init(dsi);
 795         dw_mipi_dsi_dphy_timing_config(dsi);
 796         dw_mipi_dsi_dphy_interface_config(dsi);
 797
 798         dw_mipi_dsi_clear_err(dsi);
 799
 800         ret = phy_ops->init(priv_data);
 801         if (ret)
 802                 DRM_DEBUG_DRIVER("Phy init() failed\n");
 803
 804         dw_mipi_dsi_dphy_enable(dsi);
 805
 806         dw_mipi_dsi_wait_for_two_frames(adjusted_mode);
 807
 808         /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
 809         dw_mipi_dsi_set_mode(dsi, 0);
 810 }
 811
 812 static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
 813 {
 814         struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
 815
 816         /* Switch to video mode for panel-bridge enable & panel enable */
 817         dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
 818 }
 819
 820 static enum drm_mode_status
 821 dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
 822                               const struct drm_display_mode *mode)
 823 {
 824         struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
 825         const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
 826         enum drm_mode_status mode_status = MODE_OK;
 827
 828         if (pdata->mode_valid)
 829                 mode_status = pdata->mode_valid(pdata->priv_data, mode);
 830
 831         return mode_status;
 832 }
 833
 834 static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge)
 835 {
 836         struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
 837
 838         if (!bridge->encoder) {
 839                 DRM_ERROR("Parent encoder object not found\n");
 840                 return -ENODEV;
 841         }
 842
 843         /* Set the encoder type as caller does not know it */
 844         bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
 845
 846         /* Attach the panel-bridge to the dsi bridge */
 847         return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge);
 848 }
 849
 850 static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
 851         .mode_set     = dw_mipi_dsi_bridge_mode_set,
 852         .enable       = dw_mipi_dsi_bridge_enable,
 853         .post_disable = dw_mipi_dsi_bridge_post_disable,
 854         .mode_valid   = dw_mipi_dsi_bridge_mode_valid,
 855         .attach       = dw_mipi_dsi_bridge_attach,
 856 };
 857
 858 static struct dw_mipi_dsi *
 859 __dw_mipi_dsi_probe(struct platform_device *pdev,
 860                     const struct dw_mipi_dsi_plat_data *plat_data)
 861 {
 862         struct device *dev = &pdev->dev;
 863         struct reset_control *apb_rst;
 864         struct dw_mipi_dsi *dsi;
 865         struct resource *res;
 866         int ret;
 867
 868         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
 869         if (!dsi)
 870                 return ERR_PTR(-ENOMEM);
 871
 872         dsi->dev = dev;
 873         dsi->plat_data = plat_data;
 874
 875         if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) {
 876                 DRM_ERROR("Phy not properly configured\n");
 877                 return ERR_PTR(-ENODEV);
 878         }
 879
 880         if (!plat_data->base) {
 881                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 882                 if (!res)
 883                         return ERR_PTR(-ENODEV);
 884
 885                 dsi->base = devm_ioremap_resource(dev, res);
 886                 if (IS_ERR(dsi->base))
 887                         return ERR_PTR(-ENODEV);
 888
 889         } else {
 890                 dsi->base = plat_data->base;
 891         }
 892
 893         dsi->pclk = devm_clk_get(dev, "pclk");
 894         if (IS_ERR(dsi->pclk)) {
 895                 ret = PTR_ERR(dsi->pclk);
 896                 dev_err(dev, "Unable to get pclk: %d\n", ret);
 897                 return ERR_PTR(ret);
 898         }
 899
 900         /*
 901          * Note that the reset was not defined in the initial device tree, so
 902          * we have to be prepared for it not being found.
 903          */
 904         apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb");
 905         if (IS_ERR(apb_rst)) {
 906                 ret = PTR_ERR(apb_rst);
 907
 908                 if (ret != -EPROBE_DEFER)
 909                         dev_err(dev, "Unable to get reset control: %d\n", ret);
 910
 911                 return ERR_PTR(ret);
 912         }
 913
 914         if (apb_rst) {
 915                 ret = clk_prepare_enable(dsi->pclk);
 916                 if (ret) {
 917                         dev_err(dev, "%s: Failed to enable pclk\n", __func__);
 918                         return ERR_PTR(ret);
 919                 }
 920
 921                 reset_control_assert(apb_rst);
 922                 usleep_range(10, 20);
 923                 reset_control_deassert(apb_rst);
 924
 925                 clk_disable_unprepare(dsi->pclk);
 926         }
 927
 928         pm_runtime_enable(dev);
 929
 930         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
 931         dsi->dsi_host.dev = dev;
 932         ret = mipi_dsi_host_register(&dsi->dsi_host);
 933         if (ret) {
 934                 dev_err(dev, "Failed to register MIPI host: %d\n", ret);
 935                 return ERR_PTR(ret);
 936         }
 937
 938         dsi->bridge.driver_private = dsi;
 939         dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
 940 #ifdef CONFIG_OF
 941         dsi->bridge.of_node = pdev->dev.of_node;
 942 #endif
 943
 944         return dsi;
 945 }
 946
 947 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
 948 {
 949         pm_runtime_disable(dsi->dev);
 950 }
 951
 952 /*
 953  * Probe/remove API, used from platforms based on the DRM bridge API.
 954  */
 955 struct dw_mipi_dsi *
 956 dw_mipi_dsi_probe(struct platform_device *pdev,
 957                   const struct dw_mipi_dsi_plat_data *plat_data)
 958 {
 959         return __dw_mipi_dsi_probe(pdev, plat_data);
 960 }
 961 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
 962
 963 void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
 964 {
 965         mipi_dsi_host_unregister(&dsi->dsi_host);
 966
 967         __dw_mipi_dsi_remove(dsi);
 968 }
 969 EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
 970
 971 /*
 972  * Bind/unbind API, used from platforms based on the component framework.
 973  */
 974 struct dw_mipi_dsi *
 975 dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
 976                  const struct dw_mipi_dsi_plat_data *plat_data)
 977 {
 978         struct dw_mipi_dsi *dsi;
 979         int ret;
 980
 981         dsi = __dw_mipi_dsi_probe(pdev, plat_data);
 982         if (IS_ERR(dsi))
 983                 return dsi;
 984
 985         ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
 986         if (ret) {
 987                 dw_mipi_dsi_remove(dsi);
 988                 DRM_ERROR("Failed to initialize bridge with drm\n");
 989                 return ERR_PTR(ret);
 990         }
 991
 992         return dsi;
 993 }
 994 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
 995
 996 void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
 997 {
 998         __dw_mipi_dsi_remove(dsi);
 999 }
1000 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
1001
1002 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1003 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
1004 MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
1005 MODULE_LICENSE("GPL");
1006 MODULE_ALIAS("platform:dw-mipi-dsi");