2 * Silicon Image SiI8620 HDMI/MHL bridge driver
4 * Copyright (C) 2015, Samsung Electronics Co., Ltd.
5 * Andrzej Hajda <a.hajda@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <asm/unaligned.h>
14 #include <drm/bridge/mhl.h>
15 #include <drm/drm_crtc.h>
16 #include <drm/drm_edid.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/i2c.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/kernel.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/mutex.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/slab.h>
31 #include "sil-sii8620.h"
33 #define SII8620_BURST_BUF_LEN 288
34 #define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3)
35 #define MHL1_MAX_LCLK 225000
36 #define MHL3_MAX_LCLK 600000
46 enum sii8620_sink_type {
52 enum sii8620_mt_state {
59 struct drm_bridge bridge;
62 struct gpio_desc *gpio_reset;
63 struct gpio_desc *gpio_int;
64 struct regulator_bulk_data supplies[2];
65 struct mutex lock; /* context lock, protects fields below */
68 unsigned int use_packed_pixel:1;
70 enum sii8620_mode mode;
71 enum sii8620_sink_type sink_type;
73 u8 stat[MHL_DST_SIZE];
74 u8 xstat[MHL_XDS_SIZE];
75 u8 devcap[MHL_DCAP_SIZE];
76 u8 xdevcap[MHL_XDC_SIZE];
77 u8 avif[HDMI_INFOFRAME_SIZE(AVI)];
79 unsigned int gen2_write_burst:1;
80 enum sii8620_mt_state mt_state;
81 struct list_head mt_queue;
93 struct sii8620_mt_msg;
95 typedef void (*sii8620_mt_msg_cb)(struct sii8620 *ctx,
96 struct sii8620_mt_msg *msg);
98 typedef void (*sii8620_cb)(struct sii8620 *ctx, int ret);
100 struct sii8620_mt_msg {
101 struct list_head node;
104 sii8620_mt_msg_cb send;
105 sii8620_mt_msg_cb recv;
106 sii8620_cb continuation;
109 static const u8 sii8620_i2c_page[] = {
110 0x39, /* Main System */
111 0x3d, /* TDM and HSIC */
112 0x49, /* TMDS Receiver, MHL EDID */
113 0x4d, /* eMSC, HDCP, HSIC */
116 0x59, /* Hardware TPI (Transmitter Programming Interface) */
117 0x61, /* eCBUS-S, eCBUS-D */
120 static void sii8620_fetch_edid(struct sii8620 *ctx);
121 static void sii8620_set_upstream_edid(struct sii8620 *ctx);
122 static void sii8620_enable_hpd(struct sii8620 *ctx);
123 static void sii8620_mhl_disconnected(struct sii8620 *ctx);
124 static void sii8620_disconnect(struct sii8620 *ctx);
126 static int sii8620_clear_error(struct sii8620 *ctx)
128 int ret = ctx->error;
134 static void sii8620_read_buf(struct sii8620 *ctx, u16 addr, u8 *buf, int len)
136 struct device *dev = ctx->dev;
137 struct i2c_client *client = to_i2c_client(dev);
139 struct i2c_msg msg[] = {
141 .addr = sii8620_i2c_page[addr >> 8],
142 .flags = client->flags,
147 .addr = sii8620_i2c_page[addr >> 8],
148 .flags = client->flags | I2C_M_RD,
158 ret = i2c_transfer(client->adapter, msg, 2);
159 dev_dbg(dev, "read at %04x: %*ph, %d\n", addr, len, buf, ret);
162 dev_err(dev, "Read at %#06x of %d bytes failed with code %d.\n",
164 ctx->error = ret < 0 ? ret : -EIO;
168 static u8 sii8620_readb(struct sii8620 *ctx, u16 addr)
172 sii8620_read_buf(ctx, addr, &ret, 1);
176 static void sii8620_write_buf(struct sii8620 *ctx, u16 addr, const u8 *buf,
179 struct device *dev = ctx->dev;
180 struct i2c_client *client = to_i2c_client(dev);
182 struct i2c_msg msg = {
183 .addr = sii8620_i2c_page[addr >> 8],
184 .flags = client->flags,
193 msg.buf = kmalloc(len + 1, GFP_KERNEL);
195 ctx->error = -ENOMEM;
198 memcpy(msg.buf + 1, buf, len);
206 ret = i2c_transfer(client->adapter, &msg, 1);
207 dev_dbg(dev, "write at %04x: %*ph, %d\n", addr, len, buf, ret);
210 dev_err(dev, "Write at %#06x of %*ph failed with code %d.\n",
211 addr, len, buf, ret);
212 ctx->error = ret ?: -EIO;
219 #define sii8620_write(ctx, addr, arr...) \
222 sii8620_write_buf(ctx, addr, d, ARRAY_SIZE(d)); \
225 static void __sii8620_write_seq(struct sii8620 *ctx, const u16 *seq, int len)
229 for (i = 0; i < len; i += 2)
230 sii8620_write(ctx, seq[i], seq[i + 1]);
233 #define sii8620_write_seq(ctx, seq...) \
235 const u16 d[] = { seq }; \
236 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \
239 #define sii8620_write_seq_static(ctx, seq...) \
241 static const u16 d[] = { seq }; \
242 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \
245 static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val)
247 val = (val & mask) | (sii8620_readb(ctx, addr) & ~mask);
248 sii8620_write(ctx, addr, val);
251 static inline bool sii8620_is_mhl3(struct sii8620 *ctx)
253 return ctx->mode >= CM_MHL3;
256 static void sii8620_mt_cleanup(struct sii8620 *ctx)
258 struct sii8620_mt_msg *msg, *n;
260 list_for_each_entry_safe(msg, n, &ctx->mt_queue, node) {
261 list_del(&msg->node);
264 ctx->mt_state = MT_STATE_READY;
267 static void sii8620_mt_work(struct sii8620 *ctx)
269 struct sii8620_mt_msg *msg;
273 if (ctx->mt_state == MT_STATE_BUSY || list_empty(&ctx->mt_queue))
276 if (ctx->mt_state == MT_STATE_DONE) {
277 ctx->mt_state = MT_STATE_READY;
278 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg,
280 list_del(&msg->node);
283 if (msg->continuation)
284 msg->continuation(ctx, msg->ret);
288 if (ctx->mt_state != MT_STATE_READY || list_empty(&ctx->mt_queue))
291 ctx->mt_state = MT_STATE_BUSY;
292 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
297 static void sii8620_enable_gen2_write_burst(struct sii8620 *ctx)
299 u8 ctrl = BIT_MDT_RCV_CTRL_MDT_RCV_EN;
301 if (ctx->gen2_write_burst)
304 if (ctx->mode >= CM_MHL1)
305 ctrl |= BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN;
307 sii8620_write_seq(ctx,
308 REG_MDT_RCV_TIMEOUT, 100,
309 REG_MDT_RCV_CTRL, ctrl
311 ctx->gen2_write_burst = 1;
314 static void sii8620_disable_gen2_write_burst(struct sii8620 *ctx)
316 if (!ctx->gen2_write_burst)
319 sii8620_write_seq_static(ctx,
320 REG_MDT_XMIT_CTRL, 0,
323 ctx->gen2_write_burst = 0;
326 static void sii8620_start_gen2_write_burst(struct sii8620 *ctx)
328 sii8620_write_seq_static(ctx,
329 REG_MDT_INT_1_MASK, BIT_MDT_RCV_TIMEOUT
330 | BIT_MDT_RCV_SM_ABORT_PKT_RCVD | BIT_MDT_RCV_SM_ERROR
331 | BIT_MDT_XMIT_TIMEOUT | BIT_MDT_XMIT_SM_ABORT_PKT_RCVD
332 | BIT_MDT_XMIT_SM_ERROR,
333 REG_MDT_INT_0_MASK, BIT_MDT_XFIFO_EMPTY
334 | BIT_MDT_IDLE_AFTER_HAWB_DISABLE
335 | BIT_MDT_RFIFO_DATA_RDY
337 sii8620_enable_gen2_write_burst(ctx);
340 static void sii8620_mt_msc_cmd_send(struct sii8620 *ctx,
341 struct sii8620_mt_msg *msg)
343 if (msg->reg[0] == MHL_SET_INT &&
344 msg->reg[1] == MHL_INT_REG(RCHANGE) &&
345 msg->reg[2] == MHL_INT_RC_FEAT_REQ)
346 sii8620_enable_gen2_write_burst(ctx);
348 sii8620_disable_gen2_write_burst(ctx);
350 switch (msg->reg[0]) {
353 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg + 1, 2);
354 sii8620_write(ctx, REG_MSC_COMMAND_START,
355 BIT_MSC_COMMAND_START_WRITE_STAT);
358 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg, 3);
359 sii8620_write(ctx, REG_MSC_COMMAND_START,
360 BIT_MSC_COMMAND_START_MSC_MSG);
362 case MHL_READ_DEVCAP_REG:
363 case MHL_READ_XDEVCAP_REG:
364 sii8620_write(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg[1]);
365 sii8620_write(ctx, REG_MSC_COMMAND_START,
366 BIT_MSC_COMMAND_START_READ_DEVCAP);
369 dev_err(ctx->dev, "%s: command %#x not supported\n", __func__,
374 static struct sii8620_mt_msg *sii8620_mt_msg_new(struct sii8620 *ctx)
376 struct sii8620_mt_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL);
379 ctx->error = -ENOMEM;
381 list_add_tail(&msg->node, &ctx->mt_queue);
386 static void sii8620_mt_set_cont(struct sii8620 *ctx, sii8620_cb cont)
388 struct sii8620_mt_msg *msg;
393 if (list_empty(&ctx->mt_queue)) {
394 ctx->error = -EINVAL;
397 msg = list_last_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
398 msg->continuation = cont;
401 static void sii8620_mt_msc_cmd(struct sii8620 *ctx, u8 cmd, u8 arg1, u8 arg2)
403 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
411 msg->send = sii8620_mt_msc_cmd_send;
414 static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val)
416 sii8620_mt_msc_cmd(ctx, MHL_WRITE_STAT, reg, val);
419 static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask)
421 sii8620_mt_msc_cmd(ctx, MHL_SET_INT, irq, mask);
424 static void sii8620_mt_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data)
426 sii8620_mt_msc_cmd(ctx, MHL_MSC_MSG, cmd, data);
429 static void sii8620_mt_rap(struct sii8620 *ctx, u8 code)
431 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code);
434 static void sii8620_mt_read_devcap_send(struct sii8620 *ctx,
435 struct sii8620_mt_msg *msg)
437 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP
438 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
439 | BIT_EDID_CTRL_EDID_MODE_EN;
441 if (msg->reg[0] == MHL_READ_XDEVCAP)
442 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN;
444 sii8620_write_seq(ctx,
445 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE,
447 REG_TPI_CBUS_START, BIT_TPI_CBUS_START_GET_DEVCAP_START
451 /* copy src to dst and set changed bits in src */
452 static void sii8620_update_array(u8 *dst, u8 *src, int count)
454 while (--count >= 0) {
460 static void sii8620_sink_detected(struct sii8620 *ctx, int ret)
462 static const char * const sink_str[] = {
463 [SINK_NONE] = "NONE",
464 [SINK_HDMI] = "HDMI",
469 struct device *dev = ctx->dev;
474 sii8620_fetch_edid(ctx);
476 dev_err(ctx->dev, "Cannot fetch EDID\n");
477 sii8620_mhl_disconnected(ctx);
481 if (drm_detect_hdmi_monitor(ctx->edid))
482 ctx->sink_type = SINK_HDMI;
484 ctx->sink_type = SINK_DVI;
486 drm_edid_get_monitor_name(ctx->edid, sink_name, ARRAY_SIZE(sink_name));
488 dev_info(dev, "detected sink(type: %s): %s\n",
489 sink_str[ctx->sink_type], sink_name);
492 static void sii8620_hsic_init(struct sii8620 *ctx)
494 if (!sii8620_is_mhl3(ctx))
497 sii8620_write(ctx, REG_FCGC,
498 BIT_FCGC_HSIC_HOSTMODE | BIT_FCGC_HSIC_ENABLE);
499 sii8620_setbits(ctx, REG_HRXCTRL3,
500 BIT_HRXCTRL3_HRX_STAY_RESET | BIT_HRXCTRL3_STATUS_EN, ~0);
501 sii8620_setbits(ctx, REG_TTXNUMB, MSK_TTXNUMB_TTX_NUMBPS, 4);
502 sii8620_setbits(ctx, REG_TRXCTRL, BIT_TRXCTRL_TRX_FROM_SE_COC, ~0);
503 sii8620_setbits(ctx, REG_HTXCTRL, BIT_HTXCTRL_HTX_DRVCONN1, 0);
504 sii8620_setbits(ctx, REG_KEEPER, MSK_KEEPER_MODE, VAL_KEEPER_MODE_HOST);
505 sii8620_write_seq_static(ctx,
507 REG_UTSRST, BIT_UTSRST_HRX_SRST | BIT_UTSRST_HTX_SRST |
508 BIT_UTSRST_KEEPER_SRST | BIT_UTSRST_FC_SRST,
509 REG_UTSRST, BIT_UTSRST_HRX_SRST | BIT_UTSRST_HTX_SRST,
529 static void sii8620_edid_read(struct sii8620 *ctx, int ret)
534 sii8620_set_upstream_edid(ctx);
535 sii8620_hsic_init(ctx);
536 sii8620_enable_hpd(ctx);
539 static void sii8620_mr_devcap(struct sii8620 *ctx)
541 u8 dcap[MHL_DCAP_SIZE];
542 struct device *dev = ctx->dev;
544 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, dcap, MHL_DCAP_SIZE);
548 dev_info(dev, "detected dongle MHL %d.%d, ChipID %02x%02x:%02x%02x\n",
549 dcap[MHL_DCAP_MHL_VERSION] / 16,
550 dcap[MHL_DCAP_MHL_VERSION] % 16,
551 dcap[MHL_DCAP_ADOPTER_ID_H], dcap[MHL_DCAP_ADOPTER_ID_L],
552 dcap[MHL_DCAP_DEVICE_ID_H], dcap[MHL_DCAP_DEVICE_ID_L]);
553 sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE);
556 static void sii8620_mr_xdevcap(struct sii8620 *ctx)
558 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, ctx->xdevcap,
562 static void sii8620_mt_read_devcap_recv(struct sii8620 *ctx,
563 struct sii8620_mt_msg *msg)
565 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP
566 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
567 | BIT_EDID_CTRL_EDID_MODE_EN;
569 if (msg->reg[0] == MHL_READ_XDEVCAP)
570 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN;
572 sii8620_write_seq(ctx,
573 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE | BIT_INTR9_EDID_DONE
574 | BIT_INTR9_EDID_ERROR,
576 REG_EDID_FIFO_ADDR, 0
579 if (msg->reg[0] == MHL_READ_XDEVCAP)
580 sii8620_mr_xdevcap(ctx);
582 sii8620_mr_devcap(ctx);
585 static void sii8620_mt_read_devcap(struct sii8620 *ctx, bool xdevcap)
587 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
592 msg->reg[0] = xdevcap ? MHL_READ_XDEVCAP : MHL_READ_DEVCAP;
593 msg->send = sii8620_mt_read_devcap_send;
594 msg->recv = sii8620_mt_read_devcap_recv;
597 static void sii8620_mt_read_devcap_reg_recv(struct sii8620 *ctx,
598 struct sii8620_mt_msg *msg)
600 u8 reg = msg->reg[1] & 0x7f;
602 if (msg->reg[1] & 0x80)
603 ctx->xdevcap[reg] = msg->ret;
605 ctx->devcap[reg] = msg->ret;
608 static void sii8620_mt_read_devcap_reg(struct sii8620 *ctx, u8 reg)
610 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
615 msg->reg[0] = (reg & 0x80) ? MHL_READ_XDEVCAP_REG : MHL_READ_DEVCAP_REG;
617 msg->send = sii8620_mt_msc_cmd_send;
618 msg->recv = sii8620_mt_read_devcap_reg_recv;
621 static inline void sii8620_mt_read_xdevcap_reg(struct sii8620 *ctx, u8 reg)
623 sii8620_mt_read_devcap_reg(ctx, reg | 0x80);
626 static void *sii8620_burst_get_tx_buf(struct sii8620 *ctx, int len)
628 u8 *buf = &ctx->burst.tx_buf[ctx->burst.tx_count];
631 if (ctx->burst.tx_count + size >= ARRAY_SIZE(ctx->burst.tx_buf)) {
632 dev_err(ctx->dev, "TX-BLK buffer exhausted\n");
633 ctx->error = -EINVAL;
637 ctx->burst.tx_count += size;
643 static u8 *sii8620_burst_get_rx_buf(struct sii8620 *ctx, int len)
645 u8 *buf = &ctx->burst.rx_buf[ctx->burst.rx_count];
648 if (ctx->burst.rx_count + size >= ARRAY_SIZE(ctx->burst.rx_buf)) {
649 dev_err(ctx->dev, "RX-BLK buffer exhausted\n");
650 ctx->error = -EINVAL;
654 ctx->burst.rx_count += size;
660 static void sii8620_burst_send(struct sii8620 *ctx)
662 int tx_left = ctx->burst.tx_count;
663 u8 *d = ctx->burst.tx_buf;
665 while (tx_left > 0) {
668 if (ctx->burst.r_count + len > ctx->burst.r_size)
670 d[0] = min(ctx->burst.rx_ack, 255);
671 ctx->burst.rx_ack -= d[0];
672 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, d, len);
673 ctx->burst.r_count += len;
678 ctx->burst.tx_count = tx_left;
680 while (ctx->burst.rx_ack > 0) {
681 u8 b[2] = { min(ctx->burst.rx_ack, 255), 0 };
683 if (ctx->burst.r_count + 2 > ctx->burst.r_size)
685 ctx->burst.rx_ack -= b[0];
686 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, b, 2);
687 ctx->burst.r_count += 2;
691 static void sii8620_burst_receive(struct sii8620 *ctx)
696 sii8620_read_buf(ctx, REG_EMSCRFIFOBCNTL, buf, 2);
697 count = get_unaligned_le16(buf);
699 int len = min(count, 3);
701 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, buf, len);
703 ctx->burst.rx_ack += len - 1;
704 ctx->burst.r_count -= buf[1];
705 if (ctx->burst.r_count < 0)
706 ctx->burst.r_count = 0;
708 if (len < 3 || !buf[2])
712 d = sii8620_burst_get_rx_buf(ctx, len);
715 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, d, len);
717 ctx->burst.rx_ack += len;
721 static void sii8620_burst_tx_rbuf_info(struct sii8620 *ctx, int size)
723 struct mhl_burst_blk_rcv_buffer_info *d =
724 sii8620_burst_get_tx_buf(ctx, sizeof(*d));
728 d->id = cpu_to_be16(MHL_BURST_ID_BLK_RCV_BUFFER_INFO);
729 d->size = cpu_to_le16(size);
732 static u8 sii8620_checksum(void *ptr, int size)
734 u8 *d = ptr, sum = 0;
742 static void sii8620_mhl_burst_hdr_set(struct mhl3_burst_header *h,
743 enum mhl_burst_id id)
745 h->id = cpu_to_be16(id);
746 h->total_entries = 1;
747 h->sequence_index = 1;
750 static void sii8620_burst_tx_bits_per_pixel_fmt(struct sii8620 *ctx, u8 fmt)
752 struct mhl_burst_bits_per_pixel_fmt *d;
753 const int size = sizeof(*d) + sizeof(d->desc[0]);
755 d = sii8620_burst_get_tx_buf(ctx, size);
759 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_BITS_PER_PIXEL_FMT);
761 d->desc[0].stream_id = 0;
762 d->desc[0].pixel_format = fmt;
763 d->hdr.checksum -= sii8620_checksum(d, size);
766 static void sii8620_burst_rx_all(struct sii8620 *ctx)
768 u8 *d = ctx->burst.rx_buf;
769 int count = ctx->burst.rx_count;
771 while (count-- > 0) {
773 int id = get_unaligned_be16(&d[0]);
776 case MHL_BURST_ID_BLK_RCV_BUFFER_INFO:
777 ctx->burst.r_size = get_unaligned_le16(&d[2]);
785 ctx->burst.rx_count = 0;
788 static void sii8620_fetch_edid(struct sii8620 *ctx)
790 u8 lm_ddc, ddc_cmd, int3, cbus;
791 unsigned long timeout;
793 int edid_len = EDID_LENGTH;
796 sii8620_readb(ctx, REG_CBUS_STATUS);
797 lm_ddc = sii8620_readb(ctx, REG_LM_DDC);
798 ddc_cmd = sii8620_readb(ctx, REG_DDC_CMD);
800 sii8620_write_seq(ctx,
802 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO,
803 REG_HDCP2X_POLL_CS, 0x71,
804 REG_HDCP2X_CTRL_0, BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX,
805 REG_LM_DDC, lm_ddc | BIT_LM_DDC_SW_TPI_EN_DISABLED,
808 for (i = 0; i < 256; ++i) {
809 u8 ddc_stat = sii8620_readb(ctx, REG_DDC_STATUS);
811 if (!(ddc_stat & BIT_DDC_STATUS_DDC_I2C_IN_PROG))
813 sii8620_write(ctx, REG_DDC_STATUS,
814 BIT_DDC_STATUS_DDC_FIFO_EMPTY);
817 sii8620_write(ctx, REG_DDC_ADDR, 0x50 << 1);
819 edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
821 ctx->error = -ENOMEM;
825 #define FETCH_SIZE 16
826 for (fetched = 0; fetched < edid_len; fetched += FETCH_SIZE) {
827 sii8620_readb(ctx, REG_DDC_STATUS);
828 sii8620_write_seq(ctx,
829 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_ABORT,
830 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO,
831 REG_DDC_STATUS, BIT_DDC_STATUS_DDC_FIFO_EMPTY
833 sii8620_write_seq(ctx,
834 REG_DDC_SEGM, fetched >> 8,
835 REG_DDC_OFFSET, fetched & 0xff,
836 REG_DDC_DIN_CNT1, FETCH_SIZE,
838 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_ENH_DDC_READ_NO_ACK
842 timeout = jiffies + msecs_to_jiffies(200);
844 cbus = sii8620_readb(ctx, REG_CBUS_STATUS);
845 if (~cbus & BIT_CBUS_STATUS_CBUS_CONNECTED) {
850 if (int3 & BIT_DDC_CMD_DONE) {
851 if (sii8620_readb(ctx, REG_DDC_DOUT_CNT)
855 int3 = sii8620_readb(ctx, REG_INTR3);
857 if (time_is_before_jiffies(timeout)) {
858 ctx->error = -ETIMEDOUT;
859 dev_err(ctx->dev, "timeout during EDID read\n");
864 usleep_range(10, 20);
867 sii8620_read_buf(ctx, REG_DDC_DATA, edid + fetched, FETCH_SIZE);
868 if (fetched + FETCH_SIZE == EDID_LENGTH) {
869 u8 ext = ((struct edid *)edid)->extensions;
874 edid_len += ext * EDID_LENGTH;
875 new_edid = krealloc(edid, edid_len, GFP_KERNEL);
878 ctx->error = -ENOMEM;
886 sii8620_write_seq(ctx,
887 REG_INTR3_MASK, BIT_DDC_CMD_DONE,
893 ctx->edid = (struct edid *)edid;
896 static void sii8620_set_upstream_edid(struct sii8620 *ctx)
898 sii8620_setbits(ctx, REG_DPD, BIT_DPD_PDNRX12 | BIT_DPD_PDIDCK_N
899 | BIT_DPD_PD_MHL_CLK_N, 0xff);
901 sii8620_write_seq_static(ctx,
902 REG_RX_HDMI_CTRL3, 0x00,
903 REG_PKT_FILTER_0, 0xFF,
904 REG_PKT_FILTER_1, 0xFF,
905 REG_ALICE0_BW_I2C, 0x06
908 sii8620_setbits(ctx, REG_RX_HDMI_CLR_BUFFER,
909 BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN, 0xff);
911 sii8620_write_seq_static(ctx,
912 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
913 | BIT_EDID_CTRL_EDID_MODE_EN,
914 REG_EDID_FIFO_ADDR, 0,
917 sii8620_write_buf(ctx, REG_EDID_FIFO_WR_DATA, (u8 *)ctx->edid,
918 (ctx->edid->extensions + 1) * EDID_LENGTH);
920 sii8620_write_seq_static(ctx,
921 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID
922 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
923 | BIT_EDID_CTRL_EDID_MODE_EN,
924 REG_INTR5_MASK, BIT_INTR_SCDT_CHANGE,
929 static void sii8620_xtal_set_rate(struct sii8620 *ctx)
931 static const struct {
936 { 19200, 0x04, 0x53 },
937 { 20000, 0x04, 0x62 },
938 { 24000, 0x05, 0x75 },
939 { 30000, 0x06, 0x92 },
940 { 38400, 0x0c, 0xbc },
942 unsigned long rate = clk_get_rate(ctx->clk_xtal) / 1000;
945 for (i = 0; i < ARRAY_SIZE(rates) - 1; ++i)
946 if (rate <= rates[i].rate)
949 if (rate != rates[i].rate)
950 dev_err(ctx->dev, "xtal clock rate(%lukHz) not supported, setting MHL for %ukHz.\n",
951 rate, rates[i].rate);
953 sii8620_write(ctx, REG_DIV_CTL_MAIN, rates[i].div);
954 sii8620_write(ctx, REG_HDCP2X_TP1, rates[i].tp1);
957 static int sii8620_hw_on(struct sii8620 *ctx)
961 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
964 usleep_range(10000, 20000);
965 return clk_prepare_enable(ctx->clk_xtal);
968 static int sii8620_hw_off(struct sii8620 *ctx)
970 clk_disable_unprepare(ctx->clk_xtal);
971 gpiod_set_value(ctx->gpio_reset, 1);
972 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
975 static void sii8620_hw_reset(struct sii8620 *ctx)
977 usleep_range(10000, 20000);
978 gpiod_set_value(ctx->gpio_reset, 0);
979 usleep_range(5000, 20000);
980 gpiod_set_value(ctx->gpio_reset, 1);
981 usleep_range(10000, 20000);
982 gpiod_set_value(ctx->gpio_reset, 0);
986 static void sii8620_cbus_reset(struct sii8620 *ctx)
988 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST
989 | BIT_PWD_SRST_CBUS_RST_SW_EN);
990 usleep_range(10000, 20000);
991 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN);
994 static void sii8620_set_auto_zone(struct sii8620 *ctx)
996 if (ctx->mode != CM_MHL1) {
997 sii8620_write_seq_static(ctx,
998 REG_TX_ZONE_CTL1, 0x0,
999 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1000 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
1001 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE
1004 sii8620_write_seq_static(ctx,
1005 REG_TX_ZONE_CTL1, VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE,
1006 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1007 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE
1012 static void sii8620_stop_video(struct sii8620 *ctx)
1016 sii8620_write_seq_static(ctx,
1018 REG_HDCP2X_INTR0_MASK, 0,
1019 REG_TPI_COPP_DATA2, 0,
1020 REG_TPI_INTR_ST0, ~0,
1023 switch (ctx->sink_type) {
1025 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN
1026 | BIT_TPI_SC_TPI_AV_MUTE;
1030 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN
1031 | BIT_TPI_SC_TPI_AV_MUTE
1032 | BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI;
1036 sii8620_write(ctx, REG_TPI_SC, val);
1039 static void sii8620_set_format(struct sii8620 *ctx)
1043 if (sii8620_is_mhl3(ctx)) {
1044 sii8620_setbits(ctx, REG_M3_P0CTRL,
1045 BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED,
1046 ctx->use_packed_pixel ? ~0 : 0);
1048 if (ctx->use_packed_pixel) {
1049 sii8620_write_seq_static(ctx,
1050 REG_VID_MODE, BIT_VID_MODE_M1080P,
1051 REG_MHL_TOP_CTL, BIT_MHL_TOP_CTL_MHL_PP_SEL | 1,
1052 REG_MHLTX_CTL6, 0x60
1055 sii8620_write_seq_static(ctx,
1058 REG_MHLTX_CTL6, 0xa0
1063 if (ctx->use_packed_pixel)
1064 out_fmt = VAL_TPI_FORMAT(YCBCR422, FULL);
1066 out_fmt = VAL_TPI_FORMAT(RGB, FULL);
1068 sii8620_write_seq(ctx,
1069 REG_TPI_INPUT, VAL_TPI_FORMAT(RGB, FULL),
1070 REG_TPI_OUTPUT, out_fmt,
1074 static int mhl3_infoframe_init(struct mhl3_infoframe *frame)
1076 memset(frame, 0, sizeof(*frame));
1079 frame->hev_format = -1;
1083 static ssize_t mhl3_infoframe_pack(struct mhl3_infoframe *frame,
1084 void *buffer, size_t size)
1086 const int frm_len = HDMI_INFOFRAME_HEADER_SIZE + MHL3_INFOFRAME_SIZE;
1092 memset(buffer, 0, size);
1093 ptr[0] = HDMI_INFOFRAME_TYPE_VENDOR;
1094 ptr[1] = frame->version;
1095 ptr[2] = MHL3_INFOFRAME_SIZE;
1096 ptr[4] = MHL3_IEEE_OUI & 0xff;
1097 ptr[5] = (MHL3_IEEE_OUI >> 8) & 0xff;
1098 ptr[6] = (MHL3_IEEE_OUI >> 16) & 0xff;
1099 ptr[7] = frame->video_format & 0x3;
1100 ptr[7] |= (frame->format_type & 0x7) << 2;
1101 ptr[7] |= frame->sep_audio ? BIT(5) : 0;
1102 if (frame->hev_format >= 0) {
1104 ptr[10] = (frame->hev_format >> 8) & 0xff;
1105 ptr[11] = frame->hev_format & 0xff;
1107 if (frame->av_delay) {
1108 bool sign = frame->av_delay < 0;
1109 int delay = sign ? -frame->av_delay : frame->av_delay;
1111 ptr[12] = (delay >> 16) & 0xf;
1114 ptr[13] = (delay >> 8) & 0xff;
1115 ptr[14] = delay & 0xff;
1117 ptr[3] -= sii8620_checksum(buffer, frm_len);
1121 static void sii8620_set_infoframes(struct sii8620 *ctx)
1123 struct mhl3_infoframe mhl_frm;
1124 union hdmi_infoframe frm;
1128 if (!sii8620_is_mhl3(ctx) || !ctx->use_packed_pixel) {
1129 sii8620_write(ctx, REG_TPI_SC,
1130 BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI);
1131 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, ctx->avif + 3,
1132 ARRAY_SIZE(ctx->avif) - 3);
1133 sii8620_write(ctx, REG_PKT_FILTER_0,
1134 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT |
1135 BIT_PKT_FILTER_0_DROP_MPEG_PKT |
1136 BIT_PKT_FILTER_0_DROP_GCP_PKT,
1137 BIT_PKT_FILTER_1_DROP_GEN_PKT);
1141 ret = hdmi_avi_infoframe_init(&frm.avi);
1142 frm.avi.colorspace = HDMI_COLORSPACE_YUV422;
1143 frm.avi.active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
1144 frm.avi.picture_aspect = HDMI_PICTURE_ASPECT_16_9;
1145 frm.avi.colorimetry = HDMI_COLORIMETRY_ITU_709;
1146 frm.avi.video_code = ctx->video_code;
1148 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, ARRAY_SIZE(buf));
1150 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, buf + 3, ret - 3);
1151 sii8620_write(ctx, REG_PKT_FILTER_0,
1152 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT |
1153 BIT_PKT_FILTER_0_DROP_MPEG_PKT |
1154 BIT_PKT_FILTER_0_DROP_AVI_PKT |
1155 BIT_PKT_FILTER_0_DROP_GCP_PKT,
1156 BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS |
1157 BIT_PKT_FILTER_1_DROP_GEN_PKT |
1158 BIT_PKT_FILTER_1_DROP_VSIF_PKT);
1160 sii8620_write(ctx, REG_TPI_INFO_FSEL, BIT_TPI_INFO_FSEL_EN
1161 | BIT_TPI_INFO_FSEL_RPT | VAL_TPI_INFO_FSEL_VSI);
1162 ret = mhl3_infoframe_init(&mhl_frm);
1164 ret = mhl3_infoframe_pack(&mhl_frm, buf, ARRAY_SIZE(buf));
1165 sii8620_write_buf(ctx, REG_TPI_INFO_B0, buf, ret);
1168 static void sii8620_start_hdmi(struct sii8620 *ctx)
1170 sii8620_write_seq_static(ctx,
1171 REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL
1172 | BIT_RX_HDMI_CTRL2_USE_AV_MUTE,
1173 REG_VID_OVRRD, BIT_VID_OVRRD_PP_AUTO_DISABLE
1174 | BIT_VID_OVRRD_M1080P_OVRRD);
1175 sii8620_set_format(ctx);
1177 if (!sii8620_is_mhl3(ctx)) {
1178 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
1179 MHL_DST_LM_CLK_MODE_NORMAL | MHL_DST_LM_PATH_ENABLED);
1180 sii8620_set_auto_zone(ctx);
1182 static const struct {
1188 { 150000, VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS,
1189 MHL_XDS_LINK_RATE_1_5_GBPS, 0x38 },
1190 { 300000, VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS,
1191 MHL_XDS_LINK_RATE_3_0_GBPS, 0x40 },
1192 { 600000, VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS,
1193 MHL_XDS_LINK_RATE_6_0_GBPS, 0x40 },
1195 u8 p0_ctrl = BIT_M3_P0CTRL_MHL3_P0_PORT_EN;
1196 int clk = ctx->pixel_clock * (ctx->use_packed_pixel ? 2 : 3);
1199 for (i = 0; i < ARRAY_SIZE(clk_spec) - 1; ++i)
1200 if (clk < clk_spec[i].max_clk)
1203 if (100 * clk >= 98 * clk_spec[i].max_clk)
1204 p0_ctrl |= BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN;
1206 sii8620_burst_tx_bits_per_pixel_fmt(ctx, ctx->use_packed_pixel);
1207 sii8620_burst_send(ctx);
1208 sii8620_write_seq(ctx,
1209 REG_MHL_DP_CTL0, 0xf0,
1210 REG_MHL3_TX_ZONE_CTL, clk_spec[i].zone);
1211 sii8620_setbits(ctx, REG_M3_P0CTRL,
1212 BIT_M3_P0CTRL_MHL3_P0_PORT_EN
1213 | BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN, p0_ctrl);
1214 sii8620_setbits(ctx, REG_M3_POSTM, MSK_M3_POSTM_RRP_DECODE,
1215 clk_spec[i].rrp_decode);
1216 sii8620_write_seq_static(ctx,
1217 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE
1218 | BIT_M3_CTRL_H2M_SWRST,
1219 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE
1221 sii8620_mt_write_stat(ctx, MHL_XDS_REG(AVLINK_MODE_CONTROL),
1222 clk_spec[i].link_rate);
1225 sii8620_set_infoframes(ctx);
1228 static void sii8620_start_video(struct sii8620 *ctx)
1230 if (!sii8620_is_mhl3(ctx))
1231 sii8620_stop_video(ctx);
1233 switch (ctx->sink_type) {
1235 sii8620_start_hdmi(ctx);
1243 static void sii8620_disable_hpd(struct sii8620 *ctx)
1245 sii8620_setbits(ctx, REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID, 0);
1246 sii8620_write_seq_static(ctx,
1247 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN,
1252 static void sii8620_enable_hpd(struct sii8620 *ctx)
1254 sii8620_setbits(ctx, REG_TMDS_CSTAT_P3,
1255 BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS
1256 | BIT_TMDS_CSTAT_P3_CLR_AVI, ~0);
1257 sii8620_write_seq_static(ctx,
1258 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN
1259 | BIT_HPD_CTRL_HPD_HIGH,
1263 static void sii8620_mhl_discover(struct sii8620 *ctx)
1265 sii8620_write_seq_static(ctx,
1266 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1267 | BIT_DISC_CTRL9_DISC_PULSE_PROCEED,
1268 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_5K, VAL_PUP_20K),
1269 REG_CBUS_DISC_INTR0_MASK, BIT_MHL3_EST_INT
1271 | BIT_NOT_MHL_EST_INT
1272 | BIT_CBUS_MHL3_DISCON_INT
1273 | BIT_CBUS_MHL12_DISCON_INT
1274 | BIT_RGND_READY_INT,
1275 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1276 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
1277 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE,
1278 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE
1279 | BIT_MHL_DP_CTL0_TX_OE_OVR,
1280 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
1281 REG_MHL_DP_CTL1, 0xA2,
1282 REG_MHL_DP_CTL2, 0x03,
1283 REG_MHL_DP_CTL3, 0x35,
1284 REG_MHL_DP_CTL5, 0x02,
1285 REG_MHL_DP_CTL6, 0x02,
1286 REG_MHL_DP_CTL7, 0x03,
1288 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12
1289 | BIT_DPD_OSC_EN | BIT_DPD_PWRON_HSIC,
1290 REG_COC_INTR_MASK, BIT_COC_PLL_LOCK_STATUS_CHANGE
1291 | BIT_COC_CALIBRATION_DONE,
1292 REG_CBUS_INT_1_MASK, BIT_CBUS_MSC_ABORT_RCVD
1293 | BIT_CBUS_CMD_ABORT,
1294 REG_CBUS_INT_0_MASK, BIT_CBUS_MSC_MT_DONE
1296 | BIT_CBUS_MSC_MR_WRITE_STAT
1297 | BIT_CBUS_MSC_MR_MSC_MSG
1298 | BIT_CBUS_MSC_MR_WRITE_BURST
1299 | BIT_CBUS_MSC_MR_SET_INT
1300 | BIT_CBUS_MSC_MT_DONE_NACK
1304 static void sii8620_peer_specific_init(struct sii8620 *ctx)
1306 if (sii8620_is_mhl3(ctx))
1307 sii8620_write_seq_static(ctx,
1308 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD,
1310 BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR
1313 sii8620_write_seq_static(ctx,
1314 REG_HDCP2X_INTR0_MASK, 0x00,
1315 REG_EMSCINTRMASK1, 0x00,
1316 REG_HDCP2X_INTR0, 0xFF,
1318 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD
1319 | BIT_SYS_CTRL1_TX_CTRL_HDMI
1323 #define SII8620_MHL_VERSION 0x32
1324 #define SII8620_SCRATCHPAD_SIZE 16
1325 #define SII8620_INT_STAT_SIZE 0x33
1327 static void sii8620_set_dev_cap(struct sii8620 *ctx)
1329 static const u8 devcap[MHL_DCAP_SIZE] = {
1330 [MHL_DCAP_MHL_VERSION] = SII8620_MHL_VERSION,
1331 [MHL_DCAP_CAT] = MHL_DCAP_CAT_SOURCE | MHL_DCAP_CAT_POWER,
1332 [MHL_DCAP_ADOPTER_ID_H] = 0x01,
1333 [MHL_DCAP_ADOPTER_ID_L] = 0x41,
1334 [MHL_DCAP_VID_LINK_MODE] = MHL_DCAP_VID_LINK_RGB444
1335 | MHL_DCAP_VID_LINK_PPIXEL
1336 | MHL_DCAP_VID_LINK_16BPP,
1337 [MHL_DCAP_AUD_LINK_MODE] = MHL_DCAP_AUD_LINK_2CH,
1338 [MHL_DCAP_VIDEO_TYPE] = MHL_DCAP_VT_GRAPHICS,
1339 [MHL_DCAP_LOG_DEV_MAP] = MHL_DCAP_LD_GUI,
1340 [MHL_DCAP_BANDWIDTH] = 0x0f,
1341 [MHL_DCAP_FEATURE_FLAG] = MHL_DCAP_FEATURE_RCP_SUPPORT
1342 | MHL_DCAP_FEATURE_RAP_SUPPORT
1343 | MHL_DCAP_FEATURE_SP_SUPPORT,
1344 [MHL_DCAP_SCRATCHPAD_SIZE] = SII8620_SCRATCHPAD_SIZE,
1345 [MHL_DCAP_INT_STAT_SIZE] = SII8620_INT_STAT_SIZE,
1347 static const u8 xdcap[MHL_XDC_SIZE] = {
1348 [MHL_XDC_ECBUS_SPEEDS] = MHL_XDC_ECBUS_S_075
1349 | MHL_XDC_ECBUS_S_8BIT,
1350 [MHL_XDC_TMDS_SPEEDS] = MHL_XDC_TMDS_150
1351 | MHL_XDC_TMDS_300 | MHL_XDC_TMDS_600,
1352 [MHL_XDC_ECBUS_ROLES] = MHL_XDC_DEV_HOST,
1353 [MHL_XDC_LOG_DEV_MAPX] = MHL_XDC_LD_PHONE,
1356 sii8620_write_buf(ctx, REG_MHL_DEVCAP_0, devcap, ARRAY_SIZE(devcap));
1357 sii8620_write_buf(ctx, REG_MHL_EXTDEVCAP_0, xdcap, ARRAY_SIZE(xdcap));
1360 static void sii8620_mhl_init(struct sii8620 *ctx)
1362 sii8620_write_seq_static(ctx,
1363 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1364 REG_CBUS_MSC_COMPAT_CTRL,
1365 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN,
1368 sii8620_peer_specific_init(ctx);
1370 sii8620_disable_hpd(ctx);
1372 sii8620_write_seq_static(ctx,
1373 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO,
1374 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1375 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1376 REG_TMDS0_CCTRL1, 0x90,
1377 REG_TMDS_CLK_EN, 0x01,
1378 REG_TMDS_CH_EN, 0x11,
1380 REG_ALICE0_ZONE_CTRL, 0xE8,
1381 REG_ALICE0_MODE_CTRL, 0x04,
1383 sii8620_setbits(ctx, REG_LM_DDC, BIT_LM_DDC_SW_TPI_EN_DISABLED, 0);
1384 sii8620_write_seq_static(ctx,
1385 REG_TPI_HW_OPT3, 0x76,
1386 REG_TMDS_CCTRL, BIT_TMDS_CCTRL_TMDS_OE,
1389 sii8620_set_dev_cap(ctx);
1390 sii8620_write_seq_static(ctx,
1391 REG_MDT_XMIT_TIMEOUT, 100,
1392 REG_MDT_XMIT_CTRL, 0x03,
1393 REG_MDT_XFIFO_STAT, 0x00,
1394 REG_MDT_RCV_TIMEOUT, 100,
1395 REG_CBUS_LINK_CTRL_8, 0x1D,
1398 sii8620_start_gen2_write_burst(ctx);
1399 sii8620_write_seq_static(ctx,
1400 REG_BIST_CTRL, 0x00,
1404 REG_COC_CTL11, 0xF8,
1405 REG_COC_CTL17, 0x61,
1406 REG_COC_CTL18, 0x46,
1407 REG_COC_CTL19, 0x15,
1408 REG_COC_CTL1A, 0x01,
1409 REG_MHL_COC_CTL3, BIT_MHL_COC_CTL3_COC_AECHO_EN,
1410 REG_MHL_COC_CTL4, 0x2D,
1411 REG_MHL_COC_CTL5, 0xF9,
1412 REG_MSC_HEARTBEAT_CTRL, 0x27,
1414 sii8620_disable_gen2_write_burst(ctx);
1416 sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), SII8620_MHL_VERSION);
1417 sii8620_mt_write_stat(ctx, MHL_DST_REG(CONNECTED_RDY),
1418 MHL_DST_CONN_DCAP_RDY | MHL_DST_CONN_XDEVCAPP_SUPP
1419 | MHL_DST_CONN_POW_STAT);
1420 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), MHL_INT_RC_DCAP_CHG);
1423 static void sii8620_emsc_enable(struct sii8620 *ctx)
1427 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_EMSC_EN
1428 | BIT_GENCTL_CLR_EMSC_RFIFO
1429 | BIT_GENCTL_CLR_EMSC_XFIFO, ~0);
1430 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_CLR_EMSC_RFIFO
1431 | BIT_GENCTL_CLR_EMSC_XFIFO, 0);
1432 sii8620_setbits(ctx, REG_COMMECNT, BIT_COMMECNT_I2C_TO_EMSC_EN, ~0);
1433 reg = sii8620_readb(ctx, REG_EMSCINTR);
1434 sii8620_write(ctx, REG_EMSCINTR, reg);
1435 sii8620_write(ctx, REG_EMSCINTRMASK, BIT_EMSCINTR_SPI_DVLD);
1438 static int sii8620_wait_for_fsm_state(struct sii8620 *ctx, u8 state)
1442 for (i = 0; i < 10; ++i) {
1443 u8 s = sii8620_readb(ctx, REG_COC_STAT_0);
1445 if ((s & MSK_COC_STAT_0_FSM_STATE) == state)
1447 if (!(s & BIT_COC_STAT_0_PLL_LOCKED))
1449 usleep_range(4000, 6000);
1454 static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode)
1458 if (ctx->mode == mode)
1463 sii8620_write_seq_static(ctx,
1464 REG_CBUS_MSC_COMPAT_CTRL, 0x02,
1465 REG_M3_CTRL, VAL_M3_CTRL_MHL1_2_VALUE,
1466 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12
1468 REG_COC_INTR_MASK, 0
1473 sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE);
1477 sii8620_emsc_enable(ctx);
1478 sii8620_write_seq_static(ctx,
1481 REG_TTXHSICNUMS, 0x14,
1482 REG_TRXHSICNUMS, 0x14,
1483 REG_TTXTOTNUMS, 0x18,
1484 REG_TRXTOTNUMS, 0x18,
1485 REG_PWD_SRST, BIT_PWD_SRST_COC_DOC_RST
1486 | BIT_PWD_SRST_CBUS_RST_SW_EN,
1487 REG_MHL_COC_CTL1, 0xbd,
1488 REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN,
1491 REG_COC_CTL14, 0x03,
1492 REG_COC_CTL15, 0x80,
1493 REG_MHL_DP_CTL6, BIT_MHL_DP_CTL6_DP_TAP1_SGN
1494 | BIT_MHL_DP_CTL6_DP_TAP1_EN
1495 | BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN,
1496 REG_MHL_DP_CTL8, 0x03
1498 ret = sii8620_wait_for_fsm_state(ctx, 0x03);
1499 sii8620_write_seq_static(ctx,
1500 REG_COC_CTL14, 0x00,
1504 sii8620_write(ctx, REG_CBUS3_CNVT, 0x85);
1506 sii8620_disconnect(ctx);
1508 case CM_DISCONNECTED:
1512 dev_err(ctx->dev, "%s mode %d not supported\n", __func__, mode);
1516 sii8620_set_auto_zone(ctx);
1518 if (mode != CM_MHL1)
1521 sii8620_write_seq_static(ctx,
1522 REG_MHL_DP_CTL0, 0xBC,
1523 REG_MHL_DP_CTL1, 0xBB,
1524 REG_MHL_DP_CTL3, 0x48,
1525 REG_MHL_DP_CTL5, 0x39,
1526 REG_MHL_DP_CTL2, 0x2A,
1527 REG_MHL_DP_CTL6, 0x2A,
1528 REG_MHL_DP_CTL7, 0x08
1532 static void sii8620_disconnect(struct sii8620 *ctx)
1534 sii8620_disable_gen2_write_burst(ctx);
1535 sii8620_stop_video(ctx);
1537 sii8620_cbus_reset(ctx);
1538 sii8620_set_mode(ctx, CM_DISCONNECTED);
1539 sii8620_write_seq_static(ctx,
1540 REG_TX_ZONE_CTL1, 0,
1541 REG_MHL_PLL_CTL0, 0x07,
1543 REG_CBUS3_CNVT, 0x84,
1544 REG_COC_CTL14, 0x00,
1547 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1548 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
1549 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE,
1550 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE
1551 | BIT_MHL_DP_CTL0_TX_OE_OVR,
1552 REG_MHL_DP_CTL1, 0xBB,
1553 REG_MHL_DP_CTL3, 0x48,
1554 REG_MHL_DP_CTL5, 0x3F,
1555 REG_MHL_DP_CTL2, 0x2F,
1556 REG_MHL_DP_CTL6, 0x2A,
1557 REG_MHL_DP_CTL7, 0x03
1559 sii8620_disable_hpd(ctx);
1560 sii8620_write_seq_static(ctx,
1561 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
1562 REG_MHL_COC_CTL1, 0x07,
1563 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1564 REG_DISC_CTRL8, 0x00,
1565 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1566 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1568 REG_MSC_HEARTBEAT_CTRL, 0x27,
1569 REG_DISC_CTRL1, 0x25,
1570 REG_CBUS_DISC_INTR0, (u8)~BIT_RGND_READY_INT,
1571 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT,
1572 REG_MDT_INT_1, 0xff,
1573 REG_MDT_INT_1_MASK, 0x00,
1574 REG_MDT_INT_0, 0xff,
1575 REG_MDT_INT_0_MASK, 0x00,
1577 REG_COC_INTR_MASK, 0x00,
1580 REG_CBUS_INT_0, 0xff,
1581 REG_CBUS_INT_0_MASK, 0x00,
1582 REG_CBUS_INT_1, 0xff,
1583 REG_CBUS_INT_1_MASK, 0x00,
1585 REG_EMSCINTRMASK, 0x00,
1586 REG_EMSCINTR1, 0xff,
1587 REG_EMSCINTRMASK1, 0x00,
1589 REG_INTR8_MASK, 0x00,
1590 REG_TPI_INTR_ST0, 0xff,
1591 REG_TPI_INTR_EN, 0x00,
1592 REG_HDCP2X_INTR0, 0xff,
1593 REG_HDCP2X_INTR0_MASK, 0x00,
1595 REG_INTR9_MASK, 0x00,
1597 REG_INTR3_MASK, 0x00,
1599 REG_INTR5_MASK, 0x00,
1601 REG_INTR2_MASK, 0x00,
1603 memset(ctx->stat, 0, sizeof(ctx->stat));
1604 memset(ctx->xstat, 0, sizeof(ctx->xstat));
1605 memset(ctx->devcap, 0, sizeof(ctx->devcap));
1606 memset(ctx->xdevcap, 0, sizeof(ctx->xdevcap));
1607 ctx->cbus_status = 0;
1608 ctx->sink_type = SINK_NONE;
1611 sii8620_mt_cleanup(ctx);
1614 static void sii8620_mhl_disconnected(struct sii8620 *ctx)
1616 sii8620_write_seq_static(ctx,
1617 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1618 REG_CBUS_MSC_COMPAT_CTRL,
1619 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN
1621 sii8620_disconnect(ctx);
1624 static void sii8620_irq_disc(struct sii8620 *ctx)
1626 u8 stat = sii8620_readb(ctx, REG_CBUS_DISC_INTR0);
1628 if (stat & VAL_CBUS_MHL_DISCON)
1629 sii8620_mhl_disconnected(ctx);
1631 if (stat & BIT_RGND_READY_INT) {
1632 u8 stat2 = sii8620_readb(ctx, REG_DISC_STAT2);
1634 if ((stat2 & MSK_DISC_STAT2_RGND) == VAL_RGND_1K) {
1635 sii8620_mhl_discover(ctx);
1637 sii8620_write_seq_static(ctx,
1638 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1639 | BIT_DISC_CTRL9_NOMHL_EST
1640 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1641 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT
1642 | BIT_CBUS_MHL3_DISCON_INT
1643 | BIT_CBUS_MHL12_DISCON_INT
1644 | BIT_NOT_MHL_EST_INT
1648 if (stat & BIT_MHL_EST_INT)
1649 sii8620_mhl_init(ctx);
1651 sii8620_write(ctx, REG_CBUS_DISC_INTR0, stat);
1654 static void sii8620_read_burst(struct sii8620 *ctx)
1658 sii8620_read_buf(ctx, REG_MDT_RCV_READ_PORT, buf, ARRAY_SIZE(buf));
1659 sii8620_write(ctx, REG_MDT_RCV_CTRL, BIT_MDT_RCV_CTRL_MDT_RCV_EN |
1660 BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN |
1661 BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR);
1662 sii8620_readb(ctx, REG_MDT_RFIFO_STAT);
1665 static void sii8620_irq_g2wb(struct sii8620 *ctx)
1667 u8 stat = sii8620_readb(ctx, REG_MDT_INT_0);
1669 if (stat & BIT_MDT_IDLE_AFTER_HAWB_DISABLE)
1670 if (sii8620_is_mhl3(ctx))
1671 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE),
1672 MHL_INT_RC_FEAT_COMPLETE);
1674 if (stat & BIT_MDT_RFIFO_DATA_RDY)
1675 sii8620_read_burst(ctx);
1677 if (stat & BIT_MDT_XFIFO_EMPTY)
1678 sii8620_write(ctx, REG_MDT_XMIT_CTRL, 0);
1680 sii8620_write(ctx, REG_MDT_INT_0, stat);
1683 static void sii8620_status_dcap_ready(struct sii8620 *ctx)
1685 enum sii8620_mode mode;
1687 mode = ctx->stat[MHL_DST_VERSION] >= 0x30 ? CM_MHL3 : CM_MHL1;
1688 if (mode > ctx->mode)
1689 sii8620_set_mode(ctx, mode);
1690 sii8620_peer_specific_init(ctx);
1691 sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE
1692 | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR);
1695 static void sii8620_status_changed_path(struct sii8620 *ctx)
1697 if (ctx->stat[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) {
1698 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
1699 MHL_DST_LM_CLK_MODE_NORMAL
1700 | MHL_DST_LM_PATH_ENABLED);
1701 if (!sii8620_is_mhl3(ctx))
1702 sii8620_mt_read_devcap(ctx, false);
1703 sii8620_mt_set_cont(ctx, sii8620_sink_detected);
1705 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
1706 MHL_DST_LM_CLK_MODE_NORMAL);
1710 static void sii8620_msc_mr_write_stat(struct sii8620 *ctx)
1712 u8 st[MHL_DST_SIZE], xst[MHL_XDS_SIZE];
1714 sii8620_read_buf(ctx, REG_MHL_STAT_0, st, MHL_DST_SIZE);
1715 sii8620_read_buf(ctx, REG_MHL_EXTSTAT_0, xst, MHL_XDS_SIZE);
1717 sii8620_update_array(ctx->stat, st, MHL_DST_SIZE);
1718 sii8620_update_array(ctx->xstat, xst, MHL_XDS_SIZE);
1720 if (ctx->stat[MHL_DST_CONNECTED_RDY] & MHL_DST_CONN_DCAP_RDY)
1721 sii8620_status_dcap_ready(ctx);
1723 if (st[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED)
1724 sii8620_status_changed_path(ctx);
1727 static void sii8620_ecbus_up(struct sii8620 *ctx, int ret)
1732 sii8620_set_mode(ctx, CM_ECBUS_S);
1735 static void sii8620_got_ecbus_speed(struct sii8620 *ctx, int ret)
1740 sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE),
1741 MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT);
1742 sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP);
1743 sii8620_mt_set_cont(ctx, sii8620_ecbus_up);
1746 static void sii8620_mhl_burst_emsc_support_set(struct mhl_burst_emsc_support *d,
1747 enum mhl_burst_id id)
1749 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_EMSC_SUPPORT);
1751 d->burst_id[0] = cpu_to_be16(id);
1754 static void sii8620_send_features(struct sii8620 *ctx)
1758 sii8620_write(ctx, REG_MDT_XMIT_CTRL, BIT_MDT_XMIT_CTRL_EN
1759 | BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN);
1760 sii8620_mhl_burst_emsc_support_set((void *)buf,
1761 MHL_BURST_ID_HID_PAYLOAD);
1762 sii8620_write_buf(ctx, REG_MDT_XMIT_WRITE_PORT, buf, ARRAY_SIZE(buf));
1765 static void sii8620_msc_mr_set_int(struct sii8620 *ctx)
1767 u8 ints[MHL_INT_SIZE];
1769 sii8620_read_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE);
1770 sii8620_write_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE);
1772 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_DCAP_CHG) {
1773 switch (ctx->mode) {
1775 sii8620_mt_read_xdevcap_reg(ctx, MHL_XDC_ECBUS_SPEEDS);
1776 sii8620_mt_set_cont(ctx, sii8620_got_ecbus_speed);
1779 sii8620_mt_read_devcap(ctx, true);
1785 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_REQ)
1786 sii8620_send_features(ctx);
1787 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_COMPLETE)
1788 sii8620_edid_read(ctx, 0);
1791 static struct sii8620_mt_msg *sii8620_msc_msg_first(struct sii8620 *ctx)
1793 struct device *dev = ctx->dev;
1795 if (list_empty(&ctx->mt_queue)) {
1796 dev_err(dev, "unexpected MSC MT response\n");
1800 return list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
1803 static void sii8620_msc_mt_done(struct sii8620 *ctx)
1805 struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx);
1810 msg->ret = sii8620_readb(ctx, REG_MSC_MT_RCVD_DATA0);
1811 ctx->mt_state = MT_STATE_DONE;
1814 static void sii8620_msc_mr_msc_msg(struct sii8620 *ctx)
1816 struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx);
1822 sii8620_read_buf(ctx, REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA, buf, 2);
1825 case MHL_MSC_MSG_RAPK:
1827 ctx->mt_state = MT_STATE_DONE;
1830 dev_err(ctx->dev, "%s message type %d,%d not supported",
1831 __func__, buf[0], buf[1]);
1835 static void sii8620_irq_msc(struct sii8620 *ctx)
1837 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_0);
1839 if (stat & ~BIT_CBUS_HPD_CHG)
1840 sii8620_write(ctx, REG_CBUS_INT_0, stat & ~BIT_CBUS_HPD_CHG);
1842 if (stat & BIT_CBUS_HPD_CHG) {
1843 u8 cbus_stat = sii8620_readb(ctx, REG_CBUS_STATUS);
1845 if ((cbus_stat ^ ctx->cbus_status) & BIT_CBUS_STATUS_CBUS_HPD) {
1846 sii8620_write(ctx, REG_CBUS_INT_0, BIT_CBUS_HPD_CHG);
1848 stat ^= BIT_CBUS_STATUS_CBUS_HPD;
1849 cbus_stat ^= BIT_CBUS_STATUS_CBUS_HPD;
1851 ctx->cbus_status = cbus_stat;
1854 if (stat & BIT_CBUS_MSC_MR_WRITE_STAT)
1855 sii8620_msc_mr_write_stat(ctx);
1857 if (stat & BIT_CBUS_MSC_MR_SET_INT)
1858 sii8620_msc_mr_set_int(ctx);
1860 if (stat & BIT_CBUS_MSC_MT_DONE)
1861 sii8620_msc_mt_done(ctx);
1863 if (stat & BIT_CBUS_MSC_MR_MSC_MSG)
1864 sii8620_msc_mr_msc_msg(ctx);
1867 static void sii8620_irq_coc(struct sii8620 *ctx)
1869 u8 stat = sii8620_readb(ctx, REG_COC_INTR);
1871 if (stat & BIT_COC_CALIBRATION_DONE) {
1872 u8 cstat = sii8620_readb(ctx, REG_COC_STAT_0);
1874 cstat &= BIT_COC_STAT_0_PLL_LOCKED | MSK_COC_STAT_0_FSM_STATE;
1875 if (cstat == (BIT_COC_STAT_0_PLL_LOCKED | 0x02)) {
1876 sii8620_write_seq_static(ctx,
1878 REG_TRXINTMH, BIT_TDM_INTR_SYNC_DATA
1879 | BIT_TDM_INTR_SYNC_WAIT
1884 sii8620_write(ctx, REG_COC_INTR, stat);
1887 static void sii8620_irq_merr(struct sii8620 *ctx)
1889 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_1);
1891 sii8620_write(ctx, REG_CBUS_INT_1, stat);
1894 static void sii8620_irq_edid(struct sii8620 *ctx)
1896 u8 stat = sii8620_readb(ctx, REG_INTR9);
1898 sii8620_write(ctx, REG_INTR9, stat);
1900 if (stat & BIT_INTR9_DEVCAP_DONE)
1901 ctx->mt_state = MT_STATE_DONE;
1904 static void sii8620_scdt_high(struct sii8620 *ctx)
1906 sii8620_write_seq_static(ctx,
1907 REG_INTR8_MASK, BIT_CEA_NEW_AVI | BIT_CEA_NEW_VSI,
1908 REG_TPI_SC, BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI,
1912 static void sii8620_irq_scdt(struct sii8620 *ctx)
1914 u8 stat = sii8620_readb(ctx, REG_INTR5);
1916 if (stat & BIT_INTR_SCDT_CHANGE) {
1917 u8 cstat = sii8620_readb(ctx, REG_TMDS_CSTAT_P3);
1919 if (cstat & BIT_TMDS_CSTAT_P3_SCDT)
1920 sii8620_scdt_high(ctx);
1923 sii8620_write(ctx, REG_INTR5, stat);
1926 static void sii8620_new_vsi(struct sii8620 *ctx)
1930 sii8620_write(ctx, REG_RX_HDMI_CTRL2,
1931 VAL_RX_HDMI_CTRL2_DEFVAL |
1932 BIT_RX_HDMI_CTRL2_VSI_MON_SEL_VSI);
1933 sii8620_read_buf(ctx, REG_RX_HDMI_MON_PKT_HEADER1, vsif,
1937 static void sii8620_new_avi(struct sii8620 *ctx)
1939 sii8620_write(ctx, REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL);
1940 sii8620_read_buf(ctx, REG_RX_HDMI_MON_PKT_HEADER1, ctx->avif,
1941 ARRAY_SIZE(ctx->avif));
1944 static void sii8620_irq_infr(struct sii8620 *ctx)
1946 u8 stat = sii8620_readb(ctx, REG_INTR8)
1947 & (BIT_CEA_NEW_VSI | BIT_CEA_NEW_AVI);
1949 sii8620_write(ctx, REG_INTR8, stat);
1951 if (stat & BIT_CEA_NEW_VSI)
1952 sii8620_new_vsi(ctx);
1954 if (stat & BIT_CEA_NEW_AVI)
1955 sii8620_new_avi(ctx);
1957 if (stat & (BIT_CEA_NEW_VSI | BIT_CEA_NEW_AVI))
1958 sii8620_start_video(ctx);
1961 static void sii8620_got_xdevcap(struct sii8620 *ctx, int ret)
1966 sii8620_mt_read_devcap(ctx, false);
1969 static void sii8620_irq_tdm(struct sii8620 *ctx)
1971 u8 stat = sii8620_readb(ctx, REG_TRXINTH);
1972 u8 tdm = sii8620_readb(ctx, REG_TRXSTA2);
1974 if ((tdm & MSK_TDM_SYNCHRONIZED) == VAL_TDM_SYNCHRONIZED) {
1975 ctx->mode = CM_ECBUS_S;
1976 ctx->burst.rx_ack = 0;
1977 ctx->burst.r_size = SII8620_BURST_BUF_LEN;
1978 sii8620_burst_tx_rbuf_info(ctx, SII8620_BURST_BUF_LEN);
1979 sii8620_mt_read_devcap(ctx, true);
1980 sii8620_mt_set_cont(ctx, sii8620_got_xdevcap);
1982 sii8620_write_seq_static(ctx,
1983 REG_MHL_PLL_CTL2, 0,
1984 REG_MHL_PLL_CTL2, BIT_MHL_PLL_CTL2_CLKDETECT_EN
1988 sii8620_write(ctx, REG_TRXINTH, stat);
1991 static void sii8620_irq_block(struct sii8620 *ctx)
1993 u8 stat = sii8620_readb(ctx, REG_EMSCINTR);
1995 if (stat & BIT_EMSCINTR_SPI_DVLD) {
1996 u8 bstat = sii8620_readb(ctx, REG_SPIBURSTSTAT);
1998 if (bstat & BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE)
1999 sii8620_burst_receive(ctx);
2002 sii8620_write(ctx, REG_EMSCINTR, stat);
2005 static void sii8620_irq_ddc(struct sii8620 *ctx)
2007 u8 stat = sii8620_readb(ctx, REG_INTR3);
2009 if (stat & BIT_DDC_CMD_DONE) {
2010 sii8620_write(ctx, REG_INTR3_MASK, 0);
2011 if (sii8620_is_mhl3(ctx))
2012 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE),
2013 MHL_INT_RC_FEAT_REQ);
2015 sii8620_edid_read(ctx, 0);
2017 sii8620_write(ctx, REG_INTR3, stat);
2020 /* endian agnostic, non-volatile version of test_bit */
2021 static bool sii8620_test_bit(unsigned int nr, const u8 *addr)
2023 return 1 & (addr[nr / BITS_PER_BYTE] >> (nr % BITS_PER_BYTE));
2026 static irqreturn_t sii8620_irq_thread(int irq, void *data)
2028 static const struct {
2030 void (*handler)(struct sii8620 *ctx);
2032 { BIT_FAST_INTR_STAT_DISC, sii8620_irq_disc },
2033 { BIT_FAST_INTR_STAT_G2WB, sii8620_irq_g2wb },
2034 { BIT_FAST_INTR_STAT_COC, sii8620_irq_coc },
2035 { BIT_FAST_INTR_STAT_TDM, sii8620_irq_tdm },
2036 { BIT_FAST_INTR_STAT_MSC, sii8620_irq_msc },
2037 { BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr },
2038 { BIT_FAST_INTR_STAT_BLOCK, sii8620_irq_block },
2039 { BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid },
2040 { BIT_FAST_INTR_STAT_DDC, sii8620_irq_ddc },
2041 { BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt },
2042 { BIT_FAST_INTR_STAT_INFR, sii8620_irq_infr },
2044 struct sii8620 *ctx = data;
2045 u8 stats[LEN_FAST_INTR_STAT];
2048 mutex_lock(&ctx->lock);
2050 sii8620_read_buf(ctx, REG_FAST_INTR_STAT, stats, ARRAY_SIZE(stats));
2051 for (i = 0; i < ARRAY_SIZE(irq_vec); ++i)
2052 if (sii8620_test_bit(irq_vec[i].bit, stats))
2053 irq_vec[i].handler(ctx);
2055 sii8620_burst_rx_all(ctx);
2056 sii8620_mt_work(ctx);
2057 sii8620_burst_send(ctx);
2059 ret = sii8620_clear_error(ctx);
2061 dev_err(ctx->dev, "Error during IRQ handling, %d.\n", ret);
2062 sii8620_mhl_disconnected(ctx);
2064 mutex_unlock(&ctx->lock);
2069 static void sii8620_cable_in(struct sii8620 *ctx)
2071 struct device *dev = ctx->dev;
2075 ret = sii8620_hw_on(ctx);
2077 dev_err(dev, "Error powering on, %d.\n", ret);
2080 sii8620_hw_reset(ctx);
2082 sii8620_read_buf(ctx, REG_VND_IDL, ver, ARRAY_SIZE(ver));
2083 ret = sii8620_clear_error(ctx);
2085 dev_err(dev, "Error accessing I2C bus, %d.\n", ret);
2089 dev_info(dev, "ChipID %02x%02x:%02x%02x rev %02x.\n", ver[1], ver[0],
2090 ver[3], ver[2], ver[4]);
2092 sii8620_write(ctx, REG_DPD,
2093 BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN);
2095 sii8620_xtal_set_rate(ctx);
2096 sii8620_disconnect(ctx);
2098 sii8620_write_seq_static(ctx,
2099 REG_MHL_CBUS_CTL0, VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG
2100 | VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734,
2101 REG_MHL_CBUS_CTL1, VAL_MHL_CBUS_CTL1_1115_OHM,
2102 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN,
2105 ret = sii8620_clear_error(ctx);
2107 dev_err(dev, "Error accessing I2C bus, %d.\n", ret);
2111 enable_irq(to_i2c_client(ctx->dev)->irq);
2114 static inline struct sii8620 *bridge_to_sii8620(struct drm_bridge *bridge)
2116 return container_of(bridge, struct sii8620, bridge);
2119 static bool sii8620_mode_fixup(struct drm_bridge *bridge,
2120 const struct drm_display_mode *mode,
2121 struct drm_display_mode *adjusted_mode)
2123 struct sii8620 *ctx = bridge_to_sii8620(bridge);
2127 mutex_lock(&ctx->lock);
2129 max_lclk = sii8620_is_mhl3(ctx) ? MHL3_MAX_LCLK : MHL1_MAX_LCLK;
2130 if (max_lclk > 3 * adjusted_mode->clock) {
2131 ctx->use_packed_pixel = 0;
2134 if ((ctx->devcap[MHL_DCAP_VID_LINK_MODE] & MHL_DCAP_VID_LINK_PPIXEL) &&
2135 max_lclk > 2 * adjusted_mode->clock) {
2136 ctx->use_packed_pixel = 1;
2142 u8 vic = drm_match_cea_mode(adjusted_mode);
2145 union hdmi_infoframe frm;
2146 u8 mhl_vic[] = { 0, 95, 94, 93, 98 };
2148 drm_hdmi_vendor_infoframe_from_display_mode(
2149 &frm.vendor.hdmi, adjusted_mode);
2150 vic = frm.vendor.hdmi.vic;
2151 if (vic >= ARRAY_SIZE(mhl_vic))
2155 ctx->video_code = vic;
2156 ctx->pixel_clock = adjusted_mode->clock;
2158 mutex_unlock(&ctx->lock);
2162 static const struct drm_bridge_funcs sii8620_bridge_funcs = {
2163 .mode_fixup = sii8620_mode_fixup,
2166 static int sii8620_probe(struct i2c_client *client,
2167 const struct i2c_device_id *id)
2169 struct device *dev = &client->dev;
2170 struct sii8620 *ctx;
2173 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
2178 mutex_init(&ctx->lock);
2179 INIT_LIST_HEAD(&ctx->mt_queue);
2181 ctx->clk_xtal = devm_clk_get(dev, "xtal");
2182 if (IS_ERR(ctx->clk_xtal)) {
2183 dev_err(dev, "failed to get xtal clock from DT\n");
2184 return PTR_ERR(ctx->clk_xtal);
2188 dev_err(dev, "no irq provided\n");
2191 irq_set_status_flags(client->irq, IRQ_NOAUTOEN);
2192 ret = devm_request_threaded_irq(dev, client->irq, NULL,
2194 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
2197 dev_err(dev, "failed to install IRQ handler\n");
2201 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
2202 if (IS_ERR(ctx->gpio_reset)) {
2203 dev_err(dev, "failed to get reset gpio from DT\n");
2204 return PTR_ERR(ctx->gpio_reset);
2207 ctx->supplies[0].supply = "cvcc10";
2208 ctx->supplies[1].supply = "iovcc18";
2209 ret = devm_regulator_bulk_get(dev, 2, ctx->supplies);
2213 i2c_set_clientdata(client, ctx);
2215 ctx->bridge.funcs = &sii8620_bridge_funcs;
2216 ctx->bridge.of_node = dev->of_node;
2217 drm_bridge_add(&ctx->bridge);
2219 sii8620_cable_in(ctx);
2224 static int sii8620_remove(struct i2c_client *client)
2226 struct sii8620 *ctx = i2c_get_clientdata(client);
2228 disable_irq(to_i2c_client(ctx->dev)->irq);
2229 drm_bridge_remove(&ctx->bridge);
2230 sii8620_hw_off(ctx);
2235 static const struct of_device_id sii8620_dt_match[] = {
2236 { .compatible = "sil,sii8620" },
2239 MODULE_DEVICE_TABLE(of, sii8620_dt_match);
2241 static const struct i2c_device_id sii8620_id[] = {
2246 MODULE_DEVICE_TABLE(i2c, sii8620_id);
2247 static struct i2c_driver sii8620_driver = {
2250 .of_match_table = of_match_ptr(sii8620_dt_match),
2252 .probe = sii8620_probe,
2253 .remove = sii8620_remove,
2254 .id_table = sii8620_id,
2257 module_i2c_driver(sii8620_driver);
2258 MODULE_LICENSE("GPL v2");