drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Cadence MHDP8546 DP bridge driver.
   4  *
   5  * Copyright (C) 2020 Cadence Design Systems, Inc.
   6  *
   7  * Author: Quentin Schulz <quentin.schulz@free-electrons.com>
   8  *         Swapnil Jakhade <sjakhade@cadence.com>
   9  */
  10
  11 #ifndef CDNS_MHDP8546_CORE_H
  12 #define CDNS_MHDP8546_CORE_H
  13
  14 #include <linux/bits.h>
  15 #include <linux/mutex.h>
  16 #include <linux/spinlock.h>
  17
  18 #include <drm/drm_bridge.h>
  19 #include <drm/drm_connector.h>
  20 #include <drm/drm_dp_helper.h>
  21
  22 struct clk;
  23 struct device;
  24 struct phy;
  25
  26 /* Register offsets */
  27 #define CDNS_APB_CTRL                           0x00000
  28 #define CDNS_CPU_STALL                          BIT(3)
  29
  30 #define CDNS_MAILBOX_FULL                       0x00008
  31 #define CDNS_MAILBOX_EMPTY                      0x0000c
  32 #define CDNS_MAILBOX_TX_DATA                    0x00010
  33 #define CDNS_MAILBOX_RX_DATA                    0x00014
  34 #define CDNS_KEEP_ALIVE                         0x00018
  35 #define CDNS_KEEP_ALIVE_MASK                    GENMASK(7, 0)
  36
  37 #define CDNS_VER_L                              0x0001C
  38 #define CDNS_VER_H                              0x00020
  39 #define CDNS_LIB_L_ADDR                         0x00024
  40 #define CDNS_LIB_H_ADDR                         0x00028
  41
  42 #define CDNS_MB_INT_MASK                        0x00034
  43 #define CDNS_MB_INT_STATUS                      0x00038
  44
  45 #define CDNS_SW_CLK_L                           0x0003c
  46 #define CDNS_SW_CLK_H                           0x00040
  47
  48 #define CDNS_SW_EVENT0                          0x00044
  49 #define CDNS_DPTX_HPD                           BIT(0)
  50
  51 #define CDNS_SW_EVENT1                          0x00048
  52 #define CDNS_SW_EVENT2                          0x0004c
  53 #define CDNS_SW_EVENT3                          0x00050
  54
  55 #define CDNS_APB_INT_MASK                       0x0006C
  56 #define CDNS_APB_INT_MASK_MAILBOX_INT           BIT(0)
  57 #define CDNS_APB_INT_MASK_SW_EVENT_INT          BIT(1)
  58
  59 #define CDNS_APB_INT_STATUS                     0x00070
  60
  61 #define CDNS_DPTX_CAR                           0x00904
  62 #define CDNS_VIF_CLK_EN                         BIT(0)
  63 #define CDNS_VIF_CLK_RSTN                       BIT(1)
  64
  65 #define CDNS_SOURCE_VIDEO_IF(s)                 (0x00b00 + ((s) * 0x20))
  66 #define CDNS_BND_HSYNC2VSYNC(s)                 (CDNS_SOURCE_VIDEO_IF(s) + \
  67                                                  0x00)
  68 #define CDNS_IP_DTCT_WIN                        GENMASK(11, 0)
  69 #define CDNS_IP_DET_INTERLACE_FORMAT            BIT(12)
  70 #define CDNS_IP_BYPASS_V_INTERFACE              BIT(13)
  71
  72 #define CDNS_HSYNC2VSYNC_POL_CTRL(s)            (CDNS_SOURCE_VIDEO_IF(s) + \
  73                                                  0x10)
  74 #define CDNS_H2V_HSYNC_POL_ACTIVE_LOW           BIT(1)
  75 #define CDNS_H2V_VSYNC_POL_ACTIVE_LOW           BIT(2)
  76
  77 #define CDNS_DPTX_PHY_CONFIG                    0x02000
  78 #define CDNS_PHY_TRAINING_EN                    BIT(0)
  79 #define CDNS_PHY_TRAINING_TYPE(x)               (((x) & GENMASK(3, 0)) << 1)
  80 #define CDNS_PHY_SCRAMBLER_BYPASS               BIT(5)
  81 #define CDNS_PHY_ENCODER_BYPASS                 BIT(6)
  82 #define CDNS_PHY_SKEW_BYPASS                    BIT(7)
  83 #define CDNS_PHY_TRAINING_AUTO                  BIT(8)
  84 #define CDNS_PHY_LANE0_SKEW(x)                  (((x) & GENMASK(2, 0)) << 9)
  85 #define CDNS_PHY_LANE1_SKEW(x)                  (((x) & GENMASK(2, 0)) << 12)
  86 #define CDNS_PHY_LANE2_SKEW(x)                  (((x) & GENMASK(2, 0)) << 15)
  87 #define CDNS_PHY_LANE3_SKEW(x)                  (((x) & GENMASK(2, 0)) << 18)
  88 #define CDNS_PHY_COMMON_CONFIG                  (CDNS_PHY_LANE1_SKEW(1) | \
  89                                                 CDNS_PHY_LANE2_SKEW(2) |  \
  90                                                 CDNS_PHY_LANE3_SKEW(3))
  91 #define CDNS_PHY_10BIT_EN                       BIT(21)
  92
  93 #define CDNS_DP_FRAMER_GLOBAL_CONFIG            0x02200
  94 #define CDNS_DP_NUM_LANES(x)                    ((x) - 1)
  95 #define CDNS_DP_MST_EN                          BIT(2)
  96 #define CDNS_DP_FRAMER_EN                       BIT(3)
  97 #define CDNS_DP_RATE_GOVERNOR_EN                BIT(4)
  98 #define CDNS_DP_NO_VIDEO_MODE                   BIT(5)
  99 #define CDNS_DP_DISABLE_PHY_RST                 BIT(6)
 100 #define CDNS_DP_WR_FAILING_EDGE_VSYNC           BIT(7)
 101
 102 #define CDNS_DP_FRAMER_TU                       0x02208
 103 #define CDNS_DP_FRAMER_TU_SIZE(x)               (((x) & GENMASK(6, 0)) << 8)
 104 #define CDNS_DP_FRAMER_TU_VS(x)                 ((x) & GENMASK(5, 0))
 105 #define CDNS_DP_FRAMER_TU_CNT_RST_EN            BIT(15)
 106
 107 #define CDNS_DP_MTPH_CONTROL                    0x02264
 108 #define CDNS_DP_MTPH_ECF_EN                     BIT(0)
 109 #define CDNS_DP_MTPH_ACT_EN                     BIT(1)
 110 #define CDNS_DP_MTPH_LVP_EN                     BIT(2)
 111
 112 #define CDNS_DP_MTPH_STATUS                     0x0226C
 113 #define CDNS_DP_MTPH_ACT_STATUS                 BIT(0)
 114
 115 #define CDNS_DP_LANE_EN                         0x02300
 116 #define CDNS_DP_LANE_EN_LANES(x)                GENMASK((x) - 1, 0)
 117
 118 #define CDNS_DP_ENHNCD                          0x02304
 119
 120 #define CDNS_DPTX_STREAM(s)                     (0x03000 + (s) * 0x80)
 121 #define CDNS_DP_MSA_HORIZONTAL_0(s)             (CDNS_DPTX_STREAM(s) + 0x00)
 122 #define CDNS_DP_MSAH0_H_TOTAL(x)                (x)
 123 #define CDNS_DP_MSAH0_HSYNC_START(x)            ((x) << 16)
 124
 125 #define CDNS_DP_MSA_HORIZONTAL_1(s)             (CDNS_DPTX_STREAM(s) + 0x04)
 126 #define CDNS_DP_MSAH1_HSYNC_WIDTH(x)            (x)
 127 #define CDNS_DP_MSAH1_HSYNC_POL_LOW             BIT(15)
 128 #define CDNS_DP_MSAH1_HDISP_WIDTH(x)            ((x) << 16)
 129
 130 #define CDNS_DP_MSA_VERTICAL_0(s)               (CDNS_DPTX_STREAM(s) + 0x08)
 131 #define CDNS_DP_MSAV0_V_TOTAL(x)                (x)
 132 #define CDNS_DP_MSAV0_VSYNC_START(x)            ((x) << 16)
 133
 134 #define CDNS_DP_MSA_VERTICAL_1(s)               (CDNS_DPTX_STREAM(s) + 0x0c)
 135 #define CDNS_DP_MSAV1_VSYNC_WIDTH(x)            (x)
 136 #define CDNS_DP_MSAV1_VSYNC_POL_LOW             BIT(15)
 137 #define CDNS_DP_MSAV1_VDISP_WIDTH(x)            ((x) << 16)
 138
 139 #define CDNS_DP_MSA_MISC(s)                     (CDNS_DPTX_STREAM(s) + 0x10)
 140 #define CDNS_DP_STREAM_CONFIG(s)                (CDNS_DPTX_STREAM(s) + 0x14)
 141 #define CDNS_DP_STREAM_CONFIG_2(s)              (CDNS_DPTX_STREAM(s) + 0x2c)
 142 #define CDNS_DP_SC2_TU_VS_DIFF(x)               ((x) << 8)
 143
 144 #define CDNS_DP_HORIZONTAL(s)                   (CDNS_DPTX_STREAM(s) + 0x30)
 145 #define CDNS_DP_H_HSYNC_WIDTH(x)                (x)
 146 #define CDNS_DP_H_H_TOTAL(x)                    ((x) << 16)
 147
 148 #define CDNS_DP_VERTICAL_0(s)                   (CDNS_DPTX_STREAM(s) + 0x34)
 149 #define CDNS_DP_V0_VHEIGHT(x)                   (x)
 150 #define CDNS_DP_V0_VSTART(x)                    ((x) << 16)
 151
 152 #define CDNS_DP_VERTICAL_1(s)                   (CDNS_DPTX_STREAM(s) + 0x38)
 153 #define CDNS_DP_V1_VTOTAL(x)                    (x)
 154 #define CDNS_DP_V1_VTOTAL_EVEN                  BIT(16)
 155
 156 #define CDNS_DP_MST_SLOT_ALLOCATE(s)            (CDNS_DPTX_STREAM(s) + 0x44)
 157 #define CDNS_DP_S_ALLOC_START_SLOT(x)           (x)
 158 #define CDNS_DP_S_ALLOC_END_SLOT(x)             ((x) << 8)
 159
 160 #define CDNS_DP_RATE_GOVERNING(s)               (CDNS_DPTX_STREAM(s) + 0x48)
 161 #define CDNS_DP_RG_TARG_AV_SLOTS_Y(x)           (x)
 162 #define CDNS_DP_RG_TARG_AV_SLOTS_X(x)           ((x) << 4)
 163 #define CDNS_DP_RG_ENABLE                       BIT(10)
 164
 165 #define CDNS_DP_FRAMER_PXL_REPR(s)              (CDNS_DPTX_STREAM(s) + 0x4c)
 166 #define CDNS_DP_FRAMER_6_BPC                    BIT(0)
 167 #define CDNS_DP_FRAMER_8_BPC                    BIT(1)
 168 #define CDNS_DP_FRAMER_10_BPC                   BIT(2)
 169 #define CDNS_DP_FRAMER_12_BPC                   BIT(3)
 170 #define CDNS_DP_FRAMER_16_BPC                   BIT(4)
 171 #define CDNS_DP_FRAMER_PXL_FORMAT               0x8
 172 #define CDNS_DP_FRAMER_RGB                      BIT(0)
 173 #define CDNS_DP_FRAMER_YCBCR444                 BIT(1)
 174 #define CDNS_DP_FRAMER_YCBCR422                 BIT(2)
 175 #define CDNS_DP_FRAMER_YCBCR420                 BIT(3)
 176 #define CDNS_DP_FRAMER_Y_ONLY                   BIT(4)
 177
 178 #define CDNS_DP_FRAMER_SP(s)                    (CDNS_DPTX_STREAM(s) + 0x50)
 179 #define CDNS_DP_FRAMER_VSYNC_POL_LOW            BIT(0)
 180 #define CDNS_DP_FRAMER_HSYNC_POL_LOW            BIT(1)
 181 #define CDNS_DP_FRAMER_INTERLACE                BIT(2)
 182
 183 #define CDNS_DP_LINE_THRESH(s)                  (CDNS_DPTX_STREAM(s) + 0x64)
 184 #define CDNS_DP_ACTIVE_LINE_THRESH(x)           (x)
 185
 186 #define CDNS_DP_VB_ID(s)                        (CDNS_DPTX_STREAM(s) + 0x68)
 187 #define CDNS_DP_VB_ID_INTERLACED                BIT(2)
 188 #define CDNS_DP_VB_ID_COMPRESSED                BIT(6)
 189
 190 #define CDNS_DP_FRONT_BACK_PORCH(s)             (CDNS_DPTX_STREAM(s) + 0x78)
 191 #define CDNS_DP_BACK_PORCH(x)                   (x)
 192 #define CDNS_DP_FRONT_PORCH(x)                  ((x) << 16)
 193
 194 #define CDNS_DP_BYTE_COUNT(s)                   (CDNS_DPTX_STREAM(s) + 0x7c)
 195 #define CDNS_DP_BYTE_COUNT_BYTES_IN_CHUNK_SHIFT 16
 196
 197 /* mailbox */
 198 #define MAILBOX_RETRY_US                        1000
 199 #define MAILBOX_TIMEOUT_US                      2000000
 200
 201 #define MB_OPCODE_ID                            0
 202 #define MB_MODULE_ID                            1
 203 #define MB_SIZE_MSB_ID                          2
 204 #define MB_SIZE_LSB_ID                          3
 205 #define MB_DATA_ID                              4
 206
 207 #define MB_MODULE_ID_DP_TX                      0x01
 208 #define MB_MODULE_ID_HDCP_TX                    0x07
 209 #define MB_MODULE_ID_HDCP_RX                    0x08
 210 #define MB_MODULE_ID_HDCP_GENERAL               0x09
 211 #define MB_MODULE_ID_GENERAL                    0x0a
 212
 213 /* firmware and opcodes */
 214 #define FW_NAME                                 "/*(DEBLOBBED)*/"
 215 #define CDNS_MHDP_IMEM                          0x10000
 216
 217 #define GENERAL_MAIN_CONTROL                    0x01
 218 #define GENERAL_TEST_ECHO                       0x02
 219 #define GENERAL_BUS_SETTINGS                    0x03
 220 #define GENERAL_TEST_ACCESS                     0x04
 221 #define GENERAL_REGISTER_READ                   0x07
 222
 223 #define DPTX_SET_POWER_MNG                      0x00
 224 #define DPTX_GET_EDID                           0x02
 225 #define DPTX_READ_DPCD                          0x03
 226 #define DPTX_WRITE_DPCD                         0x04
 227 #define DPTX_ENABLE_EVENT                       0x05
 228 #define DPTX_WRITE_REGISTER                     0x06
 229 #define DPTX_READ_REGISTER                      0x07
 230 #define DPTX_WRITE_FIELD                        0x08
 231 #define DPTX_READ_EVENT                         0x0a
 232 #define DPTX_GET_LAST_AUX_STAUS                 0x0e
 233 #define DPTX_HPD_STATE                          0x11
 234 #define DPTX_ADJUST_LT                          0x12
 235
 236 #define FW_STANDBY                              0
 237 #define FW_ACTIVE                               1
 238
 239 /* HPD */
 240 #define DPTX_READ_EVENT_HPD_TO_HIGH             BIT(0)
 241 #define DPTX_READ_EVENT_HPD_TO_LOW              BIT(1)
 242 #define DPTX_READ_EVENT_HPD_PULSE               BIT(2)
 243 #define DPTX_READ_EVENT_HPD_STATE               BIT(3)
 244
 245 /* general */
 246 #define CDNS_DP_TRAINING_PATTERN_4              0x7
 247
 248 #define CDNS_KEEP_ALIVE_TIMEOUT                 2000
 249
 250 #define CDNS_VOLT_SWING(x)                      ((x) & GENMASK(1, 0))
 251 #define CDNS_FORCE_VOLT_SWING                   BIT(2)
 252
 253 #define CDNS_PRE_EMPHASIS(x)                    ((x) & GENMASK(1, 0))
 254 #define CDNS_FORCE_PRE_EMPHASIS                 BIT(2)
 255
 256 #define CDNS_SUPPORT_TPS(x)                     BIT((x) - 1)
 257
 258 #define CDNS_FAST_LINK_TRAINING                 BIT(0)
 259
 260 #define CDNS_LANE_MAPPING_TYPE_C_LANE_0(x)      ((x) & GENMASK(1, 0))
 261 #define CDNS_LANE_MAPPING_TYPE_C_LANE_1(x)      ((x) & GENMASK(3, 2))
 262 #define CDNS_LANE_MAPPING_TYPE_C_LANE_2(x)      ((x) & GENMASK(5, 4))
 263 #define CDNS_LANE_MAPPING_TYPE_C_LANE_3(x)      ((x) & GENMASK(7, 6))
 264 #define CDNS_LANE_MAPPING_NORMAL                0xe4
 265 #define CDNS_LANE_MAPPING_FLIPPED               0x1b
 266
 267 #define CDNS_DP_MAX_NUM_LANES                   4
 268 #define CDNS_DP_TEST_VSC_SDP                    BIT(6) /* 1.3+ */
 269 #define CDNS_DP_TEST_COLOR_FORMAT_RAW_Y_ONLY    BIT(7)
 270
 271 #define CDNS_MHDP_MAX_STREAMS                   4
 272
 273 #define DP_LINK_CAP_ENHANCED_FRAMING            BIT(0)
 274
 275 struct cdns_mhdp_link {
 276         unsigned char revision;
 277         unsigned int rate;
 278         unsigned int num_lanes;
 279         unsigned long capabilities;
 280 };
 281
 282 struct cdns_mhdp_host {
 283         unsigned int link_rate;
 284         u8 lanes_cnt;
 285         u8 volt_swing;
 286         u8 pre_emphasis;
 287         u8 pattern_supp;
 288         u8 lane_mapping;
 289         bool fast_link;
 290         bool enhanced;
 291         bool scrambler;
 292         bool ssc;
 293 };
 294
 295 struct cdns_mhdp_sink {
 296         unsigned int link_rate;
 297         u8 lanes_cnt;
 298         u8 pattern_supp;
 299         bool fast_link;
 300         bool enhanced;
 301         bool ssc;
 302 };
 303
 304 struct cdns_mhdp_display_fmt {
 305         u32 color_format;
 306         u32 bpc;
 307         bool y_only;
 308 };
 309
 310 /*
 311  * These enums present MHDP hw initialization state
 312  * Legal state transitions are:
 313  * MHDP_HW_READY <-> MHDP_HW_STOPPED
 314  */
 315 enum mhdp_hw_state {
 316         MHDP_HW_READY = 1,      /* HW ready, FW active */
 317         MHDP_HW_STOPPED         /* Driver removal FW to be stopped */
 318 };
 319
 320 struct cdns_mhdp_device;
 321
 322 struct mhdp_platform_ops {
 323         int (*init)(struct cdns_mhdp_device *mhdp);
 324         void (*exit)(struct cdns_mhdp_device *mhdp);
 325         void (*enable)(struct cdns_mhdp_device *mhdp);
 326         void (*disable)(struct cdns_mhdp_device *mhdp);
 327 };
 328
 329 struct cdns_mhdp_bridge_state {
 330         struct drm_bridge_state base;
 331         struct drm_display_mode *current_mode;
 332 };
 333
 334 struct cdns_mhdp_platform_info {
 335         const struct drm_bridge_timings *timings;
 336         const struct mhdp_platform_ops *ops;
 337 };
 338
 339 #define to_cdns_mhdp_bridge_state(s) \
 340                 container_of(s, struct cdns_mhdp_bridge_state, base)
 341
 342 struct cdns_mhdp_device {
 343         void __iomem *regs;
 344         void __iomem *j721e_regs;
 345
 346         struct device *dev;
 347         struct clk *clk;
 348         struct phy *phy;
 349
 350         const struct cdns_mhdp_platform_info *info;
 351
 352         /* This is to protect mailbox communications with the firmware */
 353         struct mutex mbox_mutex;
 354
 355         /*
 356          * "link_mutex" protects the access to all the link parameters
 357          * including the link training process. Link training will be
 358          * invoked both from threaded interrupt handler and from atomic
 359          * callbacks when link_up is not set. So this mutex protects
 360          * flags such as link_up, bridge_enabled, link.num_lanes,
 361          * link.rate etc.
 362          */
 363         struct mutex link_mutex;
 364
 365         struct drm_connector connector;
 366         struct drm_bridge bridge;
 367
 368         struct cdns_mhdp_link link;
 369         struct drm_dp_aux aux;
 370
 371         struct cdns_mhdp_host host;
 372         struct cdns_mhdp_sink sink;
 373         struct cdns_mhdp_display_fmt display_fmt;
 374         u8 stream_id;
 375
 376         bool link_up;
 377         bool plugged;
 378
 379         /*
 380          * "start_lock" protects the access to bridge_attached and
 381          * hw_state data members that control the delayed firmware
 382          * loading and attaching the bridge. They are accessed from
 383          * both the DRM core and cdns_mhdp_fw_cb(). In most cases just
 384          * protecting the data members is enough, but the irq mask
 385          * setting needs to be protected when enabling the FW.
 386          */
 387         spinlock_t start_lock;
 388         bool bridge_attached;
 389         bool bridge_enabled;
 390         enum mhdp_hw_state hw_state;
 391         wait_queue_head_t fw_load_wq;
 392
 393         /* Work struct to schedule a uevent on link train failure */
 394         struct work_struct modeset_retry_work;
 395 };
 396
 397 #define connector_to_mhdp(x) container_of(x, struct cdns_mhdp_device, connector)
 398 #define bridge_to_mhdp(x) container_of(x, struct cdns_mhdp_device, bridge)
 399
 400 #endif