2 * Analogix DP (Display Port) core interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
18 #include <linux/iopoll.h>
19 #include <linux/interrupt.h>
21 #include <linux/of_gpio.h>
22 #include <linux/gpio.h>
23 #include <linux/component.h>
24 #include <linux/phy/phy.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_crtc_helper.h>
30 #include <drm/drm_panel.h>
32 #include <drm/bridge/analogix_dp.h>
34 #include "analogix_dp_core.h"
35 #include "analogix_dp_reg.h"
37 #define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
39 static const bool verify_fast_training;
42 struct i2c_client *client;
43 struct device_node *node;
46 static int analogix_dp_init_dp(struct analogix_dp_device *dp)
50 analogix_dp_reset(dp);
52 analogix_dp_swreset(dp);
54 analogix_dp_init_analog_param(dp);
55 analogix_dp_init_interrupt(dp);
57 /* SW defined function Normal operation */
58 analogix_dp_enable_sw_function(dp);
60 analogix_dp_config_interrupt(dp);
61 ret = analogix_dp_init_analog_func(dp);
65 analogix_dp_init_hpd(dp);
66 analogix_dp_init_aux(dp);
70 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
74 while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
75 if (analogix_dp_get_plug_in_status(dp) == 0)
79 usleep_range(1000, 1100);
83 * Some edp screen do not have hpd signal, so we can't just
84 * return failed when hpd plug in detect failed, DT property
85 * "force-hpd" would indicate whether driver need this.
91 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
92 * will not work, so we need to give a force hpd action to
93 * set HPD_STATUS manually.
95 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
97 analogix_dp_force_hpd(dp);
99 if (analogix_dp_get_plug_in_status(dp) != 0) {
100 dev_err(dp->dev, "failed to get hpd plug in status\n");
104 dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
109 int analogix_dp_psr_enabled(struct analogix_dp_device *dp)
112 return dp->psr_enable;
114 EXPORT_SYMBOL_GPL(analogix_dp_psr_enabled);
116 int analogix_dp_enable_psr(struct analogix_dp_device *dp)
118 struct edp_vsc_psr psr_vsc;
123 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
124 memset(&psr_vsc, 0, sizeof(psr_vsc));
125 psr_vsc.sdp_header.HB0 = 0;
126 psr_vsc.sdp_header.HB1 = 0x7;
127 psr_vsc.sdp_header.HB2 = 0x2;
128 psr_vsc.sdp_header.HB3 = 0x8;
131 psr_vsc.DB1 = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
133 return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
135 EXPORT_SYMBOL_GPL(analogix_dp_enable_psr);
137 int analogix_dp_disable_psr(struct analogix_dp_device *dp)
139 struct edp_vsc_psr psr_vsc;
145 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
146 memset(&psr_vsc, 0, sizeof(psr_vsc));
147 psr_vsc.sdp_header.HB0 = 0;
148 psr_vsc.sdp_header.HB1 = 0x7;
149 psr_vsc.sdp_header.HB2 = 0x2;
150 psr_vsc.sdp_header.HB3 = 0x8;
155 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
157 dev_err(dp->dev, "Failed to set DP Power0 %d\n", ret);
161 return analogix_dp_send_psr_spd(dp, &psr_vsc, false);
163 EXPORT_SYMBOL_GPL(analogix_dp_disable_psr);
165 static int analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
167 unsigned char psr_version;
170 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
172 dev_err(dp->dev, "failed to get PSR version, disable it\n");
176 dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
178 dp->psr_enable = (psr_version & DP_PSR_IS_SUPPORTED) ? true : false;
183 static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
185 unsigned char psr_en;
188 /* Disable psr function */
189 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
191 dev_err(dp->dev, "failed to get psr config\n");
195 psr_en &= ~DP_PSR_ENABLE;
196 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
198 dev_err(dp->dev, "failed to disable panel psr\n");
202 /* Main-Link transmitter remains active during PSR active states */
203 psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION;
204 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
206 dev_err(dp->dev, "failed to set panel psr\n");
210 /* Enable psr function */
211 psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE |
212 DP_PSR_CRC_VERIFICATION;
213 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
215 dev_err(dp->dev, "failed to set panel psr\n");
219 analogix_dp_enable_psr_crc(dp);
223 dev_err(dp->dev, "enable psr fail, force to disable psr\n");
224 dp->psr_enable = false;
230 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
236 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
241 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
242 DP_LANE_COUNT_ENHANCED_FRAME_EN |
243 DPCD_LANE_COUNT_SET(data));
245 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
246 DPCD_LANE_COUNT_SET(data));
248 return ret < 0 ? ret : 0;
251 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp,
252 u8 *enhanced_mode_support)
257 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
259 *enhanced_mode_support = 0;
263 *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
268 static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
273 ret = analogix_dp_is_enhanced_mode_available(dp, &data);
277 ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
281 analogix_dp_enable_enhanced_mode(dp, data);
286 static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
290 analogix_dp_set_training_pattern(dp, DP_NONE);
292 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
293 DP_TRAINING_PATTERN_DISABLE);
295 return ret < 0 ? ret : 0;
299 analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
300 int pre_emphasis, int lane)
304 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
307 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
311 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
315 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
320 static int analogix_dp_link_start(struct analogix_dp_device *dp)
323 int lane, lane_count, pll_tries, retval;
325 lane_count = dp->link_train.lane_count;
327 dp->link_train.lt_state = CLOCK_RECOVERY;
328 dp->link_train.eq_loop = 0;
330 for (lane = 0; lane < lane_count; lane++)
331 dp->link_train.cr_loop[lane] = 0;
333 /* Set link rate and count as you want to establish*/
334 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
335 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
337 /* Setup RX configuration */
338 buf[0] = dp->link_train.link_rate;
339 buf[1] = dp->link_train.lane_count;
340 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
343 /* set enhanced mode if available */
344 retval = analogix_dp_set_enhanced_mode(dp);
346 dev_err(dp->dev, "failed to set enhance mode\n");
350 /* Set TX pre-emphasis to minimum */
351 for (lane = 0; lane < lane_count; lane++)
352 analogix_dp_set_lane_lane_pre_emphasis(dp,
353 PRE_EMPHASIS_LEVEL_0, lane);
355 /* Wait for PLL lock */
357 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
358 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
359 dev_err(dp->dev, "Wait for PLL lock timed out\n");
364 usleep_range(90, 120);
367 /* Set training pattern 1 */
368 analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
370 /* Set RX training pattern */
371 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
372 DP_LINK_SCRAMBLING_DISABLE |
373 DP_TRAINING_PATTERN_1);
377 for (lane = 0; lane < lane_count; lane++)
378 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
379 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
381 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
389 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
391 int shift = (lane & 1) * 4;
392 u8 link_value = link_status[lane >> 1];
394 return (link_value >> shift) & 0xf;
397 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
402 for (lane = 0; lane < lane_count; lane++) {
403 lane_status = analogix_dp_get_lane_status(link_status, lane);
404 if ((lane_status & DP_LANE_CR_DONE) == 0)
410 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
416 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
419 for (lane = 0; lane < lane_count; lane++) {
420 lane_status = analogix_dp_get_lane_status(link_status, lane);
421 lane_status &= DP_CHANNEL_EQ_BITS;
422 if (lane_status != DP_CHANNEL_EQ_BITS)
430 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
432 int shift = (lane & 1) * 4;
433 u8 link_value = adjust_request[lane >> 1];
435 return (link_value >> shift) & 0x3;
438 static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
439 u8 adjust_request[2],
442 int shift = (lane & 1) * 4;
443 u8 link_value = adjust_request[lane >> 1];
445 return ((link_value >> shift) & 0xc) >> 2;
448 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
449 u8 training_lane_set, int lane)
453 analogix_dp_set_lane0_link_training(dp, training_lane_set);
456 analogix_dp_set_lane1_link_training(dp, training_lane_set);
460 analogix_dp_set_lane2_link_training(dp, training_lane_set);
464 analogix_dp_set_lane3_link_training(dp, training_lane_set);
470 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
477 reg = analogix_dp_get_lane0_link_training(dp);
480 reg = analogix_dp_get_lane1_link_training(dp);
483 reg = analogix_dp_get_lane2_link_training(dp);
486 reg = analogix_dp_get_lane3_link_training(dp);
496 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
498 analogix_dp_training_pattern_dis(dp);
499 analogix_dp_set_enhanced_mode(dp);
501 dp->link_train.lt_state = FAILED;
504 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
505 u8 adjust_request[2])
507 int lane, lane_count;
508 u8 voltage_swing, pre_emphasis, training_lane;
510 lane_count = dp->link_train.lane_count;
511 for (lane = 0; lane < lane_count; lane++) {
512 voltage_swing = analogix_dp_get_adjust_request_voltage(
513 adjust_request, lane);
514 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
515 adjust_request, lane);
516 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
517 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
519 if (voltage_swing == VOLTAGE_LEVEL_3)
520 training_lane |= DP_TRAIN_MAX_SWING_REACHED;
521 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
522 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
524 dp->link_train.training_lane[lane] = training_lane;
528 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
530 int lane, lane_count, retval;
531 u8 voltage_swing, pre_emphasis, training_lane;
532 u8 link_status[2], adjust_request[2];
534 usleep_range(100, 101);
536 lane_count = dp->link_train.lane_count;
538 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
542 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
547 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
548 /* set training pattern 2 for EQ */
549 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
551 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
552 DP_LINK_SCRAMBLING_DISABLE |
553 DP_TRAINING_PATTERN_2);
557 dev_info(dp->dev, "Link Training Clock Recovery success\n");
558 dp->link_train.lt_state = EQUALIZER_TRAINING;
560 for (lane = 0; lane < lane_count; lane++) {
561 training_lane = analogix_dp_get_lane_link_training(
563 voltage_swing = analogix_dp_get_adjust_request_voltage(
564 adjust_request, lane);
565 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
566 adjust_request, lane);
568 if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
570 DPCD_PRE_EMPHASIS_GET(training_lane) ==
572 dp->link_train.cr_loop[lane]++;
574 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
575 voltage_swing == VOLTAGE_LEVEL_3 ||
576 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
577 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
578 dp->link_train.cr_loop[lane],
579 voltage_swing, pre_emphasis);
580 analogix_dp_reduce_link_rate(dp);
586 analogix_dp_get_adjust_training_lane(dp, adjust_request);
588 for (lane = 0; lane < lane_count; lane++)
589 analogix_dp_set_lane_link_training(dp,
590 dp->link_train.training_lane[lane], lane);
592 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
593 dp->link_train.training_lane, lane_count);
600 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
602 int lane, lane_count, retval;
604 u8 link_align, link_status[2], adjust_request[2];
606 usleep_range(400, 401);
608 lane_count = dp->link_train.lane_count;
610 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
614 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
615 analogix_dp_reduce_link_rate(dp);
619 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
624 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
629 analogix_dp_get_adjust_training_lane(dp, adjust_request);
631 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
632 /* traing pattern Set to Normal */
633 retval = analogix_dp_training_pattern_dis(dp);
637 dev_info(dp->dev, "Link Training success!\n");
638 analogix_dp_get_link_bandwidth(dp, ®);
639 dp->link_train.link_rate = reg;
640 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
641 dp->link_train.link_rate);
643 analogix_dp_get_lane_count(dp, ®);
644 dp->link_train.lane_count = reg;
645 dev_dbg(dp->dev, "final lane count = %.2x\n",
646 dp->link_train.lane_count);
648 dp->link_train.lt_state = FINISHED;
654 dp->link_train.eq_loop++;
656 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
657 dev_err(dp->dev, "EQ Max loop\n");
658 analogix_dp_reduce_link_rate(dp);
662 for (lane = 0; lane < lane_count; lane++)
663 analogix_dp_set_lane_link_training(dp,
664 dp->link_train.training_lane[lane], lane);
666 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
667 dp->link_train.training_lane, lane_count);
674 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
680 * For DP rev.1.1, Maximum link rate of Main Link lanes
681 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
682 * For DP rev.1.2, Maximum link rate of Main Link lanes
683 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
685 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
689 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
695 * For DP rev.1.1, Maximum number of Main Link lanes
696 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
698 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
699 *lane_count = DPCD_MAX_LANE_COUNT(data);
702 static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
703 u32 max_lanes, u32 max_rate)
706 bool training_finished = false;
709 * MACRO_RST must be applied after the PLL_LOCK to avoid
710 * the DP inter pair skew issue for at least 10 us
712 analogix_dp_reset_macro(dp);
714 /* Initialize by reading RX's DPCD */
715 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
716 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
718 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
719 (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
720 (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
721 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
722 dp->link_train.link_rate);
723 dp->link_train.link_rate = DP_LINK_BW_1_62;
726 if (dp->link_train.lane_count == 0) {
727 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
728 dp->link_train.lane_count);
729 dp->link_train.lane_count = (u8)LANE_COUNT1;
732 /* Setup TX lane count & rate */
733 if (dp->link_train.lane_count > max_lanes)
734 dp->link_train.lane_count = max_lanes;
735 if (dp->link_train.link_rate > max_rate)
736 dp->link_train.link_rate = max_rate;
738 /* All DP analog module power up */
739 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
741 dp->link_train.lt_state = START;
744 while (!retval && !training_finished) {
745 switch (dp->link_train.lt_state) {
747 retval = analogix_dp_link_start(dp);
749 dev_err(dp->dev, "LT link start failed!\n");
752 retval = analogix_dp_process_clock_recovery(dp);
754 dev_err(dp->dev, "LT CR failed!\n");
756 case EQUALIZER_TRAINING:
757 retval = analogix_dp_process_equalizer_training(dp);
759 dev_err(dp->dev, "LT EQ failed!\n");
762 training_finished = 1;
769 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
774 static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
777 u8 link_align, link_status[2];
778 enum pll_status status;
780 analogix_dp_reset_macro(dp);
782 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
783 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
785 for (i = 0; i < dp->link_train.lane_count; i++) {
786 analogix_dp_set_lane_link_training(dp,
787 dp->link_train.training_lane[i], i);
790 ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
791 status != PLL_UNLOCKED, 120,
792 120 * DP_TIMEOUT_LOOP_COUNT);
794 DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
798 /* source Set training pattern 1 */
799 analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
800 /* From DP spec, pattern must be on-screen for a minimum 500us */
801 usleep_range(500, 600);
803 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
804 /* From DP spec, pattern must be on-screen for a minimum 500us */
805 usleep_range(500, 600);
807 /* TODO: enhanced_mode?*/
808 analogix_dp_set_training_pattern(dp, DP_NONE);
811 * Useful for debugging issues with fast link training, disable for more
814 if (verify_fast_training) {
815 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
818 DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
823 ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
826 DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
831 if (analogix_dp_clock_recovery_ok(link_status,
832 dp->link_train.lane_count)) {
833 DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
834 analogix_dp_reduce_link_rate(dp);
838 if (analogix_dp_channel_eq_ok(link_status, link_align,
839 dp->link_train.lane_count)) {
840 DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
841 analogix_dp_reduce_link_rate(dp);
849 static int analogix_dp_train_link(struct analogix_dp_device *dp)
851 if (dp->fast_train_enable)
852 return analogix_dp_fast_link_train(dp);
854 return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
855 dp->video_info.max_link_rate);
858 static int analogix_dp_config_video(struct analogix_dp_device *dp)
860 int timeout_loop = 0;
863 analogix_dp_config_video_slave_mode(dp);
865 analogix_dp_set_video_color_format(dp);
867 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
868 dev_err(dp->dev, "PLL is not locked yet.\n");
874 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
876 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
877 dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
880 usleep_range(1000, 1001);
883 /* Set to use the register calculated M/N video */
884 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
886 /* For video bist, Video timing must be generated by register */
887 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
889 /* Disable video mute */
890 analogix_dp_enable_video_mute(dp, 0);
892 /* Configure video slave mode */
893 analogix_dp_enable_video_master(dp, 0);
896 analogix_dp_start_video(dp);
902 if (analogix_dp_is_video_stream_on(dp) == 0) {
906 } else if (done_count) {
909 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
911 "Ignoring timeout of video streamclk ok\n");
915 usleep_range(1000, 1001);
921 static int analogix_dp_enable_scramble(struct analogix_dp_device *dp,
928 analogix_dp_enable_scrambling(dp);
930 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
934 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
935 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
937 analogix_dp_disable_scrambling(dp);
939 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
943 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
944 (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
946 return ret < 0 ? ret : 0;
949 static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
951 struct analogix_dp_device *dp = arg;
952 irqreturn_t ret = IRQ_NONE;
953 enum dp_irq_type irq_type;
955 irq_type = analogix_dp_get_irq_type(dp);
956 if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
957 analogix_dp_mute_hpd_interrupt(dp);
958 ret = IRQ_WAKE_THREAD;
964 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
966 struct analogix_dp_device *dp = arg;
967 enum dp_irq_type irq_type;
969 irq_type = analogix_dp_get_irq_type(dp);
970 if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
971 irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
972 dev_dbg(dp->dev, "Detected cable status changed!\n");
974 drm_helper_hpd_irq_event(dp->drm_dev);
977 if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
978 analogix_dp_clear_hotplug_interrupts(dp);
979 analogix_dp_unmute_hpd_interrupt(dp);
985 static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
990 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
992 dev_err(dp->dev, "failed to read downspread %d\n", ret);
995 dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
996 dev_dbg(dp->dev, "fast link training %s\n",
997 dp->fast_train_enable ? "supported" : "unsupported");
1001 static int analogix_dp_commit(struct analogix_dp_device *dp)
1005 /* Keep the panel disabled while we configure video */
1006 if (dp->plat_data->panel) {
1007 if (drm_panel_disable(dp->plat_data->panel))
1008 DRM_ERROR("failed to disable the panel\n");
1011 ret = analogix_dp_train_link(dp);
1013 dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
1017 ret = analogix_dp_enable_scramble(dp, 1);
1019 dev_err(dp->dev, "can not enable scramble\n");
1023 analogix_dp_init_video(dp);
1024 ret = analogix_dp_config_video(dp);
1026 dev_err(dp->dev, "unable to config video\n");
1030 /* Safe to enable the panel now */
1031 if (dp->plat_data->panel) {
1032 ret = drm_panel_enable(dp->plat_data->panel);
1034 DRM_ERROR("failed to enable the panel\n");
1039 ret = analogix_dp_detect_sink_psr(dp);
1043 /* Check whether panel supports fast training */
1044 ret = analogix_dp_fast_link_train_detection(dp);
1046 dp->psr_enable = false;
1048 if (dp->psr_enable) {
1049 ret = analogix_dp_enable_sink_psr(dp);
1059 * This function is a bit of a catch-all for panel preparation, hopefully
1060 * simplifying the logic of functions that need to prepare/unprepare the panel
1063 * If @prepare is true, this function will prepare the panel. Conversely, if it
1064 * is false, the panel will be unprepared.
1066 * If @is_modeset_prepare is true, the function will disregard the current state
1067 * of the panel and either prepare/unprepare the panel based on @prepare. Once
1068 * it finishes, it will update dp->panel_is_modeset to reflect the current state
1071 static int analogix_dp_prepare_panel(struct analogix_dp_device *dp,
1072 bool prepare, bool is_modeset_prepare)
1076 if (!dp->plat_data->panel)
1079 mutex_lock(&dp->panel_lock);
1082 * Exit early if this is a temporary prepare/unprepare and we're already
1083 * modeset (since we neither want to prepare twice or unprepare early).
1085 if (dp->panel_is_modeset && !is_modeset_prepare)
1089 ret = drm_panel_prepare(dp->plat_data->panel);
1091 ret = drm_panel_unprepare(dp->plat_data->panel);
1096 if (is_modeset_prepare)
1097 dp->panel_is_modeset = prepare;
1100 mutex_unlock(&dp->panel_lock);
1104 static int analogix_dp_get_modes(struct drm_connector *connector)
1106 struct analogix_dp_device *dp = to_dp(connector);
1108 int ret, num_modes = 0;
1110 if (dp->plat_data->panel) {
1111 num_modes += drm_panel_get_modes(dp->plat_data->panel);
1113 ret = analogix_dp_prepare_panel(dp, true, false);
1115 DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1119 pm_runtime_get_sync(dp->dev);
1120 edid = drm_get_edid(connector, &dp->aux.ddc);
1121 pm_runtime_put(dp->dev);
1123 drm_connector_update_edid_property(&dp->connector,
1125 num_modes += drm_add_edid_modes(&dp->connector, edid);
1129 ret = analogix_dp_prepare_panel(dp, false, false);
1131 DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1134 if (dp->plat_data->get_modes)
1135 num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
1140 static struct drm_encoder *
1141 analogix_dp_best_encoder(struct drm_connector *connector)
1143 struct analogix_dp_device *dp = to_dp(connector);
1148 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
1149 .get_modes = analogix_dp_get_modes,
1150 .best_encoder = analogix_dp_best_encoder,
1153 static enum drm_connector_status
1154 analogix_dp_detect(struct drm_connector *connector, bool force)
1156 struct analogix_dp_device *dp = to_dp(connector);
1157 enum drm_connector_status status = connector_status_disconnected;
1160 if (dp->plat_data->panel)
1161 return connector_status_connected;
1163 ret = analogix_dp_prepare_panel(dp, true, false);
1165 DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1166 return connector_status_disconnected;
1169 if (!analogix_dp_detect_hpd(dp))
1170 status = connector_status_connected;
1172 ret = analogix_dp_prepare_panel(dp, false, false);
1174 DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1179 static const struct drm_connector_funcs analogix_dp_connector_funcs = {
1180 .fill_modes = drm_helper_probe_single_connector_modes,
1181 .detect = analogix_dp_detect,
1182 .destroy = drm_connector_cleanup,
1183 .reset = drm_atomic_helper_connector_reset,
1184 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1185 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1188 static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
1190 struct analogix_dp_device *dp = bridge->driver_private;
1191 struct drm_encoder *encoder = dp->encoder;
1192 struct drm_connector *connector = NULL;
1195 if (!bridge->encoder) {
1196 DRM_ERROR("Parent encoder object not found");
1200 if (!dp->plat_data->skip_connector) {
1201 connector = &dp->connector;
1202 connector->polled = DRM_CONNECTOR_POLL_HPD;
1204 ret = drm_connector_init(dp->drm_dev, connector,
1205 &analogix_dp_connector_funcs,
1206 DRM_MODE_CONNECTOR_eDP);
1208 DRM_ERROR("Failed to initialize connector with drm\n");
1212 drm_connector_helper_add(connector,
1213 &analogix_dp_connector_helper_funcs);
1214 drm_connector_attach_encoder(connector, encoder);
1218 * NOTE: the connector registration is implemented in analogix
1219 * platform driver, that to say connector would be exist after
1220 * plat_data->attch return, that's why we record the connector
1221 * point after plat attached.
1223 if (dp->plat_data->attach) {
1224 ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1226 DRM_ERROR("Failed at platform attch func\n");
1231 if (dp->plat_data->panel) {
1232 ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
1234 DRM_ERROR("Failed to attach panel\n");
1242 static void analogix_dp_bridge_pre_enable(struct drm_bridge *bridge)
1244 struct analogix_dp_device *dp = bridge->driver_private;
1247 ret = analogix_dp_prepare_panel(dp, true, true);
1249 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1252 static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
1256 pm_runtime_get_sync(dp->dev);
1258 ret = clk_prepare_enable(dp->clock);
1260 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1261 goto out_dp_clk_pre;
1264 if (dp->plat_data->power_on_start)
1265 dp->plat_data->power_on_start(dp->plat_data);
1267 phy_power_on(dp->phy);
1269 ret = analogix_dp_init_dp(dp);
1274 * According to DP spec v1.3 chap 3.5.1.2 Link Training,
1275 * We should first make sure the HPD signal is asserted high by device
1276 * when we want to establish a link with it.
1278 ret = analogix_dp_detect_hpd(dp);
1280 DRM_ERROR("failed to get hpd single ret = %d\n", ret);
1284 ret = analogix_dp_commit(dp);
1286 DRM_ERROR("dp commit error, ret = %d\n", ret);
1290 if (dp->plat_data->power_on_end)
1291 dp->plat_data->power_on_end(dp->plat_data);
1293 enable_irq(dp->irq);
1297 phy_power_off(dp->phy);
1298 if (dp->plat_data->power_off)
1299 dp->plat_data->power_off(dp->plat_data);
1300 clk_disable_unprepare(dp->clock);
1302 pm_runtime_put_sync(dp->dev);
1307 static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
1309 struct analogix_dp_device *dp = bridge->driver_private;
1310 int timeout_loop = 0;
1312 if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1315 while (timeout_loop < MAX_PLL_LOCK_LOOP) {
1316 if (analogix_dp_set_bridge(dp) == 0) {
1317 dp->dpms_mode = DRM_MODE_DPMS_ON;
1320 dev_err(dp->dev, "failed to set bridge, retry: %d\n",
1323 usleep_range(10, 11);
1325 dev_err(dp->dev, "too many times retry set bridge, give it up\n");
1328 static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1330 struct analogix_dp_device *dp = bridge->driver_private;
1333 if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1336 if (dp->plat_data->panel) {
1337 if (drm_panel_disable(dp->plat_data->panel)) {
1338 DRM_ERROR("failed to disable the panel\n");
1343 disable_irq(dp->irq);
1345 if (dp->plat_data->power_off)
1346 dp->plat_data->power_off(dp->plat_data);
1348 analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
1349 phy_power_off(dp->phy);
1351 clk_disable_unprepare(dp->clock);
1353 pm_runtime_put_sync(dp->dev);
1355 ret = analogix_dp_prepare_panel(dp, false, true);
1357 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1359 dp->psr_enable = false;
1360 dp->fast_train_enable = false;
1361 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1364 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
1365 struct drm_display_mode *orig_mode,
1366 struct drm_display_mode *mode)
1368 struct analogix_dp_device *dp = bridge->driver_private;
1369 struct drm_display_info *display_info = &dp->connector.display_info;
1370 struct video_info *video = &dp->video_info;
1371 struct device_node *dp_node = dp->dev->of_node;
1374 /* Input video interlaces & hsync pol & vsync pol */
1375 video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1376 video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1377 video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1379 /* Input video dynamic_range & colorimetry */
1380 vic = drm_match_cea_mode(mode);
1381 if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
1382 (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
1383 video->dynamic_range = CEA;
1384 video->ycbcr_coeff = COLOR_YCBCR601;
1386 video->dynamic_range = CEA;
1387 video->ycbcr_coeff = COLOR_YCBCR709;
1389 video->dynamic_range = VESA;
1390 video->ycbcr_coeff = COLOR_YCBCR709;
1393 /* Input vide bpc and color_formats */
1394 switch (display_info->bpc) {
1396 video->color_depth = COLOR_12;
1399 video->color_depth = COLOR_10;
1402 video->color_depth = COLOR_8;
1405 video->color_depth = COLOR_6;
1408 video->color_depth = COLOR_8;
1411 if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
1412 video->color_space = COLOR_YCBCR444;
1413 else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
1414 video->color_space = COLOR_YCBCR422;
1415 else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
1416 video->color_space = COLOR_RGB;
1418 video->color_space = COLOR_RGB;
1421 * NOTE: those property parsing code is used for providing backward
1422 * compatibility for samsung platform.
1423 * Due to we used the "of_property_read_u32" interfaces, when this
1424 * property isn't present, the "video_info" can keep the original
1425 * values and wouldn't be modified.
1427 of_property_read_u32(dp_node, "samsung,color-space",
1428 &video->color_space);
1429 of_property_read_u32(dp_node, "samsung,dynamic-range",
1430 &video->dynamic_range);
1431 of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1432 &video->ycbcr_coeff);
1433 of_property_read_u32(dp_node, "samsung,color-depth",
1434 &video->color_depth);
1435 if (of_property_read_bool(dp_node, "hsync-active-high"))
1436 video->h_sync_polarity = true;
1437 if (of_property_read_bool(dp_node, "vsync-active-high"))
1438 video->v_sync_polarity = true;
1439 if (of_property_read_bool(dp_node, "interlaced"))
1440 video->interlaced = true;
1443 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
1448 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1449 .pre_enable = analogix_dp_bridge_pre_enable,
1450 .enable = analogix_dp_bridge_enable,
1451 .disable = analogix_dp_bridge_disable,
1452 .post_disable = analogix_dp_bridge_nop,
1453 .mode_set = analogix_dp_bridge_mode_set,
1454 .attach = analogix_dp_bridge_attach,
1457 static int analogix_dp_create_bridge(struct drm_device *drm_dev,
1458 struct analogix_dp_device *dp)
1460 struct drm_bridge *bridge;
1463 bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
1465 DRM_ERROR("failed to allocate for drm bridge\n");
1469 dp->bridge = bridge;
1471 bridge->driver_private = dp;
1472 bridge->funcs = &analogix_dp_bridge_funcs;
1474 ret = drm_bridge_attach(dp->encoder, bridge, NULL);
1476 DRM_ERROR("failed to attach drm bridge\n");
1483 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1485 struct device_node *dp_node = dp->dev->of_node;
1486 struct video_info *video_info = &dp->video_info;
1488 switch (dp->plat_data->dev_type) {
1492 * Like Rk3288 DisplayPort TRM indicate that "Main link
1493 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
1495 video_info->max_link_rate = 0x0A;
1496 video_info->max_lane_count = 0x04;
1500 * NOTE: those property parseing code is used for
1501 * providing backward compatibility for samsung platform.
1503 of_property_read_u32(dp_node, "samsung,link-rate",
1504 &video_info->max_link_rate);
1505 of_property_read_u32(dp_node, "samsung,lane-count",
1506 &video_info->max_lane_count);
1513 static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux,
1514 struct drm_dp_aux_msg *msg)
1516 struct analogix_dp_device *dp = to_dp(aux);
1518 return analogix_dp_transfer(dp, msg);
1521 struct analogix_dp_device *
1522 analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
1523 struct analogix_dp_plat_data *plat_data)
1525 struct platform_device *pdev = to_platform_device(dev);
1526 struct analogix_dp_device *dp;
1527 struct resource *res;
1528 unsigned int irq_flags;
1532 dev_err(dev, "Invalided input plat_data\n");
1533 return ERR_PTR(-EINVAL);
1536 dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
1538 return ERR_PTR(-ENOMEM);
1540 dp->dev = &pdev->dev;
1541 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1543 mutex_init(&dp->panel_lock);
1544 dp->panel_is_modeset = false;
1547 * platform dp driver need containor_of the plat_data to get
1548 * the driver private data, so we need to store the point of
1549 * plat_data, not the context of plat_data.
1551 dp->plat_data = plat_data;
1553 ret = analogix_dp_dt_parse_pdata(dp);
1555 return ERR_PTR(ret);
1557 dp->phy = devm_phy_get(dp->dev, "dp");
1558 if (IS_ERR(dp->phy)) {
1559 dev_err(dp->dev, "no DP phy configured\n");
1560 ret = PTR_ERR(dp->phy);
1563 * phy itself is not enabled, so we can move forward
1564 * assigning NULL to phy pointer.
1566 if (ret == -ENOSYS || ret == -ENODEV)
1569 return ERR_PTR(ret);
1573 dp->clock = devm_clk_get(&pdev->dev, "dp");
1574 if (IS_ERR(dp->clock)) {
1575 dev_err(&pdev->dev, "failed to get clock\n");
1576 return ERR_CAST(dp->clock);
1579 clk_prepare_enable(dp->clock);
1581 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1583 dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1584 if (IS_ERR(dp->reg_base))
1585 return ERR_CAST(dp->reg_base);
1587 dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
1589 dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
1590 if (!gpio_is_valid(dp->hpd_gpio))
1591 dp->hpd_gpio = of_get_named_gpio(dev->of_node,
1592 "samsung,hpd-gpio", 0);
1594 if (gpio_is_valid(dp->hpd_gpio)) {
1596 * Set up the hotplug GPIO from the device tree as an interrupt.
1597 * Simply specifying a different interrupt in the device tree
1598 * doesn't work since we handle hotplug rather differently when
1599 * using a GPIO. We also need the actual GPIO specifier so
1600 * that we can get the current state of the GPIO.
1602 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
1605 dev_err(&pdev->dev, "failed to get hpd gpio\n");
1606 return ERR_PTR(ret);
1608 dp->irq = gpio_to_irq(dp->hpd_gpio);
1609 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1611 dp->hpd_gpio = -ENODEV;
1612 dp->irq = platform_get_irq(pdev, 0);
1616 if (dp->irq == -ENXIO) {
1617 dev_err(&pdev->dev, "failed to get irq\n");
1618 return ERR_PTR(-ENODEV);
1621 ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
1622 analogix_dp_hardirq,
1623 analogix_dp_irq_thread,
1624 irq_flags, "analogix-dp", dp);
1626 dev_err(&pdev->dev, "failed to request irq\n");
1627 goto err_disable_pm_runtime;
1629 disable_irq(dp->irq);
1631 dp->drm_dev = drm_dev;
1632 dp->encoder = dp->plat_data->encoder;
1634 dp->aux.name = "DP-AUX";
1635 dp->aux.transfer = analogix_dpaux_transfer;
1636 dp->aux.dev = &pdev->dev;
1638 ret = drm_dp_aux_register(&dp->aux);
1640 return ERR_PTR(ret);
1642 pm_runtime_enable(dev);
1644 ret = analogix_dp_create_bridge(drm_dev, dp);
1646 DRM_ERROR("failed to create bridge (%d)\n", ret);
1647 goto err_disable_pm_runtime;
1652 err_disable_pm_runtime:
1654 pm_runtime_disable(dev);
1656 return ERR_PTR(ret);
1658 EXPORT_SYMBOL_GPL(analogix_dp_bind);
1660 void analogix_dp_unbind(struct analogix_dp_device *dp)
1662 analogix_dp_bridge_disable(dp->bridge);
1663 dp->connector.funcs->destroy(&dp->connector);
1665 if (dp->plat_data->panel) {
1666 if (drm_panel_unprepare(dp->plat_data->panel))
1667 DRM_ERROR("failed to turnoff the panel\n");
1668 if (drm_panel_detach(dp->plat_data->panel))
1669 DRM_ERROR("failed to detach the panel\n");
1672 drm_dp_aux_unregister(&dp->aux);
1673 pm_runtime_disable(dp->dev);
1674 clk_disable_unprepare(dp->clock);
1676 EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1679 int analogix_dp_suspend(struct analogix_dp_device *dp)
1681 clk_disable_unprepare(dp->clock);
1683 if (dp->plat_data->panel) {
1684 if (drm_panel_unprepare(dp->plat_data->panel))
1685 DRM_ERROR("failed to turnoff the panel\n");
1690 EXPORT_SYMBOL_GPL(analogix_dp_suspend);
1692 int analogix_dp_resume(struct analogix_dp_device *dp)
1696 ret = clk_prepare_enable(dp->clock);
1698 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1702 if (dp->plat_data->panel) {
1703 if (drm_panel_prepare(dp->plat_data->panel)) {
1704 DRM_ERROR("failed to setup the panel\n");
1711 EXPORT_SYMBOL_GPL(analogix_dp_resume);
1714 int analogix_dp_start_crc(struct drm_connector *connector)
1716 struct analogix_dp_device *dp = to_dp(connector);
1718 if (!connector->state->crtc) {
1719 DRM_ERROR("Connector %s doesn't currently have a CRTC.\n",
1724 return drm_dp_start_crc(&dp->aux, connector->state->crtc);
1726 EXPORT_SYMBOL_GPL(analogix_dp_start_crc);
1728 int analogix_dp_stop_crc(struct drm_connector *connector)
1730 struct analogix_dp_device *dp = to_dp(connector);
1732 return drm_dp_stop_crc(&dp->aux);
1734 EXPORT_SYMBOL_GPL(analogix_dp_stop_crc);
1736 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1737 MODULE_DESCRIPTION("Analogix DP Core Driver");
1738 MODULE_LICENSE("GPL v2");