2 #include <linux/firmware.h>
7 int ast_load_dp501_microcode(struct drm_device *dev)
9 struct ast_private *ast = dev->dev_private;
10 static char *fw_name = "/*(DEBLOBBED)*/";
12 err = reject_firmware(&ast->dp501_fw, fw_name, dev->dev);
19 static void send_ack(struct ast_private *ast)
22 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
24 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
27 static void send_nack(struct ast_private *ast)
30 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
32 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
35 static bool wait_ack(struct ast_private *ast)
40 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
43 } while ((!waitack) && (retry++ < 1000));
51 static bool wait_nack(struct ast_private *ast)
56 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
59 } while ((waitack) && (retry++ < 1000));
67 static void set_cmd_trigger(struct ast_private *ast)
69 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40);
72 static void clear_cmd_trigger(struct ast_private *ast)
74 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00);
78 static bool wait_fw_ready(struct ast_private *ast)
83 waitready = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
86 } while ((!waitready) && (retry++ < 1000));
95 static bool ast_write_cmd(struct drm_device *dev, u8 data)
97 struct ast_private *ast = dev->dev_private;
101 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
103 set_cmd_trigger(ast);
106 clear_cmd_trigger(ast);
110 } while (retry++ < 100);
112 clear_cmd_trigger(ast);
117 static bool ast_write_data(struct drm_device *dev, u8 data)
119 struct ast_private *ast = dev->dev_private;
121 if (wait_nack(ast)) {
123 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
135 static bool ast_read_data(struct drm_device *dev, u8 *data)
137 struct ast_private *ast = dev->dev_private;
142 if (wait_ack(ast) == false)
144 tmp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd3, 0xff);
146 if (wait_nack(ast) == false) {
154 static void clear_cmd(struct ast_private *ast)
157 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00);
161 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode)
163 ast_write_cmd(dev, 0x40);
164 ast_write_data(dev, mode);
169 static u32 get_fw_base(struct ast_private *ast)
171 return ast_mindwm(ast, 0x1e6e2104) & 0x7fffffff;
174 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size)
176 struct ast_private *ast = dev->dev_private;
180 data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
182 boot_address = get_fw_base(ast);
183 for (i = 0; i < size; i += 4)
184 *(u32 *)(addr + i) = ast_mindwm(ast, boot_address + i);
190 bool ast_launch_m68k(struct drm_device *dev)
192 struct ast_private *ast = dev->dev_private;
193 u32 i, data, len = 0;
198 data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
201 if (ast->dp501_fw_addr) {
202 fw_addr = ast->dp501_fw_addr;
204 } else if (ast->dp501_fw) {
205 fw_addr = (u8 *)ast->dp501_fw->data;
206 len = ast->dp501_fw->size;
208 /* Get BootAddress */
209 ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
210 data = ast_mindwm(ast, 0x1e6e0004);
211 switch (data & 0x03) {
213 boot_address = 0x44000000;
217 boot_address = 0x48000000;
220 boot_address = 0x50000000;
223 boot_address = 0x60000000;
226 boot_address -= 0x200000; /* -2MB */
228 /* copy image to buffer */
229 for (i = 0; i < len; i += 4) {
230 data = *(u32 *)(fw_addr + i);
231 ast_moutdwm(ast, boot_address + i, data);
235 ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
238 ast_moutdwm(ast, 0x1e6e2104, 0x80000000 + boot_address);
239 ast_moutdwm(ast, 0x1e6e2100, 1);
242 data = ast_mindwm(ast, 0x1e6e2040) & 0xfffff1ff; /* D[11:9] = 100b: UEFI handling */
244 ast_moutdwm(ast, 0x1e6e2040, data);
246 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */
248 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x99, jreg);
253 u8 ast_get_dp501_max_clk(struct drm_device *dev)
255 struct ast_private *ast = dev->dev_private;
256 u32 boot_address, offset, data;
257 u8 linkcap[4], linkrate, linklanes, maxclk = 0xff;
259 boot_address = get_fw_base(ast);
261 /* validate FW version */
263 data = ast_mindwm(ast, boot_address + offset);
264 if ((data & 0xf0) != 0x10) /* version: 1x */
267 /* Read Link Capability */
269 *(u32 *)linkcap = ast_mindwm(ast, boot_address + offset);
270 if (linkcap[2] == 0) {
271 linkrate = linkcap[0];
272 linklanes = linkcap[1];
273 data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * linklanes);
281 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata)
283 struct ast_private *ast = dev->dev_private;
284 u32 i, boot_address, offset, data;
286 boot_address = get_fw_base(ast);
288 /* validate FW version */
290 data = ast_mindwm(ast, boot_address + offset);
291 if ((data & 0xf0) != 0x10)
294 /* validate PnP Monitor */
296 data = ast_mindwm(ast, boot_address + offset);
302 for (i = 0; i < 128; i += 4) {
303 data = ast_mindwm(ast, boot_address + offset + i);
304 *(u32 *)(ediddata + i) = data;
310 static bool ast_init_dvo(struct drm_device *dev)
312 struct ast_private *ast = dev->dev_private;
315 ast_write32(ast, 0xf004, 0x1e6e0000);
316 ast_write32(ast, 0xf000, 0x1);
317 ast_write32(ast, 0x12000, 0x1688a8a8);
319 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
320 if (!(jreg & 0x80)) {
321 /* Init SCU DVO Settings */
322 data = ast_read32(ast, 0x12008);
326 ast_write32(ast, 0x12008, data);
328 if (ast->chip == AST2300) {
329 data = ast_read32(ast, 0x12084);
330 /* multi-pins for DVO single-edge */
332 ast_write32(ast, 0x12084, data);
334 data = ast_read32(ast, 0x12088);
335 /* multi-pins for DVO single-edge */
337 ast_write32(ast, 0x12088, data);
339 data = ast_read32(ast, 0x12090);
340 /* multi-pins for DVO single-edge */
343 ast_write32(ast, 0x12090, data);
344 } else { /* AST2400 */
345 data = ast_read32(ast, 0x12088);
346 /* multi-pins for DVO single-edge */
348 ast_write32(ast, 0x12088, data);
350 data = ast_read32(ast, 0x1208c);
351 /* multi-pins for DVO single-edge */
353 ast_write32(ast, 0x1208c, data);
355 data = ast_read32(ast, 0x120a4);
356 /* multi-pins for DVO single-edge */
358 ast_write32(ast, 0x120a4, data);
360 data = ast_read32(ast, 0x120a8);
361 /* multi-pins for DVO single-edge */
363 ast_write32(ast, 0x120a8, data);
365 data = ast_read32(ast, 0x12094);
366 /* multi-pins for DVO single-edge */
368 ast_write32(ast, 0x12094, data);
373 data = ast_read32(ast, 0x1202c);
375 ast_write32(ast, 0x1202c, data);
377 /* Init VGA DVO Settings */
378 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);
383 static void ast_init_analog(struct drm_device *dev)
385 struct ast_private *ast = dev->dev_private;
389 * Set DAC source to VGA mode in SCU2C via the P2A
390 * bridge. First configure the P2U to target the SCU
391 * in case it isn't at this stage.
393 ast_write32(ast, 0xf004, 0x1e6e0000);
394 ast_write32(ast, 0xf000, 0x1);
396 /* Then unlock the SCU with the magic password */
397 ast_write32(ast, 0x12000, 0x1688a8a8);
398 ast_write32(ast, 0x12000, 0x1688a8a8);
399 ast_write32(ast, 0x12000, 0x1688a8a8);
401 /* Finally, clear bits [17:16] of SCU2c */
402 data = ast_read32(ast, 0x1202c);
404 ast_write32(ast, 0, data);
407 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x00);
410 void ast_init_3rdtx(struct drm_device *dev)
412 struct ast_private *ast = dev->dev_private;
415 if (ast->chip == AST2300 || ast->chip == AST2400) {
416 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
417 switch (jreg & 0x0e) {
422 ast_launch_m68k(dev);
428 if (ast->tx_chip_type == AST_TX_SIL164)
431 ast_init_analog(dev);