2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <drm/drm_plane_helper.h>
11 #include "armada_crtc.h"
12 #include "armada_drm.h"
13 #include "armada_fb.h"
14 #include "armada_gem.h"
15 #include "armada_hw.h"
16 #include <drm/armada_drm.h>
17 #include "armada_ioctlP.h"
19 struct armada_ovl_plane_properties {
23 #define K2R(val) (((val) >> 0) & 0xff)
24 #define K2G(val) (((val) >> 8) & 0xff)
25 #define K2B(val) (((val) >> 16) & 0xff)
29 uint32_t colorkey_mode;
30 uint32_t colorkey_enable;
33 struct armada_ovl_plane {
34 struct armada_plane base;
35 struct drm_framebuffer *old_fb;
41 struct armada_plane_work work;
42 struct armada_regs regs[13];
44 struct armada_ovl_plane_properties prop;
46 #define drm_to_armada_ovl_plane(p) \
47 container_of(p, struct armada_ovl_plane, base.base)
51 armada_ovl_update_attr(struct armada_ovl_plane_properties *prop,
52 struct armada_crtc *dcrtc)
54 writel_relaxed(prop->colorkey_yr, dcrtc->base + LCD_SPU_COLORKEY_Y);
55 writel_relaxed(prop->colorkey_ug, dcrtc->base + LCD_SPU_COLORKEY_U);
56 writel_relaxed(prop->colorkey_vb, dcrtc->base + LCD_SPU_COLORKEY_V);
58 writel_relaxed(prop->brightness << 16 | prop->contrast,
59 dcrtc->base + LCD_SPU_CONTRAST);
60 /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
61 writel_relaxed(prop->saturation << 16,
62 dcrtc->base + LCD_SPU_SATURATION);
63 writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE);
65 spin_lock_irq(&dcrtc->irq_lock);
66 armada_updatel(prop->colorkey_mode,
67 CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
68 dcrtc->base + LCD_SPU_DMA_CTRL1);
69 if (dcrtc->variant->has_spu_adv_reg)
70 armada_updatel(prop->colorkey_enable,
71 ADV_GRACOLORKEY | ADV_VIDCOLORKEY,
72 dcrtc->base + LCD_SPU_ADV_REG);
73 spin_unlock_irq(&dcrtc->irq_lock);
76 static void armada_ovl_retire_fb(struct armada_ovl_plane *dplane,
77 struct drm_framebuffer *fb)
79 struct drm_framebuffer *old_fb;
81 old_fb = xchg(&dplane->old_fb, fb);
84 armada_drm_queue_unref_work(dplane->base.base.dev, old_fb);
87 /* === Plane support === */
88 static void armada_ovl_plane_work(struct armada_crtc *dcrtc,
89 struct armada_plane *plane, struct armada_plane_work *work)
91 struct armada_ovl_plane *dplane = container_of(plane, struct armada_ovl_plane, base);
93 armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs);
94 armada_ovl_retire_fb(dplane, NULL);
98 armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
99 struct drm_framebuffer *fb,
100 int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
101 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h)
103 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
104 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
105 struct drm_rect src = {
111 struct drm_rect dest = {
114 .x2 = crtc_x + crtc_w,
115 .y2 = crtc_y + crtc_h,
117 const struct drm_rect clip = {
118 .x2 = crtc->mode.hdisplay,
119 .y2 = crtc->mode.vdisplay,
126 ret = drm_plane_helper_check_update(plane, crtc, fb, &src, &dest, &clip,
128 0, INT_MAX, true, false, &visible);
132 ctrl0 = CFG_DMA_FMT(drm_fb_to_armada_fb(fb)->fmt) |
133 CFG_DMA_MOD(drm_fb_to_armada_fb(fb)->mod) |
134 CFG_CBSH_ENA | CFG_DMA_HSMOOTH | CFG_DMA_ENA;
136 /* Does the position/size result in nothing to display? */
138 ctrl0 &= ~CFG_DMA_ENA;
141 dcrtc->plane = plane;
142 armada_ovl_update_attr(&dplane->prop, dcrtc);
145 /* FIXME: overlay on an interlaced display */
146 /* Just updating the position/size? */
147 if (plane->fb == fb && dplane->ctrl0 == ctrl0) {
148 val = (drm_rect_height(&src) & 0xffff0000) |
149 drm_rect_width(&src) >> 16;
150 dplane->src_hw = val;
151 writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN);
153 val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
154 dplane->dst_hw = val;
155 writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN);
157 val = dest.y1 << 16 | dest.x1;
158 dplane->dst_yx = val;
159 writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN);
162 } else if (~dplane->ctrl0 & ctrl0 & CFG_DMA_ENA) {
163 /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */
164 armada_updatel(0, CFG_PDWN16x66 | CFG_PDWN32x66,
165 dcrtc->base + LCD_SPU_SRAM_PARA1);
168 if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0)
169 armada_drm_plane_work_cancel(dcrtc, &dplane->base);
171 if (plane->fb != fb) {
172 struct armada_gem_object *obj = drm_fb_obj(fb);
173 uint32_t addr[3], pixel_format;
174 int i, num_planes, hsub;
177 * Take a reference on the new framebuffer - we want to
178 * hold on to it while the hardware is displaying it.
180 drm_framebuffer_reference(fb);
183 armada_ovl_retire_fb(dplane, plane->fb);
185 src_y = src.y1 >> 16;
186 src_x = src.x1 >> 16;
188 pixel_format = fb->pixel_format;
189 hsub = drm_format_horz_chroma_subsampling(pixel_format);
190 num_planes = drm_format_num_planes(pixel_format);
193 * Annoyingly, shifting a YUYV-format image by one pixel
194 * causes the U/V planes to toggle. Toggle the UV swap.
195 * (Unfortunately, this causes momentary colour flickering.)
197 if (src_x & (hsub - 1) && num_planes == 1)
198 ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
200 for (i = 0; i < num_planes; i++)
201 addr[i] = obj->dev_addr + fb->offsets[i] +
202 src_y * fb->pitches[i] +
203 src_x * drm_format_plane_cpp(pixel_format, i);
204 for (; i < ARRAY_SIZE(addr); i++)
207 armada_reg_queue_set(dplane->vbl.regs, idx, addr[0],
208 LCD_SPU_DMA_START_ADDR_Y0);
209 armada_reg_queue_set(dplane->vbl.regs, idx, addr[1],
210 LCD_SPU_DMA_START_ADDR_U0);
211 armada_reg_queue_set(dplane->vbl.regs, idx, addr[2],
212 LCD_SPU_DMA_START_ADDR_V0);
213 armada_reg_queue_set(dplane->vbl.regs, idx, addr[0],
214 LCD_SPU_DMA_START_ADDR_Y1);
215 armada_reg_queue_set(dplane->vbl.regs, idx, addr[1],
216 LCD_SPU_DMA_START_ADDR_U1);
217 armada_reg_queue_set(dplane->vbl.regs, idx, addr[2],
218 LCD_SPU_DMA_START_ADDR_V1);
220 val = fb->pitches[0] << 16 | fb->pitches[0];
221 armada_reg_queue_set(dplane->vbl.regs, idx, val,
222 LCD_SPU_DMA_PITCH_YC);
223 val = fb->pitches[1] << 16 | fb->pitches[2];
224 armada_reg_queue_set(dplane->vbl.regs, idx, val,
225 LCD_SPU_DMA_PITCH_UV);
228 val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16;
229 if (dplane->src_hw != val) {
230 dplane->src_hw = val;
231 armada_reg_queue_set(dplane->vbl.regs, idx, val,
232 LCD_SPU_DMA_HPXL_VLN);
235 val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
236 if (dplane->dst_hw != val) {
237 dplane->dst_hw = val;
238 armada_reg_queue_set(dplane->vbl.regs, idx, val,
239 LCD_SPU_DZM_HPXL_VLN);
242 val = dest.y1 << 16 | dest.x1;
243 if (dplane->dst_yx != val) {
244 dplane->dst_yx = val;
245 armada_reg_queue_set(dplane->vbl.regs, idx, val,
246 LCD_SPU_DMA_OVSA_HPXL_VLN);
249 if (dplane->ctrl0 != ctrl0) {
250 dplane->ctrl0 = ctrl0;
251 armada_reg_queue_mod(dplane->vbl.regs, idx, ctrl0,
252 CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE |
253 CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE |
254 CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU |
255 CFG_YUV2RGB) | CFG_DMA_ENA,
259 armada_reg_queue_end(dplane->vbl.regs, idx);
260 armada_drm_plane_work_queue(dcrtc, &dplane->base,
266 static int armada_ovl_plane_disable(struct drm_plane *plane)
268 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
269 struct drm_framebuffer *fb;
270 struct armada_crtc *dcrtc;
272 if (!dplane->base.base.crtc)
275 dcrtc = drm_to_armada_crtc(dplane->base.base.crtc);
277 armada_drm_plane_work_cancel(dcrtc, &dplane->base);
278 armada_drm_crtc_plane_disable(dcrtc, plane);
283 fb = xchg(&dplane->old_fb, NULL);
285 drm_framebuffer_unreference(fb);
290 static void armada_ovl_plane_destroy(struct drm_plane *plane)
292 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
294 drm_plane_cleanup(plane);
299 static int armada_ovl_plane_set_property(struct drm_plane *plane,
300 struct drm_property *property, uint64_t val)
302 struct armada_private *priv = plane->dev->dev_private;
303 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
304 bool update_attr = false;
306 if (property == priv->colorkey_prop) {
307 #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
308 dplane->prop.colorkey_yr = CCC(K2R(val));
309 dplane->prop.colorkey_ug = CCC(K2G(val));
310 dplane->prop.colorkey_vb = CCC(K2B(val));
313 } else if (property == priv->colorkey_min_prop) {
314 dplane->prop.colorkey_yr &= ~0x00ff0000;
315 dplane->prop.colorkey_yr |= K2R(val) << 16;
316 dplane->prop.colorkey_ug &= ~0x00ff0000;
317 dplane->prop.colorkey_ug |= K2G(val) << 16;
318 dplane->prop.colorkey_vb &= ~0x00ff0000;
319 dplane->prop.colorkey_vb |= K2B(val) << 16;
321 } else if (property == priv->colorkey_max_prop) {
322 dplane->prop.colorkey_yr &= ~0xff000000;
323 dplane->prop.colorkey_yr |= K2R(val) << 24;
324 dplane->prop.colorkey_ug &= ~0xff000000;
325 dplane->prop.colorkey_ug |= K2G(val) << 24;
326 dplane->prop.colorkey_vb &= ~0xff000000;
327 dplane->prop.colorkey_vb |= K2B(val) << 24;
329 } else if (property == priv->colorkey_val_prop) {
330 dplane->prop.colorkey_yr &= ~0x0000ff00;
331 dplane->prop.colorkey_yr |= K2R(val) << 8;
332 dplane->prop.colorkey_ug &= ~0x0000ff00;
333 dplane->prop.colorkey_ug |= K2G(val) << 8;
334 dplane->prop.colorkey_vb &= ~0x0000ff00;
335 dplane->prop.colorkey_vb |= K2B(val) << 8;
337 } else if (property == priv->colorkey_alpha_prop) {
338 dplane->prop.colorkey_yr &= ~0x000000ff;
339 dplane->prop.colorkey_yr |= K2R(val);
340 dplane->prop.colorkey_ug &= ~0x000000ff;
341 dplane->prop.colorkey_ug |= K2G(val);
342 dplane->prop.colorkey_vb &= ~0x000000ff;
343 dplane->prop.colorkey_vb |= K2B(val);
345 } else if (property == priv->colorkey_mode_prop) {
346 if (val == CKMODE_DISABLE) {
347 dplane->prop.colorkey_mode =
348 CFG_CKMODE(CKMODE_DISABLE) |
349 CFG_ALPHAM_CFG | CFG_ALPHA(255);
350 dplane->prop.colorkey_enable = 0;
352 dplane->prop.colorkey_mode =
354 CFG_ALPHAM_GRA | CFG_ALPHA(0);
355 dplane->prop.colorkey_enable = ADV_GRACOLORKEY;
358 } else if (property == priv->brightness_prop) {
359 dplane->prop.brightness = val - 256;
361 } else if (property == priv->contrast_prop) {
362 dplane->prop.contrast = val;
364 } else if (property == priv->saturation_prop) {
365 dplane->prop.saturation = val;
369 if (update_attr && dplane->base.base.crtc)
370 armada_ovl_update_attr(&dplane->prop,
371 drm_to_armada_crtc(dplane->base.base.crtc));
376 static const struct drm_plane_funcs armada_ovl_plane_funcs = {
377 .update_plane = armada_ovl_plane_update,
378 .disable_plane = armada_ovl_plane_disable,
379 .destroy = armada_ovl_plane_destroy,
380 .set_property = armada_ovl_plane_set_property,
383 static const uint32_t armada_ovl_formats[] = {
404 static struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
405 { CKMODE_DISABLE, "disabled" },
406 { CKMODE_Y, "Y component" },
407 { CKMODE_U, "U component" },
408 { CKMODE_V, "V component" },
409 { CKMODE_RGB, "RGB" },
410 { CKMODE_R, "R component" },
411 { CKMODE_G, "G component" },
412 { CKMODE_B, "B component" },
415 static int armada_overlay_create_properties(struct drm_device *dev)
417 struct armada_private *priv = dev->dev_private;
419 if (priv->colorkey_prop)
422 priv->colorkey_prop = drm_property_create_range(dev, 0,
423 "colorkey", 0, 0xffffff);
424 priv->colorkey_min_prop = drm_property_create_range(dev, 0,
425 "colorkey_min", 0, 0xffffff);
426 priv->colorkey_max_prop = drm_property_create_range(dev, 0,
427 "colorkey_max", 0, 0xffffff);
428 priv->colorkey_val_prop = drm_property_create_range(dev, 0,
429 "colorkey_val", 0, 0xffffff);
430 priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
431 "colorkey_alpha", 0, 0xffffff);
432 priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
434 armada_drm_colorkey_enum_list,
435 ARRAY_SIZE(armada_drm_colorkey_enum_list));
436 priv->brightness_prop = drm_property_create_range(dev, 0,
437 "brightness", 0, 256 + 255);
438 priv->contrast_prop = drm_property_create_range(dev, 0,
439 "contrast", 0, 0x7fff);
440 priv->saturation_prop = drm_property_create_range(dev, 0,
441 "saturation", 0, 0x7fff);
443 if (!priv->colorkey_prop)
449 int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
451 struct armada_private *priv = dev->dev_private;
452 struct drm_mode_object *mobj;
453 struct armada_ovl_plane *dplane;
456 ret = armada_overlay_create_properties(dev);
460 dplane = kzalloc(sizeof(*dplane), GFP_KERNEL);
464 ret = armada_drm_plane_init(&dplane->base);
470 dplane->vbl.work.fn = armada_ovl_plane_work;
472 ret = drm_universal_plane_init(dev, &dplane->base.base, crtcs,
473 &armada_ovl_plane_funcs,
475 ARRAY_SIZE(armada_ovl_formats),
476 DRM_PLANE_TYPE_OVERLAY, NULL);
482 dplane->prop.colorkey_yr = 0xfefefe00;
483 dplane->prop.colorkey_ug = 0x01010100;
484 dplane->prop.colorkey_vb = 0x01010100;
485 dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB) |
486 CFG_ALPHAM_GRA | CFG_ALPHA(0);
487 dplane->prop.colorkey_enable = ADV_GRACOLORKEY;
488 dplane->prop.brightness = 0;
489 dplane->prop.contrast = 0x4000;
490 dplane->prop.saturation = 0x4000;
492 mobj = &dplane->base.base.base;
493 drm_object_attach_property(mobj, priv->colorkey_prop,
495 drm_object_attach_property(mobj, priv->colorkey_min_prop,
497 drm_object_attach_property(mobj, priv->colorkey_max_prop,
499 drm_object_attach_property(mobj, priv->colorkey_val_prop,
501 drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
503 drm_object_attach_property(mobj, priv->colorkey_mode_prop,
505 drm_object_attach_property(mobj, priv->brightness_prop, 256);
506 drm_object_attach_property(mobj, priv->contrast_prop,
507 dplane->prop.contrast);
508 drm_object_attach_property(mobj, priv->saturation_prop,
509 dplane->prop.saturation);