2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/component.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_plane_helper.h>
16 #include "armada_crtc.h"
17 #include "armada_drm.h"
18 #include "armada_fb.h"
19 #include "armada_gem.h"
20 #include "armada_hw.h"
22 struct armada_frame_work {
23 struct armada_plane_work work;
24 struct drm_pending_vblank_event *event;
25 struct armada_regs regs[4];
26 struct drm_framebuffer *old_fb;
37 static const uint32_t armada_primary_formats[] = {
55 * A note about interlacing. Let's consider HDMI 1920x1080i.
56 * The timing parameters we have from X are:
57 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
58 * 1920 2448 2492 2640 1080 1084 1094 1125
59 * Which get translated to:
60 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
61 * 1920 2448 2492 2640 540 542 547 562
63 * This is how it is defined by CEA-861-D - line and pixel numbers are
64 * referenced to the rising edge of VSYNC and HSYNC. Total clocks per
65 * line: 2640. The odd frame, the first active line is at line 21, and
66 * the even frame, the first active line is 584.
68 * LN: 560 561 562 563 567 568 569
69 * DE: ~~~|____________________________//__________________________
70 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
71 * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
72 * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge).
74 * LN: 1123 1124 1125 1 5 6 7
75 * DE: ~~~|____________________________//__________________________
76 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
77 * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
80 * The Armada LCD Controller line and pixel numbers are, like X timings,
81 * referenced to the top left of the active frame.
83 * So, translating these to our LCD controller:
84 * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
85 * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
86 * Note: Vsync front porch remains constant!
89 * vtotal = mode->crtc_vtotal + 1;
90 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
91 * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
93 * vtotal = mode->crtc_vtotal;
94 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
95 * vhorizpos = mode->crtc_hsync_start;
97 * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
99 * So, we need to reprogram these registers on each vsync event:
100 * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
102 * Note: we do not use the frame done interrupts because these appear
103 * to happen too early, and lead to jitter on the display (presumably
104 * they occur at the end of the last active line, before the vsync back
105 * porch, which we're reprogramming.)
109 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
111 while (regs->offset != ~0) {
112 void __iomem *reg = dcrtc->base + regs->offset;
117 val &= readl_relaxed(reg);
118 writel_relaxed(val | regs->val, reg);
123 #define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON)
125 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
129 dumb_ctrl = dcrtc->cfg_dumb_ctrl;
131 if (!dpms_blanked(dcrtc->dpms))
132 dumb_ctrl |= CFG_DUMB_ENA;
135 * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
136 * be using SPI or GPIO. If we set this to DUMB_BLANK, we will
137 * force LCD_D[23:0] to output blank color, overriding the GPIO or
138 * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode.
140 if (dpms_blanked(dcrtc->dpms) &&
141 (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
142 dumb_ctrl &= ~DUMB_MASK;
143 dumb_ctrl |= DUMB_BLANK;
147 * The documentation doesn't indicate what the normal state of
148 * the sync signals are. Sebastian Hesselbart kindly probed
149 * these signals on his board to determine their state.
151 * The non-inverted state of the sync signals is active high.
152 * Setting these bits makes the appropriate signal active low.
154 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
155 dumb_ctrl |= CFG_INV_CSYNC;
156 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
157 dumb_ctrl |= CFG_INV_HSYNC;
158 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
159 dumb_ctrl |= CFG_INV_VSYNC;
161 if (dcrtc->dumb_ctrl != dumb_ctrl) {
162 dcrtc->dumb_ctrl = dumb_ctrl;
163 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
167 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
168 int x, int y, struct armada_regs *regs, bool interlaced)
170 struct armada_gem_object *obj = drm_fb_obj(fb);
171 unsigned pitch = fb->pitches[0];
172 unsigned offset = y * pitch + x * fb->bits_per_pixel / 8;
173 uint32_t addr_odd, addr_even;
176 DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
177 pitch, x, y, fb->bits_per_pixel);
179 addr_odd = addr_even = obj->dev_addr + offset;
186 /* write offset, base, and pitch */
187 armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
188 armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
189 armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
194 static void armada_drm_plane_work_run(struct armada_crtc *dcrtc,
195 struct armada_plane *plane)
197 struct armada_plane_work *work = xchg(&plane->work, NULL);
199 /* Handle any pending frame work. */
201 work->fn(dcrtc, plane, work);
202 drm_crtc_vblank_put(&dcrtc->crtc);
205 wake_up(&plane->frame_wait);
208 int armada_drm_plane_work_queue(struct armada_crtc *dcrtc,
209 struct armada_plane *plane, struct armada_plane_work *work)
213 ret = drm_crtc_vblank_get(&dcrtc->crtc);
215 DRM_ERROR("failed to acquire vblank counter\n");
219 ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0;
221 drm_crtc_vblank_put(&dcrtc->crtc);
226 int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout)
228 return wait_event_timeout(plane->frame_wait, !plane->work, timeout);
231 struct armada_plane_work *armada_drm_plane_work_cancel(
232 struct armada_crtc *dcrtc, struct armada_plane *plane)
234 struct armada_plane_work *work = xchg(&plane->work, NULL);
237 drm_crtc_vblank_put(&dcrtc->crtc);
242 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
243 struct armada_frame_work *work)
245 struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary);
247 return armada_drm_plane_work_queue(dcrtc, plane, &work->work);
250 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc,
251 struct armada_plane *plane, struct armada_plane_work *work)
253 struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work);
254 struct drm_device *dev = dcrtc->crtc.dev;
257 spin_lock_irqsave(&dcrtc->irq_lock, flags);
258 armada_drm_crtc_update_regs(dcrtc, fwork->regs);
259 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
262 spin_lock_irqsave(&dev->event_lock, flags);
263 drm_crtc_send_vblank_event(&dcrtc->crtc, fwork->event);
264 spin_unlock_irqrestore(&dev->event_lock, flags);
267 /* Finally, queue the process-half of the cleanup. */
268 __armada_drm_queue_unref_work(dcrtc->crtc.dev, fwork->old_fb);
272 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
273 struct drm_framebuffer *fb, bool force)
275 struct armada_frame_work *work;
281 /* Display is disabled, so just drop the old fb */
282 drm_framebuffer_unreference(fb);
286 work = kmalloc(sizeof(*work), GFP_KERNEL);
289 work->work.fn = armada_drm_crtc_complete_frame_work;
292 armada_reg_queue_end(work->regs, i);
294 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
301 * Oops - just drop the reference immediately and hope for
302 * the best. The worst that will happen is the buffer gets
303 * reused before it has finished being displayed.
305 drm_framebuffer_unreference(fb);
308 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
310 struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary);
313 * Tell the DRM core that vblank IRQs aren't going to happen for
314 * a while. This cleans up any pending vblank events for us.
316 drm_crtc_vblank_off(&dcrtc->crtc);
317 armada_drm_plane_work_run(dcrtc, plane);
320 void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
325 void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
330 /* The mode_config.mutex will be held for this call */
331 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
333 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
335 if (dpms_blanked(dcrtc->dpms) != dpms_blanked(dpms)) {
336 if (dpms_blanked(dpms))
337 armada_drm_vblank_off(dcrtc);
338 else if (!IS_ERR(dcrtc->clk))
339 WARN_ON(clk_prepare_enable(dcrtc->clk));
341 armada_drm_crtc_update(dcrtc);
342 if (!dpms_blanked(dpms))
343 drm_crtc_vblank_on(&dcrtc->crtc);
344 else if (!IS_ERR(dcrtc->clk))
345 clk_disable_unprepare(dcrtc->clk);
346 } else if (dcrtc->dpms != dpms) {
352 * Prepare for a mode set. Turn off overlay to ensure that we don't end
353 * up with the overlay size being bigger than the active screen size.
354 * We rely upon X refreshing this state after the mode set has completed.
356 * The mode_config.mutex will be held for this call
358 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
360 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
361 struct drm_plane *plane;
364 * If we have an overlay plane associated with this CRTC, disable
365 * it before the modeset to avoid its coordinates being outside
366 * the new mode parameters.
368 plane = dcrtc->plane;
370 drm_plane_force_disable(plane);
373 /* The mode_config.mutex will be held for this call */
374 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
376 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
378 if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
379 dcrtc->dpms = DRM_MODE_DPMS_ON;
380 armada_drm_crtc_update(dcrtc);
384 /* The mode_config.mutex will be held for this call */
385 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
386 const struct drm_display_mode *mode, struct drm_display_mode *adj)
388 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
391 /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
392 if (!dcrtc->variant->has_spu_adv_reg &&
393 adj->flags & DRM_MODE_FLAG_INTERLACE)
396 /* Check whether the display mode is possible */
397 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
404 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
406 void __iomem *base = dcrtc->base;
407 struct drm_plane *ovl_plane;
409 if (stat & DMA_FF_UNDERFLOW)
410 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
411 if (stat & GRA_FF_UNDERFLOW)
412 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
414 if (stat & VSYNC_IRQ)
415 drm_crtc_handle_vblank(&dcrtc->crtc);
417 spin_lock(&dcrtc->irq_lock);
418 ovl_plane = dcrtc->plane;
420 struct armada_plane *plane = drm_to_armada_plane(ovl_plane);
421 armada_drm_plane_work_run(dcrtc, plane);
424 if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
425 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
428 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
429 writel_relaxed(dcrtc->v[i].spu_v_h_total,
430 base + LCD_SPUT_V_H_TOTAL);
432 val = readl_relaxed(base + LCD_SPU_ADV_REG);
433 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
434 val |= dcrtc->v[i].spu_adv_reg;
435 writel_relaxed(val, base + LCD_SPU_ADV_REG);
438 if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
439 writel_relaxed(dcrtc->cursor_hw_pos,
440 base + LCD_SPU_HWC_OVSA_HPXL_VLN);
441 writel_relaxed(dcrtc->cursor_hw_sz,
442 base + LCD_SPU_HWC_HPXL_VLN);
443 armada_updatel(CFG_HWC_ENA,
444 CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
445 base + LCD_SPU_DMA_CTRL0);
446 dcrtc->cursor_update = false;
447 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
450 spin_unlock(&dcrtc->irq_lock);
452 if (stat & GRA_FRAME_IRQ) {
453 struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary);
454 armada_drm_plane_work_run(dcrtc, plane);
458 static irqreturn_t armada_drm_irq(int irq, void *arg)
460 struct armada_crtc *dcrtc = arg;
461 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
464 * This is rediculous - rather than writing bits to clear, we
465 * have to set the actual status register value. This is racy.
467 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
469 /* Mask out those interrupts we haven't enabled */
470 v = stat & dcrtc->irq_ena;
472 if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
473 armada_drm_crtc_irq(dcrtc, stat);
479 /* These are locked by dev->vbl_lock */
480 void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
482 if (dcrtc->irq_ena & mask) {
483 dcrtc->irq_ena &= ~mask;
484 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
488 void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
490 if ((dcrtc->irq_ena & mask) != mask) {
491 dcrtc->irq_ena |= mask;
492 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
493 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
494 writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
498 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
500 struct drm_display_mode *adj = &dcrtc->crtc.mode;
503 if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
504 val |= CFG_CSC_YUV_CCIR709;
505 if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
506 val |= CFG_CSC_RGB_STUDIO;
509 * In auto mode, set the colorimetry, based upon the HDMI spec.
510 * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
511 * ITU601. It may be more appropriate to set this depending on
512 * the source - but what if the graphic frame is YUV and the
513 * video frame is RGB?
515 if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
516 !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
517 (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
518 if (dcrtc->csc_yuv_mode == CSC_AUTO)
519 val |= CFG_CSC_YUV_CCIR709;
523 * We assume we're connected to a TV-like device, so the YUV->RGB
524 * conversion should produce a limited range. We should set this
525 * depending on the connectors attached to this CRTC, and what
526 * kind of device they report being connected.
528 if (dcrtc->csc_rgb_mode == CSC_AUTO)
529 val |= CFG_CSC_RGB_STUDIO;
534 /* The mode_config.mutex will be held for this call */
535 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
536 struct drm_display_mode *mode, struct drm_display_mode *adj,
537 int x, int y, struct drm_framebuffer *old_fb)
539 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
540 struct armada_regs regs[17];
541 uint32_t lm, rm, tm, bm, val, sclk;
546 drm_framebuffer_reference(crtc->primary->fb);
548 interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
550 i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb,
551 x, y, regs, interlaced);
553 rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
554 lm = adj->crtc_htotal - adj->crtc_hsync_end;
555 bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
556 tm = adj->crtc_vtotal - adj->crtc_vsync_end;
558 DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
560 adj->crtc_hsync_start,
562 adj->crtc_htotal, lm, rm);
563 DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
565 adj->crtc_vsync_start,
567 adj->crtc_vtotal, tm, bm);
569 /* Wait for pending flips to complete */
570 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
571 MAX_SCHEDULE_TIMEOUT);
573 drm_crtc_vblank_off(crtc);
575 val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
576 if (val != dcrtc->dumb_ctrl) {
577 dcrtc->dumb_ctrl = val;
578 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
582 * If we are blanked, we would have disabled the clock. Re-enable
583 * it so that compute_clock() does the right thing.
585 if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms))
586 WARN_ON(clk_prepare_enable(dcrtc->clk));
588 /* Now compute the divider for real */
589 dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
591 /* Ensure graphic fifo is enabled */
592 armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
593 armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
595 if (interlaced ^ dcrtc->interlaced) {
596 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
597 drm_crtc_vblank_get(&dcrtc->crtc);
599 drm_crtc_vblank_put(&dcrtc->crtc);
600 dcrtc->interlaced = interlaced;
603 spin_lock_irqsave(&dcrtc->irq_lock, flags);
605 /* Even interlaced/progressive frame */
606 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
608 dcrtc->v[1].spu_v_porch = tm << 16 | bm;
609 val = adj->crtc_hsync_start;
610 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
611 dcrtc->variant->spu_adv_reg;
614 /* Odd interlaced frame */
615 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
617 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
618 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
619 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
620 dcrtc->variant->spu_adv_reg;
622 dcrtc->v[0] = dcrtc->v[1];
625 val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
627 armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
628 armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN);
629 armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN);
630 armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
631 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
632 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
635 if (dcrtc->variant->has_spu_adv_reg) {
636 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
637 ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
638 ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
641 val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
642 val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
643 val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
645 if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
646 val |= CFG_PALETTE_ENA;
649 val |= CFG_GRA_FTOGGLE;
651 armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT |
652 CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
653 CFG_SWAPYU | CFG_YUV2RGB) |
654 CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
657 val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
658 armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
660 val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
661 armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
662 armada_reg_queue_end(regs, i);
664 armada_drm_crtc_update_regs(dcrtc, regs);
665 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
667 armada_drm_crtc_update(dcrtc);
669 drm_crtc_vblank_on(crtc);
670 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
675 /* The mode_config.mutex will be held for this call */
676 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
677 struct drm_framebuffer *old_fb)
679 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
680 struct armada_regs regs[4];
683 i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
685 armada_reg_queue_end(regs, i);
687 /* Wait for pending flips to complete */
688 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
689 MAX_SCHEDULE_TIMEOUT);
691 /* Take a reference to the new fb as we're using it */
692 drm_framebuffer_reference(crtc->primary->fb);
694 /* Update the base in the CRTC */
695 armada_drm_crtc_update_regs(dcrtc, regs);
697 /* Drop our previously held reference */
698 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
703 void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc,
704 struct drm_plane *plane)
706 u32 sram_para1, dma_ctrl0_mask;
709 * Drop our reference on any framebuffer attached to this plane.
710 * We don't need to NULL this out as drm_plane_force_disable(),
711 * and __setplane_internal() will do so for an overlay plane, and
712 * __drm_helper_disable_unused_functions() will do so for the
716 drm_framebuffer_unreference(plane->fb);
718 /* Power down the Y/U/V FIFOs */
719 sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
721 /* Power down most RAMs and FIFOs if this is the primary plane */
722 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
723 sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
724 CFG_PDWN32x32 | CFG_PDWN64x66;
725 dma_ctrl0_mask = CFG_GRA_ENA;
727 dma_ctrl0_mask = CFG_DMA_ENA;
730 spin_lock_irq(&dcrtc->irq_lock);
731 armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0);
732 spin_unlock_irq(&dcrtc->irq_lock);
734 armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1);
737 /* The mode_config.mutex will be held for this call */
738 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
740 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
742 armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
743 armada_drm_crtc_plane_disable(dcrtc, crtc->primary);
746 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
747 .dpms = armada_drm_crtc_dpms,
748 .prepare = armada_drm_crtc_prepare,
749 .commit = armada_drm_crtc_commit,
750 .mode_fixup = armada_drm_crtc_mode_fixup,
751 .mode_set = armada_drm_crtc_mode_set,
752 .mode_set_base = armada_drm_crtc_mode_set_base,
753 .disable = armada_drm_crtc_disable,
756 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
757 unsigned stride, unsigned width, unsigned height)
762 addr = SRAM_HWC32_RAM1;
763 for (y = 0; y < height; y++) {
764 uint32_t *p = &pix[y * stride];
767 for (x = 0; x < width; x++, p++) {
770 val = (val & 0xff00ff00) |
771 (val & 0x000000ff) << 16 |
772 (val & 0x00ff0000) >> 16;
775 base + LCD_SPU_SRAM_WRDAT);
776 writel_relaxed(addr | SRAM_WRITE,
777 base + LCD_SPU_SRAM_CTRL);
778 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
780 if ((addr & 0x00ff) == 0)
782 if ((addr & 0x30ff) == 0)
783 addr = SRAM_HWC32_RAM2;
788 static void armada_drm_crtc_cursor_tran(void __iomem *base)
792 for (addr = 0; addr < 256; addr++) {
793 /* write the default value */
794 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
795 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
796 base + LCD_SPU_SRAM_CTRL);
800 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
802 uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
803 uint32_t yoff, yscr, h = dcrtc->cursor_h;
807 * Calculate the visible width and height of the cursor,
808 * screen position, and the position in the cursor bitmap.
810 if (dcrtc->cursor_x < 0) {
811 xoff = -dcrtc->cursor_x;
814 } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
816 xscr = dcrtc->cursor_x;
817 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
820 xscr = dcrtc->cursor_x;
823 if (dcrtc->cursor_y < 0) {
824 yoff = -dcrtc->cursor_y;
827 } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
829 yscr = dcrtc->cursor_y;
830 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
833 yscr = dcrtc->cursor_y;
836 /* On interlaced modes, the vertical cursor size must be halved */
838 if (dcrtc->interlaced) {
844 if (!dcrtc->cursor_obj || !h || !w) {
845 spin_lock_irq(&dcrtc->irq_lock);
846 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
847 dcrtc->cursor_update = false;
848 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
849 spin_unlock_irq(&dcrtc->irq_lock);
853 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
854 armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
855 dcrtc->base + LCD_SPU_SRAM_PARA1);
858 * Initialize the transparency if the SRAM was powered down.
859 * We must also reload the cursor data as well.
861 if (!(para1 & CFG_CSB_256x32)) {
862 armada_drm_crtc_cursor_tran(dcrtc->base);
866 if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
867 spin_lock_irq(&dcrtc->irq_lock);
868 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
869 dcrtc->cursor_update = false;
870 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
871 spin_unlock_irq(&dcrtc->irq_lock);
875 struct armada_gem_object *obj = dcrtc->cursor_obj;
877 /* Set the top-left corner of the cursor image */
879 pix += yoff * s + xoff;
880 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
883 /* Reload the cursor position, size and enable in the IRQ handler */
884 spin_lock_irq(&dcrtc->irq_lock);
885 dcrtc->cursor_hw_pos = yscr << 16 | xscr;
886 dcrtc->cursor_hw_sz = h << 16 | w;
887 dcrtc->cursor_update = true;
888 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
889 spin_unlock_irq(&dcrtc->irq_lock);
894 static void cursor_update(void *data)
896 armada_drm_crtc_cursor_update(data, true);
899 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
900 struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
902 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
903 struct armada_gem_object *obj = NULL;
906 /* If no cursor support, replicate drm's return value */
907 if (!dcrtc->variant->has_spu_adv_reg)
910 if (handle && w > 0 && h > 0) {
911 /* maximum size is 64x32 or 32x64 */
912 if (w > 64 || h > 64 || (w > 32 && h > 32))
915 obj = armada_gem_object_lookup(file, handle);
919 /* Must be a kernel-mapped object */
921 drm_gem_object_unreference_unlocked(&obj->obj);
925 if (obj->obj.size < w * h * 4) {
926 DRM_ERROR("buffer is too small\n");
927 drm_gem_object_unreference_unlocked(&obj->obj);
932 if (dcrtc->cursor_obj) {
933 dcrtc->cursor_obj->update = NULL;
934 dcrtc->cursor_obj->update_data = NULL;
935 drm_gem_object_unreference_unlocked(&dcrtc->cursor_obj->obj);
937 dcrtc->cursor_obj = obj;
940 ret = armada_drm_crtc_cursor_update(dcrtc, true);
942 obj->update_data = dcrtc;
943 obj->update = cursor_update;
949 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
951 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
954 /* If no cursor support, replicate drm's return value */
955 if (!dcrtc->variant->has_spu_adv_reg)
960 ret = armada_drm_crtc_cursor_update(dcrtc, false);
965 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
967 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
968 struct armada_private *priv = crtc->dev->dev_private;
970 if (dcrtc->cursor_obj)
971 drm_gem_object_unreference_unlocked(&dcrtc->cursor_obj->obj);
973 priv->dcrtc[dcrtc->num] = NULL;
974 drm_crtc_cleanup(&dcrtc->crtc);
976 if (!IS_ERR(dcrtc->clk))
977 clk_disable_unprepare(dcrtc->clk);
979 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
981 of_node_put(dcrtc->crtc.port);
987 * The mode_config lock is held here, to prevent races between this
990 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
991 struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
993 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
994 struct armada_frame_work *work;
998 /* We don't support changing the pixel format */
999 if (fb->pixel_format != crtc->primary->fb->pixel_format)
1002 work = kmalloc(sizeof(*work), GFP_KERNEL);
1006 work->work.fn = armada_drm_crtc_complete_frame_work;
1007 work->event = event;
1008 work->old_fb = dcrtc->crtc.primary->fb;
1010 i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
1012 armada_reg_queue_end(work->regs, i);
1015 * Ensure that we hold a reference on the new framebuffer.
1016 * This has to match the behaviour in mode_set.
1018 drm_framebuffer_reference(fb);
1020 ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
1022 /* Undo our reference above */
1023 drm_framebuffer_unreference(fb);
1029 * Don't take a reference on the new framebuffer;
1030 * drm_mode_page_flip_ioctl() has already grabbed a reference and
1031 * will _not_ drop that reference on successful return from this
1032 * function. Simply mark this new framebuffer as the current one.
1034 dcrtc->crtc.primary->fb = fb;
1037 * Finally, if the display is blanked, we won't receive an
1038 * interrupt, so complete it now.
1040 if (dpms_blanked(dcrtc->dpms))
1041 armada_drm_plane_work_run(dcrtc, drm_to_armada_plane(dcrtc->crtc.primary));
1047 armada_drm_crtc_set_property(struct drm_crtc *crtc,
1048 struct drm_property *property, uint64_t val)
1050 struct armada_private *priv = crtc->dev->dev_private;
1051 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1052 bool update_csc = false;
1054 if (property == priv->csc_yuv_prop) {
1055 dcrtc->csc_yuv_mode = val;
1057 } else if (property == priv->csc_rgb_prop) {
1058 dcrtc->csc_rgb_mode = val;
1065 val = dcrtc->spu_iopad_ctrl |
1066 armada_drm_crtc_calculate_csc(dcrtc);
1067 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1073 static const struct drm_crtc_funcs armada_crtc_funcs = {
1074 .cursor_set = armada_drm_crtc_cursor_set,
1075 .cursor_move = armada_drm_crtc_cursor_move,
1076 .destroy = armada_drm_crtc_destroy,
1077 .set_config = drm_crtc_helper_set_config,
1078 .page_flip = armada_drm_crtc_page_flip,
1079 .set_property = armada_drm_crtc_set_property,
1082 static const struct drm_plane_funcs armada_primary_plane_funcs = {
1083 .update_plane = drm_primary_helper_update,
1084 .disable_plane = drm_primary_helper_disable,
1085 .destroy = drm_primary_helper_destroy,
1088 int armada_drm_plane_init(struct armada_plane *plane)
1090 init_waitqueue_head(&plane->frame_wait);
1095 static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1096 { CSC_AUTO, "Auto" },
1097 { CSC_YUV_CCIR601, "CCIR601" },
1098 { CSC_YUV_CCIR709, "CCIR709" },
1101 static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1102 { CSC_AUTO, "Auto" },
1103 { CSC_RGB_COMPUTER, "Computer system" },
1104 { CSC_RGB_STUDIO, "Studio" },
1107 static int armada_drm_crtc_create_properties(struct drm_device *dev)
1109 struct armada_private *priv = dev->dev_private;
1111 if (priv->csc_yuv_prop)
1114 priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1115 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1116 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1117 priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1118 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1119 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1121 if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1127 static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1128 struct resource *res, int irq, const struct armada_variant *variant,
1129 struct device_node *port)
1131 struct armada_private *priv = drm->dev_private;
1132 struct armada_crtc *dcrtc;
1133 struct armada_plane *primary;
1137 ret = armada_drm_crtc_create_properties(drm);
1141 base = devm_ioremap_resource(dev, res);
1143 return PTR_ERR(base);
1145 dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1147 DRM_ERROR("failed to allocate Armada crtc\n");
1151 if (dev != drm->dev)
1152 dev_set_drvdata(dev, dcrtc);
1154 dcrtc->variant = variant;
1156 dcrtc->num = drm->mode_config.num_crtc;
1157 dcrtc->clk = ERR_PTR(-EINVAL);
1158 dcrtc->csc_yuv_mode = CSC_AUTO;
1159 dcrtc->csc_rgb_mode = CSC_AUTO;
1160 dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1161 dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1162 spin_lock_init(&dcrtc->irq_lock);
1163 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1165 /* Initialize some registers which we don't otherwise set */
1166 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1167 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1168 writel_relaxed(dcrtc->spu_iopad_ctrl,
1169 dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1170 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1171 writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1172 CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1173 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1174 writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1175 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN);
1176 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1177 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1179 ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1184 if (dcrtc->variant->init) {
1185 ret = dcrtc->variant->init(dcrtc, dev);
1190 /* Ensure AXI pipeline is enabled */
1191 armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1193 priv->dcrtc[dcrtc->num] = dcrtc;
1195 dcrtc->crtc.port = port;
1197 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
1203 ret = armada_drm_plane_init(primary);
1209 ret = drm_universal_plane_init(drm, &primary->base, 0,
1210 &armada_primary_plane_funcs,
1211 armada_primary_formats,
1212 ARRAY_SIZE(armada_primary_formats),
1213 DRM_PLANE_TYPE_PRIMARY, NULL);
1219 ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL,
1220 &armada_crtc_funcs, NULL);
1224 drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1226 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1227 dcrtc->csc_yuv_mode);
1228 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1229 dcrtc->csc_rgb_mode);
1231 return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1234 primary->base.funcs->destroy(&primary->base);
1242 armada_lcd_bind(struct device *dev, struct device *master, void *data)
1244 struct platform_device *pdev = to_platform_device(dev);
1245 struct drm_device *drm = data;
1246 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1247 int irq = platform_get_irq(pdev, 0);
1248 const struct armada_variant *variant;
1249 struct device_node *port = NULL;
1254 if (!dev->of_node) {
1255 const struct platform_device_id *id;
1257 id = platform_get_device_id(pdev);
1261 variant = (const struct armada_variant *)id->driver_data;
1263 const struct of_device_id *match;
1264 struct device_node *np, *parent = dev->of_node;
1266 match = of_match_device(dev->driver->of_match_table, dev);
1270 np = of_get_child_by_name(parent, "ports");
1273 port = of_get_child_by_name(parent, "port");
1276 dev_err(dev, "no port node found in %s\n",
1281 variant = match->data;
1284 return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1288 armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1290 struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1292 armada_drm_crtc_destroy(&dcrtc->crtc);
1295 static const struct component_ops armada_lcd_ops = {
1296 .bind = armada_lcd_bind,
1297 .unbind = armada_lcd_unbind,
1300 static int armada_lcd_probe(struct platform_device *pdev)
1302 return component_add(&pdev->dev, &armada_lcd_ops);
1305 static int armada_lcd_remove(struct platform_device *pdev)
1307 component_del(&pdev->dev, &armada_lcd_ops);
1311 static struct of_device_id armada_lcd_of_match[] = {
1313 .compatible = "marvell,dove-lcd",
1314 .data = &armada510_ops,
1318 MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1320 static const struct platform_device_id armada_lcd_platform_ids[] = {
1322 .name = "armada-lcd",
1323 .driver_data = (unsigned long)&armada510_ops,
1325 .name = "armada-510-lcd",
1326 .driver_data = (unsigned long)&armada510_ops,
1330 MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1332 struct platform_driver armada_lcd_platform_driver = {
1333 .probe = armada_lcd_probe,
1334 .remove = armada_lcd_remove,
1336 .name = "armada-lcd",
1337 .owner = THIS_MODULE,
1338 .of_match_table = armada_lcd_of_match,
1340 .id_table = armada_lcd_platform_ids,