1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Russell King
5 * Armada 510 (aka Dove) variant support
9 #include <drm/drm_probe_helper.h>
10 #include "armada_crtc.h"
11 #include "armada_drm.h"
12 #include "armada_hw.h"
14 struct armada510_variant_data {
19 static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev)
21 struct armada510_variant_data *v;
25 v = devm_kzalloc(dev, sizeof(*v), GFP_KERNEL);
29 dcrtc->variant_data = v;
32 struct property *prop;
35 of_property_for_each_string(dev->of_node, "clock-names", prop,
37 if (!strcmp(s, "ext_ref_clk0"))
39 else if (!strcmp(s, "ext_ref_clk1"))
41 else if (!strcmp(s, "plldivider"))
43 else if (!strcmp(s, "axibus"))
48 clk = devm_clk_get(dev, s);
50 return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER :
55 clk = devm_clk_get(dev, "ext_ref_clk1");
57 return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER :
64 * Lower the watermark so to eliminate jitter at higher bandwidths.
65 * Disable SRAM read wait state to avoid system hang with external
68 armada_updatel(CFG_DMA_WM(0x20), CFG_SRAM_WAIT | CFG_DMA_WM_MASK,
69 dcrtc->base + LCD_CFG_RDREG4F);
71 /* Initialise SPU register */
72 writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
73 dcrtc->base + LCD_SPU_ADV_REG);
78 static const u32 armada510_clk_sels[] = {
85 static const struct armada_clocking_params armada510_clocking = {
86 /* HDMI requires -0.6%..+0.5% */
87 .permillage_min = 994,
88 .permillage_max = 1005,
89 .settable = BIT(0) | BIT(1),
90 .div_max = SCLK_510_INT_DIV_MASK,
94 * Armada510 specific SCLK register selection.
95 * This gets called with sclk = NULL to test whether the mode is
96 * supportable, and again with sclk != NULL to set the clocks up for
97 * that. The former can return an error, but the latter is expected
100 static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc,
101 const struct drm_display_mode *mode, uint32_t *sclk)
103 struct armada510_variant_data *v = dcrtc->variant_data;
104 unsigned long desired_khz = mode->crtc_clock;
105 struct armada_clk_result res;
108 idx = armada_crtc_select_clock(dcrtc, &res, &armada510_clocking,
109 v->clks, ARRAY_SIZE(v->clks),
114 ret = clk_prepare_enable(res.clk);
119 clk_set_rate(res.clk, res.desired_clk_hz);
121 *sclk = res.div | armada510_clk_sels[idx];
123 /* We are now using this clock */
124 v->sel_clk = res.clk;
125 swap(dcrtc->clk, res.clk);
128 clk_disable_unprepare(res.clk);
133 static void armada510_crtc_disable(struct armada_crtc *dcrtc)
136 clk_disable_unprepare(dcrtc->clk);
141 static void armada510_crtc_enable(struct armada_crtc *dcrtc,
142 const struct drm_display_mode *mode)
144 struct armada510_variant_data *v = dcrtc->variant_data;
146 if (!dcrtc->clk && v->sel_clk) {
147 if (!WARN_ON(clk_prepare_enable(v->sel_clk)))
148 dcrtc->clk = v->sel_clk;
152 const struct armada_variant armada510_ops = {
153 .has_spu_adv_reg = true,
154 .init = armada510_crtc_init,
155 .compute_clock = armada510_crtc_compute_clock,
156 .disable = armada510_crtc_disable,
157 .enable = armada510_crtc_enable,