2 * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
5 * This program is free software and is provided to you under the terms of the
6 * GNU General Public License version 2 as published by the Free Software
7 * Foundation, and any use by you of this program is subject to the terms
10 * ARM Mali DP500/DP550/DP650 hardware manipulation routines. This is where
11 * the difference between various versions of the hardware is being dealt with
12 * in an attempt to provide to the rest of the driver code a unified view
15 #include <linux/types.h>
18 #include <video/videomode.h>
19 #include <video/display_timing.h>
21 #include "malidp_drv.h"
22 #include "malidp_hw.h"
24 static const struct malidp_input_format malidp500_de_formats[] = {
25 /* fourcc, layers supporting the format, internal id */
26 { DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 0 },
27 { DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 1 },
28 { DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 2 },
29 { DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 3 },
30 { DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 4 },
31 { DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 5 },
32 { DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 6 },
33 { DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 7 },
34 { DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 8 },
35 { DRM_FORMAT_ABGR1555, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 9 },
36 { DRM_FORMAT_RGB565, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 10 },
37 { DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 11 },
38 { DRM_FORMAT_UYVY, DE_VIDEO1, 12 },
39 { DRM_FORMAT_YUYV, DE_VIDEO1, 13 },
40 { DRM_FORMAT_NV12, DE_VIDEO1, 14 },
41 { DRM_FORMAT_YUV420, DE_VIDEO1, 15 },
44 #define MALIDP_ID(__group, __format) \
45 ((((__group) & 0x7) << 3) | ((__format) & 0x7))
47 #define MALIDP_COMMON_FORMATS \
48 /* fourcc, layers supporting the format, internal id */ \
49 { DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 0) }, \
50 { DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 1) }, \
51 { DRM_FORMAT_RGBA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 2) }, \
52 { DRM_FORMAT_BGRA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 3) }, \
53 { DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 0) }, \
54 { DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 1) }, \
55 { DRM_FORMAT_RGBA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 2) }, \
56 { DRM_FORMAT_BGRA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 3) }, \
57 { DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 0) }, \
58 { DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 1) }, \
59 { DRM_FORMAT_RGBX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 2) }, \
60 { DRM_FORMAT_BGRX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 3) }, \
61 { DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 0) }, \
62 { DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 1) }, \
63 { DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 0) }, \
64 { DRM_FORMAT_ABGR1555, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 1) }, \
65 { DRM_FORMAT_RGB565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 2) }, \
66 { DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 3) }, \
67 { DRM_FORMAT_YUYV, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 2) }, \
68 { DRM_FORMAT_UYVY, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 3) }, \
69 { DRM_FORMAT_NV12, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 6) }, \
70 { DRM_FORMAT_YUV420, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 7) }
72 static const struct malidp_input_format malidp550_de_formats[] = {
73 MALIDP_COMMON_FORMATS,
76 static const struct malidp_layer malidp500_layers[] = {
77 { DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE },
78 { DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE },
79 { DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE },
82 static const struct malidp_layer malidp550_layers[] = {
83 { DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE },
84 { DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE },
85 { DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE },
86 { DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE },
89 #define MALIDP_DE_DEFAULT_PREFETCH_START 5
91 static int malidp500_query_hw(struct malidp_hw_device *hwdev)
93 u32 conf = malidp_hw_read(hwdev, MALIDP500_CONFIG_ID);
94 /* bit 4 of the CONFIG_ID register holds the line size multiplier */
95 u8 ln_size_mult = conf & 0x10 ? 2 : 1;
97 hwdev->min_line_size = 2;
98 hwdev->max_line_size = SZ_2K * ln_size_mult;
99 hwdev->rotation_memory[0] = SZ_1K * 64 * ln_size_mult;
100 hwdev->rotation_memory[1] = 0; /* no second rotation memory bank */
105 static void malidp500_enter_config_mode(struct malidp_hw_device *hwdev)
107 u32 status, count = 100;
109 malidp_hw_setbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
111 status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
112 if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
115 * entering config mode can take as long as the rendering
116 * of a full frame, hence the long sleep here
118 usleep_range(1000, 10000);
121 WARN(count == 0, "timeout while entering config mode");
124 static void malidp500_leave_config_mode(struct malidp_hw_device *hwdev)
126 u32 status, count = 100;
128 malidp_hw_clearbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
130 status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
131 if ((status & MALIDP500_DC_CONFIG_REQ) == 0)
133 usleep_range(100, 1000);
136 WARN(count == 0, "timeout while leaving config mode");
139 static bool malidp500_in_config_mode(struct malidp_hw_device *hwdev)
143 status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
144 if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
150 static void malidp500_set_config_valid(struct malidp_hw_device *hwdev)
152 malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID);
155 static void malidp500_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
159 malidp_hw_clearbits(hwdev, MALIDP500_DC_CLEAR_MASK, MALIDP500_DC_CONTROL);
160 if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
161 val |= MALIDP500_HSYNCPOL;
162 if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
163 val |= MALIDP500_VSYNCPOL;
164 val |= MALIDP_DE_DEFAULT_PREFETCH_START;
165 malidp_hw_setbits(hwdev, val, MALIDP500_DC_CONTROL);
168 * Mali-DP500 encodes the background color like this:
169 * - red @ MALIDP500_BGND_COLOR[12:0]
170 * - green @ MALIDP500_BGND_COLOR[27:16]
171 * - blue @ (MALIDP500_BGND_COLOR + 4)[12:0]
173 val = ((MALIDP_BGND_COLOR_G & 0xfff) << 16) |
174 (MALIDP_BGND_COLOR_R & 0xfff);
175 malidp_hw_write(hwdev, val, MALIDP500_BGND_COLOR);
176 malidp_hw_write(hwdev, MALIDP_BGND_COLOR_B, MALIDP500_BGND_COLOR + 4);
178 val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) |
179 MALIDP_DE_H_BACKPORCH(mode->hback_porch);
180 malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
182 val = MALIDP500_DE_V_FRONTPORCH(mode->vfront_porch) |
183 MALIDP_DE_V_BACKPORCH(mode->vback_porch);
184 malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
186 val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) |
187 MALIDP_DE_V_SYNCWIDTH(mode->vsync_len);
188 malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
190 val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive);
191 malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
193 if (mode->flags & DISPLAY_FLAGS_INTERLACED)
194 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
196 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
199 static int malidp500_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt)
204 /* RGB888 or BGR888 can't be rotated */
205 if ((fmt == DRM_FORMAT_RGB888) || (fmt == DRM_FORMAT_BGR888))
209 * Each layer needs enough rotation memory to fit 8 lines
210 * worth of pixel data. Required size is then:
211 * size = rotated_width * (bpp / 8) * 8;
213 drm_fb_get_bpp_depth(fmt, &depth, &bpp);
218 static int malidp550_query_hw(struct malidp_hw_device *hwdev)
220 u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
221 u8 ln_size = (conf >> 4) & 0x3, rsize;
223 hwdev->min_line_size = 2;
227 hwdev->max_line_size = SZ_2K;
228 /* two banks of 64KB for rotation memory */
232 hwdev->max_line_size = SZ_4K;
233 /* two banks of 128KB for rotation memory */
237 hwdev->max_line_size = 1280;
238 /* two banks of 40KB for rotation memory */
243 hwdev->max_line_size = 0;
247 hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
251 static void malidp550_enter_config_mode(struct malidp_hw_device *hwdev)
253 u32 status, count = 100;
255 malidp_hw_setbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
257 status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
258 if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
261 * entering config mode can take as long as the rendering
262 * of a full frame, hence the long sleep here
264 usleep_range(1000, 10000);
267 WARN(count == 0, "timeout while entering config mode");
270 static void malidp550_leave_config_mode(struct malidp_hw_device *hwdev)
272 u32 status, count = 100;
274 malidp_hw_clearbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
276 status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
277 if ((status & MALIDP550_DC_CONFIG_REQ) == 0)
279 usleep_range(100, 1000);
282 WARN(count == 0, "timeout while leaving config mode");
285 static bool malidp550_in_config_mode(struct malidp_hw_device *hwdev)
289 status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
290 if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
296 static void malidp550_set_config_valid(struct malidp_hw_device *hwdev)
298 malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID);
301 static void malidp550_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
303 u32 val = MALIDP_DE_DEFAULT_PREFETCH_START;
305 malidp_hw_write(hwdev, val, MALIDP550_DE_CONTROL);
307 * Mali-DP550 and Mali-DP650 encode the background color like this:
308 * - red @ MALIDP550_DE_BGND_COLOR[23:16]
309 * - green @ MALIDP550_DE_BGND_COLOR[15:8]
310 * - blue @ MALIDP550_DE_BGND_COLOR[7:0]
312 * We need to truncate the least significant 4 bits from the default
313 * MALIDP_BGND_COLOR_x values
315 val = (((MALIDP_BGND_COLOR_R >> 4) & 0xff) << 16) |
316 (((MALIDP_BGND_COLOR_G >> 4) & 0xff) << 8) |
317 ((MALIDP_BGND_COLOR_B >> 4) & 0xff);
318 malidp_hw_write(hwdev, val, MALIDP550_DE_BGND_COLOR);
320 val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) |
321 MALIDP_DE_H_BACKPORCH(mode->hback_porch);
322 malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
324 val = MALIDP550_DE_V_FRONTPORCH(mode->vfront_porch) |
325 MALIDP_DE_V_BACKPORCH(mode->vback_porch);
326 malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
328 val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) |
329 MALIDP_DE_V_SYNCWIDTH(mode->vsync_len);
330 if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
331 val |= MALIDP550_HSYNCPOL;
332 if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
333 val |= MALIDP550_VSYNCPOL;
334 malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
336 val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive);
337 malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
339 if (mode->flags & DISPLAY_FLAGS_INTERLACED)
340 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
342 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
345 static int malidp550_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt)
349 /* raw RGB888 or BGR888 can't be rotated */
350 if ((fmt == DRM_FORMAT_RGB888) || (fmt == DRM_FORMAT_BGR888))
354 /* 8 lines at 4 bytes per pixel */
355 case DRM_FORMAT_ARGB2101010:
356 case DRM_FORMAT_ABGR2101010:
357 case DRM_FORMAT_RGBA1010102:
358 case DRM_FORMAT_BGRA1010102:
359 case DRM_FORMAT_ARGB8888:
360 case DRM_FORMAT_ABGR8888:
361 case DRM_FORMAT_RGBA8888:
362 case DRM_FORMAT_BGRA8888:
363 case DRM_FORMAT_XRGB8888:
364 case DRM_FORMAT_XBGR8888:
365 case DRM_FORMAT_RGBX8888:
366 case DRM_FORMAT_BGRX8888:
367 case DRM_FORMAT_RGB888:
368 case DRM_FORMAT_BGR888:
369 /* 16 lines at 2 bytes per pixel */
370 case DRM_FORMAT_RGBA5551:
371 case DRM_FORMAT_ABGR1555:
372 case DRM_FORMAT_RGB565:
373 case DRM_FORMAT_BGR565:
374 case DRM_FORMAT_UYVY:
375 case DRM_FORMAT_YUYV:
378 /* 16 lines at 1.5 bytes per pixel */
379 case DRM_FORMAT_NV12:
380 case DRM_FORMAT_YUV420:
387 return w * bytes_per_col;
390 static int malidp650_query_hw(struct malidp_hw_device *hwdev)
392 u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
393 u8 ln_size = (conf >> 4) & 0x3, rsize;
395 hwdev->min_line_size = 4;
400 /* reserved values */
401 hwdev->max_line_size = 0;
404 hwdev->max_line_size = SZ_4K;
405 /* two banks of 128KB for rotation memory */
409 hwdev->max_line_size = 2560;
410 /* two banks of 80KB for rotation memory */
414 hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
418 const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = {
421 .se_base = MALIDP500_SE_BASE,
422 .dc_base = MALIDP500_DC_BASE,
423 .out_depth_base = MALIDP500_OUTPUT_DEPTH,
424 .features = 0, /* no CLEARIRQ register */
425 .n_layers = ARRAY_SIZE(malidp500_layers),
426 .layers = malidp500_layers,
428 .irq_mask = MALIDP_DE_IRQ_UNDERRUN |
429 MALIDP500_DE_IRQ_AXI_ERR |
430 MALIDP500_DE_IRQ_VSYNC |
431 MALIDP500_DE_IRQ_GLOBAL,
432 .vsync_irq = MALIDP500_DE_IRQ_VSYNC,
435 .irq_mask = MALIDP500_SE_IRQ_CONF_MODE |
436 MALIDP500_SE_IRQ_GLOBAL,
440 .irq_mask = MALIDP500_DE_IRQ_CONF_VALID,
441 .vsync_irq = MALIDP500_DE_IRQ_CONF_VALID,
443 .input_formats = malidp500_de_formats,
444 .n_input_formats = ARRAY_SIZE(malidp500_de_formats),
446 .query_hw = malidp500_query_hw,
447 .enter_config_mode = malidp500_enter_config_mode,
448 .leave_config_mode = malidp500_leave_config_mode,
449 .in_config_mode = malidp500_in_config_mode,
450 .set_config_valid = malidp500_set_config_valid,
451 .modeset = malidp500_modeset,
452 .rotmem_required = malidp500_rotmem_required,
456 .se_base = MALIDP550_SE_BASE,
457 .dc_base = MALIDP550_DC_BASE,
458 .out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
459 .features = MALIDP_REGMAP_HAS_CLEARIRQ,
460 .n_layers = ARRAY_SIZE(malidp550_layers),
461 .layers = malidp550_layers,
463 .irq_mask = MALIDP_DE_IRQ_UNDERRUN |
464 MALIDP550_DE_IRQ_VSYNC,
465 .vsync_irq = MALIDP550_DE_IRQ_VSYNC,
468 .irq_mask = MALIDP550_SE_IRQ_EOW |
469 MALIDP550_SE_IRQ_AXI_ERR,
472 .irq_mask = MALIDP550_DC_IRQ_CONF_VALID,
473 .vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
475 .input_formats = malidp550_de_formats,
476 .n_input_formats = ARRAY_SIZE(malidp550_de_formats),
478 .query_hw = malidp550_query_hw,
479 .enter_config_mode = malidp550_enter_config_mode,
480 .leave_config_mode = malidp550_leave_config_mode,
481 .in_config_mode = malidp550_in_config_mode,
482 .set_config_valid = malidp550_set_config_valid,
483 .modeset = malidp550_modeset,
484 .rotmem_required = malidp550_rotmem_required,
488 .se_base = MALIDP550_SE_BASE,
489 .dc_base = MALIDP550_DC_BASE,
490 .out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
491 .features = MALIDP_REGMAP_HAS_CLEARIRQ,
492 .n_layers = ARRAY_SIZE(malidp550_layers),
493 .layers = malidp550_layers,
495 .irq_mask = MALIDP_DE_IRQ_UNDERRUN |
496 MALIDP650_DE_IRQ_DRIFT |
497 MALIDP550_DE_IRQ_VSYNC,
498 .vsync_irq = MALIDP550_DE_IRQ_VSYNC,
501 .irq_mask = MALIDP550_SE_IRQ_EOW |
502 MALIDP550_SE_IRQ_AXI_ERR,
505 .irq_mask = MALIDP550_DC_IRQ_CONF_VALID,
506 .vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
508 .input_formats = malidp550_de_formats,
509 .n_input_formats = ARRAY_SIZE(malidp550_de_formats),
511 .query_hw = malidp650_query_hw,
512 .enter_config_mode = malidp550_enter_config_mode,
513 .leave_config_mode = malidp550_leave_config_mode,
514 .in_config_mode = malidp550_in_config_mode,
515 .set_config_valid = malidp550_set_config_valid,
516 .modeset = malidp550_modeset,
517 .rotmem_required = malidp550_rotmem_required,
521 u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
522 u8 layer_id, u32 format)
526 for (i = 0; i < map->n_input_formats; i++) {
527 if (((map->input_formats[i].layer & layer_id) == layer_id) &&
528 (map->input_formats[i].format == format))
529 return map->input_formats[i].id;
532 return MALIDP_INVALID_FORMAT_ID;
535 static void malidp_hw_clear_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq)
537 u32 base = malidp_get_block_base(hwdev, block);
539 if (hwdev->map.features & MALIDP_REGMAP_HAS_CLEARIRQ)
540 malidp_hw_write(hwdev, irq, base + MALIDP_REG_CLEARIRQ);
542 malidp_hw_write(hwdev, irq, base + MALIDP_REG_STATUS);
545 static irqreturn_t malidp_de_irq(int irq, void *arg)
547 struct drm_device *drm = arg;
548 struct malidp_drm *malidp = drm->dev_private;
549 struct malidp_hw_device *hwdev;
550 const struct malidp_irq_map *de;
551 u32 status, mask, dc_status;
552 irqreturn_t ret = IRQ_NONE;
554 if (!drm->dev_private)
558 de = &hwdev->map.de_irq_map;
560 /* first handle the config valid IRQ */
561 dc_status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
562 if (dc_status & hwdev->map.dc_irq_map.vsync_irq) {
563 /* we have a page flip event */
564 atomic_set(&malidp->config_valid, 1);
565 malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status);
566 ret = IRQ_WAKE_THREAD;
569 status = malidp_hw_read(hwdev, MALIDP_REG_STATUS);
570 if (!(status & de->irq_mask))
573 mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ);
575 if (status & de->vsync_irq)
576 drm_crtc_handle_vblank(&malidp->crtc);
578 malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, status);
580 return (ret == IRQ_NONE) ? IRQ_HANDLED : ret;
583 static irqreturn_t malidp_de_irq_thread_handler(int irq, void *arg)
585 struct drm_device *drm = arg;
586 struct malidp_drm *malidp = drm->dev_private;
588 wake_up(&malidp->wq);
593 int malidp_de_irq_init(struct drm_device *drm, int irq)
595 struct malidp_drm *malidp = drm->dev_private;
596 struct malidp_hw_device *hwdev = malidp->dev;
599 /* ensure interrupts are disabled */
600 malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
601 malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
602 malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
603 malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
605 ret = devm_request_threaded_irq(drm->dev, irq, malidp_de_irq,
606 malidp_de_irq_thread_handler,
607 IRQF_SHARED, "malidp-de", drm);
609 DRM_ERROR("failed to install DE IRQ handler\n");
613 /* first enable the DC block IRQs */
614 malidp_hw_enable_irq(hwdev, MALIDP_DC_BLOCK,
615 hwdev->map.dc_irq_map.irq_mask);
617 /* now enable the DE block IRQs */
618 malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
619 hwdev->map.de_irq_map.irq_mask);
624 void malidp_de_irq_fini(struct drm_device *drm)
626 struct malidp_drm *malidp = drm->dev_private;
627 struct malidp_hw_device *hwdev = malidp->dev;
629 malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
630 hwdev->map.de_irq_map.irq_mask);
631 malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK,
632 hwdev->map.dc_irq_map.irq_mask);
635 static irqreturn_t malidp_se_irq(int irq, void *arg)
637 struct drm_device *drm = arg;
638 struct malidp_drm *malidp = drm->dev_private;
639 struct malidp_hw_device *hwdev = malidp->dev;
642 status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS);
643 if (!(status & hwdev->map.se_irq_map.irq_mask))
646 mask = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_MASKIRQ);
647 status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS);
649 /* ToDo: status decoding and firing up of VSYNC and page flip events */
651 malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, status);
656 static irqreturn_t malidp_se_irq_thread_handler(int irq, void *arg)
661 int malidp_se_irq_init(struct drm_device *drm, int irq)
663 struct malidp_drm *malidp = drm->dev_private;
664 struct malidp_hw_device *hwdev = malidp->dev;
667 /* ensure interrupts are disabled */
668 malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
669 malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
671 ret = devm_request_threaded_irq(drm->dev, irq, malidp_se_irq,
672 malidp_se_irq_thread_handler,
673 IRQF_SHARED, "malidp-se", drm);
675 DRM_ERROR("failed to install SE IRQ handler\n");
679 malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK,
680 hwdev->map.se_irq_map.irq_mask);
685 void malidp_se_irq_fini(struct drm_device *drm)
687 struct malidp_drm *malidp = drm->dev_private;
688 struct malidp_hw_device *hwdev = malidp->dev;
690 malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK,
691 hwdev->map.se_irq_map.irq_mask);