2 * Copyright (C) 2013-2015 ARM Limited
3 * Author: Liviu Dudau <Liviu.Dudau@arm.com>
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive
12 #include <linux/module.h>
13 #include <linux/spinlock.h>
14 #include <linux/clk.h>
15 #include <linux/component.h>
16 #include <linux/console.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/list.h>
19 #include <linux/of_graph.h>
20 #include <linux/of_reserved_mem.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
24 #include <drm/drm_atomic_helper.h>
25 #include <drm/drm_crtc.h>
26 #include <drm/drm_debugfs.h>
27 #include <drm/drm_drv.h>
28 #include <drm/drm_fb_cma_helper.h>
29 #include <drm/drm_fb_helper.h>
30 #include <drm/drm_gem_cma_helper.h>
31 #include <drm/drm_gem_framebuffer_helper.h>
32 #include <drm/drm_modeset_helper.h>
33 #include <drm/drm_module.h>
34 #include <drm/drm_of.h>
35 #include <drm/drm_probe_helper.h>
36 #include <drm/drm_vblank.h>
38 #include "hdlcd_drv.h"
39 #include "hdlcd_regs.h"
41 static irqreturn_t hdlcd_irq(int irq, void *arg)
43 struct drm_device *drm = arg;
44 struct hdlcd_drm_private *hdlcd = drm->dev_private;
45 unsigned long irq_status;
47 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
49 #ifdef CONFIG_DEBUG_FS
50 if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
51 atomic_inc(&hdlcd->buffer_underrun_count);
53 if (irq_status & HDLCD_INTERRUPT_DMA_END)
54 atomic_inc(&hdlcd->dma_end_count);
56 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
57 atomic_inc(&hdlcd->bus_error_count);
59 if (irq_status & HDLCD_INTERRUPT_VSYNC)
60 atomic_inc(&hdlcd->vsync_count);
63 if (irq_status & HDLCD_INTERRUPT_VSYNC)
64 drm_crtc_handle_vblank(&hdlcd->crtc);
66 /* acknowledge interrupt(s) */
67 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
72 static void hdlcd_irq_preinstall(struct drm_device *drm)
74 struct hdlcd_drm_private *hdlcd = drm->dev_private;
75 /* Ensure interrupts are disabled */
76 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
77 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
80 static void hdlcd_irq_postinstall(struct drm_device *drm)
82 #ifdef CONFIG_DEBUG_FS
83 struct hdlcd_drm_private *hdlcd = drm->dev_private;
84 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
86 /* enable debug interrupts */
87 irq_mask |= HDLCD_DEBUG_INT_MASK;
89 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
93 static int hdlcd_irq_install(struct drm_device *drm, int irq)
97 if (irq == IRQ_NOTCONNECTED)
100 hdlcd_irq_preinstall(drm);
102 ret = request_irq(irq, hdlcd_irq, 0, drm->driver->name, drm);
106 hdlcd_irq_postinstall(drm);
111 static void hdlcd_irq_uninstall(struct drm_device *drm)
113 struct hdlcd_drm_private *hdlcd = drm->dev_private;
114 /* disable all the interrupts that we might have enabled */
115 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
117 #ifdef CONFIG_DEBUG_FS
118 /* disable debug interrupts */
119 irq_mask &= ~HDLCD_DEBUG_INT_MASK;
122 /* disable vsync interrupts */
123 irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
124 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
126 free_irq(hdlcd->irq, drm);
129 static int hdlcd_load(struct drm_device *drm, unsigned long flags)
131 struct hdlcd_drm_private *hdlcd = drm->dev_private;
132 struct platform_device *pdev = to_platform_device(drm->dev);
133 struct resource *res;
137 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
138 if (IS_ERR(hdlcd->clk))
139 return PTR_ERR(hdlcd->clk);
141 #ifdef CONFIG_DEBUG_FS
142 atomic_set(&hdlcd->buffer_underrun_count, 0);
143 atomic_set(&hdlcd->bus_error_count, 0);
144 atomic_set(&hdlcd->vsync_count, 0);
145 atomic_set(&hdlcd->dma_end_count, 0);
148 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
149 hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
150 if (IS_ERR(hdlcd->mmio)) {
151 DRM_ERROR("failed to map control registers area\n");
152 ret = PTR_ERR(hdlcd->mmio);
157 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
158 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
159 DRM_ERROR("unknown product id: 0x%x\n", version);
162 DRM_INFO("found ARM HDLCD version r%dp%d\n",
163 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
164 version & HDLCD_VERSION_MINOR_MASK);
166 /* Get the optional framebuffer memory resource */
167 ret = of_reserved_mem_device_init(drm->dev);
168 if (ret && ret != -ENODEV)
171 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
175 ret = hdlcd_setup_crtc(drm);
177 DRM_ERROR("failed to create crtc\n");
181 ret = platform_get_irq(pdev, 0);
186 ret = hdlcd_irq_install(drm, hdlcd->irq);
188 DRM_ERROR("failed to install IRQ handler\n");
195 drm_crtc_cleanup(&hdlcd->crtc);
197 of_reserved_mem_device_release(drm->dev);
202 static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
203 .fb_create = drm_gem_fb_create,
204 .atomic_check = drm_atomic_helper_check,
205 .atomic_commit = drm_atomic_helper_commit,
208 static void hdlcd_setup_mode_config(struct drm_device *drm)
210 drm_mode_config_init(drm);
211 drm->mode_config.min_width = 0;
212 drm->mode_config.min_height = 0;
213 drm->mode_config.max_width = HDLCD_MAX_XRES;
214 drm->mode_config.max_height = HDLCD_MAX_YRES;
215 drm->mode_config.funcs = &hdlcd_mode_config_funcs;
218 #ifdef CONFIG_DEBUG_FS
219 static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
221 struct drm_info_node *node = (struct drm_info_node *)m->private;
222 struct drm_device *drm = node->minor->dev;
223 struct hdlcd_drm_private *hdlcd = drm->dev_private;
225 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
226 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
227 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
228 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
232 static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
234 struct drm_info_node *node = (struct drm_info_node *)m->private;
235 struct drm_device *drm = node->minor->dev;
236 struct hdlcd_drm_private *hdlcd = drm->dev_private;
237 unsigned long clkrate = clk_get_rate(hdlcd->clk);
238 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
240 seq_printf(m, "hw : %lu\n", clkrate);
241 seq_printf(m, "mode: %lu\n", mode_clock);
245 static struct drm_info_list hdlcd_debugfs_list[] = {
246 { "interrupt_count", hdlcd_show_underrun_count, 0 },
247 { "clocks", hdlcd_show_pxlclock, 0 },
250 static void hdlcd_debugfs_init(struct drm_minor *minor)
252 drm_debugfs_create_files(hdlcd_debugfs_list,
253 ARRAY_SIZE(hdlcd_debugfs_list),
254 minor->debugfs_root, minor);
258 DEFINE_DRM_GEM_CMA_FOPS(fops);
260 static const struct drm_driver hdlcd_driver = {
261 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
262 DRM_GEM_CMA_DRIVER_OPS,
263 #ifdef CONFIG_DEBUG_FS
264 .debugfs_init = hdlcd_debugfs_init,
268 .desc = "ARM HDLCD Controller DRM",
274 static int hdlcd_drm_bind(struct device *dev)
276 struct drm_device *drm;
277 struct hdlcd_drm_private *hdlcd;
280 hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
284 drm = drm_dev_alloc(&hdlcd_driver, dev);
288 drm->dev_private = hdlcd;
289 dev_set_drvdata(dev, drm);
291 hdlcd_setup_mode_config(drm);
292 ret = hdlcd_load(drm, 0);
296 /* Set the CRTC's port so that the encoder component can find it */
297 hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
299 ret = component_bind_all(dev, drm);
301 DRM_ERROR("Failed to bind all components\n");
305 ret = pm_runtime_set_active(dev);
309 pm_runtime_enable(dev);
311 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
313 DRM_ERROR("failed to initialise vblank\n");
317 drm_mode_config_reset(drm);
318 drm_kms_helper_poll_init(drm);
320 ret = drm_dev_register(drm, 0);
324 drm_fbdev_generic_setup(drm, 32);
329 drm_kms_helper_poll_fini(drm);
331 pm_runtime_disable(drm->dev);
333 drm_atomic_helper_shutdown(drm);
334 component_unbind_all(dev, drm);
336 of_node_put(hdlcd->crtc.port);
337 hdlcd->crtc.port = NULL;
338 hdlcd_irq_uninstall(drm);
339 of_reserved_mem_device_release(drm->dev);
341 drm_mode_config_cleanup(drm);
342 dev_set_drvdata(dev, NULL);
348 static void hdlcd_drm_unbind(struct device *dev)
350 struct drm_device *drm = dev_get_drvdata(dev);
351 struct hdlcd_drm_private *hdlcd = drm->dev_private;
353 drm_dev_unregister(drm);
354 drm_kms_helper_poll_fini(drm);
355 component_unbind_all(dev, drm);
356 of_node_put(hdlcd->crtc.port);
357 hdlcd->crtc.port = NULL;
358 pm_runtime_get_sync(dev);
359 drm_atomic_helper_shutdown(drm);
360 hdlcd_irq_uninstall(drm);
362 if (pm_runtime_enabled(dev))
363 pm_runtime_disable(dev);
364 of_reserved_mem_device_release(dev);
365 drm_mode_config_cleanup(drm);
366 drm->dev_private = NULL;
367 dev_set_drvdata(dev, NULL);
371 static const struct component_master_ops hdlcd_master_ops = {
372 .bind = hdlcd_drm_bind,
373 .unbind = hdlcd_drm_unbind,
376 static int compare_dev(struct device *dev, void *data)
378 return dev->of_node == data;
381 static int hdlcd_probe(struct platform_device *pdev)
383 struct device_node *port;
384 struct component_match *match = NULL;
386 /* there is only one output port inside each device, find it */
387 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
391 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
394 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
398 static int hdlcd_remove(struct platform_device *pdev)
400 component_master_del(&pdev->dev, &hdlcd_master_ops);
404 static const struct of_device_id hdlcd_of_match[] = {
405 { .compatible = "arm,hdlcd" },
408 MODULE_DEVICE_TABLE(of, hdlcd_of_match);
410 static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
412 struct drm_device *drm = dev_get_drvdata(dev);
414 return drm_mode_config_helper_suspend(drm);
417 static int __maybe_unused hdlcd_pm_resume(struct device *dev)
419 struct drm_device *drm = dev_get_drvdata(dev);
421 drm_mode_config_helper_resume(drm);
426 static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
428 static struct platform_driver hdlcd_platform_driver = {
429 .probe = hdlcd_probe,
430 .remove = hdlcd_remove,
434 .of_match_table = hdlcd_of_match,
438 drm_module_platform_driver(hdlcd_platform_driver);
440 MODULE_AUTHOR("Liviu Dudau");
441 MODULE_DESCRIPTION("ARM HDLCD DRM driver");
442 MODULE_LICENSE("GPL v2");