drivers/gpu/drm/amd/powerplay/inc/smu75.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef SMU75_H
  24 #define SMU75_H
  25
  26 #pragma pack(push, 1)
  27
  28 typedef struct {
  29         uint32_t high;
  30         uint32_t low;
  31 } data_64_t;
  32
  33 typedef struct {
  34         data_64_t high;
  35         data_64_t low;
  36 } data_128_t;
  37
  38 #define SMU__DGPU_ONLY
  39
  40 #define SMU__NUM_SCLK_DPM_STATE  8
  41 #define SMU__NUM_MCLK_DPM_LEVELS 4
  42 #define SMU__NUM_LCLK_DPM_LEVELS 8
  43 #define SMU__NUM_PCIE_DPM_LEVELS 8
  44
  45 #define SMU7_CONTEXT_ID_SMC        1
  46 #define SMU7_CONTEXT_ID_VBIOS      2
  47
  48 #define SMU75_MAX_LEVELS_VDDC            16
  49 #define SMU75_MAX_LEVELS_VDDGFX          16
  50 #define SMU75_MAX_LEVELS_VDDCI           8
  51 #define SMU75_MAX_LEVELS_MVDD            4
  52
  53 #define SMU_MAX_SMIO_LEVELS              4
  54
  55 #define SMU75_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE
  56 #define SMU75_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS
  57 #define SMU75_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS
  58 #define SMU75_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS
  59 #define SMU75_MAX_LEVELS_UVD             8
  60 #define SMU75_MAX_LEVELS_VCE             8
  61 #define SMU75_MAX_LEVELS_ACP             8
  62 #define SMU75_MAX_LEVELS_SAMU            8
  63 #define SMU75_MAX_ENTRIES_SMIO           32
  64
  65 #define DPM_NO_LIMIT 0
  66 #define DPM_NO_UP 1
  67 #define DPM_GO_DOWN 2
  68 #define DPM_GO_UP 3
  69
  70 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
  71 #define SMU7_FIRST_DPM_MEMORY_LEVEL      0
  72
  73 #define GPIO_CLAMP_MODE_VRHOT      1
  74 #define GPIO_CLAMP_MODE_THERM      2
  75 #define GPIO_CLAMP_MODE_DC         4
  76
  77 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
  78 #define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
  79 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
  80 #define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
  81 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
  82 #define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
  83 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
  84 #define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
  85 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
  86 #define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
  87 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
  88 #define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
  89 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
  90 #define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
  91 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
  92 #define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
  93 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
  94 #define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
  95 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
  96 #define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
  97
  98 /* Virtualization Defines */
  99 #define CG_XDMA_MASK  0x1
 100 #define CG_XDMA_SHIFT 0
 101 #define CG_UVD_MASK   0x2
 102 #define CG_UVD_SHIFT  1
 103 #define CG_VCE_MASK   0x4
 104 #define CG_VCE_SHIFT  2
 105 #define CG_SAMU_MASK  0x8
 106 #define CG_SAMU_SHIFT 3
 107 #define CG_GFX_MASK   0x10
 108 #define CG_GFX_SHIFT  4
 109 #define CG_SDMA_MASK  0x20
 110 #define CG_SDMA_SHIFT 5
 111 #define CG_HDP_MASK   0x40
 112 #define CG_HDP_SHIFT  6
 113 #define CG_MC_MASK    0x80
 114 #define CG_MC_SHIFT   7
 115 #define CG_DRM_MASK   0x100
 116 #define CG_DRM_SHIFT  8
 117 #define CG_ROM_MASK   0x200
 118 #define CG_ROM_SHIFT  9
 119 #define CG_BIF_MASK   0x400
 120 #define CG_BIF_SHIFT  10
 121
 122 #if defined SMU__DGPU_ONLY
 123 #define SMU75_DTE_ITERATIONS 5
 124 #define SMU75_DTE_SOURCES 3
 125 #define SMU75_DTE_SINKS 1
 126 #define SMU75_NUM_CPU_TES 0
 127 #define SMU75_NUM_GPU_TES 1
 128 #define SMU75_NUM_NON_TES 2
 129 #define SMU75_DTE_FAN_SCALAR_MIN 0x100
 130 #define SMU75_DTE_FAN_SCALAR_MAX 0x166
 131 #define SMU75_DTE_FAN_TEMP_MAX 93
 132 #define SMU75_DTE_FAN_TEMP_MIN 83
 133 #endif
 134 #define SMU75_THERMAL_INPUT_LOOP_COUNT 2
 135 #define SMU75_THERMAL_CLAMP_MODE_COUNT 2
 136
 137 #define EXP_M1_1  93
 138 #define EXP_M2_1  195759
 139 #define EXP_B_1   111176531
 140
 141 #define EXP_M1_2  67
 142 #define EXP_M2_2  153720
 143 #define EXP_B_2   94415767
 144
 145 #define EXP_M1_3  48
 146 #define EXP_M2_3  119796
 147 #define EXP_B_3   79195279
 148
 149 #define EXP_M1_4  550
 150 #define EXP_M2_4  1484190
 151 #define EXP_B_4   1051432828
 152
 153 #define EXP_M1_5  394
 154 #define EXP_M2_5  1143049
 155 #define EXP_B_5   864288432
 156
 157 struct SMU7_HystController_Data {
 158         uint16_t waterfall_up;
 159         uint16_t waterfall_down;
 160         uint16_t waterfall_limit;
 161         uint16_t release_cnt;
 162         uint16_t release_limit;
 163         uint16_t spare;
 164 };
 165
 166 typedef struct SMU7_HystController_Data SMU7_HystController_Data;
 167
 168 struct SMU75_PIDController {
 169         uint32_t Ki;
 170         int32_t LFWindupUpperLim;
 171         int32_t LFWindupLowerLim;
 172         uint32_t StatePrecision;
 173         uint32_t LfPrecision;
 174         uint32_t LfOffset;
 175         uint32_t MaxState;
 176         uint32_t MaxLfFraction;
 177         uint32_t StateShift;
 178 };
 179
 180 typedef struct SMU75_PIDController SMU75_PIDController;
 181
 182 struct SMU7_LocalDpmScoreboard {
 183         uint32_t PercentageBusy;
 184
 185         int32_t  PIDError;
 186         int32_t  PIDIntegral;
 187         int32_t  PIDOutput;
 188
 189         uint32_t SigmaDeltaAccum;
 190         uint32_t SigmaDeltaOutput;
 191         uint32_t SigmaDeltaLevel;
 192
 193         uint32_t UtilizationSetpoint;
 194
 195         uint8_t  TdpClampMode;
 196         uint8_t  TdcClampMode;
 197         uint8_t  ThermClampMode;
 198         uint8_t  VoltageBusy;
 199
 200         int8_t   CurrLevel;
 201         int8_t   TargLevel;
 202         uint8_t  LevelChangeInProgress;
 203         uint8_t  UpHyst;
 204
 205         uint8_t  DownHyst;
 206         uint8_t  VoltageDownHyst;
 207         uint8_t  DpmEnable;
 208         uint8_t  DpmRunning;
 209
 210         uint8_t  DpmForce;
 211         uint8_t  DpmForceLevel;
 212         uint8_t  DisplayWatermark;
 213         uint8_t  McArbIndex;
 214
 215         uint32_t MinimumPerfSclk;
 216
 217         uint8_t  AcpiReq;
 218         uint8_t  AcpiAck;
 219         uint8_t  GfxClkSlow;
 220         uint8_t  GpioClampMode;
 221
 222         uint8_t  EnableModeSwitchRLCNotification;
 223         uint8_t  EnabledLevelsChange;
 224         uint8_t  DteClampMode;
 225         uint8_t  FpsClampMode;
 226
 227         uint16_t LevelResidencyCounters [SMU75_MAX_LEVELS_GRAPHICS];
 228         uint16_t LevelSwitchCounters [SMU75_MAX_LEVELS_GRAPHICS];
 229
 230         void     (*TargetStateCalculator)(uint8_t);
 231         void     (*SavedTargetStateCalculator)(uint8_t);
 232
 233         uint16_t AutoDpmInterval;
 234         uint16_t AutoDpmRange;
 235
 236         uint8_t  FpsEnabled;
 237         uint8_t  MaxPerfLevel;
 238         uint8_t  AllowLowClkInterruptToHost;
 239         uint8_t  FpsRunning;
 240
 241         uint32_t MaxAllowedFrequency;
 242
 243         uint32_t FilteredSclkFrequency;
 244         uint32_t LastSclkFrequency;
 245         uint32_t FilteredSclkFrequencyCnt;
 246
 247         uint8_t MinPerfLevel;
 248 #ifdef SMU__FIRMWARE_SCKS_PRESENT__1
 249         uint8_t ScksClampMode;
 250         uint8_t padding[2];
 251 #else
 252         uint8_t padding[3];
 253 #endif
 254
 255         uint16_t FpsAlpha;
 256         uint16_t DeltaTime;
 257         uint32_t CurrentFps;
 258         uint32_t FilteredFps;
 259         uint32_t FrameCount;
 260         uint32_t FrameCountLast;
 261         uint16_t FpsTargetScalar;
 262         uint16_t FpsWaterfallLimitScalar;
 263         uint16_t FpsAlphaScalar;
 264         uint16_t spare8;
 265         SMU7_HystController_Data HystControllerData;
 266 };
 267
 268 typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
 269
 270 #define SMU7_MAX_VOLTAGE_CLIENTS 12
 271
 272 typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
 273
 274 #define VDDC_MASK    0x00007FFF
 275 #define VDDC_SHIFT   0
 276 #define VDDCI_MASK   0x3FFF8000
 277 #define VDDCI_SHIFT  15
 278 #define PHASES_MASK  0xC0000000
 279 #define PHASES_SHIFT 30
 280
 281 typedef uint32_t SMU_VoltageLevel;
 282
 283 struct SMU7_VoltageScoreboard {
 284         SMU_VoltageLevel TargetVoltage;
 285         uint16_t MaxVid;
 286         uint8_t  HighestVidOffset;
 287         uint8_t  CurrentVidOffset;
 288
 289         uint16_t CurrentVddc;
 290         uint16_t CurrentVddci;
 291
 292         uint8_t  ControllerBusy;
 293         uint8_t  CurrentVid;
 294         uint8_t  CurrentVddciVid;
 295         uint8_t  padding;
 296
 297         SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
 298         SMU_VoltageLevel TargetVoltageState;
 299         uint8_t  EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
 300
 301         uint8_t  padding2;
 302         uint8_t  padding3;
 303         uint8_t  ControllerEnable;
 304         uint8_t  ControllerRunning;
 305         uint16_t CurrentStdVoltageHiSidd;
 306         uint16_t CurrentStdVoltageLoSidd;
 307         uint8_t  OverrideVoltage;
 308         uint8_t  padding4;
 309         uint8_t  padding5;
 310         uint8_t  CurrentPhases;
 311
 312         VoltageChangeHandler_t ChangeVddc;
 313         VoltageChangeHandler_t ChangeVddci;
 314         VoltageChangeHandler_t ChangePhase;
 315         VoltageChangeHandler_t ChangeMvdd;
 316
 317         VoltageChangeHandler_t functionLinks[6];
 318
 319         uint16_t * VddcFollower1;
 320         int16_t  Driver_OD_RequestedVidOffset1;
 321         int16_t  Driver_OD_RequestedVidOffset2;
 322 };
 323
 324 typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
 325
 326 #define SMU7_MAX_PCIE_LINK_SPEEDS 3
 327
 328 struct SMU7_PCIeLinkSpeedScoreboard {
 329         uint8_t     DpmEnable;
 330         uint8_t     DpmRunning;
 331         uint8_t     DpmForce;
 332         uint8_t     DpmForceLevel;
 333
 334         uint8_t     CurrentLinkSpeed;
 335         uint8_t     EnabledLevelsChange;
 336         uint16_t    AutoDpmInterval;
 337
 338         uint16_t    AutoDpmRange;
 339         uint16_t    AutoDpmCount;
 340
 341         uint8_t     DpmMode;
 342         uint8_t     AcpiReq;
 343         uint8_t     AcpiAck;
 344         uint8_t     CurrentLinkLevel;
 345 };
 346
 347 typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
 348
 349 #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
 350 #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
 351
 352 #define SMU7_SCALE_I  7
 353 #define SMU7_SCALE_R 12
 354
 355 struct SMU7_PowerScoreboard {
 356         uint32_t GpuPower;
 357
 358         uint32_t VddcPower;
 359         uint32_t VddcVoltage;
 360         uint32_t VddcCurrent;
 361
 362         uint32_t VddciPower;
 363         uint32_t VddciVoltage;
 364         uint32_t VddciCurrent;
 365
 366         uint32_t RocPower;
 367
 368         uint16_t Telemetry_1_slope;
 369         uint16_t Telemetry_2_slope;
 370         int32_t  Telemetry_1_offset;
 371         int32_t  Telemetry_2_offset;
 372
 373         uint8_t MCLK_patch_flag;
 374         uint8_t reserved[3];
 375 };
 376
 377 typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
 378
 379 #define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
 380 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
 381 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
 382 #define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
 383 #define SMU7_UVD_DPM_CONFIG_MASK                         0x10
 384 #define SMU7_VCE_DPM_CONFIG_MASK                         0x20
 385 #define SMU7_ACP_DPM_CONFIG_MASK                         0x40
 386 #define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
 387 #define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
 388
 389 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
 390 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
 391 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
 392 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
 393 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
 394 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
 395
 396 struct SMU75_SoftRegisters {
 397         uint32_t        RefClockFrequency;
 398         uint32_t        PmTimerPeriod;
 399         uint32_t        FeatureEnables;
 400 #if defined (SMU__DGPU_ONLY)
 401         uint32_t        PreVBlankGap;
 402         uint32_t        VBlankTimeout;
 403         uint32_t        TrainTimeGap;
 404         uint32_t        MvddSwitchTime;
 405         uint32_t        LongestAcpiTrainTime;
 406         uint32_t        AcpiDelay;
 407         uint32_t        G5TrainTime;
 408         uint32_t        DelayMpllPwron;
 409         uint32_t        VoltageChangeTimeout;
 410 #endif
 411         uint32_t        HandshakeDisables;
 412
 413         uint8_t         DisplayPhy1Config;
 414         uint8_t         DisplayPhy2Config;
 415         uint8_t         DisplayPhy3Config;
 416         uint8_t         DisplayPhy4Config;
 417
 418         uint8_t         DisplayPhy5Config;
 419         uint8_t         DisplayPhy6Config;
 420         uint8_t         DisplayPhy7Config;
 421         uint8_t         DisplayPhy8Config;
 422
 423         uint32_t        AverageGraphicsActivity;
 424         uint32_t        AverageMemoryActivity;
 425         uint32_t        AverageGioActivity;
 426
 427         uint8_t         SClkDpmEnabledLevels;
 428         uint8_t         MClkDpmEnabledLevels;
 429         uint8_t         LClkDpmEnabledLevels;
 430         uint8_t         PCIeDpmEnabledLevels;
 431
 432         uint8_t         UVDDpmEnabledLevels;
 433         uint8_t         SAMUDpmEnabledLevels;
 434         uint8_t         ACPDpmEnabledLevels;
 435         uint8_t         VCEDpmEnabledLevels;
 436
 437         uint32_t        DRAM_LOG_ADDR_H;
 438         uint32_t        DRAM_LOG_ADDR_L;
 439         uint32_t        DRAM_LOG_PHY_ADDR_H;
 440         uint32_t        DRAM_LOG_PHY_ADDR_L;
 441         uint32_t        DRAM_LOG_BUFF_SIZE;
 442         uint32_t        UlvEnterCount;
 443         uint32_t        UlvTime;
 444         uint32_t        UcodeLoadStatus;
 445         uint32_t        AllowMvddSwitch;
 446         uint8_t         Activity_Weight;
 447         uint8_t         Reserved8[3];
 448 };
 449
 450 typedef struct SMU75_SoftRegisters SMU75_SoftRegisters;
 451
 452 struct SMU75_Firmware_Header {
 453         uint32_t Digest[5];
 454         uint32_t Version;
 455         uint32_t HeaderSize;
 456         uint32_t Flags;
 457         uint32_t EntryPoint;
 458         uint32_t CodeSize;
 459         uint32_t ImageSize;
 460
 461         uint32_t Rtos;
 462         uint32_t SoftRegisters;
 463         uint32_t DpmTable;
 464         uint32_t FanTable;
 465         uint32_t CacConfigTable;
 466         uint32_t CacStatusTable;
 467         uint32_t mcRegisterTable;
 468         uint32_t mcArbDramTimingTable;
 469         uint32_t PmFuseTable;
 470         uint32_t Globals;
 471         uint32_t ClockStretcherTable;
 472         uint32_t VftTable;
 473         uint32_t Reserved1;
 474         uint32_t AvfsCksOff_AvfsGbvTable;
 475         uint32_t AvfsCksOff_BtcGbvTable;
 476         uint32_t MM_AvfsTable;
 477         uint32_t PowerSharingTable;
 478         uint32_t AvfsTable;
 479         uint32_t AvfsCksOffGbvTable;
 480         uint32_t AvfsMeanNSigma;
 481         uint32_t AvfsSclkOffsetTable;
 482         uint32_t Reserved[12];
 483         uint32_t Signature;
 484 };
 485
 486 typedef struct SMU75_Firmware_Header SMU75_Firmware_Header;
 487
 488 #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
 489
 490 enum  DisplayConfig {
 491         PowerDown = 1,
 492         DP54x4,
 493         DP54x2,
 494         DP54x1,
 495         DP27x4,
 496         DP27x2,
 497         DP27x1,
 498         HDMI297,
 499         HDMI162,
 500         LVDS,
 501         DP324x4,
 502         DP324x2,
 503         DP324x1
 504 };
 505
 506 #define MC_BLOCK_COUNT 1
 507 #define CPL_BLOCK_COUNT 5
 508 #define SE_BLOCK_COUNT 15
 509 #define GC_BLOCK_COUNT 24
 510
 511 struct SMU7_Local_Cac {
 512         uint8_t BlockId;
 513         uint8_t SignalId;
 514         uint8_t Threshold;
 515         uint8_t Padding;
 516 };
 517
 518 typedef struct SMU7_Local_Cac SMU7_Local_Cac;
 519
 520 struct SMU7_Local_Cac_Table {
 521         SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
 522         SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
 523         SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
 524         SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
 525 };
 526
 527 typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
 528
 529 #pragma pack(pop)
 530
 531 #define CG_SYS_BITMASK_FIRST_BIT      0
 532 #define CG_SYS_BITMASK_LAST_BIT       10
 533 #define CG_SYS_BIF_MGLS_SHIFT         0
 534 #define CG_SYS_ROM_SHIFT              1
 535 #define CG_SYS_MC_MGCG_SHIFT          2
 536 #define CG_SYS_MC_MGLS_SHIFT          3
 537 #define CG_SYS_SDMA_MGCG_SHIFT        4
 538 #define CG_SYS_SDMA_MGLS_SHIFT        5
 539 #define CG_SYS_DRM_MGCG_SHIFT         6
 540 #define CG_SYS_HDP_MGCG_SHIFT         7
 541 #define CG_SYS_HDP_MGLS_SHIFT         8
 542 #define CG_SYS_DRM_MGLS_SHIFT         9
 543 #define CG_SYS_BIF_MGCG_SHIFT         10
 544
 545 #define CG_SYS_BIF_MGLS_MASK          0x1
 546 #define CG_SYS_ROM_MASK               0x2
 547 #define CG_SYS_MC_MGCG_MASK           0x4
 548 #define CG_SYS_MC_MGLS_MASK           0x8
 549 #define CG_SYS_SDMA_MGCG_MASK         0x10
 550 #define CG_SYS_SDMA_MGLS_MASK         0x20
 551 #define CG_SYS_DRM_MGCG_MASK          0x40
 552 #define CG_SYS_HDP_MGCG_MASK          0x80
 553 #define CG_SYS_HDP_MGLS_MASK          0x100
 554 #define CG_SYS_DRM_MGLS_MASK          0x200
 555 #define CG_SYS_BIF_MGCG_MASK          0x400
 556
 557 #define CG_GFX_BITMASK_FIRST_BIT      16
 558 #define CG_GFX_BITMASK_LAST_BIT       24
 559
 560 #define CG_GFX_CGCG_SHIFT             16
 561 #define CG_GFX_CGLS_SHIFT             17
 562 #define CG_CPF_MGCG_SHIFT             18
 563 #define CG_RLC_MGCG_SHIFT             19
 564 #define CG_GFX_OTHERS_MGCG_SHIFT      20
 565 #define CG_GFX_3DCG_SHIFT             21
 566 #define CG_GFX_3DLS_SHIFT             22
 567 #define CG_GFX_RLC_LS_SHIFT           23
 568 #define CG_GFX_CP_LS_SHIFT            24
 569
 570 #define CG_GFX_CGCG_MASK              0x00010000
 571 #define CG_GFX_CGLS_MASK              0x00020000
 572 #define CG_CPF_MGCG_MASK              0x00040000
 573 #define CG_RLC_MGCG_MASK              0x00080000
 574 #define CG_GFX_OTHERS_MGCG_MASK       0x00100000
 575 #define CG_GFX_3DCG_MASK              0x00200000
 576 #define CG_GFX_3DLS_MASK              0x00400000
 577 #define CG_GFX_RLC_LS_MASK            0x00800000
 578 #define CG_GFX_CP_LS_MASK             0x01000000
 579
 580
 581 #define VRCONF_VDDC_MASK         0x000000FF
 582 #define VRCONF_VDDC_SHIFT        0
 583 #define VRCONF_VDDGFX_MASK       0x0000FF00
 584 #define VRCONF_VDDGFX_SHIFT      8
 585 #define VRCONF_VDDCI_MASK        0x00FF0000
 586 #define VRCONF_VDDCI_SHIFT       16
 587 #define VRCONF_MVDD_MASK         0xFF000000
 588 #define VRCONF_MVDD_SHIFT        24
 589
 590 #define VR_MERGED_WITH_VDDC      0
 591 #define VR_SVI2_PLANE_1          1
 592 #define VR_SVI2_PLANE_2          2
 593 #define VR_SMIO_PATTERN_1        3
 594 #define VR_SMIO_PATTERN_2        4
 595 #define VR_STATIC_VOLTAGE        5
 596
 597 #define CLOCK_STRETCHER_MAX_ENTRIES 0x4
 598 #define CKS_LOOKUPTable_MAX_ENTRIES 0x4
 599
 600 #define CLOCK_STRETCHER_SETTING_DDT_MASK             0x01
 601 #define CLOCK_STRETCHER_SETTING_DDT_SHIFT            0x0
 602 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK  0x1E
 603 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
 604 #define CLOCK_STRETCHER_SETTING_ENABLE_MASK          0x80
 605 #define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT         0x7
 606
 607 struct SMU_ClockStretcherDataTableEntry {
 608         uint8_t minVID;
 609         uint8_t maxVID;
 610
 611         uint16_t setting;
 612 };
 613 typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
 614
 615 struct SMU_ClockStretcherDataTable {
 616         SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
 617 };
 618 typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
 619
 620 struct SMU_CKS_LOOKUPTableEntry {
 621         uint16_t minFreq;
 622         uint16_t maxFreq;
 623
 624         uint8_t setting;
 625         uint8_t padding[3];
 626 };
 627 typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
 628
 629 struct SMU_CKS_LOOKUPTable {
 630         SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
 631 };
 632 typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
 633
 634 struct AgmAvfsData_t {
 635         uint16_t avgPsmCount[28];
 636         uint16_t minPsmCount[28];
 637 };
 638 typedef struct AgmAvfsData_t AgmAvfsData_t;
 639
 640 enum VFT_COLUMNS {
 641         SCLK0,
 642         SCLK1,
 643         SCLK2,
 644         SCLK3,
 645         SCLK4,
 646         SCLK5,
 647         SCLK6,
 648         SCLK7,
 649
 650         NUM_VFT_COLUMNS
 651 };
 652 enum {
 653   SCS_FUSE_T0,
 654   SCS_FUSE_T1,
 655   NUM_SCS_FUSE_TEMPERATURE
 656 };
 657 enum {
 658   SCKS_ON,
 659   SCKS_OFF,
 660   NUM_SCKS_STATE_TYPES
 661 };
 662
 663 #define VFT_TABLE_DEFINED
 664
 665 #define TEMP_RANGE_MAXSTEPS 12
 666 struct VFT_CELL_t {
 667         uint16_t Voltage;
 668 };
 669
 670 typedef struct VFT_CELL_t VFT_CELL_t;
 671 #ifdef SMU__FIRMWARE_SCKS_PRESENT__1
 672 struct SCS_CELL_t {
 673         uint16_t PsmCnt[NUM_SCKS_STATE_TYPES];
 674 };
 675 typedef struct SCS_CELL_t SCS_CELL_t;
 676 #endif
 677
 678 struct VFT_TABLE_t {
 679         VFT_CELL_t    Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS];
 680         uint16_t      AvfsGbv [NUM_VFT_COLUMNS];
 681         uint16_t      BtcGbv  [NUM_VFT_COLUMNS];
 682         int16_t       Temperature [TEMP_RANGE_MAXSTEPS];
 683
 684 #ifdef SMU__FIRMWARE_SCKS_PRESENT__1
 685         SCS_CELL_t    ScksCell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS];
 686 #endif
 687
 688         uint8_t       NumTemperatureSteps;
 689         uint8_t       padding[3];
 690 };
 691 typedef struct VFT_TABLE_t VFT_TABLE_t;
 692
 693 #define BTCGB_VDROOP_TABLE_MAX_ENTRIES 2
 694 #define AVFSGB_VDROOP_TABLE_MAX_ENTRIES 2
 695
 696 struct GB_VDROOP_TABLE_t {
 697         int32_t a0;
 698         int32_t a1;
 699         int32_t a2;
 700         uint32_t spare;
 701 };
 702 typedef struct GB_VDROOP_TABLE_t GB_VDROOP_TABLE_t;
 703
 704 struct SMU_QuadraticCoeffs {
 705         int32_t m1;
 706         int32_t b;
 707
 708         int16_t m2;
 709         uint8_t m1_shift;
 710         uint8_t m2_shift;
 711 };
 712 typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
 713
 714 struct AVFS_Margin_t {
 715         VFT_CELL_t Cell[NUM_VFT_COLUMNS];
 716 };
 717 typedef struct AVFS_Margin_t AVFS_Margin_t;
 718
 719 struct AVFS_CksOff_Gbv_t {
 720         VFT_CELL_t Cell[NUM_VFT_COLUMNS];
 721 };
 722 typedef struct AVFS_CksOff_Gbv_t AVFS_CksOff_Gbv_t;
 723
 724 struct AVFS_CksOff_AvfsGbv_t {
 725         VFT_CELL_t Cell[NUM_VFT_COLUMNS];
 726 };
 727 typedef struct AVFS_CksOff_AvfsGbv_t AVFS_CksOff_AvfsGbv_t;
 728
 729 struct AVFS_CksOff_BtcGbv_t {
 730         VFT_CELL_t Cell[NUM_VFT_COLUMNS];
 731 };
 732 typedef struct AVFS_CksOff_BtcGbv_t AVFS_CksOff_BtcGbv_t;
 733
 734 struct AVFS_meanNsigma_t {
 735         uint32_t Aconstant[3];
 736         uint16_t DC_tol_sigma;
 737         uint16_t Platform_mean;
 738         uint16_t Platform_sigma;
 739         uint16_t PSM_Age_CompFactor;
 740         uint8_t  Static_Voltage_Offset[NUM_VFT_COLUMNS];
 741 };
 742 typedef struct AVFS_meanNsigma_t AVFS_meanNsigma_t;
 743
 744 struct AVFS_Sclk_Offset_t {
 745         uint16_t Sclk_Offset[8];
 746 };
 747 typedef struct AVFS_Sclk_Offset_t AVFS_Sclk_Offset_t;
 748
 749 struct Power_Sharing_t {
 750         uint32_t EnergyCounter;
 751         uint32_t EngeryThreshold;
 752         uint64_t AM_SCLK_CNT;
 753         uint64_t AM_0_BUSY_CNT;
 754 };
 755 typedef struct Power_Sharing_t  Power_Sharing_t;
 756
 757
 758 #endif
 759
 760