1 #ifndef SMU72_DISCRETE_H
2 #define SMU72_DISCRETE_H
6 #if !defined(SMC_MICROCODE)
16 typedef struct SMIO_Pattern SMIO_Pattern;
19 SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
22 typedef struct SMIO_Table SMIO_Table;
24 struct SMU72_Discrete_GraphicsLevel {
25 SMU_VoltageLevel MinVoltage;
27 uint32_t SclkFrequency;
30 uint8_t DeepSleepDivId;
31 uint16_t ActivityLevel;
33 uint32_t CgSpllFuncCntl3;
34 uint32_t CgSpllFuncCntl4;
35 uint32_t SpllSpreadSpectrum;
36 uint32_t SpllSpreadSpectrum2;
40 uint8_t DisplayWatermark;
41 uint8_t EnabledForActivity;
42 uint8_t EnabledForThrottle;
45 uint8_t VoltageDownHyst;
46 uint8_t PowerThrottle;
49 typedef struct SMU72_Discrete_GraphicsLevel SMU72_Discrete_GraphicsLevel;
51 struct SMU72_Discrete_ACPILevel {
53 SMU_VoltageLevel MinVoltage;
54 uint32_t SclkFrequency;
56 uint8_t DisplayWatermark;
57 uint8_t DeepSleepDivId;
59 uint32_t CgSpllFuncCntl;
60 uint32_t CgSpllFuncCntl2;
61 uint32_t CgSpllFuncCntl3;
62 uint32_t CgSpllFuncCntl4;
63 uint32_t SpllSpreadSpectrum;
64 uint32_t SpllSpreadSpectrum2;
69 typedef struct SMU72_Discrete_ACPILevel SMU72_Discrete_ACPILevel;
71 struct SMU72_Discrete_Ulv {
75 uint8_t VddcOffsetVid;
80 typedef struct SMU72_Discrete_Ulv SMU72_Discrete_Ulv;
82 struct SMU72_Discrete_MemoryLevel {
83 SMU_VoltageLevel MinVoltage;
86 uint32_t MclkFrequency;
88 uint8_t EdcReadEnable;
89 uint8_t EdcWriteEnable;
91 uint8_t StutterEnable;
95 uint8_t EnabledForThrottle;
96 uint8_t EnabledForActivity;
100 uint8_t VoltageDownHyst;
103 uint16_t ActivityLevel;
104 uint8_t DisplayWatermark;
107 uint32_t MpllFuncCntl;
108 uint32_t MpllFuncCntl_1;
109 uint32_t MpllFuncCntl_2;
110 uint32_t MpllAdFuncCntl;
111 uint32_t MpllDqFuncCntl;
112 uint32_t MclkPwrmgtCntl;
118 typedef struct SMU72_Discrete_MemoryLevel SMU72_Discrete_MemoryLevel;
120 struct SMU72_Discrete_LinkLevel {
121 uint8_t PcieGenSpeed; /*< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
122 uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
123 uint8_t EnabledForActivity;
125 uint32_t DownThreshold;
126 uint32_t UpThreshold;
130 typedef struct SMU72_Discrete_LinkLevel SMU72_Discrete_LinkLevel;
132 /* MC ARB DRAM Timing registers. */
133 struct SMU72_Discrete_MCArbDramTimingTableEntry {
134 uint32_t McArbDramTiming;
135 uint32_t McArbDramTiming2;
136 uint8_t McArbBurstTime;
140 typedef struct SMU72_Discrete_MCArbDramTimingTableEntry SMU72_Discrete_MCArbDramTimingTableEntry;
142 struct SMU72_Discrete_MCArbDramTimingTable {
143 SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
146 typedef struct SMU72_Discrete_MCArbDramTimingTable SMU72_Discrete_MCArbDramTimingTable;
148 /* UVD VCLK/DCLK state (level) definition. */
149 struct SMU72_Discrete_UvdLevel {
150 uint32_t VclkFrequency;
151 uint32_t DclkFrequency;
152 SMU_VoltageLevel MinVoltage;
158 typedef struct SMU72_Discrete_UvdLevel SMU72_Discrete_UvdLevel;
160 /* Clocks for other external blocks (VCE, ACP, SAMU). */
161 struct SMU72_Discrete_ExtClkLevel {
163 SMU_VoltageLevel MinVoltage;
168 typedef struct SMU72_Discrete_ExtClkLevel SMU72_Discrete_ExtClkLevel;
170 struct SMU72_Discrete_StateInfo {
171 uint32_t SclkFrequency;
172 uint32_t MclkFrequency;
173 uint32_t VclkFrequency;
174 uint32_t DclkFrequency;
175 uint32_t SamclkFrequency;
176 uint32_t AclkFrequency;
177 uint32_t EclkFrequency;
178 uint16_t MvddVoltage;
180 uint8_t DisplayWatermark;
191 typedef struct SMU72_Discrete_StateInfo SMU72_Discrete_StateInfo;
193 struct SMU72_Discrete_DpmTable {
194 /* Multi-DPM controller settings */
195 SMU72_PIDController GraphicsPIDController;
196 SMU72_PIDController MemoryPIDController;
197 SMU72_PIDController LinkPIDController;
199 uint32_t SystemFlags;
201 /* SMIO masks for voltage and phase controls */
205 SMIO_Table SmioTable1;
206 SMIO_Table SmioTable2;
208 uint32_t VddcLevelCount;
209 uint32_t VddciLevelCount;
210 uint32_t VddGfxLevelCount;
211 uint32_t MvddLevelCount;
213 uint16_t VddcTable[SMU72_MAX_LEVELS_VDDC];
214 uint16_t VddGfxTable[SMU72_MAX_LEVELS_VDDGFX];
215 uint16_t VddciTable[SMU72_MAX_LEVELS_VDDCI];
217 uint8_t BapmVddGfxVidHiSidd[SMU72_MAX_LEVELS_VDDGFX];
218 uint8_t BapmVddGfxVidLoSidd[SMU72_MAX_LEVELS_VDDGFX];
219 uint8_t BapmVddGfxVidHiSidd2[SMU72_MAX_LEVELS_VDDGFX];
221 uint8_t BapmVddcVidHiSidd[SMU72_MAX_LEVELS_VDDC];
222 uint8_t BapmVddcVidLoSidd[SMU72_MAX_LEVELS_VDDC];
223 uint8_t BapmVddcVidHiSidd2[SMU72_MAX_LEVELS_VDDC];
225 uint8_t GraphicsDpmLevelCount;
226 uint8_t MemoryDpmLevelCount;
227 uint8_t LinkLevelCount;
228 uint8_t MasterDeepSleepControl;
230 uint8_t UvdLevelCount;
231 uint8_t VceLevelCount;
232 uint8_t AcpLevelCount;
233 uint8_t SamuLevelCount;
235 uint8_t ThermOutGpio;
236 uint8_t ThermOutPolarity;
237 uint8_t ThermOutMode;
238 uint8_t DPMFreezeAndForced;
239 uint32_t Reserved[4];
241 /* State table entries for each DPM state */
242 SMU72_Discrete_GraphicsLevel GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS];
243 SMU72_Discrete_MemoryLevel MemoryACPILevel;
244 SMU72_Discrete_MemoryLevel MemoryLevel[SMU72_MAX_LEVELS_MEMORY];
245 SMU72_Discrete_LinkLevel LinkLevel[SMU72_MAX_LEVELS_LINK];
246 SMU72_Discrete_ACPILevel ACPILevel;
247 SMU72_Discrete_UvdLevel UvdLevel[SMU72_MAX_LEVELS_UVD];
248 SMU72_Discrete_ExtClkLevel VceLevel[SMU72_MAX_LEVELS_VCE];
249 SMU72_Discrete_ExtClkLevel AcpLevel[SMU72_MAX_LEVELS_ACP];
250 SMU72_Discrete_ExtClkLevel SamuLevel[SMU72_MAX_LEVELS_SAMU];
251 SMU72_Discrete_Ulv Ulv;
253 uint32_t SclkStepSize;
254 uint32_t Smio[SMU72_MAX_ENTRIES_SMIO];
256 uint8_t UvdBootLevel;
257 uint8_t VceBootLevel;
258 uint8_t AcpBootLevel;
259 uint8_t SamuBootLevel;
261 uint8_t GraphicsBootLevel;
262 uint8_t GraphicsVoltageChangeEnable;
263 uint8_t GraphicsThermThrottleEnable;
264 uint8_t GraphicsInterval;
266 uint8_t VoltageInterval;
267 uint8_t ThermalInterval;
268 uint16_t TemperatureLimitHigh;
270 uint16_t TemperatureLimitLow;
271 uint8_t MemoryBootLevel;
272 uint8_t MemoryVoltageChangeEnable;
275 uint8_t MemoryInterval;
276 uint8_t MemoryThermThrottleEnable;
278 uint16_t VoltageResponseTime;
279 uint16_t PhaseResponseTime;
281 uint8_t PCIeBootLinkLevel;
282 uint8_t PCIeGenInterval;
291 uint16_t PPM_PkgPwrLimit;
292 uint16_t PPM_TemperatureLimit;
297 uint16_t FpsHighThreshold;
298 uint16_t FpsLowThreshold;
300 uint16_t BAPMTI_R[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
301 uint16_t BAPMTI_RC[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
303 uint8_t DTEAmbientTempBase;
308 SMU_VoltageLevel BootVoltage;
310 uint32_t BAPM_TEMP_GRADIENT;
312 uint32_t LowSclkInterruptThreshold;
313 uint32_t VddGfxReChkWait;
315 uint8_t ClockStretcherAmount;
317 uint8_t Sclk_CKS_masterEn0_7;
318 uint8_t Sclk_CKS_masterEn8_15;
321 uint8_t Sclk_voltageOffset[8];
323 SMU_ClockStretcherDataTable ClockStretcherDataTable;
324 SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
327 typedef struct SMU72_Discrete_DpmTable SMU72_Discrete_DpmTable;
329 /* --------------------------------------------------- AC Timing Parameters ------------------------------------------------ */
330 #define SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
331 #define SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU72_MAX_LEVELS_MEMORY /* DPM */
333 struct SMU72_Discrete_MCRegisterAddress {
338 typedef struct SMU72_Discrete_MCRegisterAddress SMU72_Discrete_MCRegisterAddress;
340 struct SMU72_Discrete_MCRegisterSet {
341 uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
344 typedef struct SMU72_Discrete_MCRegisterSet SMU72_Discrete_MCRegisterSet;
346 struct SMU72_Discrete_MCRegisters {
349 SMU72_Discrete_MCRegisterAddress address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
350 SMU72_Discrete_MCRegisterSet data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
353 typedef struct SMU72_Discrete_MCRegisters SMU72_Discrete_MCRegisters;
356 /* --------------------------------------------------- Fan Table ----------------------------------------------------------- */
358 struct SMU72_Discrete_FanTable {
373 uint32_t RefreshPeriod;
376 int8_t FanControl_GL_Flag;
379 typedef struct SMU72_Discrete_FanTable SMU72_Discrete_FanTable;
381 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
382 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
384 struct SMU7_MclkDpmScoreboard {
386 uint32_t PercentageBusy;
392 uint32_t SigmaDeltaAccum;
393 uint32_t SigmaDeltaOutput;
394 uint32_t SigmaDeltaLevel;
396 uint32_t UtilizationSetpoint;
398 uint8_t TdpClampMode;
399 uint8_t TdcClampMode;
400 uint8_t ThermClampMode;
405 uint8_t LevelChangeInProgress;
409 uint8_t VoltageDownHyst;
414 uint8_t DpmForceLevel;
415 uint8_t DisplayWatermark;
418 uint32_t MinimumPerfMclk;
422 uint8_t MclkSwitchInProgress;
423 uint8_t MclkSwitchCritical;
425 uint8_t IgnoreVBlank;
426 uint8_t TargetMclkIndex;
427 uint8_t TargetMvddIndex;
428 uint8_t MclkSwitchResult;
430 uint16_t VbiFailureCount;
431 uint8_t VbiWaitCounter;
432 uint8_t EnabledLevelsChange;
434 uint16_t LevelResidencyCountersN[SMU72_MAX_LEVELS_MEMORY];
435 uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_MEMORY];
437 void (*TargetStateCalculator)(uint8_t);
438 void (*SavedTargetStateCalculator)(uint8_t);
440 uint16_t AutoDpmInterval;
441 uint16_t AutoDpmRange;
443 uint16_t VbiTimeoutCount;
444 uint16_t MclkSwitchingTime;
447 uint8_t Save_PIC_VDDGFX_EXIT;
448 uint8_t Save_PIC_VDDGFX_ENTER;
453 typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
455 struct SMU7_UlvScoreboard {
459 uint8_t WaitingForUlv;
462 uint8_t UlvMasterEnable;
464 uint32_t UlvAbortedCount;
465 uint32_t UlvTimeStamp;
468 typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
470 struct VddgfxSavedRegisters {
472 uint32_t MEC_BaseAddress_Hi;
473 uint32_t MEC_BaseAddress_Lo;
474 uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
475 uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
476 uint32_t CP_INT_CNTL;
479 typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
481 struct SMU7_VddGfxScoreboard {
482 uint8_t VddGfxEnable;
483 uint8_t VddGfxActive;
484 uint8_t VPUResetOccured;
487 uint32_t VddGfxEnteredCount;
488 uint32_t VddGfxAbortedCount;
492 VddgfxSavedRegisters SavedRegisters;
495 typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
497 struct SMU7_TdcLimitScoreboard {
501 uint32_t FilteredIddc;
504 SMU7_HystController_Data HystControllerData;
507 typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
509 struct SMU7_PkgPwrLimitScoreboard {
513 uint32_t FilteredPkgPwr;
516 uint32_t LimitFromDriver;
517 SMU7_HystController_Data HystControllerData;
520 typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
522 struct SMU7_BapmScoreboard {
523 uint32_t source_powers[SMU72_DTE_SOURCES];
524 uint32_t source_powers_last[SMU72_DTE_SOURCES];
525 int32_t entity_temperatures[SMU72_NUM_GPU_TES];
526 int32_t initial_entity_temperatures[SMU72_NUM_GPU_TES];
529 int32_t therm_influence_coeff_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS * 2];
530 int32_t therm_node_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
531 uint16_t ConfigTDPPowerScalar;
532 uint16_t FanSpeedPowerScalar;
533 uint16_t OverDrivePowerScalar;
534 uint16_t OverDriveLimitScalar;
535 uint16_t FinalPowerScalar;
539 SMU7_HystController_Data HystControllerData;
541 int32_t temperature_gradient_slope;
542 int32_t temperature_gradient;
543 uint32_t measured_temperature;
547 typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
549 struct SMU7_AcpiScoreboard {
550 uint32_t SavedInterruptMask[2];
551 uint8_t LastACPIRequest;
555 SMU72_Discrete_ACPILevel D0Level;
558 typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
560 struct SMU72_Discrete_PmFuses {
562 uint8_t SviLoadLineEn;
563 uint8_t SviLoadLineVddC;
564 uint8_t SviLoadLineTrimVddC;
565 uint8_t SviLoadLineOffsetVddC;
568 uint16_t TDC_VDDC_PkgLimit;
569 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
573 uint8_t TdcWaterfallCtl;
574 uint8_t LPMLTemperatureMin;
575 uint8_t LPMLTemperatureMax;
579 uint8_t LPMLTemperatureScaler[16];
582 int16_t FuzzyFan_ErrorSetDelta;
583 int16_t FuzzyFan_ErrorRateSetDelta;
584 int16_t FuzzyFan_PwmSetDelta;
591 uint8_t GnbLPMLMaxVid;
592 uint8_t GnbLPMLMinVid;
593 uint8_t Reserved1[2];
596 uint16_t BapmVddCBaseLeakageHiSidd;
597 uint16_t BapmVddCBaseLeakageLoSidd;
600 typedef struct SMU72_Discrete_PmFuses SMU72_Discrete_PmFuses;
602 struct SMU7_Discrete_Log_Header_Table {
608 uint32_t num_of_entries;
612 uint32_t filler_1[2];
615 typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
617 struct SMU7_Discrete_Log_Cntl {
622 uint32_t SamplesLogged;
628 typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
630 #define CAC_ACC_NW_NUM_OF_SIGNALS 87
632 struct SMU7_Discrete_Cac_Collection_Table {
633 uint32_t temperature;
634 uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
637 typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
639 struct SMU7_Discrete_Cac_Verification_Table {
640 uint32_t VddcTotalPower;
641 uint32_t VddcLeakagePower;
642 uint32_t VddcConstantPower;
643 uint32_t VddcGfxDynamicPower;
644 uint32_t VddcUvdDynamicPower;
645 uint32_t VddcVceDynamicPower;
646 uint32_t VddcAcpDynamicPower;
647 uint32_t VddcPcieDynamicPower;
648 uint32_t VddcDceDynamicPower;
649 uint32_t VddcCurrent;
650 uint32_t VddcVoltage;
651 uint32_t VddciTotalPower;
652 uint32_t VddciLeakagePower;
653 uint32_t VddciConstantPower;
654 uint32_t VddciDynamicPower;
655 uint32_t Vddr1TotalPower;
656 uint32_t Vddr1LeakagePower;
657 uint32_t Vddr1ConstantPower;
658 uint32_t Vddr1DynamicPower;
660 uint32_t temperature;
663 typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
665 struct SMU7_Discrete_Pm_Status_Table {
666 /* Thermal entities */
671 uint32_t P_scalar_acc;
678 uint32_t I_calc_acc_vddci;
679 uint32_t V_calc_noload_acc;
680 uint32_t V_calc_load_acc;
681 uint32_t V_calc_noload_acc_vddci;
683 uint32_t V_meas_noload_acc;
684 uint32_t V_meas_load_acc;
686 uint32_t P_meas_acc_vddci;
687 uint32_t V_meas_noload_acc_vddci;
688 uint32_t V_meas_load_acc_vddci;
689 uint32_t I_meas_acc_vddci;
692 uint16_t Sclk_dpm_residency[8];
693 uint16_t Uvd_dpm_residency[8];
694 uint16_t Vce_dpm_residency[8];
695 uint16_t Mclk_dpm_residency[4];
698 uint32_t P_vddci_acc;
699 uint32_t P_vddr1_acc;
703 uint32_t MclkSwitchingTime_max;
704 uint32_t MclkSwitchingTime_acc;
711 typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
713 /*FIXME THESE NEED TO BE UPDATED */
714 #define SMU7_SCLK_CAC 0x561
715 #define SMU7_MCLK_CAC 0xF9
716 #define SMU7_VCLK_CAC 0x2DE
717 #define SMU7_DCLK_CAC 0x2DE
718 #define SMU7_ECLK_CAC 0x25E
719 #define SMU7_ACLK_CAC 0x25E
720 #define SMU7_SAMCLK_CAC 0x25E
721 #define SMU7_DISPCLK_CAC 0x100
722 #define SMU7_CAC_CONSTANT 0x2EE3430
723 #define SMU7_CAC_CONSTANT_SHIFT 18
725 #define SMU7_VDDCI_MCLK_CONST 1765
726 #define SMU7_VDDCI_MCLK_CONST_SHIFT 16
727 #define SMU7_VDDCI_VDDCI_CONST 50958
728 #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
729 #define SMU7_VDDCI_CONST 11781
731 #define SMU7_12C_VDDCI_MCLK_CONST 1623
732 #define SMU7_12C_VDDCI_MCLK_CONST_SHIFT 15
733 #define SMU7_12C_VDDCI_VDDCI_CONST 40088
734 #define SMU7_12C_VDDCI_VDDCI_CONST_SHIFT 13
735 #define SMU7_12C_VDDCI_CONST 20856
737 #define SMU7_VDDCI_STROBE_PWR 1331
739 #define SMU7_VDDR1_CONST 693
740 #define SMU7_VDDR1_CAC_WEIGHT 20
741 #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
742 #define SMU7_VDDR1_STROBE_PWR 512
744 #define SMU7_AREA_COEFF_UVD 0xA78
745 #define SMU7_AREA_COEFF_VCE 0x190A
746 #define SMU7_AREA_COEFF_ACP 0x22D1
747 #define SMU7_AREA_COEFF_SAMU 0x534
749 /*ThermOutMode values */
750 #define SMU7_THERM_OUT_MODE_DISABLE 0x0
751 #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
752 #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
754 #if !defined(SMC_MICROCODE)