drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef _HARDWARE_MANAGER_H_
  24 #define _HARDWARE_MANAGER_H_
  25
  26
  27
  28 struct pp_hwmgr;
  29 struct pp_hw_power_state;
  30 struct pp_power_state;
  31 enum amd_dpm_forced_level;
  32 struct PP_TemperatureRange;
  33
  34
  35 struct phm_fan_speed_info {
  36         uint32_t min_percent;
  37         uint32_t max_percent;
  38         uint32_t min_rpm;
  39         uint32_t max_rpm;
  40         bool supports_percent_read;
  41         bool supports_percent_write;
  42         bool supports_rpm_read;
  43         bool supports_rpm_write;
  44 };
  45
  46 /* Automatic Power State Throttling */
  47 enum PHM_AutoThrottleSource
  48 {
  49     PHM_AutoThrottleSource_Thermal,
  50     PHM_AutoThrottleSource_External
  51 };
  52
  53 typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource;
  54
  55 enum phm_platform_caps {
  56         PHM_PlatformCaps_AtomBiosPpV1 = 0,
  57         PHM_PlatformCaps_PowerPlaySupport,
  58         PHM_PlatformCaps_ACOverdriveSupport,
  59         PHM_PlatformCaps_BacklightSupport,
  60         PHM_PlatformCaps_ThermalController,
  61         PHM_PlatformCaps_BiosPowerSourceControl,
  62         PHM_PlatformCaps_DisableVoltageTransition,
  63         PHM_PlatformCaps_DisableEngineTransition,
  64         PHM_PlatformCaps_DisableMemoryTransition,
  65         PHM_PlatformCaps_DynamicPowerManagement,
  66         PHM_PlatformCaps_EnableASPML0s,
  67         PHM_PlatformCaps_EnableASPML1,
  68         PHM_PlatformCaps_OD5inACSupport,
  69         PHM_PlatformCaps_OD5inDCSupport,
  70         PHM_PlatformCaps_SoftStateOD5,
  71         PHM_PlatformCaps_NoOD5Support,
  72         PHM_PlatformCaps_ContinuousHardwarePerformanceRange,
  73         PHM_PlatformCaps_ActivityReporting,
  74         PHM_PlatformCaps_EnableBackbias,
  75         PHM_PlatformCaps_OverdriveDisabledByPowerBudget,
  76         PHM_PlatformCaps_ShowPowerBudgetWarning,
  77         PHM_PlatformCaps_PowerBudgetWaiverAvailable,
  78         PHM_PlatformCaps_GFXClockGatingSupport,
  79         PHM_PlatformCaps_MMClockGatingSupport,
  80         PHM_PlatformCaps_AutomaticDCTransition,
  81         PHM_PlatformCaps_GeminiPrimary,
  82         PHM_PlatformCaps_MemorySpreadSpectrumSupport,
  83         PHM_PlatformCaps_EngineSpreadSpectrumSupport,
  84         PHM_PlatformCaps_StepVddc,
  85         PHM_PlatformCaps_DynamicPCIEGen2Support,
  86         PHM_PlatformCaps_SMC,
  87         PHM_PlatformCaps_FaultyInternalThermalReading,          /* Internal thermal controller reports faulty temperature value when DAC2 is active */
  88         PHM_PlatformCaps_EnableVoltageControl,                  /* indicates voltage can be controlled */
  89         PHM_PlatformCaps_EnableSideportControl,                 /* indicates Sideport can be controlled */
  90         PHM_PlatformCaps_VideoPlaybackEEUNotification,          /* indicates EEU notification of video start/stop is required */
  91         PHM_PlatformCaps_TurnOffPll_ASPML1,                     /* PCIE Turn Off PLL in ASPM L1 */
  92         PHM_PlatformCaps_EnableHTLinkControl,                   /* indicates HT Link can be controlled by ACPI or CLMC overridden/automated mode. */
  93         PHM_PlatformCaps_PerformanceStateOnly,                  /* indicates only performance power state to be used on current system. */
  94         PHM_PlatformCaps_ExclusiveModeAlwaysHigh,               /* In Exclusive (3D) mode always stay in High state. */
  95         PHM_PlatformCaps_DisableMGClockGating,                  /* to disable Medium Grain Clock Gating or not */
  96         PHM_PlatformCaps_DisableMGCGTSSM,                       /* TO disable Medium Grain Clock Gating Shader Complex control */
  97         PHM_PlatformCaps_UVDAlwaysHigh,                         /* In UVD mode always stay in High state */
  98         PHM_PlatformCaps_DisablePowerGating,                    /* to disable power gating */
  99         PHM_PlatformCaps_CustomThermalPolicy,                   /* indicates only performance power state to be used on current system. */
 100         PHM_PlatformCaps_StayInBootState,                       /* Stay in Boot State, do not do clock/voltage or PCIe Lane and Gen switching (RV7xx and up). */
 101         PHM_PlatformCaps_SMCAllowSeparateSWThermalState,        /* SMC use separate SW thermal state, instead of the default SMC thermal policy. */
 102         PHM_PlatformCaps_MultiUVDStateSupport,                  /* Powerplay state table supports multi UVD states. */
 103         PHM_PlatformCaps_EnableSCLKDeepSleepForUVD,             /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */
 104         PHM_PlatformCaps_EnableMCUHTLinkControl,                /* Enable HT link control by MCU */
 105         PHM_PlatformCaps_ABM,                                   /* ABM support.*/
 106         PHM_PlatformCaps_KongThermalPolicy,                     /* A thermal policy specific for Kong */
 107         PHM_PlatformCaps_SwitchVDDNB,                           /* if the users want to switch VDDNB */
 108         PHM_PlatformCaps_ULPS,                                  /* support ULPS mode either through ACPI state or ULPS state */
 109         PHM_PlatformCaps_NativeULPS,                            /* hardware capable of ULPS state (other than through the ACPI state) */
 110         PHM_PlatformCaps_EnableMVDDControl,                     /* indicates that memory voltage can be controlled */
 111         PHM_PlatformCaps_ControlVDDCI,                          /* Control VDDCI separately from VDDC. */
 112         PHM_PlatformCaps_DisableDCODT,                          /* indicates if DC ODT apply or not */
 113         PHM_PlatformCaps_DynamicACTiming,                       /* if the SMC dynamically re-programs MC SEQ register values */
 114         PHM_PlatformCaps_EnableThermalIntByGPIO,                /* enable throttle control through GPIO */
 115         PHM_PlatformCaps_BootStateOnAlert,                      /* Go to boot state on alerts, e.g. on an AC->DC transition. */
 116         PHM_PlatformCaps_DontWaitForVBlankOnAlert,              /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
 117         PHM_PlatformCaps_Force3DClockSupport,                   /* indicates if the platform supports force 3D clock. */
 118         PHM_PlatformCaps_MicrocodeFanControl,                   /* Fan is controlled by the SMC microcode. */
 119         PHM_PlatformCaps_AdjustUVDPriorityForSP,
 120         PHM_PlatformCaps_DisableLightSleep,                     /* Light sleep for evergreen family. */
 121         PHM_PlatformCaps_DisableMCLS,                           /* MC Light sleep */
 122         PHM_PlatformCaps_RegulatorHot,                          /* Enable throttling on 'regulator hot' events. */
 123         PHM_PlatformCaps_BACO,                                  /* Support Bus Alive Chip Off mode */
 124         PHM_PlatformCaps_DisableDPM,                            /* Disable DPM, supported from Llano */
 125         PHM_PlatformCaps_DynamicM3Arbiter,                      /* support dynamically change m3 arbitor parameters */
 126         PHM_PlatformCaps_SclkDeepSleep,                         /* support sclk deep sleep */
 127         PHM_PlatformCaps_DynamicPatchPowerState,                /* this ASIC supports to patch power state dynamically */
 128         PHM_PlatformCaps_ThermalAutoThrottling,                 /* enabling auto thermal throttling, */
 129         PHM_PlatformCaps_SumoThermalPolicy,                     /* A thermal policy specific for Sumo */
 130         PHM_PlatformCaps_PCIEPerformanceRequest,                /* support to change RC voltage */
 131         PHM_PlatformCaps_BLControlledByGPU,                     /* support varibright */
 132         PHM_PlatformCaps_PowerContainment,                      /* support DPM2 power containment (AKA TDP clamping) */
 133         PHM_PlatformCaps_SQRamping,                             /* support DPM2 SQ power throttle */
 134         PHM_PlatformCaps_CAC,                                   /* support Capacitance * Activity power estimation */
 135         PHM_PlatformCaps_NIChipsets,                            /* Northern Island and beyond chipsets */
 136         PHM_PlatformCaps_TrinityChipsets,                       /* Trinity chipset */
 137         PHM_PlatformCaps_EvergreenChipsets,                     /* Evergreen family chipset */
 138         PHM_PlatformCaps_PowerControl,                          /* Cayman and beyond chipsets */
 139         PHM_PlatformCaps_DisableLSClockGating,                  /* to disable Light Sleep control for HDP memories */
 140         PHM_PlatformCaps_BoostState,                            /* this ASIC supports boost state */
 141         PHM_PlatformCaps_UserMaxClockForMultiDisplays,          /* indicates if max memory clock is used for all status when multiple displays are connected */
 142         PHM_PlatformCaps_RegWriteDelay,                         /* indicates if back to back reg write delay is required */
 143         PHM_PlatformCaps_NonABMSupportInPPLib,                  /* ABM is not supported in PPLIB, (moved from PPLIB to DAL) */
 144         PHM_PlatformCaps_GFXDynamicMGPowerGating,               /* Enable Dynamic MG PowerGating on Trinity */
 145         PHM_PlatformCaps_DisableSMUUVDHandshake,                /* Disable SMU UVD Handshake */
 146         PHM_PlatformCaps_DTE,                                   /* Support Digital Temperature Estimation */
 147         PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE,            /* This is for the feature requested by David B., and Tonny W.*/
 148         PHM_PlatformCaps_UVDPowerGating,                        /* enable UVD power gating, supported from Llano */
 149         PHM_PlatformCaps_UVDDynamicPowerGating,                 /* enable UVD Dynamic power gating, supported from UVD5 */
 150         PHM_PlatformCaps_VCEPowerGating,                        /* Enable VCE power gating, supported for TN and later ASICs */
 151         PHM_PlatformCaps_SamuPowerGating,                       /* Enable SAMU power gating, supported for KV and later ASICs */
 152         PHM_PlatformCaps_UVDDPM,                                /* UVD clock DPM */
 153         PHM_PlatformCaps_VCEDPM,                                /* VCE clock DPM */
 154         PHM_PlatformCaps_SamuDPM,                               /* SAMU clock DPM */
 155         PHM_PlatformCaps_AcpDPM,                                /* ACP clock DPM */
 156         PHM_PlatformCaps_SclkDeepSleepAboveLow,                 /* Enable SCLK Deep Sleep on all DPM states */
 157         PHM_PlatformCaps_DynamicUVDState,                       /* Dynamic UVD State */
 158         PHM_PlatformCaps_WantSAMClkWithDummyBackEnd,            /* Set SAM Clk With Dummy Back End */
 159         PHM_PlatformCaps_WantUVDClkWithDummyBackEnd,            /* Set UVD Clk With Dummy Back End */
 160         PHM_PlatformCaps_WantVCEClkWithDummyBackEnd,            /* Set VCE Clk With Dummy Back End */
 161         PHM_PlatformCaps_WantACPClkWithDummyBackEnd,            /* Set SAM Clk With Dummy Back End */
 162         PHM_PlatformCaps_OD6inACSupport,                        /* indicates that the ASIC/back end supports OD6 */
 163         PHM_PlatformCaps_OD6inDCSupport,                        /* indicates that the ASIC/back end supports OD6 in DC */
 164         PHM_PlatformCaps_EnablePlatformPowerManagement,         /* indicates that Platform Power Management feature is supported */
 165         PHM_PlatformCaps_SurpriseRemoval,                       /* indicates that surprise removal feature is requested */
 166         PHM_PlatformCaps_NewCACVoltage,                         /* indicates new CAC voltage table support */
 167         PHM_PlatformCaps_DiDtSupport,                           /* for dI/dT feature */
 168         PHM_PlatformCaps_DBRamping,                             /* for dI/dT feature */
 169         PHM_PlatformCaps_TDRamping,                             /* for dI/dT feature */
 170         PHM_PlatformCaps_TCPRamping,                            /* for dI/dT feature */
 171         PHM_PlatformCaps_DBRRamping,                            /* for dI/dT feature */
 172         PHM_PlatformCaps_DiDtEDCEnable,                         /* for dI/dT feature */
 173         PHM_PlatformCaps_GCEDC,                                 /* for dI/dT feature */
 174         PHM_PlatformCaps_PSM,                                   /* for dI/dT feature */
 175         PHM_PlatformCaps_EnableSMU7ThermalManagement,           /* SMC will manage thermal events */
 176         PHM_PlatformCaps_FPS,                                   /* FPS support */
 177         PHM_PlatformCaps_ACP,                                   /* ACP support */
 178         PHM_PlatformCaps_SclkThrottleLowNotification,           /* SCLK Throttle Low Notification */
 179         PHM_PlatformCaps_XDMAEnabled,                           /* XDMA engine is enabled */
 180         PHM_PlatformCaps_UseDummyBackEnd,                       /* use dummy back end */
 181         PHM_PlatformCaps_EnableDFSBypass,                       /* Enable DFS bypass */
 182         PHM_PlatformCaps_VddNBDirectRequest,
 183         PHM_PlatformCaps_PauseMMSessions,
 184         PHM_PlatformCaps_UnTabledHardwareInterface,             /* Tableless/direct call hardware interface for CI and newer ASICs */
 185         PHM_PlatformCaps_SMU7,                                  /* indicates that vpuRecoveryBegin without SMU shutdown */
 186         PHM_PlatformCaps_RevertGPIO5Polarity,                   /* indicates revert GPIO5 plarity table support */
 187         PHM_PlatformCaps_Thermal2GPIO17,                        /* indicates thermal2GPIO17 table support */
 188         PHM_PlatformCaps_ThermalOutGPIO,                        /* indicates ThermalOutGPIO support, pin number is assigned by VBIOS */
 189         PHM_PlatformCaps_DisableMclkSwitchingForFrameLock,      /* Disable memory clock switch during Framelock */
 190         PHM_PlatformCaps_ForceMclkHigh,                         /* Disable memory clock switching by forcing memory clock high */
 191         PHM_PlatformCaps_VRHotGPIOConfigurable,                 /* indicates VR_HOT GPIO configurable */
 192         PHM_PlatformCaps_TempInversion,                         /* enable Temp Inversion feature */
 193         PHM_PlatformCaps_IOIC3,
 194         PHM_PlatformCaps_ConnectedStandby,
 195         PHM_PlatformCaps_EVV,
 196         PHM_PlatformCaps_EnableLongIdleBACOSupport,
 197         PHM_PlatformCaps_CombinePCCWithThermalSignal,
 198         PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc,
 199         PHM_PlatformCaps_StablePState,
 200         PHM_PlatformCaps_OD6PlusinACSupport,
 201         PHM_PlatformCaps_OD6PlusinDCSupport,
 202         PHM_PlatformCaps_ODThermalLimitUnlock,
 203         PHM_PlatformCaps_ReducePowerLimit,
 204         PHM_PlatformCaps_ODFuzzyFanControlSupport,
 205         PHM_PlatformCaps_GeminiRegulatorFanControlSupport,
 206         PHM_PlatformCaps_ControlVDDGFX,
 207         PHM_PlatformCaps_BBBSupported,
 208         PHM_PlatformCaps_DisableVoltageIsland,
 209         PHM_PlatformCaps_FanSpeedInTableIsRPM,
 210         PHM_PlatformCaps_GFXClockGatingManagedInCAIL,
 211         PHM_PlatformCaps_IcelandULPSSWWorkAround,
 212         PHM_PlatformCaps_FPSEnhancement,
 213         PHM_PlatformCaps_LoadPostProductionFirmware,
 214         PHM_PlatformCaps_VpuRecoveryInProgress,
 215         PHM_PlatformCaps_Falcon_QuickTransition,
 216         PHM_PlatformCaps_AVFS,
 217         PHM_PlatformCaps_ClockStretcher,
 218         PHM_PlatformCaps_TablelessHardwareInterface,
 219         PHM_PlatformCaps_EnableDriverEVV,
 220         PHM_PlatformCaps_SPLLShutdownSupport,
 221         PHM_PlatformCaps_VirtualBatteryState,
 222         PHM_PlatformCaps_IgnoreForceHighClockRequestsInAPUs,
 223         PHM_PlatformCaps_DisableMclkSwitchForVR,
 224         PHM_PlatformCaps_SMU8,
 225         PHM_PlatformCaps_VRHotPolarityHigh,
 226         PHM_PlatformCaps_IPS_UlpsExclusive,
 227         PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme,
 228         PHM_PlatformCaps_GeminiAsymmetricPower,
 229         PHM_PlatformCaps_OCLPowerOptimization,
 230         PHM_PlatformCaps_MaxPCIEBandWidth,
 231         PHM_PlatformCaps_PerfPerWattOptimizationSupport,
 232         PHM_PlatformCaps_UVDClientMCTuning,
 233         PHM_PlatformCaps_ODNinACSupport,
 234         PHM_PlatformCaps_ODNinDCSupport,
 235         PHM_PlatformCaps_Max
 236 };
 237
 238 #define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8)
 239
 240 /* Number of uint32_t entries used by CAPS table */
 241 #define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \
 242         ((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD))
 243
 244 struct pp_hw_descriptor {
 245         uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
 246 };
 247
 248 enum PHM_PerformanceLevelDesignation {
 249         PHM_PerformanceLevelDesignation_Activity,
 250         PHM_PerformanceLevelDesignation_PowerContainment
 251 };
 252
 253 typedef enum PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation;
 254
 255 struct PHM_PerformanceLevel {
 256     uint32_t    coreClock;
 257     uint32_t    memory_clock;
 258     uint32_t  vddc;
 259     uint32_t  vddci;
 260     uint32_t    nonLocalMemoryFreq;
 261     uint32_t nonLocalMemoryWidth;
 262 };
 263
 264 typedef struct PHM_PerformanceLevel PHM_PerformanceLevel;
 265
 266 /* Function for setting a platform cap */
 267 static inline void phm_cap_set(uint32_t *caps,
 268                         enum phm_platform_caps c)
 269 {
 270         caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL <<
 271                              (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
 272 }
 273
 274 static inline void phm_cap_unset(uint32_t *caps,
 275                         enum phm_platform_caps c)
 276 {
 277         caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
 278 }
 279
 280 static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)
 281 {
 282         return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &
 283                   (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
 284 }
 285
 286 #define PP_PCIEGenInvalid  0xffff
 287 enum PP_PCIEGen {
 288     PP_PCIEGen1 = 0,                /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
 289     PP_PCIEGen2,                    /*PCIE 2.0 - Transfer rate of 5.0 GT/s */
 290     PP_PCIEGen3                     /*PCIE 3.0 - Transfer rate of 8.0 GT/s */
 291 };
 292
 293 typedef enum PP_PCIEGen PP_PCIEGen;
 294
 295 #define PP_Min_PCIEGen     PP_PCIEGen1
 296 #define PP_Max_PCIEGen     PP_PCIEGen3
 297 #define PP_Min_PCIELane    1
 298 #define PP_Max_PCIELane    32
 299
 300 enum phm_clock_Type {
 301         PHM_DispClock = 1,
 302         PHM_SClock,
 303         PHM_MemClock
 304 };
 305
 306 #define MAX_NUM_CLOCKS 16
 307
 308 struct PP_Clocks {
 309         uint32_t engineClock;
 310         uint32_t memoryClock;
 311         uint32_t BusBandwidth;
 312         uint32_t engineClockInSR;
 313         uint32_t dcefClock;
 314         uint32_t dcefClockInSR;
 315 };
 316
 317 struct pp_clock_info {
 318         uint32_t min_mem_clk;
 319         uint32_t max_mem_clk;
 320         uint32_t min_eng_clk;
 321         uint32_t max_eng_clk;
 322         uint32_t min_bus_bandwidth;
 323         uint32_t max_bus_bandwidth;
 324 };
 325
 326 struct phm_platform_descriptor {
 327         uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
 328         uint32_t vbiosInterruptId;
 329         struct PP_Clocks overdriveLimit;
 330         struct PP_Clocks clockStep;
 331         uint32_t hardwareActivityPerformanceLevels;
 332         uint32_t minimumClocksReductionPercentage;
 333         uint32_t minOverdriveVDDC;
 334         uint32_t maxOverdriveVDDC;
 335         uint32_t overdriveVDDCStep;
 336         uint32_t hardwarePerformanceLevels;
 337         uint16_t powerBudget;
 338         uint32_t TDPLimit;
 339         uint32_t nearTDPLimit;
 340         uint32_t nearTDPLimitAdjusted;
 341         uint32_t SQRampingThreshold;
 342         uint32_t CACLeakage;
 343         uint16_t TDPODLimit;
 344         uint32_t TDPAdjustment;
 345         bool TDPAdjustmentPolarity;
 346         uint16_t LoadLineSlope;
 347         uint32_t  VidMinLimit;
 348         uint32_t  VidMaxLimit;
 349         uint32_t  VidStep;
 350         uint32_t  VidAdjustment;
 351         bool VidAdjustmentPolarity;
 352 };
 353
 354 struct phm_clocks {
 355         uint32_t num_of_entries;
 356         uint32_t clock[MAX_NUM_CLOCKS];
 357 };
 358
 359 struct phm_odn_performance_level {
 360         uint32_t clock;
 361         uint32_t vddc;
 362         bool enabled;
 363 };
 364
 365 struct phm_odn_clock_levels {
 366         uint32_t size;
 367         uint32_t options;
 368         uint32_t flags;
 369         uint32_t number_of_performance_levels;
 370         /* variable-sized array, specify by ulNumberOfPerformanceLevels. */
 371         struct phm_odn_performance_level performance_level_entries[8];
 372 };
 373
 374 extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
 375 extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
 376 extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
 377 extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);
 378 extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
 379 extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
 380 extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
 381 extern int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr);
 382 extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr);
 383 extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block);
 384 extern int phm_set_power_state(struct pp_hwmgr *hwmgr,
 385                     const struct pp_hw_power_state *pcurrent_state,
 386                  const struct pp_hw_power_state *pnew_power_state);
 387
 388 extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 389                                    struct pp_power_state *adjusted_ps,
 390                              const struct pp_power_state *current_ps);
 391
 392 extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
 393 extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
 394 extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
 395 extern int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info);
 396 extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range);
 397 extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
 398 extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr);
 399
 400 extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
 401                                  const struct pp_hw_power_state *pstate1,
 402                                  const struct pp_hw_power_state *pstate2,
 403                                  bool *equal);
 404
 405 extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
 406                 const struct amd_pp_display_configuration *display_config);
 407
 408 extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
 409                 struct amd_pp_simple_clock_info *info);
 410
 411 extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
 412
 413 extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);
 414
 415 extern int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
 416                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
 417                                 PHM_PerformanceLevel *level);
 418
 419 extern int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
 420                         struct pp_clock_info *pclock_info,
 421                         PHM_PerformanceLevelDesignation designation);
 422
 423 extern int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
 424
 425 extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
 426
 427 extern int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
 428                 enum amd_pp_clock_type type,
 429                 struct pp_clock_levels_with_latency *clocks);
 430 extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
 431                 enum amd_pp_clock_type type,
 432                 struct pp_clock_levels_with_voltage *clocks);
 433 extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
 434                 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
 435 extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
 436                 struct pp_display_clock_request *clock);
 437
 438 extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
 439 extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr);
 440 #endif /* _HARDWARE_MANAGER_H_ */
 441