drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "vega10_thermal.h"
  25 #include "vega10_hwmgr.h"
  26 #include "vega10_ppsmc.h"
  27 #include "vega10_inc.h"
  28 #include "soc15_common.h"
  29 #include "pp_debug.h"
  30
  31 static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
  32 {
  33         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm);
  34         *current_rpm = smum_get_argument(hwmgr);
  35         return 0;
  36 }
  37
  38 int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
  39                 struct phm_fan_speed_info *fan_speed_info)
  40 {
  41
  42         if (hwmgr->thermal_controller.fanInfo.bNoFan)
  43                 return 0;
  44
  45         fan_speed_info->supports_percent_read = true;
  46         fan_speed_info->supports_percent_write = true;
  47         fan_speed_info->min_percent = 0;
  48         fan_speed_info->max_percent = 100;
  49
  50         if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
  51                 hwmgr->thermal_controller.fanInfo.
  52                 ucTachometerPulsesPerRevolution) {
  53                 fan_speed_info->supports_rpm_read = true;
  54                 fan_speed_info->supports_rpm_write = true;
  55                 fan_speed_info->min_rpm =
  56                                 hwmgr->thermal_controller.fanInfo.ulMinRPM;
  57                 fan_speed_info->max_rpm =
  58                                 hwmgr->thermal_controller.fanInfo.ulMaxRPM;
  59         } else {
  60                 fan_speed_info->min_rpm = 0;
  61                 fan_speed_info->max_rpm = 0;
  62         }
  63
  64         return 0;
  65 }
  66
  67 int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
  68                 uint32_t *speed)
  69 {
  70         uint32_t current_rpm;
  71         uint32_t percent = 0;
  72
  73         if (hwmgr->thermal_controller.fanInfo.bNoFan)
  74                 return 0;
  75
  76         if (vega10_get_current_rpm(hwmgr, &current_rpm))
  77                 return -1;
  78
  79         if (hwmgr->thermal_controller.
  80                         advanceFanControlParameters.usMaxFanRPM != 0)
  81                 percent = current_rpm * 100 /
  82                         hwmgr->thermal_controller.
  83                         advanceFanControlParameters.usMaxFanRPM;
  84
  85         *speed = percent > 100 ? 100 : percent;
  86
  87         return 0;
  88 }
  89
  90 int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
  91 {
  92         struct amdgpu_device *adev = hwmgr->adev;
  93         struct vega10_hwmgr *data = hwmgr->backend;
  94         uint32_t tach_period;
  95         uint32_t crystal_clock_freq;
  96         int result = 0;
  97
  98         if (hwmgr->thermal_controller.fanInfo.bNoFan)
  99                 return -1;
 100
 101         if (data->smu_features[GNLD_FAN_CONTROL].supported) {
 102                 result = vega10_get_current_rpm(hwmgr, speed);
 103         } else {
 104                 tach_period =
 105                         REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
 106                                           CG_TACH_STATUS,
 107                                           TACH_PERIOD);
 108
 109                 if (tach_period == 0)
 110                         return -EINVAL;
 111
 112                 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
 113
 114                 *speed = 60 * crystal_clock_freq * 10000 / tach_period;
 115         }
 116
 117         return result;
 118 }
 119
 120 /**
 121 * Set Fan Speed Control to static mode,
 122 * so that the user can decide what speed to use.
 123 * @param    hwmgr  the address of the powerplay hardware manager.
 124 *           mode the fan control mode, 0 default, 1 by percent, 5, by RPM
 125 * @exception Should always succeed.
 126 */
 127 int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
 128 {
 129         struct amdgpu_device *adev = hwmgr->adev;
 130
 131         if (hwmgr->fan_ctrl_is_in_default_mode) {
 132                 hwmgr->fan_ctrl_default_mode =
 133                         REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
 134                                 CG_FDO_CTRL2, FDO_PWM_MODE);
 135                 hwmgr->tmin =
 136                         REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
 137                                 CG_FDO_CTRL2, TMIN);
 138                 hwmgr->fan_ctrl_is_in_default_mode = false;
 139         }
 140
 141         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
 142                         REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
 143                                 CG_FDO_CTRL2, TMIN, 0));
 144         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
 145                         REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
 146                                 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
 147
 148         return 0;
 149 }
 150
 151 /**
 152 * Reset Fan Speed Control to default mode.
 153 * @param    hwmgr  the address of the powerplay hardware manager.
 154 * @exception Should always succeed.
 155 */
 156 int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
 157 {
 158         struct amdgpu_device *adev = hwmgr->adev;
 159
 160         if (!hwmgr->fan_ctrl_is_in_default_mode) {
 161                 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
 162                         REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
 163                                 CG_FDO_CTRL2, FDO_PWM_MODE,
 164                                 hwmgr->fan_ctrl_default_mode));
 165                 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
 166                         REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
 167                                 CG_FDO_CTRL2, TMIN,
 168                                 hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
 169                 hwmgr->fan_ctrl_is_in_default_mode = true;
 170         }
 171
 172         return 0;
 173 }
 174
 175 /**
 176  * @fn vega10_enable_fan_control_feature
 177  * @brief Enables the SMC Fan Control Feature.
 178  *
 179  * @param    hwmgr - the address of the powerplay hardware manager.
 180  * @return   0 on success. -1 otherwise.
 181  */
 182 static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
 183 {
 184         struct vega10_hwmgr *data = hwmgr->backend;
 185
 186         if (data->smu_features[GNLD_FAN_CONTROL].supported) {
 187                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
 188                                 hwmgr, true,
 189                                 data->smu_features[GNLD_FAN_CONTROL].
 190                                 smu_feature_bitmap),
 191                                 "Attempt to Enable FAN CONTROL feature Failed!",
 192                                 return -1);
 193                 data->smu_features[GNLD_FAN_CONTROL].enabled = true;
 194         }
 195
 196         return 0;
 197 }
 198
 199 static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
 200 {
 201         struct vega10_hwmgr *data = hwmgr->backend;
 202
 203         if (data->smu_features[GNLD_FAN_CONTROL].supported) {
 204                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
 205                                 hwmgr, false,
 206                                 data->smu_features[GNLD_FAN_CONTROL].
 207                                 smu_feature_bitmap),
 208                                 "Attempt to Enable FAN CONTROL feature Failed!",
 209                                 return -1);
 210                 data->smu_features[GNLD_FAN_CONTROL].enabled = false;
 211         }
 212
 213         return 0;
 214 }
 215
 216 int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
 217 {
 218         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 219                 return -1;
 220
 221         PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),
 222                         "Attempt to Enable SMC FAN CONTROL Feature Failed!",
 223                         return -1);
 224
 225         return 0;
 226 }
 227
 228
 229 int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
 230 {
 231         struct vega10_hwmgr *data = hwmgr->backend;
 232
 233         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 234                 return -1;
 235
 236         if (data->smu_features[GNLD_FAN_CONTROL].supported) {
 237                 PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),
 238                                 "Attempt to Disable SMC FAN CONTROL Feature Failed!",
 239                                 return -1);
 240         }
 241         return 0;
 242 }
 243
 244 /**
 245 * Set Fan Speed in percent.
 246 * @param    hwmgr  the address of the powerplay hardware manager.
 247 * @param    speed is the percentage value (0% - 100%) to be set.
 248 * @exception Fails is the 100% setting appears to be 0.
 249 */
 250 int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
 251                 uint32_t speed)
 252 {
 253         struct amdgpu_device *adev = hwmgr->adev;
 254         uint32_t duty100;
 255         uint32_t duty;
 256         uint64_t tmp64;
 257
 258         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 259                 return 0;
 260
 261         if (speed > 100)
 262                 speed = 100;
 263
 264         if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
 265                 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
 266
 267         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
 268                                     CG_FDO_CTRL1, FMAX_DUTY100);
 269
 270         if (duty100 == 0)
 271                 return -EINVAL;
 272
 273         tmp64 = (uint64_t)speed * duty100;
 274         do_div(tmp64, 100);
 275         duty = (uint32_t)tmp64;
 276
 277         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
 278                 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
 279                         CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
 280
 281         return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
 282 }
 283
 284 /**
 285 * Reset Fan Speed to default.
 286 * @param    hwmgr  the address of the powerplay hardware manager.
 287 * @exception Always succeeds.
 288 */
 289 int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
 290 {
 291         if (hwmgr->thermal_controller.fanInfo.bNoFan)
 292                 return 0;
 293
 294         if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
 295                 return vega10_fan_ctrl_start_smc_fan_control(hwmgr);
 296         else
 297                 return vega10_fan_ctrl_set_default_mode(hwmgr);
 298 }
 299
 300 /**
 301 * Set Fan Speed in RPM.
 302 * @param    hwmgr  the address of the powerplay hardware manager.
 303 * @param    speed is the percentage value (min - max) to be set.
 304 * @exception Fails is the speed not lie between min and max.
 305 */
 306 int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
 307 {
 308         struct amdgpu_device *adev = hwmgr->adev;
 309         uint32_t tach_period;
 310         uint32_t crystal_clock_freq;
 311         int result = 0;
 312
 313         if (hwmgr->thermal_controller.fanInfo.bNoFan ||
 314             (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
 315             (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
 316                 return -1;
 317
 318         if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
 319                 result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
 320
 321         if (!result) {
 322                 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
 323                 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
 324                 WREG32_SOC15(THM, 0, mmCG_TACH_STATUS,
 325                                 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
 326                                         CG_TACH_STATUS, TACH_PERIOD,
 327                                         tach_period));
 328         }
 329         return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
 330 }
 331
 332 /**
 333 * Reads the remote temperature from the SIslands thermal controller.
 334 *
 335 * @param    hwmgr The address of the hardware manager.
 336 */
 337 int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
 338 {
 339         struct amdgpu_device *adev = hwmgr->adev;
 340         int temp;
 341
 342         temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
 343
 344         temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
 345                         CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
 346
 347         temp = temp & 0x1ff;
 348
 349         temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
 350
 351         return temp;
 352 }
 353
 354 /**
 355 * Set the requested temperature range for high and low alert signals
 356 *
 357 * @param    hwmgr The address of the hardware manager.
 358 * @param    range Temperature range to be programmed for
 359 *           high and low alert signals
 360 * @exception PP_Result_BadInput if the input data is not valid.
 361 */
 362 static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
 363                 struct PP_TemperatureRange *range)
 364 {
 365         struct phm_ppt_v2_information *pp_table_info =
 366                 (struct phm_ppt_v2_information *)(hwmgr->pptable);
 367         struct phm_tdp_table *tdp_table = pp_table_info->tdp_table;
 368         struct amdgpu_device *adev = hwmgr->adev;
 369         int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
 370                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
 371         int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
 372                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
 373         uint32_t val;
 374
 375         if (low < range->min)
 376                 low = range->min;
 377         if (high > tdp_table->usSoftwareShutdownTemp)
 378                 high = tdp_table->usSoftwareShutdownTemp;
 379
 380         if (low > high)
 381                 return -EINVAL;
 382
 383         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
 384
 385         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
 386         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
 387         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
 388         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
 389         val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &
 390                         (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &
 391                         (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
 392
 393         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
 394
 395         return 0;
 396 }
 397
 398 /**
 399 * Programs thermal controller one-time setting registers
 400 *
 401 * @param    hwmgr The address of the hardware manager.
 402 */
 403 static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
 404 {
 405         struct amdgpu_device *adev = hwmgr->adev;
 406
 407         if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
 408                 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
 409                         REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
 410                                 CG_TACH_CTRL, EDGE_PER_REV,
 411                                 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1));
 412         }
 413
 414         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
 415                 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
 416                         CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28));
 417
 418         return 0;
 419 }
 420
 421 /**
 422 * Enable thermal alerts on the RV770 thermal controller.
 423 *
 424 * @param    hwmgr The address of the hardware manager.
 425 */
 426 static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
 427 {
 428         struct amdgpu_device *adev = hwmgr->adev;
 429         struct vega10_hwmgr *data = hwmgr->backend;
 430         uint32_t val = 0;
 431
 432         if (data->smu_features[GNLD_FW_CTF].supported) {
 433                 if (data->smu_features[GNLD_FW_CTF].enabled)
 434                         printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
 435
 436                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
 437                                 true,
 438                                 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
 439                                 "Attempt to Enable FW CTF feature Failed!",
 440                                 return -1);
 441                 data->smu_features[GNLD_FW_CTF].enabled = true;
 442         }
 443
 444         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
 445         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
 446         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
 447
 448         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
 449
 450         return 0;
 451 }
 452
 453 /**
 454 * Disable thermal alerts on the RV770 thermal controller.
 455 * @param    hwmgr The address of the hardware manager.
 456 */
 457 int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
 458 {
 459         struct amdgpu_device *adev = hwmgr->adev;
 460         struct vega10_hwmgr *data = hwmgr->backend;
 461
 462         if (data->smu_features[GNLD_FW_CTF].supported) {
 463                 if (!data->smu_features[GNLD_FW_CTF].enabled)
 464                         printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
 465
 466
 467                 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
 468                         false,
 469                         data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
 470                         "Attempt to disable FW CTF feature Failed!",
 471                         return -1);
 472                 data->smu_features[GNLD_FW_CTF].enabled = false;
 473         }
 474
 475         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
 476
 477         return 0;
 478 }
 479
 480 /**
 481 * Uninitialize the thermal controller.
 482 * Currently just disables alerts.
 483 * @param    hwmgr The address of the hardware manager.
 484 */
 485 int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
 486 {
 487         int result = vega10_thermal_disable_alert(hwmgr);
 488
 489         if (!hwmgr->thermal_controller.fanInfo.bNoFan)
 490                 vega10_fan_ctrl_set_default_mode(hwmgr);
 491
 492         return result;
 493 }
 494
 495 /**
 496 * Set up the fan table to control the fan using the SMC.
 497 * @param    hwmgr  the address of the powerplay hardware manager.
 498 * @param    pInput the pointer to input data
 499 * @param    pOutput the pointer to output data
 500 * @param    pStorage the pointer to temporary storage
 501 * @param    Result the last failure code
 502 * @return   result from set temperature range routine
 503 */
 504 int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
 505 {
 506         int ret;
 507         struct vega10_hwmgr *data = hwmgr->backend;
 508         PPTable_t *table = &(data->smc_state_table.pp_table);
 509
 510         if (!data->smu_features[GNLD_FAN_CONTROL].supported)
 511                 return 0;
 512
 513         table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller.
 514                         advanceFanControlParameters.usMaxFanRPM;
 515         table->FanThrottlingRpm = hwmgr->thermal_controller.
 516                         advanceFanControlParameters.usFanRPMMaxLimit;
 517         table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller.
 518                         advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
 519         table->FanTargetTemperature = hwmgr->thermal_controller.
 520                         advanceFanControlParameters.usTMax;
 521
 522         smum_send_msg_to_smc_with_parameter(hwmgr,
 523                                 PPSMC_MSG_SetFanTemperatureTarget,
 524                                 (uint32_t)table->FanTargetTemperature);
 525
 526         table->FanPwmMin = hwmgr->thermal_controller.
 527                         advanceFanControlParameters.usPWMMin * 255 / 100;
 528         table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller.
 529                         advanceFanControlParameters.ulTargetGfxClk);
 530         table->FanGainEdge = hwmgr->thermal_controller.
 531                         advanceFanControlParameters.usFanGainEdge;
 532         table->FanGainHotspot = hwmgr->thermal_controller.
 533                         advanceFanControlParameters.usFanGainHotspot;
 534         table->FanGainLiquid = hwmgr->thermal_controller.
 535                         advanceFanControlParameters.usFanGainLiquid;
 536         table->FanGainVrVddc = hwmgr->thermal_controller.
 537                         advanceFanControlParameters.usFanGainVrVddc;
 538         table->FanGainVrMvdd = hwmgr->thermal_controller.
 539                         advanceFanControlParameters.usFanGainVrMvdd;
 540         table->FanGainPlx = hwmgr->thermal_controller.
 541                         advanceFanControlParameters.usFanGainPlx;
 542         table->FanGainHbm = hwmgr->thermal_controller.
 543                         advanceFanControlParameters.usFanGainHbm;
 544         table->FanZeroRpmEnable = hwmgr->thermal_controller.
 545                         advanceFanControlParameters.ucEnableZeroRPM;
 546         table->FanStopTemp = hwmgr->thermal_controller.
 547                         advanceFanControlParameters.usZeroRPMStopTemperature;
 548         table->FanStartTemp = hwmgr->thermal_controller.
 549                         advanceFanControlParameters.usZeroRPMStartTemperature;
 550
 551         ret = smum_smc_table_manager(hwmgr,
 552                                 (uint8_t *)(&(data->smc_state_table.pp_table)),
 553                                 PPTABLE, false);
 554         if (ret)
 555                 pr_info("Failed to update Fan Control Table in PPTable!");
 556
 557         return ret;
 558 }
 559
 560 /**
 561 * Start the fan control on the SMC.
 562 * @param    hwmgr  the address of the powerplay hardware manager.
 563 * @param    pInput the pointer to input data
 564 * @param    pOutput the pointer to output data
 565 * @param    pStorage the pointer to temporary storage
 566 * @param    Result the last failure code
 567 * @return   result from set temperature range routine
 568 */
 569 int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
 570 {
 571 /* If the fantable setup has failed we could have disabled
 572  * PHM_PlatformCaps_MicrocodeFanControl even after
 573  * this function was included in the table.
 574  * Make sure that we still think controlling the fan is OK.
 575 */
 576         if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
 577                 vega10_fan_ctrl_start_smc_fan_control(hwmgr);
 578
 579         return 0;
 580 }
 581
 582
 583 int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
 584                                 struct PP_TemperatureRange *range)
 585 {
 586         int ret = 0;
 587
 588         if (range == NULL)
 589                 return -EINVAL;
 590
 591         vega10_thermal_initialize(hwmgr);
 592         ret = vega10_thermal_set_temperature_range(hwmgr, range);
 593         if (ret)
 594                 return -EINVAL;
 595
 596         vega10_thermal_enable_alert(hwmgr);
 597 /* We should restrict performance levels to low before we halt the SMC.
 598  * On the other hand we are still in boot state when we do this
 599  * so it would be pointless.
 600  * If this assumption changes we have to revisit this table.
 601  */
 602         ret = vega10_thermal_setup_fan_table(hwmgr);
 603         if (ret)
 604                 return -EINVAL;
 605
 606         vega10_thermal_start_smc_fan_control(hwmgr);
 607
 608         return 0;
 609 };
 610
 611
 612
 613
 614 int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
 615 {
 616         if (!hwmgr->thermal_controller.fanInfo.bNoFan) {
 617                 vega10_fan_ctrl_set_default_mode(hwmgr);
 618                 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
 619         }
 620         return 0;
 621 }