2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 #include <asm/div64.h>
29 #include <drm/amdgpu_drm.h>
30 #include "ppatomctrl.h"
32 #include "pptable_v1_0.h"
33 #include "pppcielanes.h"
34 #include "amd_pcie_helpers.h"
35 #include "hardwaremanager.h"
36 #include "process_pptables_v1_0.h"
37 #include "cgs_common.h"
39 #include "smu7_common.h"
42 #include "smu7_hwmgr.h"
43 #include "smu_ucode_xfer_vi.h"
44 #include "smu7_powertune.h"
45 #include "smu7_dyn_defaults.h"
46 #include "smu7_thermal.h"
47 #include "smu7_clockpowergating.h"
48 #include "processpptables.h"
49 #include "pp_thermal.h"
51 #include "ivsrcid/ivsrcid_vislands30.h"
53 #define MC_CG_ARB_FREQ_F0 0x0a
54 #define MC_CG_ARB_FREQ_F1 0x0b
55 #define MC_CG_ARB_FREQ_F2 0x0c
56 #define MC_CG_ARB_FREQ_F3 0x0d
58 #define MC_CG_SEQ_DRAMCONF_S0 0x05
59 #define MC_CG_SEQ_DRAMCONF_S1 0x06
60 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
61 #define MC_CG_SEQ_YCLK_RESUME 0x0a
63 #define SMC_CG_IND_START 0xc0030000
64 #define SMC_CG_IND_END 0xc0040000
66 #define MEM_FREQ_LOW_LATENCY 25000
67 #define MEM_FREQ_HIGH_LATENCY 80000
69 #define MEM_LATENCY_HIGH 45
70 #define MEM_LATENCY_LOW 35
71 #define MEM_LATENCY_ERR 0xFFFF
73 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
74 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
75 #define MC_SEQ_MISC0_GDDR5_VALUE 5
77 #define PCIE_BUS_CLK 10000
78 #define TCLK (PCIE_BUS_CLK / 10)
80 static const struct profile_mode_setting smu7_profiling[6] =
81 {{1, 0, 100, 30, 1, 0, 100, 10},
82 {1, 10, 0, 30, 0, 0, 0, 0},
83 {0, 0, 0, 0, 1, 10, 16, 31},
84 {1, 0, 11, 50, 1, 0, 100, 10},
85 {1, 0, 5, 30, 0, 0, 0, 0},
86 {0, 0, 0, 0, 0, 0, 0, 0},
89 #define PPSMC_MSG_SetVBITimeout_VEGAM ((uint16_t) 0x310)
91 #define ixPWR_SVI2_PLANE1_LOAD 0xC0200280
92 #define PWR_SVI2_PLANE1_LOAD__PSI1_MASK 0x00000020L
93 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK 0x00000040L
94 #define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT 0x00000005
95 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT 0x00000006
97 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
99 DPM_EVENT_SRC_ANALOG = 0,
100 DPM_EVENT_SRC_EXTERNAL = 1,
101 DPM_EVENT_SRC_DIGITAL = 2,
102 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
103 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
106 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
107 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
108 enum pp_clock_type type, uint32_t mask);
110 static struct smu7_power_state *cast_phw_smu7_power_state(
111 struct pp_hw_power_state *hw_ps)
113 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
114 "Invalid Powerstate Type!",
117 return (struct smu7_power_state *)hw_ps;
120 static const struct smu7_power_state *cast_const_phw_smu7_power_state(
121 const struct pp_hw_power_state *hw_ps)
123 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
124 "Invalid Powerstate Type!",
127 return (const struct smu7_power_state *)hw_ps;
131 * Find the MC microcode version and store it in the HwMgr struct
133 * @param hwmgr the address of the powerplay hardware manager.
136 static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
138 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
140 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
145 static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
147 uint32_t speedCntl = 0;
149 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
150 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
151 ixPCIE_LC_SPEED_CNTL);
152 return((uint16_t)PHM_GET_FIELD(speedCntl,
153 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
156 static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
160 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
161 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
162 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
164 PP_ASSERT_WITH_CODE((7 >= link_width),
165 "Invalid PCIe lane width!", return 0);
167 return decode_pcie_lane_width(link_width);
171 * Enable voltage control
173 * @param pHwMgr the address of the powerplay hardware manager.
174 * @return always PP_Result_OK
176 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
178 if (hwmgr->chip_id == CHIP_VEGAM) {
179 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
180 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI1, 0);
181 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
182 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI0_EN, 0);
185 if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
186 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable);
192 * Checks if we want to support voltage control
194 * @param hwmgr the address of the powerplay hardware manager.
196 static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr)
198 const struct smu7_hwmgr *data =
199 (const struct smu7_hwmgr *)(hwmgr->backend);
201 return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control);
205 * Enable voltage control
207 * @param hwmgr the address of the powerplay hardware manager.
210 static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr)
212 /* enable voltage control */
213 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
214 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
219 static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table,
220 struct phm_clock_voltage_dependency_table *voltage_dependency_table
225 PP_ASSERT_WITH_CODE((NULL != voltage_table),
226 "Voltage Dependency Table empty.", return -EINVAL;);
228 voltage_table->mask_low = 0;
229 voltage_table->phase_delay = 0;
230 voltage_table->count = voltage_dependency_table->count;
232 for (i = 0; i < voltage_dependency_table->count; i++) {
233 voltage_table->entries[i].value =
234 voltage_dependency_table->entries[i].v;
235 voltage_table->entries[i].smio_low = 0;
243 * Create Voltage Tables.
245 * @param hwmgr the address of the powerplay hardware manager.
248 static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
250 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
251 struct phm_ppt_v1_information *table_info =
252 (struct phm_ppt_v1_information *)hwmgr->pptable;
256 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
257 result = atomctrl_get_voltage_table_v3(hwmgr,
258 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
259 &(data->mvdd_voltage_table));
260 PP_ASSERT_WITH_CODE((0 == result),
261 "Failed to retrieve MVDD table.",
263 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
264 if (hwmgr->pp_table_version == PP_TABLE_V1)
265 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
266 table_info->vdd_dep_on_mclk);
267 else if (hwmgr->pp_table_version == PP_TABLE_V0)
268 result = phm_get_svi2_voltage_table_v0(&(data->mvdd_voltage_table),
269 hwmgr->dyn_state.mvdd_dependency_on_mclk);
271 PP_ASSERT_WITH_CODE((0 == result),
272 "Failed to retrieve SVI2 MVDD table from dependancy table.",
276 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
277 result = atomctrl_get_voltage_table_v3(hwmgr,
278 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
279 &(data->vddci_voltage_table));
280 PP_ASSERT_WITH_CODE((0 == result),
281 "Failed to retrieve VDDCI table.",
283 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
284 if (hwmgr->pp_table_version == PP_TABLE_V1)
285 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
286 table_info->vdd_dep_on_mclk);
287 else if (hwmgr->pp_table_version == PP_TABLE_V0)
288 result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table),
289 hwmgr->dyn_state.vddci_dependency_on_mclk);
290 PP_ASSERT_WITH_CODE((0 == result),
291 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
295 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
296 /* VDDGFX has only SVI2 voltage control */
297 result = phm_get_svi2_vdd_voltage_table(&(data->vddgfx_voltage_table),
298 table_info->vddgfx_lookup_table);
299 PP_ASSERT_WITH_CODE((0 == result),
300 "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
304 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
305 result = atomctrl_get_voltage_table_v3(hwmgr,
306 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT,
307 &data->vddc_voltage_table);
308 PP_ASSERT_WITH_CODE((0 == result),
309 "Failed to retrieve VDDC table.", return result;);
310 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
312 if (hwmgr->pp_table_version == PP_TABLE_V0)
313 result = phm_get_svi2_voltage_table_v0(&data->vddc_voltage_table,
314 hwmgr->dyn_state.vddc_dependency_on_mclk);
315 else if (hwmgr->pp_table_version == PP_TABLE_V1)
316 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
317 table_info->vddc_lookup_table);
319 PP_ASSERT_WITH_CODE((0 == result),
320 "Failed to retrieve SVI2 VDDC table from dependancy table.", return result;);
323 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
325 (data->vddc_voltage_table.count <= tmp),
326 "Too many voltage values for VDDC. Trimming to fit state table.",
327 phm_trim_voltage_table_to_fit_state_table(tmp,
328 &(data->vddc_voltage_table)));
330 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
332 (data->vddgfx_voltage_table.count <= tmp),
333 "Too many voltage values for VDDC. Trimming to fit state table.",
334 phm_trim_voltage_table_to_fit_state_table(tmp,
335 &(data->vddgfx_voltage_table)));
337 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
339 (data->vddci_voltage_table.count <= tmp),
340 "Too many voltage values for VDDCI. Trimming to fit state table.",
341 phm_trim_voltage_table_to_fit_state_table(tmp,
342 &(data->vddci_voltage_table)));
344 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
346 (data->mvdd_voltage_table.count <= tmp),
347 "Too many voltage values for MVDD. Trimming to fit state table.",
348 phm_trim_voltage_table_to_fit_state_table(tmp,
349 &(data->mvdd_voltage_table)));
355 * Programs static screed detection parameters
357 * @param hwmgr the address of the powerplay hardware manager.
360 static int smu7_program_static_screen_threshold_parameters(
361 struct pp_hwmgr *hwmgr)
363 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
365 /* Set static screen threshold unit */
366 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
367 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
368 data->static_screen_threshold_unit);
369 /* Set static screen threshold */
370 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
371 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
372 data->static_screen_threshold);
378 * Setup display gap for glitch free memory clock switching.
380 * @param hwmgr the address of the powerplay hardware manager.
383 static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr)
385 uint32_t display_gap =
386 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
387 ixCG_DISPLAY_GAP_CNTL);
389 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
390 DISP_GAP, DISPLAY_GAP_IGNORE);
392 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
393 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
395 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
396 ixCG_DISPLAY_GAP_CNTL, display_gap);
402 * Programs activity state transition voting clients
404 * @param hwmgr the address of the powerplay hardware manager.
407 static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
409 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
412 /* Clear reset for voting clients before enabling DPM */
413 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
414 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
415 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
416 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
418 for (i = 0; i < 8; i++)
419 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
420 ixCG_FREQ_TRAN_VOTING_0 + i * 4,
421 data->voting_rights_clients[i]);
425 static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr)
429 /* Reset voting clients before disabling DPM */
430 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
431 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
432 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
433 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
435 for (i = 0; i < 8; i++)
436 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
437 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0);
442 /* Copy one arb setting to another and then switch the active set.
443 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
445 static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
446 uint32_t arb_src, uint32_t arb_dest)
448 uint32_t mc_arb_dram_timing;
449 uint32_t mc_arb_dram_timing2;
451 uint32_t mc_cg_config;
454 case MC_CG_ARB_FREQ_F0:
455 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
456 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
457 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
459 case MC_CG_ARB_FREQ_F1:
460 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
461 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
462 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
469 case MC_CG_ARB_FREQ_F0:
470 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
471 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
472 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
474 case MC_CG_ARB_FREQ_F1:
475 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
476 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
477 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
483 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
484 mc_cg_config |= 0x0000000F;
485 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
486 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
491 static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
493 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults);
497 * Initial switch from ARB F0->F1
499 * @param hwmgr the address of the powerplay hardware manager.
501 * This function is to be called from the SetPowerState table.
503 static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
505 return smu7_copy_and_switch_arb_sets(hwmgr,
506 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
509 static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
513 tmp = (cgs_read_ind_register(hwmgr->device,
514 CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
517 if (tmp == MC_CG_ARB_FREQ_F0)
520 return smu7_copy_and_switch_arb_sets(hwmgr,
521 tmp, MC_CG_ARB_FREQ_F0);
524 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
526 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
528 struct phm_ppt_v1_information *table_info =
529 (struct phm_ppt_v1_information *)(hwmgr->pptable);
530 struct phm_ppt_v1_pcie_table *pcie_table = NULL;
532 uint32_t i, max_entry;
535 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
536 data->use_pcie_power_saving_levels), "No pcie performance levels!",
539 if (table_info != NULL)
540 pcie_table = table_info->pcie_table;
542 if (data->use_pcie_performance_levels &&
543 !data->use_pcie_power_saving_levels) {
544 data->pcie_gen_power_saving = data->pcie_gen_performance;
545 data->pcie_lane_power_saving = data->pcie_lane_performance;
546 } else if (!data->use_pcie_performance_levels &&
547 data->use_pcie_power_saving_levels) {
548 data->pcie_gen_performance = data->pcie_gen_power_saving;
549 data->pcie_lane_performance = data->pcie_lane_power_saving;
551 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
552 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
554 MAX_REGULAR_DPM_NUMBER);
556 if (pcie_table != NULL) {
557 /* max_entry is used to make sure we reserve one PCIE level
558 * for boot level (fix for A+A PSPP issue).
559 * If PCIE table from PPTable have ULV entry + 8 entries,
560 * then ignore the last entry.*/
561 max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count;
562 for (i = 1; i < max_entry; i++) {
563 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
564 get_pcie_gen_support(data->pcie_gen_cap,
565 pcie_table->entries[i].gen_speed),
566 get_pcie_lane_support(data->pcie_lane_cap,
567 pcie_table->entries[i].lane_width));
569 data->dpm_table.pcie_speed_table.count = max_entry - 1;
570 smum_update_smc_table(hwmgr, SMU_BIF_TABLE);
572 /* Hardcode Pcie Table */
573 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
574 get_pcie_gen_support(data->pcie_gen_cap,
576 get_pcie_lane_support(data->pcie_lane_cap,
578 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
579 get_pcie_gen_support(data->pcie_gen_cap,
581 get_pcie_lane_support(data->pcie_lane_cap,
583 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
584 get_pcie_gen_support(data->pcie_gen_cap,
586 get_pcie_lane_support(data->pcie_lane_cap,
588 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
589 get_pcie_gen_support(data->pcie_gen_cap,
591 get_pcie_lane_support(data->pcie_lane_cap,
593 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
594 get_pcie_gen_support(data->pcie_gen_cap,
596 get_pcie_lane_support(data->pcie_lane_cap,
598 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
599 get_pcie_gen_support(data->pcie_gen_cap,
601 get_pcie_lane_support(data->pcie_lane_cap,
604 data->dpm_table.pcie_speed_table.count = 6;
606 /* Populate last level for boot PCIE level, but do not increment count. */
607 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
608 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++)
609 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i,
610 get_pcie_gen_support(data->pcie_gen_cap,
612 data->vbios_boot_state.pcie_lane_bootup_value);
614 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
615 data->dpm_table.pcie_speed_table.count,
616 get_pcie_gen_support(data->pcie_gen_cap,
618 get_pcie_lane_support(data->pcie_lane_cap,
624 static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr)
626 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
628 memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table));
630 phm_reset_single_dpm_table(
631 &data->dpm_table.sclk_table,
632 smum_get_mac_definition(hwmgr,
633 SMU_MAX_LEVELS_GRAPHICS),
634 MAX_REGULAR_DPM_NUMBER);
635 phm_reset_single_dpm_table(
636 &data->dpm_table.mclk_table,
637 smum_get_mac_definition(hwmgr,
638 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER);
640 phm_reset_single_dpm_table(
641 &data->dpm_table.vddc_table,
642 smum_get_mac_definition(hwmgr,
643 SMU_MAX_LEVELS_VDDC),
644 MAX_REGULAR_DPM_NUMBER);
645 phm_reset_single_dpm_table(
646 &data->dpm_table.vddci_table,
647 smum_get_mac_definition(hwmgr,
648 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER);
650 phm_reset_single_dpm_table(
651 &data->dpm_table.mvdd_table,
652 smum_get_mac_definition(hwmgr,
653 SMU_MAX_LEVELS_MVDD),
654 MAX_REGULAR_DPM_NUMBER);
658 * This function is to initialize all DPM state tables
659 * for SMU7 based on the dependency table.
660 * Dynamic state patching function will then trim these
661 * state tables to the allowed range based
662 * on the power policy or external client requests,
663 * such as UVD request, etc.
666 static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
668 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
669 struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table =
670 hwmgr->dyn_state.vddc_dependency_on_sclk;
671 struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table =
672 hwmgr->dyn_state.vddc_dependency_on_mclk;
673 struct phm_cac_leakage_table *std_voltage_table =
674 hwmgr->dyn_state.cac_leakage_table;
677 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL,
678 "SCLK dependency table is missing. This table is mandatory", return -EINVAL);
679 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1,
680 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
682 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
683 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
684 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1,
685 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL);
688 /* Initialize Sclk DPM table based on allow Sclk values*/
689 data->dpm_table.sclk_table.count = 0;
691 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
692 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value !=
693 allowed_vdd_sclk_table->entries[i].clk) {
694 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
695 allowed_vdd_sclk_table->entries[i].clk;
696 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0;
697 data->dpm_table.sclk_table.count++;
701 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL,
702 "MCLK dependency table is missing. This table is mandatory", return -EINVAL);
703 /* Initialize Mclk DPM table based on allow Mclk values */
704 data->dpm_table.mclk_table.count = 0;
705 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
706 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value !=
707 allowed_vdd_mclk_table->entries[i].clk) {
708 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
709 allowed_vdd_mclk_table->entries[i].clk;
710 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0;
711 data->dpm_table.mclk_table.count++;
715 /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */
716 for (i = 0; i < allowed_vdd_sclk_table->count; i++) {
717 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
718 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage;
719 /* param1 is for corresponding std voltage */
720 data->dpm_table.vddc_table.dpm_levels[i].enabled = 1;
723 data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count;
724 allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
726 if (NULL != allowed_vdd_mclk_table) {
727 /* Initialize Vddci DPM table based on allow Mclk values */
728 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
729 data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
730 data->dpm_table.vddci_table.dpm_levels[i].enabled = 1;
732 data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count;
735 allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
737 if (NULL != allowed_vdd_mclk_table) {
739 * Initialize MVDD DPM table based on allow Mclk
742 for (i = 0; i < allowed_vdd_mclk_table->count; i++) {
743 data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v;
744 data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1;
746 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count;
752 static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
754 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
755 struct phm_ppt_v1_information *table_info =
756 (struct phm_ppt_v1_information *)(hwmgr->pptable);
759 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
760 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
762 if (table_info == NULL)
765 dep_sclk_table = table_info->vdd_dep_on_sclk;
766 dep_mclk_table = table_info->vdd_dep_on_mclk;
768 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
769 "SCLK dependency table is missing.",
771 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
772 "SCLK dependency table count is 0.",
775 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
776 "MCLK dependency table is missing.",
778 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
779 "MCLK dependency table count is 0",
782 /* Initialize Sclk DPM table based on allow Sclk values */
783 data->dpm_table.sclk_table.count = 0;
784 for (i = 0; i < dep_sclk_table->count; i++) {
785 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
786 dep_sclk_table->entries[i].clk) {
788 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
789 dep_sclk_table->entries[i].clk;
791 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
792 (i == 0) ? true : false;
793 data->dpm_table.sclk_table.count++;
796 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
797 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk;
798 /* Initialize Mclk DPM table based on allow Mclk values */
799 data->dpm_table.mclk_table.count = 0;
800 for (i = 0; i < dep_mclk_table->count; i++) {
801 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
802 [data->dpm_table.mclk_table.count - 1].value !=
803 dep_mclk_table->entries[i].clk) {
804 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
805 dep_mclk_table->entries[i].clk;
806 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
807 (i == 0) ? true : false;
808 data->dpm_table.mclk_table.count++;
812 if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
813 hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk;
817 static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
819 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
820 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
821 struct phm_ppt_v1_information *table_info =
822 (struct phm_ppt_v1_information *)(hwmgr->pptable);
825 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
826 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
827 struct phm_odn_performance_level *entries;
829 if (table_info == NULL)
832 dep_sclk_table = table_info->vdd_dep_on_sclk;
833 dep_mclk_table = table_info->vdd_dep_on_mclk;
835 odn_table->odn_core_clock_dpm_levels.num_of_pl =
836 data->golden_dpm_table.sclk_table.count;
837 entries = odn_table->odn_core_clock_dpm_levels.entries;
838 for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
839 entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value;
840 entries[i].enabled = true;
841 entries[i].vddc = dep_sclk_table->entries[i].vddc;
844 smu_get_voltage_dependency_table_ppt_v1(dep_sclk_table,
845 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
847 odn_table->odn_memory_clock_dpm_levels.num_of_pl =
848 data->golden_dpm_table.mclk_table.count;
849 entries = odn_table->odn_memory_clock_dpm_levels.entries;
850 for (i=0; i<data->golden_dpm_table.mclk_table.count; i++) {
851 entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value;
852 entries[i].enabled = true;
853 entries[i].vddc = dep_mclk_table->entries[i].vddc;
856 smu_get_voltage_dependency_table_ppt_v1(dep_mclk_table,
857 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
862 static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr)
864 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
865 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
866 struct phm_ppt_v1_information *table_info =
867 (struct phm_ppt_v1_information *)(hwmgr->pptable);
868 uint32_t min_vddc = 0;
869 uint32_t max_vddc = 0;
874 dep_sclk_table = table_info->vdd_dep_on_sclk;
876 atomctrl_get_voltage_range(hwmgr, &max_vddc, &min_vddc);
878 if (min_vddc == 0 || min_vddc > 2000
879 || min_vddc > dep_sclk_table->entries[0].vddc)
880 min_vddc = dep_sclk_table->entries[0].vddc;
882 if (max_vddc == 0 || max_vddc > 2000
883 || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc)
884 max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc;
886 data->odn_dpm_table.min_vddc = min_vddc;
887 data->odn_dpm_table.max_vddc = max_vddc;
890 static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
892 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
893 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
894 struct phm_ppt_v1_information *table_info =
895 (struct phm_ppt_v1_information *)(hwmgr->pptable);
898 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
899 struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
901 if (table_info == NULL)
904 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
905 if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=
906 data->dpm_table.sclk_table.dpm_levels[i].value) {
907 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
912 for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
913 if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=
914 data->dpm_table.mclk_table.dpm_levels[i].value) {
915 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
920 dep_table = table_info->vdd_dep_on_mclk;
921 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk);
923 for (i = 0; i < dep_table->count; i++) {
924 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
925 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
930 dep_table = table_info->vdd_dep_on_sclk;
931 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk);
932 for (i = 0; i < dep_table->count; i++) {
933 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
934 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
938 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
939 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC;
940 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
944 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
946 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
948 smu7_reset_dpm_tables(hwmgr);
950 if (hwmgr->pp_table_version == PP_TABLE_V1)
951 smu7_setup_dpm_tables_v1(hwmgr);
952 else if (hwmgr->pp_table_version == PP_TABLE_V0)
953 smu7_setup_dpm_tables_v0(hwmgr);
955 smu7_setup_default_pcie_table(hwmgr);
957 /* save a copy of the default DPM table */
958 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
959 sizeof(struct smu7_dpm_table));
961 /* initialize ODN table */
962 if (hwmgr->od_enabled) {
963 if (data->odn_dpm_table.max_vddc) {
964 smu7_check_dpm_table_updated(hwmgr);
966 smu7_setup_voltage_range_from_vbios(hwmgr);
967 smu7_odn_initial_default_setting(hwmgr);
973 static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
976 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
977 PHM_PlatformCaps_RegulatorHot))
978 return smum_send_msg_to_smc(hwmgr,
979 PPSMC_MSG_EnableVRHotGPIOInterrupt);
984 static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr)
986 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
991 static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
993 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
995 if (data->ulv_supported)
996 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV);
1001 static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
1003 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1005 if (data->ulv_supported)
1006 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV);
1011 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1013 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1014 PHM_PlatformCaps_SclkDeepSleep)) {
1015 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON))
1016 PP_ASSERT_WITH_CODE(false,
1017 "Attempt to enable Master Deep Sleep switch failed!",
1020 if (smum_send_msg_to_smc(hwmgr,
1021 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
1022 PP_ASSERT_WITH_CODE(false,
1023 "Attempt to disable Master Deep Sleep switch failed!",
1031 static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
1033 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1034 PHM_PlatformCaps_SclkDeepSleep)) {
1035 if (smum_send_msg_to_smc(hwmgr,
1036 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
1037 PP_ASSERT_WITH_CODE(false,
1038 "Attempt to disable Master Deep Sleep switch failed!",
1046 static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr)
1048 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1049 uint32_t soft_register_value = 0;
1050 uint32_t handshake_disables_offset = data->soft_regs_start
1051 + smum_get_offsetof(hwmgr,
1052 SMU_SoftRegisters, HandshakeDisables);
1054 soft_register_value = cgs_read_ind_register(hwmgr->device,
1055 CGS_IND_REG__SMC, handshake_disables_offset);
1056 soft_register_value |= SMU7_VCE_SCLK_HANDSHAKE_DISABLE;
1057 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1058 handshake_disables_offset, soft_register_value);
1062 static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
1064 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1065 uint32_t soft_register_value = 0;
1066 uint32_t handshake_disables_offset = data->soft_regs_start
1067 + smum_get_offsetof(hwmgr,
1068 SMU_SoftRegisters, HandshakeDisables);
1070 soft_register_value = cgs_read_ind_register(hwmgr->device,
1071 CGS_IND_REG__SMC, handshake_disables_offset);
1072 soft_register_value |= smum_get_mac_definition(hwmgr,
1073 SMU_UVD_MCLK_HANDSHAKE_DISABLE);
1074 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1075 handshake_disables_offset, soft_register_value);
1079 static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1081 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1083 /* enable SCLK dpm */
1084 if (!data->sclk_dpm_key_disabled) {
1085 if (hwmgr->chip_id == CHIP_VEGAM)
1086 smu7_disable_sclk_vce_handshake(hwmgr);
1088 PP_ASSERT_WITH_CODE(
1089 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable)),
1090 "Failed to enable SCLK DPM during DPM Start Function!",
1094 /* enable MCLK dpm */
1095 if (0 == data->mclk_dpm_key_disabled) {
1096 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
1097 smu7_disable_handshake_uvd(hwmgr);
1099 PP_ASSERT_WITH_CODE(
1100 (0 == smum_send_msg_to_smc(hwmgr,
1101 PPSMC_MSG_MCLKDPM_Enable)),
1102 "Failed to enable MCLK DPM during DPM Start Function!",
1105 if (hwmgr->chip_family != CHIP_VEGAM)
1106 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
1109 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1110 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5);
1111 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5);
1112 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005);
1114 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005);
1115 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005);
1116 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005);
1118 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
1119 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
1120 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
1122 if (hwmgr->chip_id == CHIP_VEGAM) {
1123 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009);
1124 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009);
1126 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
1127 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
1129 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
1136 static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
1138 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1140 /*enable general power management */
1142 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1143 GLOBAL_PWRMGT_EN, 1);
1145 /* enable sclk deep sleep */
1147 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1150 /* prepare for PCIE DPM */
1152 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1153 data->soft_regs_start +
1154 smum_get_offsetof(hwmgr, SMU_SoftRegisters,
1155 VoltageChangeTimeout), 0x1000);
1156 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
1157 SWRST_COMMAND_1, RESETLC, 0x0);
1159 if (hwmgr->chip_family == AMDGPU_FAMILY_CI)
1160 cgs_write_register(hwmgr->device, 0x1488,
1161 (cgs_read_register(hwmgr->device, 0x1488) & ~0x1));
1163 if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
1164 pr_err("Failed to enable Sclk DPM and Mclk DPM!");
1168 /* enable PCIE dpm */
1169 if (0 == data->pcie_dpm_key_disabled) {
1170 PP_ASSERT_WITH_CODE(
1171 (0 == smum_send_msg_to_smc(hwmgr,
1172 PPSMC_MSG_PCIeDPM_Enable)),
1173 "Failed to enable pcie DPM during DPM Start Function!",
1177 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1178 PHM_PlatformCaps_Falcon_QuickTransition)) {
1179 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
1180 PPSMC_MSG_EnableACDCGPIOInterrupt)),
1181 "Failed to enable AC DC GPIO Interrupt!",
1188 static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
1190 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1192 /* disable SCLK dpm */
1193 if (!data->sclk_dpm_key_disabled) {
1194 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1195 "Trying to disable SCLK DPM when DPM is disabled",
1197 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable);
1200 /* disable MCLK dpm */
1201 if (!data->mclk_dpm_key_disabled) {
1202 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1203 "Trying to disable MCLK DPM when DPM is disabled",
1205 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable);
1211 static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
1213 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1215 /* disable general power management */
1216 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1217 GLOBAL_PWRMGT_EN, 0);
1218 /* disable sclk deep sleep */
1219 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1222 /* disable PCIE dpm */
1223 if (!data->pcie_dpm_key_disabled) {
1224 PP_ASSERT_WITH_CODE(
1225 (smum_send_msg_to_smc(hwmgr,
1226 PPSMC_MSG_PCIeDPM_Disable) == 0),
1227 "Failed to disable pcie DPM during DPM Stop Function!",
1231 smu7_disable_sclk_mclk_dpm(hwmgr);
1233 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
1234 "Trying to disable voltage DPM when DPM is disabled",
1237 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable);
1242 static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
1245 enum DPM_EVENT_SRC src;
1249 pr_err("Unknown throttling event sources.");
1255 case (1 << PHM_AutoThrottleSource_Thermal):
1257 src = DPM_EVENT_SRC_DIGITAL;
1259 case (1 << PHM_AutoThrottleSource_External):
1261 src = DPM_EVENT_SRC_EXTERNAL;
1263 case (1 << PHM_AutoThrottleSource_External) |
1264 (1 << PHM_AutoThrottleSource_Thermal):
1266 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
1269 /* Order matters - don't enable thermal protection for the wrong source. */
1271 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
1272 DPM_EVENT_SRC, src);
1273 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1274 THERMAL_PROTECTION_DIS,
1275 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1276 PHM_PlatformCaps_ThermalController));
1278 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
1279 THERMAL_PROTECTION_DIS, 1);
1282 static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1283 PHM_AutoThrottleSource source)
1285 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1287 if (!(data->active_auto_throttle_sources & (1 << source))) {
1288 data->active_auto_throttle_sources |= 1 << source;
1289 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1294 static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1296 return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1299 static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
1300 PHM_AutoThrottleSource source)
1302 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1304 if (data->active_auto_throttle_sources & (1 << source)) {
1305 data->active_auto_throttle_sources &= ~(1 << source);
1306 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
1311 static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
1313 return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
1316 static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
1318 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1319 data->pcie_performance_request = true;
1324 static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1329 if (smu7_voltage_control(hwmgr)) {
1330 tmp_result = smu7_enable_voltage_control(hwmgr);
1331 PP_ASSERT_WITH_CODE(tmp_result == 0,
1332 "Failed to enable voltage control!",
1333 result = tmp_result);
1335 tmp_result = smu7_construct_voltage_tables(hwmgr);
1336 PP_ASSERT_WITH_CODE((0 == tmp_result),
1337 "Failed to construct voltage tables!",
1338 result = tmp_result);
1340 smum_initialize_mc_reg_table(hwmgr);
1342 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1343 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
1344 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1345 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
1347 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1348 PHM_PlatformCaps_ThermalController))
1349 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1350 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
1352 tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr);
1353 PP_ASSERT_WITH_CODE((0 == tmp_result),
1354 "Failed to program static screen threshold parameters!",
1355 result = tmp_result);
1357 tmp_result = smu7_enable_display_gap(hwmgr);
1358 PP_ASSERT_WITH_CODE((0 == tmp_result),
1359 "Failed to enable display gap!", result = tmp_result);
1361 tmp_result = smu7_program_voting_clients(hwmgr);
1362 PP_ASSERT_WITH_CODE((0 == tmp_result),
1363 "Failed to program voting clients!", result = tmp_result);
1365 tmp_result = smum_process_firmware_header(hwmgr);
1366 PP_ASSERT_WITH_CODE((0 == tmp_result),
1367 "Failed to process firmware header!", result = tmp_result);
1369 if (hwmgr->chip_id != CHIP_VEGAM) {
1370 tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr);
1371 PP_ASSERT_WITH_CODE((0 == tmp_result),
1372 "Failed to initialize switch from ArbF0 to F1!",
1373 result = tmp_result);
1376 result = smu7_setup_default_dpm_tables(hwmgr);
1377 PP_ASSERT_WITH_CODE(0 == result,
1378 "Failed to setup default DPM tables!", return result);
1380 tmp_result = smum_init_smc_table(hwmgr);
1381 PP_ASSERT_WITH_CODE((0 == tmp_result),
1382 "Failed to initialize SMC table!", result = tmp_result);
1384 tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr);
1385 PP_ASSERT_WITH_CODE((0 == tmp_result),
1386 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
1388 smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay);
1390 tmp_result = smu7_enable_sclk_control(hwmgr);
1391 PP_ASSERT_WITH_CODE((0 == tmp_result),
1392 "Failed to enable SCLK control!", result = tmp_result);
1394 tmp_result = smu7_enable_smc_voltage_controller(hwmgr);
1395 PP_ASSERT_WITH_CODE((0 == tmp_result),
1396 "Failed to enable voltage control!", result = tmp_result);
1398 tmp_result = smu7_enable_ulv(hwmgr);
1399 PP_ASSERT_WITH_CODE((0 == tmp_result),
1400 "Failed to enable ULV!", result = tmp_result);
1402 tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr);
1403 PP_ASSERT_WITH_CODE((0 == tmp_result),
1404 "Failed to enable deep sleep master switch!", result = tmp_result);
1406 tmp_result = smu7_enable_didt_config(hwmgr);
1407 PP_ASSERT_WITH_CODE((tmp_result == 0),
1408 "Failed to enable deep sleep master switch!", result = tmp_result);
1410 tmp_result = smu7_start_dpm(hwmgr);
1411 PP_ASSERT_WITH_CODE((0 == tmp_result),
1412 "Failed to start DPM!", result = tmp_result);
1414 tmp_result = smu7_enable_smc_cac(hwmgr);
1415 PP_ASSERT_WITH_CODE((0 == tmp_result),
1416 "Failed to enable SMC CAC!", result = tmp_result);
1418 tmp_result = smu7_enable_power_containment(hwmgr);
1419 PP_ASSERT_WITH_CODE((0 == tmp_result),
1420 "Failed to enable power containment!", result = tmp_result);
1422 tmp_result = smu7_power_control_set_level(hwmgr);
1423 PP_ASSERT_WITH_CODE((0 == tmp_result),
1424 "Failed to power control set level!", result = tmp_result);
1426 tmp_result = smu7_enable_thermal_auto_throttle(hwmgr);
1427 PP_ASSERT_WITH_CODE((0 == tmp_result),
1428 "Failed to enable thermal auto throttle!", result = tmp_result);
1430 tmp_result = smu7_pcie_performance_request(hwmgr);
1431 PP_ASSERT_WITH_CODE((0 == tmp_result),
1432 "pcie performance request failed!", result = tmp_result);
1437 static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
1439 if (!hwmgr->avfs_supported)
1443 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1444 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1445 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1446 hwmgr, PPSMC_MSG_EnableAvfs),
1447 "Failed to enable AVFS!",
1450 } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
1451 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
1452 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
1453 hwmgr, PPSMC_MSG_DisableAvfs),
1454 "Failed to disable AVFS!",
1461 static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
1463 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1465 if (!hwmgr->avfs_supported)
1468 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
1469 smu7_avfs_control(hwmgr, false);
1470 } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
1471 smu7_avfs_control(hwmgr, false);
1472 smu7_avfs_control(hwmgr, true);
1474 smu7_avfs_control(hwmgr, true);
1480 int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
1482 int tmp_result, result = 0;
1484 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1485 PHM_PlatformCaps_ThermalController))
1486 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1487 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
1489 tmp_result = smu7_disable_power_containment(hwmgr);
1490 PP_ASSERT_WITH_CODE((tmp_result == 0),
1491 "Failed to disable power containment!", result = tmp_result);
1493 tmp_result = smu7_disable_smc_cac(hwmgr);
1494 PP_ASSERT_WITH_CODE((tmp_result == 0),
1495 "Failed to disable SMC CAC!", result = tmp_result);
1497 tmp_result = smu7_disable_didt_config(hwmgr);
1498 PP_ASSERT_WITH_CODE((tmp_result == 0),
1499 "Failed to disable DIDT!", result = tmp_result);
1501 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1502 CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
1503 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1504 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
1506 tmp_result = smu7_disable_thermal_auto_throttle(hwmgr);
1507 PP_ASSERT_WITH_CODE((tmp_result == 0),
1508 "Failed to disable thermal auto throttle!", result = tmp_result);
1510 tmp_result = smu7_avfs_control(hwmgr, false);
1511 PP_ASSERT_WITH_CODE((tmp_result == 0),
1512 "Failed to disable AVFS!", result = tmp_result);
1514 tmp_result = smu7_stop_dpm(hwmgr);
1515 PP_ASSERT_WITH_CODE((tmp_result == 0),
1516 "Failed to stop DPM!", result = tmp_result);
1518 tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr);
1519 PP_ASSERT_WITH_CODE((tmp_result == 0),
1520 "Failed to disable deep sleep master switch!", result = tmp_result);
1522 tmp_result = smu7_disable_ulv(hwmgr);
1523 PP_ASSERT_WITH_CODE((tmp_result == 0),
1524 "Failed to disable ULV!", result = tmp_result);
1526 tmp_result = smu7_clear_voting_clients(hwmgr);
1527 PP_ASSERT_WITH_CODE((tmp_result == 0),
1528 "Failed to clear voting clients!", result = tmp_result);
1530 tmp_result = smu7_reset_to_default(hwmgr);
1531 PP_ASSERT_WITH_CODE((tmp_result == 0),
1532 "Failed to reset to default!", result = tmp_result);
1534 tmp_result = smum_stop_smc(hwmgr);
1535 PP_ASSERT_WITH_CODE((tmp_result == 0),
1536 "Failed to stop smc!", result = tmp_result);
1538 tmp_result = smu7_force_switch_to_arbf0(hwmgr);
1539 PP_ASSERT_WITH_CODE((tmp_result == 0),
1540 "Failed to force to switch arbf0!", result = tmp_result);
1545 int smu7_reset_asic_tasks(struct pp_hwmgr *hwmgr)
1551 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
1553 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1554 struct phm_ppt_v1_information *table_info =
1555 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1556 struct amdgpu_device *adev = hwmgr->adev;
1558 data->dll_default_on = false;
1559 data->mclk_dpm0_activity_target = 0xa;
1560 data->vddc_vddgfx_delta = 300;
1561 data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT;
1562 data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT;
1563 data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0;
1564 data->voting_rights_clients[1]= SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
1565 data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2;
1566 data->voting_rights_clients[3]= SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
1567 data->voting_rights_clients[4]= SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
1568 data->voting_rights_clients[5]= SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
1569 data->voting_rights_clients[6]= SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
1570 data->voting_rights_clients[7]= SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
1572 data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
1573 data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
1574 data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
1575 /* need to set voltage control types before EVV patching */
1576 data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
1577 data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
1578 data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE;
1579 data->enable_tdc_limit_feature = true;
1580 data->enable_pkg_pwr_tracking_feature = true;
1581 data->force_pcie_gen = PP_PCIEGenInvalid;
1582 data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
1583 data->current_profile_setting.bupdate_sclk = 1;
1584 data->current_profile_setting.sclk_up_hyst = 0;
1585 data->current_profile_setting.sclk_down_hyst = 100;
1586 data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT;
1587 data->current_profile_setting.bupdate_mclk = 1;
1588 data->current_profile_setting.mclk_up_hyst = 0;
1589 data->current_profile_setting.mclk_down_hyst = 100;
1590 data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT;
1591 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
1592 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1593 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1595 if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {
1598 atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
1600 tmp3 = (tmp3 >> 5) & 0x3;
1601 data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3;
1602 } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
1603 data->vddc_phase_shed_control = 1;
1605 data->vddc_phase_shed_control = 0;
1608 if (hwmgr->chip_id == CHIP_HAWAII) {
1609 data->thermal_temp_setting.temperature_low = 94500;
1610 data->thermal_temp_setting.temperature_high = 95000;
1611 data->thermal_temp_setting.temperature_shutdown = 104000;
1613 data->thermal_temp_setting.temperature_low = 99500;
1614 data->thermal_temp_setting.temperature_high = 100000;
1615 data->thermal_temp_setting.temperature_shutdown = 104000;
1618 data->fast_watermark_threshold = 100;
1619 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1620 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
1621 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1622 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1623 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
1624 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1626 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1627 PHM_PlatformCaps_ControlVDDGFX)) {
1628 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1629 VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
1630 data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1634 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1635 PHM_PlatformCaps_EnableMVDDControl)) {
1636 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1637 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
1638 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1639 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1640 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
1641 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1644 if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control)
1645 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1646 PHM_PlatformCaps_ControlVDDGFX);
1648 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1649 PHM_PlatformCaps_ControlVDDCI)) {
1650 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1651 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
1652 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
1653 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
1654 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
1655 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
1658 if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE)
1659 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1660 PHM_PlatformCaps_EnableMVDDControl);
1662 if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE)
1663 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1664 PHM_PlatformCaps_ControlVDDCI);
1666 if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK)
1667 && (table_info->cac_dtp_table->usClockStretchAmount != 0))
1668 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1669 PHM_PlatformCaps_ClockStretcher);
1671 data->pcie_gen_performance.max = PP_PCIEGen1;
1672 data->pcie_gen_performance.min = PP_PCIEGen3;
1673 data->pcie_gen_power_saving.max = PP_PCIEGen1;
1674 data->pcie_gen_power_saving.min = PP_PCIEGen3;
1675 data->pcie_lane_performance.max = 0;
1676 data->pcie_lane_performance.min = 16;
1677 data->pcie_lane_power_saving.max = 0;
1678 data->pcie_lane_power_saving.min = 16;
1681 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1682 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1683 PHM_PlatformCaps_UVDPowerGating);
1684 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
1685 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1686 PHM_PlatformCaps_VCEPowerGating);
1690 * Get Leakage VDDC based on leakage ID.
1692 * @param hwmgr the address of the powerplay hardware manager.
1695 static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
1697 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1700 uint16_t vddgfx = 0;
1703 struct phm_ppt_v1_information *table_info =
1704 (struct phm_ppt_v1_information *)hwmgr->pptable;
1705 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL;
1708 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
1709 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1711 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1712 if ((hwmgr->pp_table_version == PP_TABLE_V1)
1713 && !phm_get_sclk_for_voltage_evv(hwmgr,
1714 table_info->vddgfx_lookup_table, vv_id, &sclk)) {
1715 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1716 PHM_PlatformCaps_ClockStretcher)) {
1717 sclk_table = table_info->vdd_dep_on_sclk;
1719 for (j = 1; j < sclk_table->count; j++) {
1720 if (sclk_table->entries[j].clk == sclk &&
1721 sclk_table->entries[j].cks_enable == 0) {
1727 if (0 == atomctrl_get_voltage_evv_on_sclk
1728 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
1730 /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
1731 PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL);
1733 /* the voltage should not be zero nor equal to leakage ID */
1734 if (vddgfx != 0 && vddgfx != vv_id) {
1735 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
1736 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id;
1737 data->vddcgfx_leakage.count++;
1740 pr_info("Error retrieving EVV voltage value!\n");
1744 if ((hwmgr->pp_table_version == PP_TABLE_V0)
1745 || !phm_get_sclk_for_voltage_evv(hwmgr,
1746 table_info->vddc_lookup_table, vv_id, &sclk)) {
1747 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1748 PHM_PlatformCaps_ClockStretcher)) {
1749 if (table_info == NULL)
1751 sclk_table = table_info->vdd_dep_on_sclk;
1753 for (j = 1; j < sclk_table->count; j++) {
1754 if (sclk_table->entries[j].clk == sclk &&
1755 sclk_table->entries[j].cks_enable == 0) {
1762 if (phm_get_voltage_evv_on_sclk(hwmgr,
1764 sclk, vv_id, &vddc) == 0) {
1765 if (vddc >= 2000 || vddc == 0)
1768 pr_debug("failed to retrieving EVV voltage!\n");
1772 /* the voltage should not be zero nor equal to leakage ID */
1773 if (vddc != 0 && vddc != vv_id) {
1774 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc);
1775 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
1776 data->vddc_leakage.count++;
1786 * Change virtual leakage voltage to actual value.
1788 * @param hwmgr the address of the powerplay hardware manager.
1789 * @param pointer to changing voltage
1790 * @param pointer to leakage table
1792 static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr,
1793 uint16_t *voltage, struct smu7_leakage_voltage *leakage_table)
1797 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
1798 for (index = 0; index < leakage_table->count; index++) {
1799 /* if this voltage matches a leakage voltage ID */
1800 /* patch with actual leakage voltage */
1801 if (leakage_table->leakage_id[index] == *voltage) {
1802 *voltage = leakage_table->actual_voltage[index];
1807 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
1808 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
1812 * Patch voltage lookup table by EVV leakages.
1814 * @param hwmgr the address of the powerplay hardware manager.
1815 * @param pointer to voltage lookup table
1816 * @param pointer to leakage table
1819 static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
1820 phm_ppt_v1_voltage_lookup_table *lookup_table,
1821 struct smu7_leakage_voltage *leakage_table)
1825 for (i = 0; i < lookup_table->count; i++)
1826 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
1827 &lookup_table->entries[i].us_vdd, leakage_table);
1832 static int smu7_patch_clock_voltage_limits_with_vddc_leakage(
1833 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table,
1836 struct phm_ppt_v1_information *table_info =
1837 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1838 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
1839 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
1840 table_info->max_clock_voltage_on_dc.vddc;
1844 static int smu7_patch_voltage_dependency_tables_with_lookup_table(
1845 struct pp_hwmgr *hwmgr)
1849 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1850 struct phm_ppt_v1_information *table_info =
1851 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1853 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1854 table_info->vdd_dep_on_sclk;
1855 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
1856 table_info->vdd_dep_on_mclk;
1857 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1858 table_info->mm_dep_table;
1860 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1861 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1862 voltage_id = sclk_table->entries[entry_id].vddInd;
1863 sclk_table->entries[entry_id].vddgfx =
1864 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd;
1867 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1868 voltage_id = sclk_table->entries[entry_id].vddInd;
1869 sclk_table->entries[entry_id].vddc =
1870 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1874 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1875 voltage_id = mclk_table->entries[entry_id].vddInd;
1876 mclk_table->entries[entry_id].vddc =
1877 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1880 for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
1881 voltage_id = mm_table->entries[entry_id].vddcInd;
1882 mm_table->entries[entry_id].vddc =
1883 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
1890 static int phm_add_voltage(struct pp_hwmgr *hwmgr,
1891 phm_ppt_v1_voltage_lookup_table *look_up_table,
1892 phm_ppt_v1_voltage_lookup_record *record)
1896 PP_ASSERT_WITH_CODE((NULL != look_up_table),
1897 "Lookup Table empty.", return -EINVAL);
1898 PP_ASSERT_WITH_CODE((0 != look_up_table->count),
1899 "Lookup Table empty.", return -EINVAL);
1901 i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
1902 PP_ASSERT_WITH_CODE((i >= look_up_table->count),
1903 "Lookup Table is full.", return -EINVAL);
1905 /* This is to avoid entering duplicate calculated records. */
1906 for (i = 0; i < look_up_table->count; i++) {
1907 if (look_up_table->entries[i].us_vdd == record->us_vdd) {
1908 if (look_up_table->entries[i].us_calculated == 1)
1914 look_up_table->entries[i].us_calculated = 1;
1915 look_up_table->entries[i].us_vdd = record->us_vdd;
1916 look_up_table->entries[i].us_cac_low = record->us_cac_low;
1917 look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
1918 look_up_table->entries[i].us_cac_high = record->us_cac_high;
1919 /* Only increment the count when we're appending, not replacing duplicate entry. */
1920 if (i == look_up_table->count)
1921 look_up_table->count++;
1927 static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
1930 struct phm_ppt_v1_voltage_lookup_record v_record;
1931 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1932 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1934 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
1935 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk;
1937 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1938 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) {
1939 if (sclk_table->entries[entry_id].vdd_offset & (1 << 15))
1940 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1941 sclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1943 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx +
1944 sclk_table->entries[entry_id].vdd_offset;
1946 sclk_table->entries[entry_id].vddc =
1947 v_record.us_cac_low = v_record.us_cac_mid =
1948 v_record.us_cac_high = v_record.us_vdd;
1950 phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
1953 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
1954 if (mclk_table->entries[entry_id].vdd_offset & (1 << 15))
1955 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1956 mclk_table->entries[entry_id].vdd_offset - 0xFFFF;
1958 v_record.us_vdd = mclk_table->entries[entry_id].vddc +
1959 mclk_table->entries[entry_id].vdd_offset;
1961 mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low =
1962 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
1963 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
1969 static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
1972 struct phm_ppt_v1_voltage_lookup_record v_record;
1973 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1974 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
1975 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
1977 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
1978 for (entry_id = 0; entry_id < mm_table->count; entry_id++) {
1979 if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15))
1980 v_record.us_vdd = mm_table->entries[entry_id].vddc +
1981 mm_table->entries[entry_id].vddgfx_offset - 0xFFFF;
1983 v_record.us_vdd = mm_table->entries[entry_id].vddc +
1984 mm_table->entries[entry_id].vddgfx_offset;
1986 /* Add the calculated VDDGFX to the VDDGFX lookup table */
1987 mm_table->entries[entry_id].vddgfx = v_record.us_cac_low =
1988 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd;
1989 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
1995 static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
1996 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
1998 uint32_t table_size, i, j;
1999 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
2000 table_size = lookup_table->count;
2002 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2003 "Lookup table is empty", return -EINVAL);
2005 /* Sorting voltages */
2006 for (i = 0; i < table_size - 1; i++) {
2007 for (j = i + 1; j > 0; j--) {
2008 if (lookup_table->entries[j].us_vdd <
2009 lookup_table->entries[j - 1].us_vdd) {
2010 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2011 lookup_table->entries[j - 1] = lookup_table->entries[j];
2012 lookup_table->entries[j] = tmp_voltage_lookup_record;
2020 static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2024 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2025 struct phm_ppt_v1_information *table_info =
2026 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2028 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
2029 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2030 table_info->vddgfx_lookup_table, &(data->vddcgfx_leakage));
2031 if (tmp_result != 0)
2032 result = tmp_result;
2034 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
2035 &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage));
2038 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
2039 table_info->vddc_lookup_table, &(data->vddc_leakage));
2041 result = tmp_result;
2043 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2044 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2046 result = tmp_result;
2049 tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2051 result = tmp_result;
2053 tmp_result = smu7_calc_voltage_dependency_tables(hwmgr);
2055 result = tmp_result;
2057 tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr);
2059 result = tmp_result;
2061 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table);
2063 result = tmp_result;
2065 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2067 result = tmp_result;
2072 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
2074 struct phm_ppt_v1_information *table_info =
2075 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2077 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2078 table_info->vdd_dep_on_sclk;
2079 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2080 table_info->vdd_dep_on_mclk;
2082 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2083 "VDD dependency on SCLK table is missing.",
2085 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2086 "VDD dependency on SCLK table has to have is missing.",
2089 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2090 "VDD dependency on MCLK table is missing",
2092 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2093 "VDD dependency on MCLK table has to have is missing.",
2096 table_info->max_clock_voltage_on_ac.sclk =
2097 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2098 table_info->max_clock_voltage_on_ac.mclk =
2099 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2100 table_info->max_clock_voltage_on_ac.vddc =
2101 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2102 table_info->max_clock_voltage_on_ac.vddci =
2103 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2105 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2106 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2107 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2108 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci;
2113 static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
2115 struct phm_ppt_v1_information *table_info =
2116 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2117 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
2118 struct phm_ppt_v1_voltage_lookup_table *lookup_table;
2120 uint32_t hw_revision, sub_vendor_id, sub_sys_id;
2121 struct amdgpu_device *adev = hwmgr->adev;
2123 if (table_info != NULL) {
2124 dep_mclk_table = table_info->vdd_dep_on_mclk;
2125 lookup_table = table_info->vddc_lookup_table;
2129 hw_revision = adev->pdev->revision;
2130 sub_sys_id = adev->pdev->subsystem_device;
2131 sub_vendor_id = adev->pdev->subsystem_vendor;
2133 if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 &&
2134 ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
2135 (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) ||
2136 (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) {
2137 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
2140 for (i = 0; i < lookup_table->count; i++) {
2141 if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
2142 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
2150 static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr)
2152 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2154 struct phm_ppt_v1_information *table_info =
2155 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2158 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
2159 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
2160 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
2162 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
2165 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
2168 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
2171 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
2174 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
2179 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
2182 if (table_info == NULL)
2185 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
2186 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
2187 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
2188 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2190 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
2191 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2193 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
2195 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
2197 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
2198 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
2200 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
2202 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
2203 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0;
2205 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2206 table_info->cac_dtp_table->usOperatingTempStep = 1;
2207 table_info->cac_dtp_table->usOperatingTempHyst = 1;
2209 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
2210 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
2212 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
2213 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
2215 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
2216 table_info->cac_dtp_table->usOperatingTempMinLimit;
2218 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
2219 table_info->cac_dtp_table->usOperatingTempMaxLimit;
2221 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
2222 table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
2224 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
2225 table_info->cac_dtp_table->usOperatingTempStep;
2227 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
2228 table_info->cac_dtp_table->usTargetOperatingTemp;
2229 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK)
2230 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2231 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2238 * Change virtual leakage voltage to actual value.
2240 * @param hwmgr the address of the powerplay hardware manager.
2241 * @param pointer to changing voltage
2242 * @param pointer to leakage table
2244 static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2245 uint32_t *voltage, struct smu7_leakage_voltage *leakage_table)
2249 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2250 for (index = 0; index < leakage_table->count; index++) {
2251 /* if this voltage matches a leakage voltage ID */
2252 /* patch with actual leakage voltage */
2253 if (leakage_table->leakage_id[index] == *voltage) {
2254 *voltage = leakage_table->actual_voltage[index];
2259 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2260 pr_err("Voltage value looks like a Leakage ID but it's not patched \n");
2264 static int smu7_patch_vddc(struct pp_hwmgr *hwmgr,
2265 struct phm_clock_voltage_dependency_table *tab)
2268 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2271 for (i = 0; i < tab->count; i++)
2272 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2273 &data->vddc_leakage);
2278 static int smu7_patch_vddci(struct pp_hwmgr *hwmgr,
2279 struct phm_clock_voltage_dependency_table *tab)
2282 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2285 for (i = 0; i < tab->count; i++)
2286 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2287 &data->vddci_leakage);
2292 static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr,
2293 struct phm_vce_clock_voltage_dependency_table *tab)
2296 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2299 for (i = 0; i < tab->count; i++)
2300 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2301 &data->vddc_leakage);
2307 static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr,
2308 struct phm_uvd_clock_voltage_dependency_table *tab)
2311 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2314 for (i = 0; i < tab->count; i++)
2315 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2316 &data->vddc_leakage);
2321 static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr,
2322 struct phm_phase_shedding_limits_table *tab)
2325 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2328 for (i = 0; i < tab->count; i++)
2329 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage,
2330 &data->vddc_leakage);
2335 static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr,
2336 struct phm_samu_clock_voltage_dependency_table *tab)
2339 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2342 for (i = 0; i < tab->count; i++)
2343 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2344 &data->vddc_leakage);
2349 static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr,
2350 struct phm_acp_clock_voltage_dependency_table *tab)
2353 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2356 for (i = 0; i < tab->count; i++)
2357 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
2358 &data->vddc_leakage);
2363 static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr,
2364 struct phm_clock_and_voltage_limits *tab)
2366 uint32_t vddc, vddci;
2367 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2371 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc,
2372 &data->vddc_leakage);
2375 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci,
2376 &data->vddci_leakage);
2383 static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab)
2387 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2390 for (i = 0; i < tab->count; i++) {
2391 vddc = (uint32_t)(tab->entries[i].Vddc);
2392 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage);
2393 tab->entries[i].Vddc = (uint16_t)vddc;
2400 static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr)
2404 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk);
2408 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk);
2412 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2416 tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk);
2420 tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table);
2424 tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
2428 tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table);
2432 tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table);
2436 tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table);
2440 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac);
2444 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc);
2448 tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table);
2456 static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
2458 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2460 struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
2461 struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
2462 struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
2464 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL,
2465 "VDDC dependency on SCLK table is missing. This table is mandatory",
2467 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1,
2468 "VDDC dependency on SCLK table has to have is missing. This table is mandatory",
2471 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL,
2472 "VDDC dependency on MCLK table is missing. This table is mandatory",
2474 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1,
2475 "VDD dependency on MCLK table has to have is missing. This table is mandatory",
2478 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v;
2479 data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2481 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
2482 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
2483 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
2484 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk;
2485 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
2486 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
2488 if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) {
2489 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v;
2490 data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
2493 if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1)
2494 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
2499 static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2501 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
2502 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
2503 kfree(hwmgr->backend);
2504 hwmgr->backend = NULL;
2509 static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr)
2511 uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id;
2512 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2515 if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) {
2516 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
2517 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2518 if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci,
2520 efuse_voltage_id) == 0) {
2521 if (vddc != 0 && vddc != virtual_voltage_id) {
2522 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
2523 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
2524 data->vddc_leakage.count++;
2526 if (vddci != 0 && vddci != virtual_voltage_id) {
2527 data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci;
2528 data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id;
2529 data->vddci_leakage.count++;
2537 static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2539 struct smu7_hwmgr *data;
2542 data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL);
2546 hwmgr->backend = data;
2547 smu7_patch_voltage_workaround(hwmgr);
2548 smu7_init_dpm_defaults(hwmgr);
2550 /* Get leakage voltage based on leakage ID. */
2551 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2552 PHM_PlatformCaps_EVV)) {
2553 result = smu7_get_evv_voltages(hwmgr);
2555 pr_info("Get EVV Voltage Failed. Abort Driver loading!\n");
2559 smu7_get_elb_voltages(hwmgr);
2562 if (hwmgr->pp_table_version == PP_TABLE_V1) {
2563 smu7_complete_dependency_tables(hwmgr);
2564 smu7_set_private_data_based_on_pptable_v1(hwmgr);
2565 } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
2566 smu7_patch_dependency_tables_with_leakage(hwmgr);
2567 smu7_set_private_data_based_on_pptable_v0(hwmgr);
2570 /* Initalize Dynamic State Adjustment Rule Settings */
2571 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
2574 struct amdgpu_device *adev = hwmgr->adev;
2576 data->is_tlu_enabled = false;
2578 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
2579 SMU7_MAX_HARDWARE_POWERLEVELS;
2580 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
2581 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
2583 data->pcie_gen_cap = adev->pm.pcie_gen_mask;
2584 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
2585 data->pcie_spc_cap = 20;
2586 data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
2588 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
2589 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
2590 hwmgr->platform_descriptor.clockStep.engineClock = 500;
2591 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
2592 smu7_thermal_parameter_init(hwmgr);
2594 /* Ignore return value in here, we are cleaning up a mess. */
2595 smu7_hwmgr_backend_fini(hwmgr);
2601 static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
2603 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2604 uint32_t level, tmp;
2606 if (!data->pcie_dpm_key_disabled) {
2607 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2609 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
2614 smum_send_msg_to_smc_with_parameter(hwmgr,
2615 PPSMC_MSG_PCIeDPM_ForceLevel, level);
2619 if (!data->sclk_dpm_key_disabled) {
2620 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2622 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
2627 smum_send_msg_to_smc_with_parameter(hwmgr,
2628 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2633 if (!data->mclk_dpm_key_disabled) {
2634 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2636 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
2641 smum_send_msg_to_smc_with_parameter(hwmgr,
2642 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2650 static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
2652 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2654 if (hwmgr->pp_table_version == PP_TABLE_V1)
2655 phm_apply_dal_min_voltage_request(hwmgr);
2656 /* TO DO for v0 iceland and Ci*/
2658 if (!data->sclk_dpm_key_disabled) {
2659 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
2660 smum_send_msg_to_smc_with_parameter(hwmgr,
2661 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2662 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2665 if (!data->mclk_dpm_key_disabled) {
2666 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
2667 smum_send_msg_to_smc_with_parameter(hwmgr,
2668 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2669 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2675 static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2677 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2679 if (!smum_is_dpm_running(hwmgr))
2682 if (!data->pcie_dpm_key_disabled) {
2683 smum_send_msg_to_smc(hwmgr,
2684 PPSMC_MSG_PCIeDPM_UnForceLevel);
2687 return smu7_upload_dpm_level_enable_mask(hwmgr);
2690 static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2692 struct smu7_hwmgr *data =
2693 (struct smu7_hwmgr *)(hwmgr->backend);
2696 if (!data->sclk_dpm_key_disabled)
2697 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
2698 level = phm_get_lowest_enabled_level(hwmgr,
2699 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
2700 smum_send_msg_to_smc_with_parameter(hwmgr,
2701 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2706 if (!data->mclk_dpm_key_disabled) {
2707 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
2708 level = phm_get_lowest_enabled_level(hwmgr,
2709 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
2710 smum_send_msg_to_smc_with_parameter(hwmgr,
2711 PPSMC_MSG_MCLKDPM_SetEnabledMask,
2716 if (!data->pcie_dpm_key_disabled) {
2717 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
2718 level = phm_get_lowest_enabled_level(hwmgr,
2719 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
2720 smum_send_msg_to_smc_with_parameter(hwmgr,
2721 PPSMC_MSG_PCIeDPM_ForceLevel,
2729 static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2730 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
2732 uint32_t percentage;
2733 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2734 struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
2739 if (golden_dpm_table->mclk_table.count < 1)
2742 percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value /
2743 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
2745 if (golden_dpm_table->mclk_table.count == 1) {
2747 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
2748 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2750 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value;
2751 *mclk_mask = golden_dpm_table->mclk_table.count - 2;
2754 tmp_sclk = tmp_mclk * percentage / 100;
2756 if (hwmgr->pp_table_version == PP_TABLE_V0) {
2757 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
2758 count >= 0; count--) {
2759 if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {
2760 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk;
2765 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2767 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk;
2770 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2771 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
2772 } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
2773 struct phm_ppt_v1_information *table_info =
2774 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2776 for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
2777 if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) {
2778 tmp_sclk = table_info->vdd_dep_on_sclk->entries[count].clk;
2783 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2785 tmp_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
2788 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2789 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
2792 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
2794 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2795 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
2797 *pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
2798 hwmgr->pstate_sclk = tmp_sclk;
2799 hwmgr->pstate_mclk = tmp_mclk;
2804 static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
2805 enum amd_dpm_forced_level level)
2808 uint32_t sclk_mask = 0;
2809 uint32_t mclk_mask = 0;
2810 uint32_t pcie_mask = 0;
2812 if (hwmgr->pstate_sclk == 0)
2813 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
2816 case AMD_DPM_FORCED_LEVEL_HIGH:
2817 ret = smu7_force_dpm_highest(hwmgr);
2819 case AMD_DPM_FORCED_LEVEL_LOW:
2820 ret = smu7_force_dpm_lowest(hwmgr);
2822 case AMD_DPM_FORCED_LEVEL_AUTO:
2823 ret = smu7_unforce_dpm_levels(hwmgr);
2825 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2826 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2827 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2828 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2829 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
2832 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
2833 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
2834 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask);
2836 case AMD_DPM_FORCED_LEVEL_MANUAL:
2837 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2843 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2844 smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2845 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
2846 smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
2851 static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr)
2853 return sizeof(struct smu7_power_state);
2856 static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
2857 uint32_t vblank_time_us)
2859 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2860 uint32_t switch_limit_us;
2862 switch (hwmgr->chip_id) {
2863 case CHIP_POLARIS10:
2864 case CHIP_POLARIS11:
2865 case CHIP_POLARIS12:
2866 switch_limit_us = data->is_memory_gddr5 ? 190 : 150;
2869 switch_limit_us = 30;
2872 switch_limit_us = data->is_memory_gddr5 ? 450 : 150;
2876 if (vblank_time_us < switch_limit_us)
2882 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
2883 struct pp_power_state *request_ps,
2884 const struct pp_power_state *current_ps)
2886 struct amdgpu_device *adev = hwmgr->adev;
2887 struct smu7_power_state *smu7_ps =
2888 cast_phw_smu7_power_state(&request_ps->hardware);
2891 struct PP_Clocks minimum_clocks = {0};
2892 bool disable_mclk_switching;
2893 bool disable_mclk_switching_for_frame_lock;
2894 const struct phm_clock_and_voltage_limits *max_limits;
2896 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2897 struct phm_ppt_v1_information *table_info =
2898 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2900 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
2902 data->battery_state = (PP_StateUILabel_Battery ==
2903 request_ps->classification.ui_label);
2905 PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2,
2906 "VI should always have 2 performance levels",
2909 max_limits = adev->pm.ac_power ?
2910 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
2911 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
2913 /* Cap clock DPM tables at DC MAX if it is in DC. */
2914 if (!adev->pm.ac_power) {
2915 for (i = 0; i < smu7_ps->performance_level_count; i++) {
2916 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk)
2917 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk;
2918 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk)
2919 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk;
2923 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
2924 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2926 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2927 PHM_PlatformCaps_StablePState)) {
2928 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
2929 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
2931 for (count = table_info->vdd_dep_on_sclk->count - 1;
2932 count >= 0; count--) {
2933 if (stable_pstate_sclk >=
2934 table_info->vdd_dep_on_sclk->entries[count].clk) {
2935 stable_pstate_sclk =
2936 table_info->vdd_dep_on_sclk->entries[count].clk;
2942 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
2944 stable_pstate_mclk = max_limits->mclk;
2946 minimum_clocks.engineClock = stable_pstate_sclk;
2947 minimum_clocks.memoryClock = stable_pstate_mclk;
2950 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
2951 hwmgr->platform_descriptor.platformCaps,
2952 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
2955 if (hwmgr->display_config->num_display == 0)
2956 disable_mclk_switching = false;
2958 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) ||
2959 disable_mclk_switching_for_frame_lock ||
2960 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time));
2962 sclk = smu7_ps->performance_levels[0].engine_clock;
2963 mclk = smu7_ps->performance_levels[0].memory_clock;
2965 if (disable_mclk_switching)
2966 mclk = smu7_ps->performance_levels
2967 [smu7_ps->performance_level_count - 1].memory_clock;
2969 if (sclk < minimum_clocks.engineClock)
2970 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
2971 max_limits->sclk : minimum_clocks.engineClock;
2973 if (mclk < minimum_clocks.memoryClock)
2974 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
2975 max_limits->mclk : minimum_clocks.memoryClock;
2977 smu7_ps->performance_levels[0].engine_clock = sclk;
2978 smu7_ps->performance_levels[0].memory_clock = mclk;
2980 smu7_ps->performance_levels[1].engine_clock =
2981 (smu7_ps->performance_levels[1].engine_clock >=
2982 smu7_ps->performance_levels[0].engine_clock) ?
2983 smu7_ps->performance_levels[1].engine_clock :
2984 smu7_ps->performance_levels[0].engine_clock;
2986 if (disable_mclk_switching) {
2987 if (mclk < smu7_ps->performance_levels[1].memory_clock)
2988 mclk = smu7_ps->performance_levels[1].memory_clock;
2990 smu7_ps->performance_levels[0].memory_clock = mclk;
2991 smu7_ps->performance_levels[1].memory_clock = mclk;
2993 if (smu7_ps->performance_levels[1].memory_clock <
2994 smu7_ps->performance_levels[0].memory_clock)
2995 smu7_ps->performance_levels[1].memory_clock =
2996 smu7_ps->performance_levels[0].memory_clock;
2999 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3000 PHM_PlatformCaps_StablePState)) {
3001 for (i = 0; i < smu7_ps->performance_level_count; i++) {
3002 smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3003 smu7_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3004 smu7_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3005 smu7_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3012 static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3014 struct pp_power_state *ps;
3015 struct smu7_power_state *smu7_ps;
3020 ps = hwmgr->request_ps;
3025 smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
3028 return smu7_ps->performance_levels[0].memory_clock;
3030 return smu7_ps->performance_levels
3031 [smu7_ps->performance_level_count-1].memory_clock;
3034 static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3036 struct pp_power_state *ps;
3037 struct smu7_power_state *smu7_ps;
3042 ps = hwmgr->request_ps;
3047 smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
3050 return smu7_ps->performance_levels[0].engine_clock;
3052 return smu7_ps->performance_levels
3053 [smu7_ps->performance_level_count-1].engine_clock;
3056 static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3057 struct pp_hw_power_state *hw_ps)
3059 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3060 struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps;
3061 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3064 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3066 /* First retrieve the Boot clocks and VDDC from the firmware info table.
3067 * We assume here that fw_info is unchanged if this call fails.
3069 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(hwmgr->adev, index,
3070 &size, &frev, &crev);
3072 /* During a test, there is no firmware info table. */
3075 /* Patch the state. */
3076 data->vbios_boot_state.sclk_bootup_value =
3077 le32_to_cpu(fw_info->ulDefaultEngineClock);
3078 data->vbios_boot_state.mclk_bootup_value =
3079 le32_to_cpu(fw_info->ulDefaultMemoryClock);
3080 data->vbios_boot_state.mvdd_bootup_value =
3081 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3082 data->vbios_boot_state.vddc_bootup_value =
3083 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3084 data->vbios_boot_state.vddci_bootup_value =
3085 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3086 data->vbios_boot_state.pcie_gen_bootup_value =
3087 smu7_get_current_pcie_speed(hwmgr);
3089 data->vbios_boot_state.pcie_lane_bootup_value =
3090 (uint16_t)smu7_get_current_pcie_lane_number(hwmgr);
3092 /* set boot power state */
3093 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3094 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3095 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3096 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3101 static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
3104 unsigned long ret = 0;
3106 if (hwmgr->pp_table_version == PP_TABLE_V0) {
3107 result = pp_tables_get_num_of_entries(hwmgr, &ret);
3108 return result ? 0 : ret;
3109 } else if (hwmgr->pp_table_version == PP_TABLE_V1) {
3110 result = get_number_of_powerplay_table_entries_v1_0(hwmgr);
3116 static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
3117 void *state, struct pp_power_state *power_state,
3118 void *pp_table, uint32_t classification_flag)
3120 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3121 struct smu7_power_state *smu7_power_state =
3122 (struct smu7_power_state *)(&(power_state->hardware));
3123 struct smu7_performance_level *performance_level;
3124 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3125 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3126 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3127 PPTable_Generic_SubTable_Header *sclk_dep_table =
3128 (PPTable_Generic_SubTable_Header *)
3129 (((unsigned long)powerplay_table) +
3130 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3132 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3133 (ATOM_Tonga_MCLK_Dependency_Table *)
3134 (((unsigned long)powerplay_table) +
3135 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3137 /* The following fields are not initialized here: id orderedList allStatesList */
3138 power_state->classification.ui_label =
3139 (le16_to_cpu(state_entry->usClassification) &
3140 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3141 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3142 power_state->classification.flags = classification_flag;
3143 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3145 power_state->classification.temporary_state = false;
3146 power_state->classification.to_be_deleted = false;
3148 power_state->validation.disallowOnDC =
3149 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3150 ATOM_Tonga_DISALLOW_ON_DC));
3152 power_state->pcie.lanes = 0;
3154 power_state->display.disableFrameModulation = false;
3155 power_state->display.limitRefreshrate = false;
3156 power_state->display.enableVariBright =
3157 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3158 ATOM_Tonga_ENABLE_VARIBRIGHT));
3160 power_state->validation.supportedPowerLevels = 0;
3161 power_state->uvd_clocks.VCLK = 0;
3162 power_state->uvd_clocks.DCLK = 0;
3163 power_state->temperatures.min = 0;
3164 power_state->temperatures.max = 0;
3166 performance_level = &(smu7_power_state->performance_levels
3167 [smu7_power_state->performance_level_count++]);
3169 PP_ASSERT_WITH_CODE(
3170 (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3171 "Performance levels exceeds SMC limit!",
3174 PP_ASSERT_WITH_CODE(
3175 (smu7_power_state->performance_level_count <=
3176 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3177 "Performance levels exceeds Driver limit!",
3180 /* Performance levels are arranged from low to high. */
3181 performance_level->memory_clock = mclk_dep_table->entries
3182 [state_entry->ucMemoryClockIndexLow].ulMclk;
3183 if (sclk_dep_table->ucRevId == 0)
3184 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3185 [state_entry->ucEngineClockIndexLow].ulSclk;
3186 else if (sclk_dep_table->ucRevId == 1)
3187 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3188 [state_entry->ucEngineClockIndexLow].ulSclk;
3189 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3190 state_entry->ucPCIEGenLow);
3191 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3192 state_entry->ucPCIELaneLow);
3194 performance_level = &(smu7_power_state->performance_levels
3195 [smu7_power_state->performance_level_count++]);
3196 performance_level->memory_clock = mclk_dep_table->entries
3197 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3199 if (sclk_dep_table->ucRevId == 0)
3200 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3201 [state_entry->ucEngineClockIndexHigh].ulSclk;
3202 else if (sclk_dep_table->ucRevId == 1)
3203 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3204 [state_entry->ucEngineClockIndexHigh].ulSclk;
3206 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3207 state_entry->ucPCIEGenHigh);
3208 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3209 state_entry->ucPCIELaneHigh);
3214 static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr,
3215 unsigned long entry_index, struct pp_power_state *state)
3218 struct smu7_power_state *ps;
3219 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3220 struct phm_ppt_v1_information *table_info =
3221 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3222 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3223 table_info->vdd_dep_on_mclk;
3225 state->hardware.magic = PHM_VIslands_Magic;
3227 ps = (struct smu7_power_state *)(&state->hardware);
3229 result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state,
3230 smu7_get_pp_table_entry_callback_func_v1);
3232 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3233 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3234 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3236 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3237 if (dep_mclk_table->entries[0].clk !=
3238 data->vbios_boot_state.mclk_bootup_value)
3239 pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3240 "does not match VBIOS boot MCLK level");
3241 if (dep_mclk_table->entries[0].vddci !=
3242 data->vbios_boot_state.vddci_bootup_value)
3243 pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3244 "does not match VBIOS boot VDDCI level");
3247 /* set DC compatible flag if this state supports DC */
3248 if (!state->validation.disallowOnDC)
3249 ps->dc_compatible = true;
3251 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3252 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3254 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3255 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3260 switch (state->classification.ui_label) {
3261 case PP_StateUILabel_Performance:
3262 data->use_pcie_performance_levels = true;
3263 for (i = 0; i < ps->performance_level_count; i++) {
3264 if (data->pcie_gen_performance.max <
3265 ps->performance_levels[i].pcie_gen)
3266 data->pcie_gen_performance.max =
3267 ps->performance_levels[i].pcie_gen;
3269 if (data->pcie_gen_performance.min >
3270 ps->performance_levels[i].pcie_gen)
3271 data->pcie_gen_performance.min =
3272 ps->performance_levels[i].pcie_gen;
3274 if (data->pcie_lane_performance.max <
3275 ps->performance_levels[i].pcie_lane)
3276 data->pcie_lane_performance.max =
3277 ps->performance_levels[i].pcie_lane;
3278 if (data->pcie_lane_performance.min >
3279 ps->performance_levels[i].pcie_lane)
3280 data->pcie_lane_performance.min =
3281 ps->performance_levels[i].pcie_lane;
3284 case PP_StateUILabel_Battery:
3285 data->use_pcie_power_saving_levels = true;
3287 for (i = 0; i < ps->performance_level_count; i++) {
3288 if (data->pcie_gen_power_saving.max <
3289 ps->performance_levels[i].pcie_gen)
3290 data->pcie_gen_power_saving.max =
3291 ps->performance_levels[i].pcie_gen;
3293 if (data->pcie_gen_power_saving.min >
3294 ps->performance_levels[i].pcie_gen)
3295 data->pcie_gen_power_saving.min =
3296 ps->performance_levels[i].pcie_gen;
3298 if (data->pcie_lane_power_saving.max <
3299 ps->performance_levels[i].pcie_lane)
3300 data->pcie_lane_power_saving.max =
3301 ps->performance_levels[i].pcie_lane;
3303 if (data->pcie_lane_power_saving.min >
3304 ps->performance_levels[i].pcie_lane)
3305 data->pcie_lane_power_saving.min =
3306 ps->performance_levels[i].pcie_lane;
3316 static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
3317 struct pp_hw_power_state *power_state,
3318 unsigned int index, const void *clock_info)
3320 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3321 struct smu7_power_state *ps = cast_phw_smu7_power_state(power_state);
3322 const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info;
3323 struct smu7_performance_level *performance_level;
3324 uint32_t engine_clock, memory_clock;
3325 uint16_t pcie_gen_from_bios;
3327 engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow;
3328 memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow;
3330 if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
3331 data->highest_mclk = memory_clock;
3333 PP_ASSERT_WITH_CODE(
3334 (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
3335 "Performance levels exceeds SMC limit!",
3338 PP_ASSERT_WITH_CODE(
3339 (ps->performance_level_count <
3340 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3341 "Performance levels exceeds Driver limit, Skip!",
3344 performance_level = &(ps->performance_levels
3345 [ps->performance_level_count++]);
3347 /* Performance levels are arranged from low to high. */
3348 performance_level->memory_clock = memory_clock;
3349 performance_level->engine_clock = engine_clock;
3351 pcie_gen_from_bios = visland_clk_info->ucPCIEGen;
3353 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, pcie_gen_from_bios);
3354 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, visland_clk_info->usPCIELane);
3359 static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr,
3360 unsigned long entry_index, struct pp_power_state *state)
3363 struct smu7_power_state *ps;
3364 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3365 struct phm_clock_voltage_dependency_table *dep_mclk_table =
3366 hwmgr->dyn_state.vddci_dependency_on_mclk;
3368 memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state));
3370 state->hardware.magic = PHM_VIslands_Magic;
3372 ps = (struct smu7_power_state *)(&state->hardware);
3374 result = pp_tables_get_entry(hwmgr, entry_index, state,
3375 smu7_get_pp_table_entry_callback_func_v0);
3378 * This is the earliest time we have all the dependency table
3379 * and the VBIOS boot state as
3380 * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot
3381 * state if there is only one VDDCI/MCLK level, check if it's
3382 * the same as VBIOS boot state
3384 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3385 if (dep_mclk_table->entries[0].clk !=
3386 data->vbios_boot_state.mclk_bootup_value)
3387 pr_debug("Single MCLK entry VDDCI/MCLK dependency table "
3388 "does not match VBIOS boot MCLK level");
3389 if (dep_mclk_table->entries[0].v !=
3390 data->vbios_boot_state.vddci_bootup_value)
3391 pr_debug("Single VDDCI entry VDDCI/MCLK dependency table "
3392 "does not match VBIOS boot VDDCI level");
3395 /* set DC compatible flag if this state supports DC */
3396 if (!state->validation.disallowOnDC)
3397 ps->dc_compatible = true;
3399 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3400 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3402 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3403 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3408 switch (state->classification.ui_label) {
3409 case PP_StateUILabel_Performance:
3410 data->use_pcie_performance_levels = true;
3412 for (i = 0; i < ps->performance_level_count; i++) {
3413 if (data->pcie_gen_performance.max <
3414 ps->performance_levels[i].pcie_gen)
3415 data->pcie_gen_performance.max =
3416 ps->performance_levels[i].pcie_gen;
3418 if (data->pcie_gen_performance.min >
3419 ps->performance_levels[i].pcie_gen)
3420 data->pcie_gen_performance.min =
3421 ps->performance_levels[i].pcie_gen;
3423 if (data->pcie_lane_performance.max <
3424 ps->performance_levels[i].pcie_lane)
3425 data->pcie_lane_performance.max =
3426 ps->performance_levels[i].pcie_lane;
3428 if (data->pcie_lane_performance.min >
3429 ps->performance_levels[i].pcie_lane)
3430 data->pcie_lane_performance.min =
3431 ps->performance_levels[i].pcie_lane;
3434 case PP_StateUILabel_Battery:
3435 data->use_pcie_power_saving_levels = true;
3437 for (i = 0; i < ps->performance_level_count; i++) {
3438 if (data->pcie_gen_power_saving.max <
3439 ps->performance_levels[i].pcie_gen)
3440 data->pcie_gen_power_saving.max =
3441 ps->performance_levels[i].pcie_gen;
3443 if (data->pcie_gen_power_saving.min >
3444 ps->performance_levels[i].pcie_gen)
3445 data->pcie_gen_power_saving.min =
3446 ps->performance_levels[i].pcie_gen;
3448 if (data->pcie_lane_power_saving.max <
3449 ps->performance_levels[i].pcie_lane)
3450 data->pcie_lane_power_saving.max =
3451 ps->performance_levels[i].pcie_lane;
3453 if (data->pcie_lane_power_saving.min >
3454 ps->performance_levels[i].pcie_lane)
3455 data->pcie_lane_power_saving.min =
3456 ps->performance_levels[i].pcie_lane;
3466 static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3467 unsigned long entry_index, struct pp_power_state *state)
3469 if (hwmgr->pp_table_version == PP_TABLE_V0)
3470 return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state);
3471 else if (hwmgr->pp_table_version == PP_TABLE_V1)
3472 return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state);
3477 static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
3479 struct amdgpu_device *adev = hwmgr->adev;
3487 * PPSMC_MSG_GetCurrPkgPwr is not supported on:
3493 if ((adev->asic_type != CHIP_HAWAII) &&
3494 (adev->asic_type != CHIP_BONAIRE) &&
3495 (adev->asic_type != CHIP_FIJI) &&
3496 (adev->asic_type != CHIP_TONGA)) {
3497 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0);
3498 tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3505 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
3506 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3507 ixSMU_PM_STATUS_95, 0);
3509 for (i = 0; i < 10; i++) {
3511 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
3512 tmp = cgs_read_ind_register(hwmgr->device,
3514 ixSMU_PM_STATUS_95);
3523 static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3524 void *value, int *size)
3526 uint32_t sclk, mclk, activity_percent;
3527 uint32_t offset, val_vid;
3528 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3530 /* size must be at least 4 bytes for all sensors */
3535 case AMDGPU_PP_SENSOR_GFX_SCLK:
3536 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
3537 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3538 *((uint32_t *)value) = sclk;
3541 case AMDGPU_PP_SENSOR_GFX_MCLK:
3542 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
3543 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3544 *((uint32_t *)value) = mclk;
3547 case AMDGPU_PP_SENSOR_GPU_LOAD:
3548 offset = data->soft_regs_start + smum_get_offsetof(hwmgr,
3550 AverageGraphicsActivity);
3552 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3553 activity_percent += 0x80;
3554 activity_percent >>= 8;
3555 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3558 case AMDGPU_PP_SENSOR_GPU_TEMP:
3559 *((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr);
3562 case AMDGPU_PP_SENSOR_UVD_POWER:
3563 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3566 case AMDGPU_PP_SENSOR_VCE_POWER:
3567 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3570 case AMDGPU_PP_SENSOR_GPU_POWER:
3571 return smu7_get_gpu_power(hwmgr, (uint32_t *)value);
3572 case AMDGPU_PP_SENSOR_VDDGFX:
3573 if ((data->vr_config & VRCONF_VDDGFX_MASK) ==
3574 (VR_SVI2_PLANE_2 << VRCONF_VDDGFX_SHIFT))
3575 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
3576 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID);
3578 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
3579 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE1_VID);
3581 *((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid);
3588 static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3590 const struct phm_set_power_state_input *states =
3591 (const struct phm_set_power_state_input *)input;
3592 const struct smu7_power_state *smu7_ps =
3593 cast_const_phw_smu7_power_state(states->pnew_state);
3594 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3595 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3596 uint32_t sclk = smu7_ps->performance_levels
3597 [smu7_ps->performance_level_count - 1].engine_clock;
3598 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3599 uint32_t mclk = smu7_ps->performance_levels
3600 [smu7_ps->performance_level_count - 1].memory_clock;
3601 struct PP_Clocks min_clocks = {0};
3604 for (i = 0; i < sclk_table->count; i++) {
3605 if (sclk == sclk_table->dpm_levels[i].value)
3609 if (i >= sclk_table->count)
3610 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3612 /* TODO: Check SCLK in DAL's minimum clocks
3613 * in case DeepSleep divider update is required.
3615 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3616 (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK ||
3617 data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
3618 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3621 for (i = 0; i < mclk_table->count; i++) {
3622 if (mclk == mclk_table->dpm_levels[i].value)
3626 if (i >= mclk_table->count)
3627 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3630 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3631 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3636 static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3637 const struct smu7_power_state *smu7_ps)
3640 uint32_t sclk, max_sclk = 0;
3641 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3642 struct smu7_dpm_table *dpm_table = &data->dpm_table;
3644 for (i = 0; i < smu7_ps->performance_level_count; i++) {
3645 sclk = smu7_ps->performance_levels[i].engine_clock;
3646 if (max_sclk < sclk)
3650 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3651 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3652 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3653 dpm_table->pcie_speed_table.dpm_levels
3654 [dpm_table->pcie_speed_table.count - 1].value :
3655 dpm_table->pcie_speed_table.dpm_levels[i].value);
3661 static int smu7_request_link_speed_change_before_state_change(
3662 struct pp_hwmgr *hwmgr, const void *input)
3664 const struct phm_set_power_state_input *states =
3665 (const struct phm_set_power_state_input *)input;
3666 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3667 const struct smu7_power_state *smu7_nps =
3668 cast_const_phw_smu7_power_state(states->pnew_state);
3669 const struct smu7_power_state *polaris10_cps =
3670 cast_const_phw_smu7_power_state(states->pcurrent_state);
3672 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_nps);
3673 uint16_t current_link_speed;
3675 if (data->force_pcie_gen == PP_PCIEGenInvalid)
3676 current_link_speed = smu7_get_maximum_link_speed(hwmgr, polaris10_cps);
3678 current_link_speed = data->force_pcie_gen;
3680 data->force_pcie_gen = PP_PCIEGenInvalid;
3681 data->pspp_notify_required = false;
3683 if (target_link_speed > current_link_speed) {
3684 switch (target_link_speed) {
3687 if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN3, false))
3689 data->force_pcie_gen = PP_PCIEGen2;
3690 if (current_link_speed == PP_PCIEGen2)
3693 if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN2, false))
3697 data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr);
3701 if (target_link_speed < current_link_speed)
3702 data->pspp_notify_required = true;
3708 static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3710 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3712 if (0 == data->need_update_smu7_dpm_table)
3715 if ((0 == data->sclk_dpm_key_disabled) &&
3716 (data->need_update_smu7_dpm_table &
3717 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3718 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3719 "Trying to freeze SCLK DPM when DPM is disabled",
3721 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3722 PPSMC_MSG_SCLKDPM_FreezeLevel),
3723 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3727 if ((0 == data->mclk_dpm_key_disabled) &&
3728 (data->need_update_smu7_dpm_table &
3729 DPMTABLE_OD_UPDATE_MCLK)) {
3730 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3731 "Trying to freeze MCLK DPM when DPM is disabled",
3733 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3734 PPSMC_MSG_MCLKDPM_FreezeLevel),
3735 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3742 static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
3743 struct pp_hwmgr *hwmgr, const void *input)
3746 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3747 struct smu7_dpm_table *dpm_table = &data->dpm_table;
3749 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
3750 struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
3751 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
3753 if (0 == data->need_update_smu7_dpm_table)
3756 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3757 for (count = 0; count < dpm_table->sclk_table.count; count++) {
3758 dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled;
3759 dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock;
3763 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3764 for (count = 0; count < dpm_table->mclk_table.count; count++) {
3765 dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled;
3766 dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock;
3770 if (data->need_update_smu7_dpm_table &
3771 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
3772 result = smum_populate_all_graphic_levels(hwmgr);
3773 PP_ASSERT_WITH_CODE((0 == result),
3774 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3778 if (data->need_update_smu7_dpm_table &
3779 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
3780 /*populate MCLK dpm table to SMU7 */
3781 result = smum_populate_all_memory_levels(hwmgr);
3782 PP_ASSERT_WITH_CODE((0 == result),
3783 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3790 static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3791 struct smu7_single_dpm_table *dpm_table,
3792 uint32_t low_limit, uint32_t high_limit)
3796 /* force the trim if mclk_switching is disabled to prevent flicker */
3797 bool force_trim = (low_limit == high_limit);
3798 for (i = 0; i < dpm_table->count; i++) {
3799 /*skip the trim if od is enabled*/
3800 if ((!hwmgr->od_enabled || force_trim)
3801 && (dpm_table->dpm_levels[i].value < low_limit
3802 || dpm_table->dpm_levels[i].value > high_limit))
3803 dpm_table->dpm_levels[i].enabled = false;
3805 dpm_table->dpm_levels[i].enabled = true;
3811 static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr,
3812 const struct smu7_power_state *smu7_ps)
3814 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3815 uint32_t high_limit_count;
3817 PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1),
3818 "power state did not have any performance level",
3821 high_limit_count = (1 == smu7_ps->performance_level_count) ? 0 : 1;
3823 smu7_trim_single_dpm_states(hwmgr,
3824 &(data->dpm_table.sclk_table),
3825 smu7_ps->performance_levels[0].engine_clock,
3826 smu7_ps->performance_levels[high_limit_count].engine_clock);
3828 smu7_trim_single_dpm_states(hwmgr,
3829 &(data->dpm_table.mclk_table),
3830 smu7_ps->performance_levels[0].memory_clock,
3831 smu7_ps->performance_levels[high_limit_count].memory_clock);
3836 static int smu7_generate_dpm_level_enable_mask(
3837 struct pp_hwmgr *hwmgr, const void *input)
3840 const struct phm_set_power_state_input *states =
3841 (const struct phm_set_power_state_input *)input;
3842 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3843 const struct smu7_power_state *smu7_ps =
3844 cast_const_phw_smu7_power_state(states->pnew_state);
3847 result = smu7_trim_dpm_states(hwmgr, smu7_ps);
3851 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
3852 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
3853 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
3854 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
3855 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
3856 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
3861 static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3863 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3865 if (0 == data->need_update_smu7_dpm_table)
3868 if ((0 == data->sclk_dpm_key_disabled) &&
3869 (data->need_update_smu7_dpm_table &
3870 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3872 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3873 "Trying to Unfreeze SCLK DPM when DPM is disabled",
3875 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3876 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
3877 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
3881 if ((0 == data->mclk_dpm_key_disabled) &&
3882 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
3884 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
3885 "Trying to Unfreeze MCLK DPM when DPM is disabled",
3887 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3888 PPSMC_MSG_MCLKDPM_UnfreezeLevel),
3889 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
3893 data->need_update_smu7_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
3898 static int smu7_notify_link_speed_change_after_state_change(
3899 struct pp_hwmgr *hwmgr, const void *input)
3901 const struct phm_set_power_state_input *states =
3902 (const struct phm_set_power_state_input *)input;
3903 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3904 const struct smu7_power_state *smu7_ps =
3905 cast_const_phw_smu7_power_state(states->pnew_state);
3906 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps);
3909 if (data->pspp_notify_required) {
3910 if (target_link_speed == PP_PCIEGen3)
3911 request = PCIE_PERF_REQ_GEN3;
3912 else if (target_link_speed == PP_PCIEGen2)
3913 request = PCIE_PERF_REQ_GEN2;
3915 request = PCIE_PERF_REQ_GEN1;
3917 if (request == PCIE_PERF_REQ_GEN1 &&
3918 smu7_get_current_pcie_speed(hwmgr) > 0)
3922 if (amdgpu_acpi_pcie_performance_request(hwmgr->adev, request, false)) {
3923 if (PP_PCIEGen2 == target_link_speed)
3924 pr_info("PSPP request to switch to Gen2 from Gen3 Failed!");
3926 pr_info("PSPP request to switch to Gen1 from Gen2 Failed!");
3934 static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
3936 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3938 if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) {
3939 if (hwmgr->chip_id == CHIP_VEGAM)
3940 smum_send_msg_to_smc_with_parameter(hwmgr,
3941 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout_VEGAM, data->frame_time_x2);
3943 smum_send_msg_to_smc_with_parameter(hwmgr,
3944 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
3946 return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL;
3949 static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
3951 int tmp_result, result = 0;
3952 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
3954 tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
3955 PP_ASSERT_WITH_CODE((0 == tmp_result),
3956 "Failed to find DPM states clocks in DPM table!",
3957 result = tmp_result);
3959 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3960 PHM_PlatformCaps_PCIEPerformanceRequest)) {
3962 smu7_request_link_speed_change_before_state_change(hwmgr, input);
3963 PP_ASSERT_WITH_CODE((0 == tmp_result),
3964 "Failed to request link speed change before state change!",
3965 result = tmp_result);
3968 tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr);
3969 PP_ASSERT_WITH_CODE((0 == tmp_result),
3970 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
3972 tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
3973 PP_ASSERT_WITH_CODE((0 == tmp_result),
3974 "Failed to populate and upload SCLK MCLK DPM levels!",
3975 result = tmp_result);
3978 * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag.
3979 * That effectively disables AVFS feature.
3981 if (hwmgr->hardcode_pp_table != NULL)
3982 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
3984 tmp_result = smu7_update_avfs(hwmgr);
3985 PP_ASSERT_WITH_CODE((0 == tmp_result),
3986 "Failed to update avfs voltages!",
3987 result = tmp_result);
3989 tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
3990 PP_ASSERT_WITH_CODE((0 == tmp_result),
3991 "Failed to generate DPM level enabled mask!",
3992 result = tmp_result);
3994 tmp_result = smum_update_sclk_threshold(hwmgr);
3995 PP_ASSERT_WITH_CODE((0 == tmp_result),
3996 "Failed to update SCLK threshold!",
3997 result = tmp_result);
3999 tmp_result = smu7_notify_smc_display(hwmgr);
4000 PP_ASSERT_WITH_CODE((0 == tmp_result),
4001 "Failed to notify smc display settings!",
4002 result = tmp_result);
4004 tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);
4005 PP_ASSERT_WITH_CODE((0 == tmp_result),
4006 "Failed to unfreeze SCLK MCLK DPM!",
4007 result = tmp_result);
4009 tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr);
4010 PP_ASSERT_WITH_CODE((0 == tmp_result),
4011 "Failed to upload DPM level enabled mask!",
4012 result = tmp_result);
4014 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4015 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4017 smu7_notify_link_speed_change_after_state_change(hwmgr, input);
4018 PP_ASSERT_WITH_CODE((0 == tmp_result),
4019 "Failed to notify link speed change after state change!",
4020 result = tmp_result);
4022 data->apply_optimized_settings = false;
4026 static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4028 hwmgr->thermal_controller.
4029 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4031 return smum_send_msg_to_smc_with_parameter(hwmgr,
4032 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4036 smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4038 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4040 return (smum_send_msg_to_smc(hwmgr, msg) == 0) ? 0 : -1;
4044 smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4046 if (hwmgr->display_config->num_display > 1 &&
4047 !hwmgr->display_config->multi_monitor_in_sync)
4048 smu7_notify_smc_display_change(hwmgr, false);
4054 * Programs the display gap
4056 * @param hwmgr the address of the powerplay hardware manager.
4059 static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
4061 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4062 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4063 uint32_t display_gap2;
4064 uint32_t pre_vbi_time_in_us;
4065 uint32_t frame_time_in_us;
4066 uint32_t ref_clock, refresh_rate;
4068 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4069 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4071 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
4072 refresh_rate = hwmgr->display_config->vrefresh;
4074 if (0 == refresh_rate)
4077 frame_time_in_us = 1000000 / refresh_rate;
4079 pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time;
4081 data->frame_time_x2 = frame_time_in_us * 2 / 100;
4083 if (data->frame_time_x2 < 280) {
4084 pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", __func__, data->frame_time_x2);
4085 data->frame_time_x2 = 280;
4088 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4090 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4092 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4093 data->soft_regs_start + smum_get_offsetof(hwmgr,
4095 PreVBlankGap), 0x64);
4097 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4098 data->soft_regs_start + smum_get_offsetof(hwmgr,
4101 (frame_time_in_us - pre_vbi_time_in_us));
4106 static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4108 return smu7_program_display_gap(hwmgr);
4112 * Set maximum target operating fan output RPM
4114 * @param hwmgr: the address of the powerplay hardware manager.
4115 * @param usMaxFanRpm: max operating fan RPM value.
4116 * @return The response that came from the SMC.
4118 static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4120 hwmgr->thermal_controller.
4121 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4123 return smum_send_msg_to_smc_with_parameter(hwmgr,
4124 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4127 static const struct amdgpu_irq_src_funcs smu7_irq_funcs = {
4128 .process = phm_irq_process,
4131 static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
4133 struct amdgpu_irq_src *source =
4134 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
4139 source->funcs = &smu7_irq_funcs;
4141 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4142 AMDGPU_IH_CLIENTID_LEGACY,
4143 VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH,
4145 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4146 AMDGPU_IH_CLIENTID_LEGACY,
4147 VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW,
4150 /* Register CTF(GPIO_19) interrupt */
4151 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
4152 AMDGPU_IH_CLIENTID_LEGACY,
4153 VISLANDS30_IV_SRCID_GPIO_19,
4160 smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4162 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4163 bool is_update_required = false;
4165 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4166 is_update_required = true;
4168 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4169 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr &&
4170 (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK ||
4171 hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
4172 is_update_required = true;
4174 return is_update_required;
4177 static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1,
4178 const struct smu7_performance_level *pl2)
4180 return ((pl1->memory_clock == pl2->memory_clock) &&
4181 (pl1->engine_clock == pl2->engine_clock) &&
4182 (pl1->pcie_gen == pl2->pcie_gen) &&
4183 (pl1->pcie_lane == pl2->pcie_lane));
4186 static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
4187 const struct pp_hw_power_state *pstate1,
4188 const struct pp_hw_power_state *pstate2, bool *equal)
4190 const struct smu7_power_state *psa;
4191 const struct smu7_power_state *psb;
4193 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4195 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4198 psa = cast_const_phw_smu7_power_state(pstate1);
4199 psb = cast_const_phw_smu7_power_state(pstate2);
4200 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4201 if (psa->performance_level_count != psb->performance_level_count) {
4206 for (i = 0; i < psa->performance_level_count; i++) {
4207 if (!smu7_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4208 /* If we have found even one performance level pair that is different the states are different. */
4214 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4215 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4216 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4217 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4218 /* For OD call, set value based on flag */
4219 *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK |
4220 DPMTABLE_OD_UPDATE_MCLK |
4221 DPMTABLE_OD_UPDATE_VDDC));
4226 static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr)
4228 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4230 uint32_t vbios_version;
4233 /* Read MC indirect register offset 0x9F bits [3:0] to see
4234 * if VBIOS has already loaded a full version of MC ucode
4238 smu7_get_mc_microcode_version(hwmgr);
4239 vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4241 data->need_long_memory_training = false;
4243 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX,
4244 ixMC_IO_DEBUG_UP_13);
4245 tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
4247 if (tmp & (1 << 23)) {
4248 data->mem_latency_high = MEM_LATENCY_HIGH;
4249 data->mem_latency_low = MEM_LATENCY_LOW;
4251 data->mem_latency_high = 330;
4252 data->mem_latency_low = 330;
4258 static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr)
4260 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4262 data->clock_registers.vCG_SPLL_FUNC_CNTL =
4263 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
4264 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
4265 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
4266 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
4267 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
4268 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
4269 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
4270 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
4271 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
4272 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
4273 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
4274 data->clock_registers.vDLL_CNTL =
4275 cgs_read_register(hwmgr->device, mmDLL_CNTL);
4276 data->clock_registers.vMCLK_PWRMGT_CNTL =
4277 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
4278 data->clock_registers.vMPLL_AD_FUNC_CNTL =
4279 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
4280 data->clock_registers.vMPLL_DQ_FUNC_CNTL =
4281 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
4282 data->clock_registers.vMPLL_FUNC_CNTL =
4283 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
4284 data->clock_registers.vMPLL_FUNC_CNTL_1 =
4285 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
4286 data->clock_registers.vMPLL_FUNC_CNTL_2 =
4287 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
4288 data->clock_registers.vMPLL_SS1 =
4289 cgs_read_register(hwmgr->device, mmMPLL_SS1);
4290 data->clock_registers.vMPLL_SS2 =
4291 cgs_read_register(hwmgr->device, mmMPLL_SS2);
4297 * Find out if memory is GDDR5.
4299 * @param hwmgr the address of the powerplay hardware manager.
4302 static int smu7_get_memory_type(struct pp_hwmgr *hwmgr)
4304 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4305 struct amdgpu_device *adev = hwmgr->adev;
4307 data->is_memory_gddr5 = (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5);
4313 * Enables Dynamic Power Management by SMC
4315 * @param hwmgr the address of the powerplay hardware manager.
4318 static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4320 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4321 GENERAL_PWRMGT, STATIC_PM_EN, 1);
4327 * Initialize PowerGating States for different engines
4329 * @param hwmgr the address of the powerplay hardware manager.
4332 static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr)
4334 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4336 data->uvd_power_gated = false;
4337 data->vce_power_gated = false;
4342 static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4344 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4346 data->low_sclk_interrupt_threshold = 0;
4350 static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
4352 int tmp_result, result = 0;
4354 smu7_check_mc_firmware(hwmgr);
4356 tmp_result = smu7_read_clock_registers(hwmgr);
4357 PP_ASSERT_WITH_CODE((0 == tmp_result),
4358 "Failed to read clock registers!", result = tmp_result);
4360 tmp_result = smu7_get_memory_type(hwmgr);
4361 PP_ASSERT_WITH_CODE((0 == tmp_result),
4362 "Failed to get memory type!", result = tmp_result);
4364 tmp_result = smu7_enable_acpi_power_management(hwmgr);
4365 PP_ASSERT_WITH_CODE((0 == tmp_result),
4366 "Failed to enable ACPI power management!", result = tmp_result);
4368 tmp_result = smu7_init_power_gate_state(hwmgr);
4369 PP_ASSERT_WITH_CODE((0 == tmp_result),
4370 "Failed to init power gate state!", result = tmp_result);
4372 tmp_result = smu7_get_mc_microcode_version(hwmgr);
4373 PP_ASSERT_WITH_CODE((0 == tmp_result),
4374 "Failed to get MC microcode version!", result = tmp_result);
4376 tmp_result = smu7_init_sclk_threshold(hwmgr);
4377 PP_ASSERT_WITH_CODE((0 == tmp_result),
4378 "Failed to init sclk threshold!", result = tmp_result);
4383 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
4384 enum pp_clock_type type, uint32_t mask)
4386 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4393 if (!data->sclk_dpm_key_disabled)
4394 smum_send_msg_to_smc_with_parameter(hwmgr,
4395 PPSMC_MSG_SCLKDPM_SetEnabledMask,
4396 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
4399 if (!data->mclk_dpm_key_disabled)
4400 smum_send_msg_to_smc_with_parameter(hwmgr,
4401 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4402 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
4406 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4408 if (!data->pcie_dpm_key_disabled) {
4409 if (fls(tmp) != ffs(tmp))
4410 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel);
4412 smum_send_msg_to_smc_with_parameter(hwmgr,
4413 PPSMC_MSG_PCIeDPM_ForceLevel,
4425 static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
4426 enum pp_clock_type type, char *buf)
4428 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4429 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4430 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4431 struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4432 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
4433 struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
4434 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
4435 int i, now, size = 0;
4436 uint32_t clock, pcie_speed;
4440 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
4441 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4443 for (i = 0; i < sclk_table->count; i++) {
4444 if (clock > sclk_table->dpm_levels[i].value)
4450 for (i = 0; i < sclk_table->count; i++)
4451 size += sprintf(buf + size, "%d: %uMhz %s\n",
4452 i, sclk_table->dpm_levels[i].value / 100,
4453 (i == now) ? "*" : "");
4456 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
4457 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4459 for (i = 0; i < mclk_table->count; i++) {
4460 if (clock > mclk_table->dpm_levels[i].value)
4466 for (i = 0; i < mclk_table->count; i++)
4467 size += sprintf(buf + size, "%d: %uMhz %s\n",
4468 i, mclk_table->dpm_levels[i].value / 100,
4469 (i == now) ? "*" : "");
4472 pcie_speed = smu7_get_current_pcie_speed(hwmgr);
4473 for (i = 0; i < pcie_table->count; i++) {
4474 if (pcie_speed != pcie_table->dpm_levels[i].value)
4480 for (i = 0; i < pcie_table->count; i++)
4481 size += sprintf(buf + size, "%d: %s %s\n", i,
4482 (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" :
4483 (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
4484 (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
4485 (i == now) ? "*" : "");
4488 if (hwmgr->od_enabled) {
4489 size = sprintf(buf, "%s:\n", "OD_SCLK");
4490 for (i = 0; i < odn_sclk_table->num_of_pl; i++)
4491 size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
4492 i, odn_sclk_table->entries[i].clock/100,
4493 odn_sclk_table->entries[i].vddc);
4497 if (hwmgr->od_enabled) {
4498 size = sprintf(buf, "%s:\n", "OD_MCLK");
4499 for (i = 0; i < odn_mclk_table->num_of_pl; i++)
4500 size += sprintf(buf + size, "%d: %10uMHz %10umV\n",
4501 i, odn_mclk_table->entries[i].clock/100,
4502 odn_mclk_table->entries[i].vddc);
4506 if (hwmgr->od_enabled) {
4507 size = sprintf(buf, "%s:\n", "OD_RANGE");
4508 size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
4509 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
4510 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4511 size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
4512 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
4513 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4514 size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
4515 data->odn_dpm_table.min_vddc,
4516 data->odn_dpm_table.max_vddc);
4525 static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4528 case AMD_FAN_CTRL_NONE:
4529 smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
4531 case AMD_FAN_CTRL_MANUAL:
4532 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4533 PHM_PlatformCaps_MicrocodeFanControl))
4534 smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
4536 case AMD_FAN_CTRL_AUTO:
4537 if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode))
4538 smu7_fan_ctrl_start_smc_fan_control(hwmgr);
4545 static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4547 return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL;
4550 static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr)
4552 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4553 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4554 struct smu7_single_dpm_table *golden_sclk_table =
4555 &(data->golden_dpm_table.sclk_table);
4558 value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
4559 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
4561 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
4566 static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4568 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4569 struct smu7_single_dpm_table *golden_sclk_table =
4570 &(data->golden_dpm_table.sclk_table);
4571 struct pp_power_state *ps;
4572 struct smu7_power_state *smu7_ps;
4577 ps = hwmgr->request_ps;
4582 smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
4584 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].engine_clock =
4585 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
4587 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
4592 static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr)
4594 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4595 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4596 struct smu7_single_dpm_table *golden_mclk_table =
4597 &(data->golden_dpm_table.mclk_table);
4600 value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
4601 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
4603 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
4608 static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4610 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4611 struct smu7_single_dpm_table *golden_mclk_table =
4612 &(data->golden_dpm_table.mclk_table);
4613 struct pp_power_state *ps;
4614 struct smu7_power_state *smu7_ps;
4619 ps = hwmgr->request_ps;
4624 smu7_ps = cast_phw_smu7_power_state(&ps->hardware);
4626 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].memory_clock =
4627 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
4629 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
4635 static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
4637 struct phm_ppt_v1_information *table_info =
4638 (struct phm_ppt_v1_information *)hwmgr->pptable;
4639 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL;
4640 struct phm_clock_voltage_dependency_table *sclk_table;
4643 if (hwmgr->pp_table_version == PP_TABLE_V1) {
4644 if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL)
4646 dep_sclk_table = table_info->vdd_dep_on_sclk;
4647 for (i = 0; i < dep_sclk_table->count; i++)
4648 clocks->clock[i] = dep_sclk_table->entries[i].clk * 10;
4649 clocks->count = dep_sclk_table->count;
4650 } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
4651 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
4652 for (i = 0; i < sclk_table->count; i++)
4653 clocks->clock[i] = sclk_table->entries[i].clk * 10;
4654 clocks->count = sclk_table->count;
4660 static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk)
4662 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4664 if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY)
4665 return data->mem_latency_high;
4666 else if (clk >= MEM_FREQ_HIGH_LATENCY)
4667 return data->mem_latency_low;
4669 return MEM_LATENCY_ERR;
4672 static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
4674 struct phm_ppt_v1_information *table_info =
4675 (struct phm_ppt_v1_information *)hwmgr->pptable;
4676 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
4678 struct phm_clock_voltage_dependency_table *mclk_table;
4680 if (hwmgr->pp_table_version == PP_TABLE_V1) {
4681 if (table_info == NULL)
4683 dep_mclk_table = table_info->vdd_dep_on_mclk;
4684 for (i = 0; i < dep_mclk_table->count; i++) {
4685 clocks->clock[i] = dep_mclk_table->entries[i].clk * 10;
4686 clocks->latency[i] = smu7_get_mem_latency(hwmgr,
4687 dep_mclk_table->entries[i].clk);
4689 clocks->count = dep_mclk_table->count;
4690 } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
4691 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
4692 for (i = 0; i < mclk_table->count; i++)
4693 clocks->clock[i] = mclk_table->entries[i].clk * 10;
4694 clocks->count = mclk_table->count;
4699 static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
4700 struct amd_pp_clocks *clocks)
4703 case amd_pp_sys_clock:
4704 smu7_get_sclks(hwmgr, clocks);
4706 case amd_pp_mem_clock:
4707 smu7_get_mclks(hwmgr, clocks);
4716 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
4717 uint32_t virtual_addr_low,
4718 uint32_t virtual_addr_hi,
4719 uint32_t mc_addr_low,
4720 uint32_t mc_addr_hi,
4723 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4725 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4726 data->soft_regs_start +
4727 smum_get_offsetof(hwmgr,
4728 SMU_SoftRegisters, DRAM_LOG_ADDR_H),
4731 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4732 data->soft_regs_start +
4733 smum_get_offsetof(hwmgr,
4734 SMU_SoftRegisters, DRAM_LOG_ADDR_L),
4737 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4738 data->soft_regs_start +
4739 smum_get_offsetof(hwmgr,
4740 SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H),
4743 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4744 data->soft_regs_start +
4745 smum_get_offsetof(hwmgr,
4746 SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L),
4749 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4750 data->soft_regs_start +
4751 smum_get_offsetof(hwmgr,
4752 SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE),
4757 static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr,
4758 struct amd_pp_simple_clock_info *clocks)
4760 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4761 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4762 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4767 clocks->memory_max_clock = mclk_table->count > 1 ?
4768 mclk_table->dpm_levels[mclk_table->count-1].value :
4769 mclk_table->dpm_levels[0].value;
4770 clocks->engine_max_clock = sclk_table->count > 1 ?
4771 sclk_table->dpm_levels[sclk_table->count-1].value :
4772 sclk_table->dpm_levels[0].value;
4776 static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
4777 struct PP_TemperatureRange *thermal_data)
4779 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4780 struct phm_ppt_v1_information *table_info =
4781 (struct phm_ppt_v1_information *)hwmgr->pptable;
4783 memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange));
4785 if (hwmgr->pp_table_version == PP_TABLE_V1)
4786 thermal_data->max = table_info->cac_dtp_table->usSoftwareShutdownTemp *
4787 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4788 else if (hwmgr->pp_table_version == PP_TABLE_V0)
4789 thermal_data->max = data->thermal_temp_setting.temperature_shutdown *
4790 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4795 static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
4796 enum PP_OD_DPM_TABLE_COMMAND type,
4800 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4802 if (voltage < data->odn_dpm_table.min_vddc || voltage > data->odn_dpm_table.max_vddc) {
4803 pr_info("OD voltage is out of range [%d - %d] mV\n",
4804 data->odn_dpm_table.min_vddc,
4805 data->odn_dpm_table.max_vddc);
4809 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
4810 if (data->golden_dpm_table.sclk_table.dpm_levels[0].value > clk ||
4811 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
4812 pr_info("OD engine clock is out of range [%d - %d] MHz\n",
4813 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100,
4814 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4817 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
4818 if (data->golden_dpm_table.mclk_table.dpm_levels[0].value > clk ||
4819 hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
4820 pr_info("OD memory clock is out of range [%d - %d] MHz\n",
4821 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100,
4822 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4832 static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
4833 enum PP_OD_DPM_TABLE_COMMAND type,
4834 long *input, uint32_t size)
4837 struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
4838 struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
4839 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4843 uint32_t input_level;
4845 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
4848 if (!hwmgr->od_enabled) {
4849 pr_info("OverDrive feature not enabled\n");
4853 if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
4854 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
4855 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
4856 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
4857 "Failed to get ODN SCLK and Voltage tables",
4859 } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
4860 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
4861 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
4863 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
4864 "Failed to get ODN MCLK and Voltage tables",
4866 } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
4867 smu7_odn_initial_default_setting(hwmgr);
4869 } else if (PP_OD_COMMIT_DPM_TABLE == type) {
4870 smu7_check_dpm_table_updated(hwmgr);
4876 for (i = 0; i < size; i += 3) {
4877 if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
4878 pr_info("invalid clock voltage input \n");
4881 input_level = input[i];
4882 input_clk = input[i+1] * 100;
4883 input_vol = input[i+2];
4885 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
4886 podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
4887 podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
4888 podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
4889 podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
4898 static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
4900 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4901 uint32_t i, size = 0;
4904 static const char *profile_name[6] = {"3D_FULL_SCREEN",
4911 static const char *title[8] = {"NUM",
4915 "SCLK_ACTIVE_LEVEL",
4918 "MCLK_ACTIVE_LEVEL"};
4923 size += sprintf(buf + size, "%s %16s %16s %16s %16s %16s %16s %16s\n",
4924 title[0], title[1], title[2], title[3],
4925 title[4], title[5], title[6], title[7]);
4927 len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);
4929 for (i = 0; i < len; i++) {
4930 if (i == hwmgr->power_profile_mode) {
4931 size += sprintf(buf + size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n",
4932 i, profile_name[i], "*",
4933 data->current_profile_setting.sclk_up_hyst,
4934 data->current_profile_setting.sclk_down_hyst,
4935 data->current_profile_setting.sclk_activity,
4936 data->current_profile_setting.mclk_up_hyst,
4937 data->current_profile_setting.mclk_down_hyst,
4938 data->current_profile_setting.mclk_activity);
4941 if (smu7_profiling[i].bupdate_sclk)
4942 size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ",
4943 i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
4944 smu7_profiling[i].sclk_down_hyst,
4945 smu7_profiling[i].sclk_activity);
4947 size += sprintf(buf + size, "%3d %16s: %8s %16s %16s ",
4948 i, profile_name[i], "-", "-", "-");
4950 if (smu7_profiling[i].bupdate_mclk)
4951 size += sprintf(buf + size, "%16d %16d %16d\n",
4952 smu7_profiling[i].mclk_up_hyst,
4953 smu7_profiling[i].mclk_down_hyst,
4954 smu7_profiling[i].mclk_activity);
4956 size += sprintf(buf + size, "%16s %16s %16s\n",
4963 static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr,
4964 enum PP_SMC_POWER_PROFILE requst)
4966 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4967 uint32_t tmp, level;
4969 if (requst == PP_SMC_POWER_PROFILE_COMPUTE) {
4970 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4972 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
4976 smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1));
4978 } else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) {
4979 smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask);
4983 static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
4985 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
4986 struct profile_mode_setting tmp;
4987 enum PP_SMC_POWER_PROFILE mode;
4994 case PP_SMC_POWER_PROFILE_CUSTOM:
4998 tmp.bupdate_sclk = input[0];
4999 tmp.sclk_up_hyst = input[1];
5000 tmp.sclk_down_hyst = input[2];
5001 tmp.sclk_activity = input[3];
5002 tmp.bupdate_mclk = input[4];
5003 tmp.mclk_up_hyst = input[5];
5004 tmp.mclk_down_hyst = input[6];
5005 tmp.mclk_activity = input[7];
5006 if (!smum_update_dpm_settings(hwmgr, &tmp)) {
5007 memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting));
5008 hwmgr->power_profile_mode = mode;
5011 case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
5012 case PP_SMC_POWER_PROFILE_POWERSAVING:
5013 case PP_SMC_POWER_PROFILE_VIDEO:
5014 case PP_SMC_POWER_PROFILE_VR:
5015 case PP_SMC_POWER_PROFILE_COMPUTE:
5016 if (mode == hwmgr->power_profile_mode)
5019 memcpy(&tmp, &smu7_profiling[mode], sizeof(struct profile_mode_setting));
5020 if (!smum_update_dpm_settings(hwmgr, &tmp)) {
5021 if (tmp.bupdate_sclk) {
5022 data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk;
5023 data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst;
5024 data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst;
5025 data->current_profile_setting.sclk_activity = tmp.sclk_activity;
5027 if (tmp.bupdate_mclk) {
5028 data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk;
5029 data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst;
5030 data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst;
5031 data->current_profile_setting.mclk_activity = tmp.mclk_activity;
5033 smu7_patch_compute_profile_mode(hwmgr, mode);
5034 hwmgr->power_profile_mode = mode;
5044 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
5045 .backend_init = &smu7_hwmgr_backend_init,
5046 .backend_fini = &smu7_hwmgr_backend_fini,
5047 .asic_setup = &smu7_setup_asic_task,
5048 .dynamic_state_management_enable = &smu7_enable_dpm_tasks,
5049 .apply_state_adjust_rules = smu7_apply_state_adjust_rules,
5050 .force_dpm_level = &smu7_force_dpm_level,
5051 .power_state_set = smu7_set_power_state_tasks,
5052 .get_power_state_size = smu7_get_power_state_size,
5053 .get_mclk = smu7_dpm_get_mclk,
5054 .get_sclk = smu7_dpm_get_sclk,
5055 .patch_boot_state = smu7_dpm_patch_boot_state,
5056 .get_pp_table_entry = smu7_get_pp_table_entry,
5057 .get_num_of_pp_table_entries = smu7_get_number_of_powerplay_table_entries,
5058 .powerdown_uvd = smu7_powerdown_uvd,
5059 .powergate_uvd = smu7_powergate_uvd,
5060 .powergate_vce = smu7_powergate_vce,
5061 .disable_clock_power_gating = smu7_disable_clock_power_gating,
5062 .update_clock_gatings = smu7_update_clock_gatings,
5063 .notify_smc_display_config_after_ps_adjustment = smu7_notify_smc_display_config_after_ps_adjustment,
5064 .display_config_changed = smu7_display_configuration_changed_task,
5065 .set_max_fan_pwm_output = smu7_set_max_fan_pwm_output,
5066 .set_max_fan_rpm_output = smu7_set_max_fan_rpm_output,
5067 .stop_thermal_controller = smu7_thermal_stop_thermal_controller,
5068 .get_fan_speed_info = smu7_fan_ctrl_get_fan_speed_info,
5069 .get_fan_speed_percent = smu7_fan_ctrl_get_fan_speed_percent,
5070 .set_fan_speed_percent = smu7_fan_ctrl_set_fan_speed_percent,
5071 .reset_fan_speed_to_default = smu7_fan_ctrl_reset_fan_speed_to_default,
5072 .get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm,
5073 .set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm,
5074 .uninitialize_thermal_controller = smu7_thermal_ctrl_uninitialize_thermal_controller,
5075 .register_irq_handlers = smu7_register_irq_handlers,
5076 .check_smc_update_required_for_display_configuration = smu7_check_smc_update_required_for_display_configuration,
5077 .check_states_equal = smu7_check_states_equal,
5078 .set_fan_control_mode = smu7_set_fan_control_mode,
5079 .get_fan_control_mode = smu7_get_fan_control_mode,
5080 .force_clock_level = smu7_force_clock_level,
5081 .print_clock_levels = smu7_print_clock_levels,
5082 .powergate_gfx = smu7_powergate_gfx,
5083 .get_sclk_od = smu7_get_sclk_od,
5084 .set_sclk_od = smu7_set_sclk_od,
5085 .get_mclk_od = smu7_get_mclk_od,
5086 .set_mclk_od = smu7_set_mclk_od,
5087 .get_clock_by_type = smu7_get_clock_by_type,
5088 .read_sensor = smu7_read_sensor,
5089 .dynamic_state_management_disable = smu7_disable_dpm_tasks,
5090 .avfs_control = smu7_avfs_control,
5091 .disable_smc_firmware_ctf = smu7_thermal_disable_alert,
5092 .start_thermal_controller = smu7_start_thermal_controller,
5093 .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
5094 .get_max_high_clocks = smu7_get_max_high_clocks,
5095 .get_thermal_temperature_range = smu7_get_thermal_temperature_range,
5096 .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
5097 .set_power_limit = smu7_set_power_limit,
5098 .get_power_profile_mode = smu7_get_power_profile_mode,
5099 .set_power_profile_mode = smu7_set_power_profile_mode,
5102 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
5103 uint32_t clock_insr)
5107 uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);
5109 PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
5110 for (i = SMU7_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
5113 if (temp >= min || i == 0)
5119 int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
5123 hwmgr->hwmgr_func = &smu7_hwmgr_funcs;
5124 if (hwmgr->pp_table_version == PP_TABLE_V0)
5125 hwmgr->pptable_func = &pptable_funcs;
5126 else if (hwmgr->pp_table_version == PP_TABLE_V1)
5127 hwmgr->pptable_func = &pptable_v1_0_funcs;