2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/errno.h>
25 #include "hardwaremanager.h"
26 #include "power_state.h"
29 #define PHM_FUNC_CHECK(hw) \
31 if ((hw) == NULL || (hw)->hwmgr_func == NULL) \
35 bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)
37 return hwmgr->block_hw_access;
40 int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block)
42 hwmgr->block_hw_access = block;
46 int phm_setup_asic(struct pp_hwmgr *hwmgr)
48 PHM_FUNC_CHECK(hwmgr);
50 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
51 PHM_PlatformCaps_TablelessHardwareInterface)) {
52 if (NULL != hwmgr->hwmgr_func->asic_setup)
53 return hwmgr->hwmgr_func->asic_setup(hwmgr);
55 return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic),
62 int phm_power_down_asic(struct pp_hwmgr *hwmgr)
64 PHM_FUNC_CHECK(hwmgr);
66 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
67 PHM_PlatformCaps_TablelessHardwareInterface)) {
68 if (NULL != hwmgr->hwmgr_func->power_off_asic)
69 return hwmgr->hwmgr_func->power_off_asic(hwmgr);
71 return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic),
78 int phm_set_power_state(struct pp_hwmgr *hwmgr,
79 const struct pp_hw_power_state *pcurrent_state,
80 const struct pp_hw_power_state *pnew_power_state)
82 struct phm_set_power_state_input states;
84 PHM_FUNC_CHECK(hwmgr);
86 states.pcurrent_state = pcurrent_state;
87 states.pnew_state = pnew_power_state;
89 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
90 PHM_PlatformCaps_TablelessHardwareInterface)) {
91 if (NULL != hwmgr->hwmgr_func->power_state_set)
92 return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
94 return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL);
100 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
104 PHM_FUNC_CHECK(hwmgr);
106 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
107 PHM_PlatformCaps_TablelessHardwareInterface)) {
108 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
109 ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
111 ret = phm_dispatch_table(hwmgr,
112 &(hwmgr->enable_dynamic_state_management),
116 enabled = ret == 0 ? true : false;
118 cgs_notify_dpm_enabled(hwmgr->device, enabled);
123 int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
128 PHM_FUNC_CHECK(hwmgr);
130 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
131 PHM_PlatformCaps_TablelessHardwareInterface)) {
132 if (hwmgr->hwmgr_func->dynamic_state_management_disable)
133 ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
135 ret = phm_dispatch_table(hwmgr,
136 &(hwmgr->disable_dynamic_state_management),
140 enabled = ret == 0 ? false : true;
142 cgs_notify_dpm_enabled(hwmgr->device, enabled);
147 int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
149 PHM_FUNC_CHECK(hwmgr);
151 if (hwmgr->hwmgr_func->force_dpm_level != NULL)
152 return hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
157 int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
158 struct pp_power_state *adjusted_ps,
159 const struct pp_power_state *current_ps)
161 PHM_FUNC_CHECK(hwmgr);
163 if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
164 return hwmgr->hwmgr_func->apply_state_adjust_rules(
171 int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
173 PHM_FUNC_CHECK(hwmgr);
175 if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
176 return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
180 int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate)
182 PHM_FUNC_CHECK(hwmgr);
184 if (hwmgr->hwmgr_func->powergate_uvd != NULL)
185 return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
189 int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate)
191 PHM_FUNC_CHECK(hwmgr);
193 if (hwmgr->hwmgr_func->powergate_vce != NULL)
194 return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
198 int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
200 PHM_FUNC_CHECK(hwmgr);
202 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
203 PHM_PlatformCaps_TablelessHardwareInterface)) {
204 if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
205 return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
207 return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL);
212 int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
214 PHM_FUNC_CHECK(hwmgr);
216 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
217 PHM_PlatformCaps_TablelessHardwareInterface)) {
218 if (NULL != hwmgr->hwmgr_func->display_config_changed)
219 hwmgr->hwmgr_func->display_config_changed(hwmgr);
221 return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL);
225 int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
227 PHM_FUNC_CHECK(hwmgr);
229 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
230 PHM_PlatformCaps_TablelessHardwareInterface))
231 if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
232 hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
237 int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
239 PHM_FUNC_CHECK(hwmgr);
241 if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
244 return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
247 int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
249 PHM_FUNC_CHECK(hwmgr);
251 if (hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
254 return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
258 * Initializes the thermal controller subsystem.
260 * @param pHwMgr the address of the powerplay hardware manager.
261 * @param pTemperatureRange the address of the structure holding the temperature range.
262 * @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
264 int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
266 return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
270 bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
272 PHM_FUNC_CHECK(hwmgr);
274 if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
277 return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
281 int phm_check_states_equal(struct pp_hwmgr *hwmgr,
282 const struct pp_hw_power_state *pstate1,
283 const struct pp_hw_power_state *pstate2,
286 PHM_FUNC_CHECK(hwmgr);
288 if (hwmgr->hwmgr_func->check_states_equal == NULL)
291 return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
294 int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
295 const struct amd_pp_display_configuration *display_config)
297 PHM_FUNC_CHECK(hwmgr);
299 if (display_config == NULL)
302 hwmgr->display_config = *display_config;
304 if (hwmgr->hwmgr_func->store_cc6_data == NULL)
307 /* TODO: pass other display configuration in the future */
309 if (hwmgr->hwmgr_func->store_cc6_data)
310 hwmgr->hwmgr_func->store_cc6_data(hwmgr,
311 display_config->cpu_pstate_separation_time,
312 display_config->cpu_cc6_disable,
313 display_config->cpu_pstate_disable,
314 display_config->nb_pstate_switch_disable);
319 int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
320 struct amd_pp_simple_clock_info *info)
322 PHM_FUNC_CHECK(hwmgr);
324 if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
326 return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
329 int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
331 PHM_FUNC_CHECK(hwmgr);
333 if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
334 return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
340 int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
341 PHM_PerformanceLevelDesignation designation, uint32_t index,
342 PHM_PerformanceLevel *level)
344 PHM_FUNC_CHECK(hwmgr);
345 if (hwmgr->hwmgr_func->get_performance_level == NULL)
348 return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level);
357 * @param pHwMgr the address of the powerplay hardware manager.
358 * @param pPowerState the address of the Power State structure.
359 * @param pClockInfo the address of PP_ClockInfo structure where the result will be returned.
360 * @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the back-end.
362 int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *pclock_info,
363 PHM_PerformanceLevelDesignation designation)
366 PHM_PerformanceLevel performance_level;
368 PHM_FUNC_CHECK(hwmgr);
370 PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
371 PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);
373 result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level);
375 PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);
378 pclock_info->min_mem_clk = performance_level.memory_clock;
379 pclock_info->min_eng_clk = performance_level.coreClock;
380 pclock_info->min_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
383 result = phm_get_performance_level(hwmgr, state, designation,
384 (hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level);
386 PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);
388 pclock_info->max_mem_clk = performance_level.memory_clock;
389 pclock_info->max_eng_clk = performance_level.coreClock;
390 pclock_info->max_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
395 int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
397 PHM_FUNC_CHECK(hwmgr);
399 if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL)
402 return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info);
406 int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
408 PHM_FUNC_CHECK(hwmgr);
410 if (hwmgr->hwmgr_func->get_clock_by_type == NULL)
413 return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);
417 int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
419 PHM_FUNC_CHECK(hwmgr);
421 if (hwmgr->hwmgr_func->get_max_high_clocks == NULL)
424 return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);