2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/gfp.h>
27 #include <linux/slab.h>
28 #include "amd_shared.h"
29 #include "amd_powerplay.h"
30 #include "pp_instance.h"
31 #include "power_state.h"
32 #include "eventmanager.h"
35 static inline int pp_check(struct pp_instance *handle)
37 if (handle == NULL || handle->pp_valid != PP_VALID)
40 if (handle->smu_mgr == NULL || handle->smu_mgr->smumgr_funcs == NULL)
43 if (handle->pm_en == 0)
44 return PP_DPM_DISABLED;
46 if (handle->hwmgr == NULL || handle->hwmgr->hwmgr_func == NULL
47 || handle->eventmgr == NULL)
48 return PP_DPM_DISABLED;
53 static int pp_early_init(void *handle)
56 struct pp_instance *pp_handle = (struct pp_instance *)handle;
58 ret = smum_early_init(pp_handle);
62 if ((pp_handle->pm_en == 0)
63 || cgs_is_virtualization_enabled(pp_handle->device))
64 return PP_DPM_DISABLED;
66 ret = hwmgr_early_init(pp_handle);
69 return PP_DPM_DISABLED;
72 ret = eventmgr_early_init(pp_handle);
74 kfree(pp_handle->hwmgr);
75 pp_handle->hwmgr = NULL;
77 return PP_DPM_DISABLED;
83 static int pp_sw_init(void *handle)
85 struct pp_smumgr *smumgr;
87 struct pp_instance *pp_handle = (struct pp_instance *)handle;
89 ret = pp_check(pp_handle);
91 if (ret == 0 || ret == PP_DPM_DISABLED) {
92 smumgr = pp_handle->smu_mgr;
94 if (smumgr->smumgr_funcs->smu_init == NULL)
97 ret = smumgr->smumgr_funcs->smu_init(smumgr);
99 pr_info("amdgpu: powerplay sw initialized\n");
104 static int pp_sw_fini(void *handle)
106 struct pp_smumgr *smumgr;
108 struct pp_instance *pp_handle = (struct pp_instance *)handle;
110 ret = pp_check(pp_handle);
111 if (ret == 0 || ret == PP_DPM_DISABLED) {
112 smumgr = pp_handle->smu_mgr;
114 if (smumgr->smumgr_funcs->smu_fini == NULL)
117 ret = smumgr->smumgr_funcs->smu_fini(smumgr);
122 static int pp_hw_init(void *handle)
124 struct pp_smumgr *smumgr;
125 struct pp_eventmgr *eventmgr;
127 struct pp_instance *pp_handle = (struct pp_instance *)handle;
129 ret = pp_check(pp_handle);
131 if (ret == 0 || ret == PP_DPM_DISABLED) {
132 smumgr = pp_handle->smu_mgr;
134 if (smumgr->smumgr_funcs->start_smu == NULL)
137 if(smumgr->smumgr_funcs->start_smu(smumgr)) {
138 pr_err("smc start failed\n");
139 smumgr->smumgr_funcs->smu_fini(smumgr);
142 if (ret == PP_DPM_DISABLED)
143 return PP_DPM_DISABLED;
146 ret = hwmgr_hw_init(pp_handle);
150 eventmgr = pp_handle->eventmgr;
151 if (eventmgr->pp_eventmgr_init == NULL ||
152 eventmgr->pp_eventmgr_init(eventmgr))
157 pp_handle->pm_en = 0;
158 kfree(pp_handle->eventmgr);
159 kfree(pp_handle->hwmgr);
160 pp_handle->hwmgr = NULL;
161 pp_handle->eventmgr = NULL;
162 return PP_DPM_DISABLED;
165 static int pp_hw_fini(void *handle)
167 struct pp_eventmgr *eventmgr;
168 struct pp_instance *pp_handle = (struct pp_instance *)handle;
171 ret = pp_check(pp_handle);
174 eventmgr = pp_handle->eventmgr;
176 if (eventmgr->pp_eventmgr_fini != NULL)
177 eventmgr->pp_eventmgr_fini(eventmgr);
179 hwmgr_hw_fini(pp_handle);
184 static bool pp_is_idle(void *handle)
189 static int pp_wait_for_idle(void *handle)
194 static int pp_sw_reset(void *handle)
200 int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id)
202 struct pp_hwmgr *hwmgr;
203 struct pp_instance *pp_handle = (struct pp_instance *)handle;
206 ret = pp_check(pp_handle);
211 hwmgr = pp_handle->hwmgr;
213 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
214 pr_info("%s was not implemented.\n", __func__);
218 return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
221 static int pp_set_powergating_state(void *handle,
222 enum amd_powergating_state state)
224 struct pp_hwmgr *hwmgr;
225 struct pp_instance *pp_handle = (struct pp_instance *)handle;
228 ret = pp_check(pp_handle);
233 hwmgr = pp_handle->hwmgr;
235 if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
236 pr_info("%s was not implemented.\n", __func__);
240 /* Enable/disable GFX per cu powergating through SMU */
241 return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
242 state == AMD_PG_STATE_GATE);
245 static int pp_suspend(void *handle)
247 struct pp_eventmgr *eventmgr;
248 struct pem_event_data event_data = { {0} };
249 struct pp_instance *pp_handle = (struct pp_instance *)handle;
252 ret = pp_check(pp_handle);
254 if (ret == PP_DPM_DISABLED)
259 eventmgr = pp_handle->eventmgr;
260 pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data);
265 static int pp_resume(void *handle)
267 struct pp_eventmgr *eventmgr;
268 struct pem_event_data event_data = { {0} };
269 struct pp_smumgr *smumgr;
271 struct pp_instance *pp_handle = (struct pp_instance *)handle;
273 ret1 = pp_check(pp_handle);
275 if (ret1 != 0 && ret1 != PP_DPM_DISABLED)
278 smumgr = pp_handle->smu_mgr;
280 if (smumgr->smumgr_funcs->start_smu == NULL)
283 ret = smumgr->smumgr_funcs->start_smu(smumgr);
285 pr_err("smc start failed\n");
286 smumgr->smumgr_funcs->smu_fini(smumgr);
290 if (ret1 == PP_DPM_DISABLED)
293 eventmgr = pp_handle->eventmgr;
295 pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data);
300 const struct amd_ip_funcs pp_ip_funcs = {
302 .early_init = pp_early_init,
304 .sw_init = pp_sw_init,
305 .sw_fini = pp_sw_fini,
306 .hw_init = pp_hw_init,
307 .hw_fini = pp_hw_fini,
308 .suspend = pp_suspend,
310 .is_idle = pp_is_idle,
311 .wait_for_idle = pp_wait_for_idle,
312 .soft_reset = pp_sw_reset,
313 .set_clockgating_state = NULL,
314 .set_powergating_state = pp_set_powergating_state,
317 static int pp_dpm_load_fw(void *handle)
322 static int pp_dpm_fw_loading_complete(void *handle)
327 static int pp_dpm_force_performance_level(void *handle,
328 enum amd_dpm_forced_level level)
330 struct pp_hwmgr *hwmgr;
331 struct pp_instance *pp_handle = (struct pp_instance *)handle;
334 ret = pp_check(pp_handle);
339 hwmgr = pp_handle->hwmgr;
341 if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
342 pr_info("%s was not implemented.\n", __func__);
346 mutex_lock(&pp_handle->pp_lock);
347 hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
348 mutex_unlock(&pp_handle->pp_lock);
352 static enum amd_dpm_forced_level pp_dpm_get_performance_level(
355 struct pp_hwmgr *hwmgr;
356 struct pp_instance *pp_handle = (struct pp_instance *)handle;
358 enum amd_dpm_forced_level level;
360 ret = pp_check(pp_handle);
365 hwmgr = pp_handle->hwmgr;
366 mutex_lock(&pp_handle->pp_lock);
367 level = hwmgr->dpm_level;
368 mutex_unlock(&pp_handle->pp_lock);
372 static int pp_dpm_get_sclk(void *handle, bool low)
374 struct pp_hwmgr *hwmgr;
375 struct pp_instance *pp_handle = (struct pp_instance *)handle;
378 ret = pp_check(pp_handle);
383 hwmgr = pp_handle->hwmgr;
385 if (hwmgr->hwmgr_func->get_sclk == NULL) {
386 pr_info("%s was not implemented.\n", __func__);
389 mutex_lock(&pp_handle->pp_lock);
390 ret = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
391 mutex_unlock(&pp_handle->pp_lock);
395 static int pp_dpm_get_mclk(void *handle, bool low)
397 struct pp_hwmgr *hwmgr;
398 struct pp_instance *pp_handle = (struct pp_instance *)handle;
401 ret = pp_check(pp_handle);
406 hwmgr = pp_handle->hwmgr;
408 if (hwmgr->hwmgr_func->get_mclk == NULL) {
409 pr_info("%s was not implemented.\n", __func__);
412 mutex_lock(&pp_handle->pp_lock);
413 ret = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
414 mutex_unlock(&pp_handle->pp_lock);
418 static int pp_dpm_powergate_vce(void *handle, bool gate)
420 struct pp_hwmgr *hwmgr;
421 struct pp_instance *pp_handle = (struct pp_instance *)handle;
424 ret = pp_check(pp_handle);
429 hwmgr = pp_handle->hwmgr;
431 if (hwmgr->hwmgr_func->powergate_vce == NULL) {
432 pr_info("%s was not implemented.\n", __func__);
435 mutex_lock(&pp_handle->pp_lock);
436 ret = hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
437 mutex_unlock(&pp_handle->pp_lock);
441 static int pp_dpm_powergate_uvd(void *handle, bool gate)
443 struct pp_hwmgr *hwmgr;
444 struct pp_instance *pp_handle = (struct pp_instance *)handle;
447 ret = pp_check(pp_handle);
452 hwmgr = pp_handle->hwmgr;
454 if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
455 pr_info("%s was not implemented.\n", __func__);
458 mutex_lock(&pp_handle->pp_lock);
459 ret = hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
460 mutex_unlock(&pp_handle->pp_lock);
464 static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state)
467 case POWER_STATE_TYPE_BATTERY:
468 return PP_StateUILabel_Battery;
469 case POWER_STATE_TYPE_BALANCED:
470 return PP_StateUILabel_Balanced;
471 case POWER_STATE_TYPE_PERFORMANCE:
472 return PP_StateUILabel_Performance;
474 return PP_StateUILabel_None;
478 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id,
479 void *input, void *output)
482 struct pem_event_data data = { {0} };
483 struct pp_instance *pp_handle = (struct pp_instance *)handle;
485 ret = pp_check(pp_handle);
489 mutex_lock(&pp_handle->pp_lock);
491 case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE:
492 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
494 case AMD_PP_EVENT_ENABLE_USER_STATE:
496 enum amd_pm_state_type ps;
502 ps = *(unsigned long *)input;
504 data.requested_ui_label = power_state_convert(ps);
505 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
508 case AMD_PP_EVENT_COMPLETE_INIT:
509 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
511 case AMD_PP_EVENT_READJUST_POWER_STATE:
512 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
517 mutex_unlock(&pp_handle->pp_lock);
521 static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
523 struct pp_hwmgr *hwmgr;
524 struct pp_power_state *state;
525 struct pp_instance *pp_handle = (struct pp_instance *)handle;
527 enum amd_pm_state_type pm_type;
529 ret = pp_check(pp_handle);
534 hwmgr = pp_handle->hwmgr;
536 if (hwmgr->current_ps == NULL)
539 mutex_lock(&pp_handle->pp_lock);
541 state = hwmgr->current_ps;
543 switch (state->classification.ui_label) {
544 case PP_StateUILabel_Battery:
545 pm_type = POWER_STATE_TYPE_BATTERY;
547 case PP_StateUILabel_Balanced:
548 pm_type = POWER_STATE_TYPE_BALANCED;
550 case PP_StateUILabel_Performance:
551 pm_type = POWER_STATE_TYPE_PERFORMANCE;
554 if (state->classification.flags & PP_StateClassificationFlag_Boot)
555 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
557 pm_type = POWER_STATE_TYPE_DEFAULT;
560 mutex_unlock(&pp_handle->pp_lock);
565 static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
567 struct pp_hwmgr *hwmgr;
568 struct pp_instance *pp_handle = (struct pp_instance *)handle;
571 ret = pp_check(pp_handle);
576 hwmgr = pp_handle->hwmgr;
578 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
579 pr_info("%s was not implemented.\n", __func__);
582 mutex_lock(&pp_handle->pp_lock);
583 ret = hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
584 mutex_unlock(&pp_handle->pp_lock);
588 static int pp_dpm_get_fan_control_mode(void *handle)
590 struct pp_hwmgr *hwmgr;
591 struct pp_instance *pp_handle = (struct pp_instance *)handle;
594 ret = pp_check(pp_handle);
599 hwmgr = pp_handle->hwmgr;
601 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
602 pr_info("%s was not implemented.\n", __func__);
605 mutex_lock(&pp_handle->pp_lock);
606 ret = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
607 mutex_unlock(&pp_handle->pp_lock);
611 static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
613 struct pp_hwmgr *hwmgr;
614 struct pp_instance *pp_handle = (struct pp_instance *)handle;
617 ret = pp_check(pp_handle);
622 hwmgr = pp_handle->hwmgr;
624 if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
625 pr_info("%s was not implemented.\n", __func__);
628 mutex_lock(&pp_handle->pp_lock);
629 ret = hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
630 mutex_unlock(&pp_handle->pp_lock);
634 static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
636 struct pp_hwmgr *hwmgr;
637 struct pp_instance *pp_handle = (struct pp_instance *)handle;
640 ret = pp_check(pp_handle);
645 hwmgr = pp_handle->hwmgr;
647 if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
648 pr_info("%s was not implemented.\n", __func__);
652 mutex_lock(&pp_handle->pp_lock);
653 ret = hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
654 mutex_unlock(&pp_handle->pp_lock);
658 static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
660 struct pp_hwmgr *hwmgr;
661 struct pp_instance *pp_handle = (struct pp_instance *)handle;
664 ret = pp_check(pp_handle);
669 hwmgr = pp_handle->hwmgr;
671 if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
674 mutex_lock(&pp_handle->pp_lock);
675 ret = hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
676 mutex_unlock(&pp_handle->pp_lock);
680 static int pp_dpm_get_temperature(void *handle)
682 struct pp_hwmgr *hwmgr;
683 struct pp_instance *pp_handle = (struct pp_instance *)handle;
686 ret = pp_check(pp_handle);
691 hwmgr = pp_handle->hwmgr;
693 if (hwmgr->hwmgr_func->get_temperature == NULL) {
694 pr_info("%s was not implemented.\n", __func__);
697 mutex_lock(&pp_handle->pp_lock);
698 ret = hwmgr->hwmgr_func->get_temperature(hwmgr);
699 mutex_unlock(&pp_handle->pp_lock);
703 static int pp_dpm_get_pp_num_states(void *handle,
704 struct pp_states_info *data)
706 struct pp_hwmgr *hwmgr;
708 struct pp_instance *pp_handle = (struct pp_instance *)handle;
711 ret = pp_check(pp_handle);
716 hwmgr = pp_handle->hwmgr;
718 if (hwmgr->ps == NULL)
721 mutex_lock(&pp_handle->pp_lock);
723 data->nums = hwmgr->num_ps;
725 for (i = 0; i < hwmgr->num_ps; i++) {
726 struct pp_power_state *state = (struct pp_power_state *)
727 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
728 switch (state->classification.ui_label) {
729 case PP_StateUILabel_Battery:
730 data->states[i] = POWER_STATE_TYPE_BATTERY;
732 case PP_StateUILabel_Balanced:
733 data->states[i] = POWER_STATE_TYPE_BALANCED;
735 case PP_StateUILabel_Performance:
736 data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
739 if (state->classification.flags & PP_StateClassificationFlag_Boot)
740 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
742 data->states[i] = POWER_STATE_TYPE_DEFAULT;
745 mutex_unlock(&pp_handle->pp_lock);
749 static int pp_dpm_get_pp_table(void *handle, char **table)
751 struct pp_hwmgr *hwmgr;
752 struct pp_instance *pp_handle = (struct pp_instance *)handle;
756 ret = pp_check(pp_handle);
761 hwmgr = pp_handle->hwmgr;
763 if (!hwmgr->soft_pp_table)
766 mutex_lock(&pp_handle->pp_lock);
767 *table = (char *)hwmgr->soft_pp_table;
768 size = hwmgr->soft_pp_table_size;
769 mutex_unlock(&pp_handle->pp_lock);
773 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
775 struct pp_hwmgr *hwmgr;
776 struct pp_instance *pp_handle = (struct pp_instance *)handle;
779 ret = pp_check(pp_handle);
784 hwmgr = pp_handle->hwmgr;
785 mutex_lock(&pp_handle->pp_lock);
786 if (!hwmgr->hardcode_pp_table) {
787 hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
788 hwmgr->soft_pp_table_size,
790 if (!hwmgr->hardcode_pp_table) {
791 mutex_unlock(&pp_handle->pp_lock);
796 memcpy(hwmgr->hardcode_pp_table, buf, size);
798 hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
799 mutex_unlock(&pp_handle->pp_lock);
801 ret = amd_powerplay_reset(handle);
805 if (hwmgr->hwmgr_func->avfs_control) {
806 ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
814 static int pp_dpm_force_clock_level(void *handle,
815 enum pp_clock_type type, uint32_t mask)
817 struct pp_hwmgr *hwmgr;
818 struct pp_instance *pp_handle = (struct pp_instance *)handle;
821 ret = pp_check(pp_handle);
826 hwmgr = pp_handle->hwmgr;
828 if (hwmgr->hwmgr_func->force_clock_level == NULL) {
829 pr_info("%s was not implemented.\n", __func__);
832 mutex_lock(&pp_handle->pp_lock);
833 hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
834 mutex_unlock(&pp_handle->pp_lock);
838 static int pp_dpm_print_clock_levels(void *handle,
839 enum pp_clock_type type, char *buf)
841 struct pp_hwmgr *hwmgr;
842 struct pp_instance *pp_handle = (struct pp_instance *)handle;
845 ret = pp_check(pp_handle);
850 hwmgr = pp_handle->hwmgr;
852 if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
853 pr_info("%s was not implemented.\n", __func__);
856 mutex_lock(&pp_handle->pp_lock);
857 ret = hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
858 mutex_unlock(&pp_handle->pp_lock);
862 static int pp_dpm_get_sclk_od(void *handle)
864 struct pp_hwmgr *hwmgr;
865 struct pp_instance *pp_handle = (struct pp_instance *)handle;
868 ret = pp_check(pp_handle);
873 hwmgr = pp_handle->hwmgr;
875 if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
876 pr_info("%s was not implemented.\n", __func__);
879 mutex_lock(&pp_handle->pp_lock);
880 ret = hwmgr->hwmgr_func->get_sclk_od(hwmgr);
881 mutex_unlock(&pp_handle->pp_lock);
885 static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
887 struct pp_hwmgr *hwmgr;
888 struct pp_instance *pp_handle = (struct pp_instance *)handle;
891 ret = pp_check(pp_handle);
896 hwmgr = pp_handle->hwmgr;
898 if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
899 pr_info("%s was not implemented.\n", __func__);
903 mutex_lock(&pp_handle->pp_lock);
904 ret = hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
905 mutex_unlock(&pp_handle->pp_lock);
909 static int pp_dpm_get_mclk_od(void *handle)
911 struct pp_hwmgr *hwmgr;
912 struct pp_instance *pp_handle = (struct pp_instance *)handle;
915 ret = pp_check(pp_handle);
920 hwmgr = pp_handle->hwmgr;
922 if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
923 pr_info("%s was not implemented.\n", __func__);
926 mutex_lock(&pp_handle->pp_lock);
927 ret = hwmgr->hwmgr_func->get_mclk_od(hwmgr);
928 mutex_unlock(&pp_handle->pp_lock);
932 static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
934 struct pp_hwmgr *hwmgr;
935 struct pp_instance *pp_handle = (struct pp_instance *)handle;
938 ret = pp_check(pp_handle);
943 hwmgr = pp_handle->hwmgr;
945 if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
946 pr_info("%s was not implemented.\n", __func__);
949 mutex_lock(&pp_handle->pp_lock);
950 ret = hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
951 mutex_unlock(&pp_handle->pp_lock);
955 static int pp_dpm_read_sensor(void *handle, int idx,
956 void *value, int *size)
958 struct pp_hwmgr *hwmgr;
959 struct pp_instance *pp_handle = (struct pp_instance *)handle;
962 ret = pp_check(pp_handle);
967 hwmgr = pp_handle->hwmgr;
969 if (hwmgr->hwmgr_func->read_sensor == NULL) {
970 pr_info("%s was not implemented.\n", __func__);
974 mutex_lock(&pp_handle->pp_lock);
975 ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
976 mutex_unlock(&pp_handle->pp_lock);
981 static struct amd_vce_state*
982 pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
984 struct pp_hwmgr *hwmgr;
985 struct pp_instance *pp_handle = (struct pp_instance *)handle;
988 ret = pp_check(pp_handle);
993 hwmgr = pp_handle->hwmgr;
995 if (hwmgr && idx < hwmgr->num_vce_state_tables)
996 return &hwmgr->vce_states[idx];
1000 static int pp_dpm_reset_power_profile_state(void *handle,
1001 struct amd_pp_profile *request)
1003 struct pp_hwmgr *hwmgr;
1004 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1006 if (!request || pp_check(pp_handle))
1009 hwmgr = pp_handle->hwmgr;
1011 if (hwmgr->hwmgr_func->set_power_profile_state == NULL) {
1012 pr_info("%s was not implemented.\n", __func__);
1016 if (request->type == AMD_PP_GFX_PROFILE) {
1017 hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
1018 return hwmgr->hwmgr_func->set_power_profile_state(hwmgr,
1019 &hwmgr->gfx_power_profile);
1020 } else if (request->type == AMD_PP_COMPUTE_PROFILE) {
1021 hwmgr->compute_power_profile =
1022 hwmgr->default_compute_power_profile;
1023 return hwmgr->hwmgr_func->set_power_profile_state(hwmgr,
1024 &hwmgr->compute_power_profile);
1029 static int pp_dpm_get_power_profile_state(void *handle,
1030 struct amd_pp_profile *query)
1032 struct pp_hwmgr *hwmgr;
1033 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1035 if (!query || pp_check(pp_handle))
1038 hwmgr = pp_handle->hwmgr;
1040 if (query->type == AMD_PP_GFX_PROFILE)
1041 memcpy(query, &hwmgr->gfx_power_profile,
1042 sizeof(struct amd_pp_profile));
1043 else if (query->type == AMD_PP_COMPUTE_PROFILE)
1044 memcpy(query, &hwmgr->compute_power_profile,
1045 sizeof(struct amd_pp_profile));
1052 static int pp_dpm_set_power_profile_state(void *handle,
1053 struct amd_pp_profile *request)
1055 struct pp_hwmgr *hwmgr;
1056 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1059 if (!request || pp_check(pp_handle))
1062 hwmgr = pp_handle->hwmgr;
1064 if (hwmgr->hwmgr_func->set_power_profile_state == NULL) {
1065 pr_info("%s was not implemented.\n", __func__);
1069 if (request->min_sclk ||
1070 request->min_mclk ||
1071 request->activity_threshold ||
1073 request->down_hyst) {
1074 if (request->type == AMD_PP_GFX_PROFILE)
1075 memcpy(&hwmgr->gfx_power_profile, request,
1076 sizeof(struct amd_pp_profile));
1077 else if (request->type == AMD_PP_COMPUTE_PROFILE)
1078 memcpy(&hwmgr->compute_power_profile, request,
1079 sizeof(struct amd_pp_profile));
1083 if (request->type == hwmgr->current_power_profile)
1084 ret = hwmgr->hwmgr_func->set_power_profile_state(
1088 /* set power profile if it exists */
1089 switch (request->type) {
1090 case AMD_PP_GFX_PROFILE:
1091 ret = hwmgr->hwmgr_func->set_power_profile_state(
1093 &hwmgr->gfx_power_profile);
1095 case AMD_PP_COMPUTE_PROFILE:
1096 ret = hwmgr->hwmgr_func->set_power_profile_state(
1098 &hwmgr->compute_power_profile);
1106 hwmgr->current_power_profile = request->type;
1111 static int pp_dpm_switch_power_profile(void *handle,
1112 enum amd_pp_profile_type type)
1114 struct pp_hwmgr *hwmgr;
1115 struct amd_pp_profile request = {0};
1116 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1118 if (pp_check(pp_handle))
1121 hwmgr = pp_handle->hwmgr;
1123 if (hwmgr->current_power_profile != type) {
1124 request.type = type;
1125 pp_dpm_set_power_profile_state(handle, &request);
1131 const struct amd_powerplay_funcs pp_dpm_funcs = {
1132 .get_temperature = pp_dpm_get_temperature,
1133 .load_firmware = pp_dpm_load_fw,
1134 .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
1135 .force_performance_level = pp_dpm_force_performance_level,
1136 .get_performance_level = pp_dpm_get_performance_level,
1137 .get_current_power_state = pp_dpm_get_current_power_state,
1138 .get_sclk = pp_dpm_get_sclk,
1139 .get_mclk = pp_dpm_get_mclk,
1140 .powergate_vce = pp_dpm_powergate_vce,
1141 .powergate_uvd = pp_dpm_powergate_uvd,
1142 .dispatch_tasks = pp_dpm_dispatch_tasks,
1143 .set_fan_control_mode = pp_dpm_set_fan_control_mode,
1144 .get_fan_control_mode = pp_dpm_get_fan_control_mode,
1145 .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
1146 .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
1147 .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
1148 .get_pp_num_states = pp_dpm_get_pp_num_states,
1149 .get_pp_table = pp_dpm_get_pp_table,
1150 .set_pp_table = pp_dpm_set_pp_table,
1151 .force_clock_level = pp_dpm_force_clock_level,
1152 .print_clock_levels = pp_dpm_print_clock_levels,
1153 .get_sclk_od = pp_dpm_get_sclk_od,
1154 .set_sclk_od = pp_dpm_set_sclk_od,
1155 .get_mclk_od = pp_dpm_get_mclk_od,
1156 .set_mclk_od = pp_dpm_set_mclk_od,
1157 .read_sensor = pp_dpm_read_sensor,
1158 .get_vce_clock_state = pp_dpm_get_vce_clock_state,
1159 .reset_power_profile_state = pp_dpm_reset_power_profile_state,
1160 .get_power_profile_state = pp_dpm_get_power_profile_state,
1161 .set_power_profile_state = pp_dpm_set_power_profile_state,
1162 .switch_power_profile = pp_dpm_switch_power_profile,
1165 int amd_powerplay_create(struct amd_pp_init *pp_init,
1168 struct pp_instance *instance;
1170 if (pp_init == NULL || handle == NULL)
1173 instance = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
1174 if (instance == NULL)
1177 instance->pp_valid = PP_VALID;
1178 instance->chip_family = pp_init->chip_family;
1179 instance->chip_id = pp_init->chip_id;
1180 instance->pm_en = pp_init->pm_en;
1181 instance->feature_mask = pp_init->feature_mask;
1182 instance->device = pp_init->device;
1183 mutex_init(&instance->pp_lock);
1188 int amd_powerplay_destroy(void *handle)
1190 struct pp_instance *instance = (struct pp_instance *)handle;
1192 if (instance->pm_en) {
1193 kfree(instance->eventmgr);
1194 kfree(instance->hwmgr);
1195 instance->hwmgr = NULL;
1196 instance->eventmgr = NULL;
1199 kfree(instance->smu_mgr);
1200 instance->smu_mgr = NULL;
1206 int amd_powerplay_reset(void *handle)
1208 struct pp_instance *instance = (struct pp_instance *)handle;
1209 struct pp_eventmgr *eventmgr;
1210 struct pem_event_data event_data = { {0} };
1213 if (cgs_is_virtualization_enabled(instance->smu_mgr->device))
1214 return PP_DPM_DISABLED;
1216 ret = pp_check(instance);
1220 ret = pp_hw_fini(handle);
1224 ret = hwmgr_hw_init(instance);
1226 return PP_DPM_DISABLED;
1228 eventmgr = instance->eventmgr;
1230 if (eventmgr->pp_eventmgr_init == NULL)
1231 return PP_DPM_DISABLED;
1233 ret = eventmgr->pp_eventmgr_init(eventmgr);
1237 return pem_handle_event(eventmgr, AMD_PP_EVENT_COMPLETE_INIT, &event_data);
1240 /* export this function to DAL */
1242 int amd_powerplay_display_configuration_change(void *handle,
1243 const struct amd_pp_display_configuration *display_config)
1245 struct pp_hwmgr *hwmgr;
1246 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1249 ret = pp_check(pp_handle);
1254 hwmgr = pp_handle->hwmgr;
1255 mutex_lock(&pp_handle->pp_lock);
1256 phm_store_dal_configuration_data(hwmgr, display_config);
1257 mutex_unlock(&pp_handle->pp_lock);
1261 int amd_powerplay_get_display_power_level(void *handle,
1262 struct amd_pp_simple_clock_info *output)
1264 struct pp_hwmgr *hwmgr;
1265 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1268 ret = pp_check(pp_handle);
1273 hwmgr = pp_handle->hwmgr;
1278 mutex_lock(&pp_handle->pp_lock);
1279 ret = phm_get_dal_power_level(hwmgr, output);
1280 mutex_unlock(&pp_handle->pp_lock);
1284 int amd_powerplay_get_current_clocks(void *handle,
1285 struct amd_pp_clock_info *clocks)
1287 struct amd_pp_simple_clock_info simple_clocks;
1288 struct pp_clock_info hw_clocks;
1289 struct pp_hwmgr *hwmgr;
1290 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1293 ret = pp_check(pp_handle);
1298 hwmgr = pp_handle->hwmgr;
1300 mutex_lock(&pp_handle->pp_lock);
1302 phm_get_dal_power_level(hwmgr, &simple_clocks);
1304 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1305 PHM_PlatformCaps_PowerContainment))
1306 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1307 &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment);
1309 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1310 &hw_clocks, PHM_PerformanceLevelDesignation_Activity);
1313 pr_info("Error in phm_get_clock_info \n");
1314 mutex_unlock(&pp_handle->pp_lock);
1318 clocks->min_engine_clock = hw_clocks.min_eng_clk;
1319 clocks->max_engine_clock = hw_clocks.max_eng_clk;
1320 clocks->min_memory_clock = hw_clocks.min_mem_clk;
1321 clocks->max_memory_clock = hw_clocks.max_mem_clk;
1322 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1323 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1325 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1326 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1328 clocks->max_clocks_state = simple_clocks.level;
1330 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
1331 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1332 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1334 mutex_unlock(&pp_handle->pp_lock);
1338 int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
1340 struct pp_hwmgr *hwmgr;
1341 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1344 ret = pp_check(pp_handle);
1349 hwmgr = pp_handle->hwmgr;
1354 mutex_lock(&pp_handle->pp_lock);
1355 ret = phm_get_clock_by_type(hwmgr, type, clocks);
1356 mutex_unlock(&pp_handle->pp_lock);
1360 int amd_powerplay_get_clock_by_type_with_latency(void *handle,
1361 enum amd_pp_clock_type type,
1362 struct pp_clock_levels_with_latency *clocks)
1364 struct pp_hwmgr *hwmgr;
1365 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1368 ret = pp_check(pp_handle);
1375 mutex_lock(&pp_handle->pp_lock);
1376 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1377 ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
1378 mutex_unlock(&pp_handle->pp_lock);
1382 int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
1383 enum amd_pp_clock_type type,
1384 struct pp_clock_levels_with_voltage *clocks)
1386 struct pp_hwmgr *hwmgr;
1387 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1390 ret = pp_check(pp_handle);
1397 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1399 mutex_lock(&pp_handle->pp_lock);
1401 ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
1403 mutex_unlock(&pp_handle->pp_lock);
1407 int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
1408 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
1410 struct pp_hwmgr *hwmgr;
1411 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1414 ret = pp_check(pp_handle);
1418 if (!wm_with_clock_ranges)
1421 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1423 mutex_lock(&pp_handle->pp_lock);
1424 ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
1425 wm_with_clock_ranges);
1426 mutex_unlock(&pp_handle->pp_lock);
1431 int amd_powerplay_display_clock_voltage_request(void *handle,
1432 struct pp_display_clock_request *clock)
1434 struct pp_hwmgr *hwmgr;
1435 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1438 ret = pp_check(pp_handle);
1445 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1447 mutex_lock(&pp_handle->pp_lock);
1448 ret = phm_display_clock_voltage_request(hwmgr, clock);
1449 mutex_unlock(&pp_handle->pp_lock);
1454 int amd_powerplay_get_display_mode_validation_clocks(void *handle,
1455 struct amd_pp_simple_clock_info *clocks)
1457 struct pp_hwmgr *hwmgr;
1458 struct pp_instance *pp_handle = (struct pp_instance *)handle;
1461 ret = pp_check(pp_handle);
1466 hwmgr = pp_handle->hwmgr;
1471 mutex_lock(&pp_handle->pp_lock);
1473 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1474 ret = phm_get_max_high_clocks(hwmgr, clocks);
1476 mutex_unlock(&pp_handle->pp_lock);