2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/gfp.h>
26 #include <linux/slab.h>
27 #include "amd_shared.h"
28 #include "amd_powerplay.h"
29 #include "pp_instance.h"
30 #include "power_state.h"
31 #include "eventmanager.h"
35 #define PP_CHECK(handle) \
37 if ((handle) == NULL || (handle)->pp_valid != PP_VALID) \
41 #define PP_CHECK_HW(hwmgr) \
43 if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \
47 static int pp_early_init(void *handle)
52 static int pp_sw_init(void *handle)
54 struct pp_instance *pp_handle;
55 struct pp_hwmgr *hwmgr;
61 pp_handle = (struct pp_instance *)handle;
62 hwmgr = pp_handle->hwmgr;
66 if (hwmgr->pptable_func == NULL ||
67 hwmgr->pptable_func->pptable_init == NULL ||
68 hwmgr->hwmgr_func->backend_init == NULL)
71 ret = hwmgr->pptable_func->pptable_init(hwmgr);
75 ret = hwmgr->hwmgr_func->backend_init(hwmgr);
79 pr_info("amdgpu: powerplay initialized\n");
83 if (hwmgr->pptable_func->pptable_fini)
84 hwmgr->pptable_func->pptable_fini(hwmgr);
86 pr_err("amdgpu: powerplay initialization failed\n");
90 static int pp_sw_fini(void *handle)
92 struct pp_instance *pp_handle;
93 struct pp_hwmgr *hwmgr;
99 pp_handle = (struct pp_instance *)handle;
100 hwmgr = pp_handle->hwmgr;
104 if (hwmgr->hwmgr_func->backend_fini != NULL)
105 ret = hwmgr->hwmgr_func->backend_fini(hwmgr);
107 if (hwmgr->pptable_func->pptable_fini)
108 hwmgr->pptable_func->pptable_fini(hwmgr);
113 static int pp_hw_init(void *handle)
115 struct pp_instance *pp_handle;
116 struct pp_smumgr *smumgr;
117 struct pp_eventmgr *eventmgr;
123 pp_handle = (struct pp_instance *)handle;
124 smumgr = pp_handle->smu_mgr;
126 if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
127 smumgr->smumgr_funcs->smu_init == NULL ||
128 smumgr->smumgr_funcs->start_smu == NULL)
131 ret = smumgr->smumgr_funcs->smu_init(smumgr);
133 printk(KERN_ERR "[ powerplay ] smc initialization failed\n");
137 ret = smumgr->smumgr_funcs->start_smu(smumgr);
139 printk(KERN_ERR "[ powerplay ] smc start failed\n");
140 smumgr->smumgr_funcs->smu_fini(smumgr);
144 hw_init_power_state_table(pp_handle->hwmgr);
145 eventmgr = pp_handle->eventmgr;
147 if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
150 ret = eventmgr->pp_eventmgr_init(eventmgr);
154 static int pp_hw_fini(void *handle)
156 struct pp_instance *pp_handle;
157 struct pp_smumgr *smumgr;
158 struct pp_eventmgr *eventmgr;
163 pp_handle = (struct pp_instance *)handle;
164 eventmgr = pp_handle->eventmgr;
166 if (eventmgr != NULL && eventmgr->pp_eventmgr_fini != NULL)
167 eventmgr->pp_eventmgr_fini(eventmgr);
169 smumgr = pp_handle->smu_mgr;
171 if (smumgr != NULL && smumgr->smumgr_funcs != NULL &&
172 smumgr->smumgr_funcs->smu_fini != NULL)
173 smumgr->smumgr_funcs->smu_fini(smumgr);
178 static bool pp_is_idle(void *handle)
183 static int pp_wait_for_idle(void *handle)
188 static int pp_sw_reset(void *handle)
194 int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id)
196 struct pp_hwmgr *hwmgr;
201 hwmgr = ((struct pp_instance *)handle)->hwmgr;
205 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
206 printk(KERN_INFO "%s was not implemented.\n", __func__);
210 return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
213 static int pp_set_powergating_state(void *handle,
214 enum amd_powergating_state state)
216 struct pp_hwmgr *hwmgr;
221 hwmgr = ((struct pp_instance *)handle)->hwmgr;
225 if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
226 printk(KERN_INFO "%s was not implemented.\n", __func__);
230 /* Enable/disable GFX per cu powergating through SMU */
231 return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
232 state == AMD_PG_STATE_GATE ? true : false);
235 static int pp_suspend(void *handle)
237 struct pp_instance *pp_handle;
238 struct pp_eventmgr *eventmgr;
239 struct pem_event_data event_data = { {0} };
244 pp_handle = (struct pp_instance *)handle;
245 eventmgr = pp_handle->eventmgr;
246 pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data);
250 static int pp_resume(void *handle)
252 struct pp_instance *pp_handle;
253 struct pp_eventmgr *eventmgr;
254 struct pem_event_data event_data = { {0} };
255 struct pp_smumgr *smumgr;
261 pp_handle = (struct pp_instance *)handle;
262 smumgr = pp_handle->smu_mgr;
264 if (smumgr == NULL || smumgr->smumgr_funcs == NULL ||
265 smumgr->smumgr_funcs->start_smu == NULL)
268 ret = smumgr->smumgr_funcs->start_smu(smumgr);
270 printk(KERN_ERR "[ powerplay ] smc start failed\n");
271 smumgr->smumgr_funcs->smu_fini(smumgr);
275 eventmgr = pp_handle->eventmgr;
276 pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data);
281 const struct amd_ip_funcs pp_ip_funcs = {
283 .early_init = pp_early_init,
285 .sw_init = pp_sw_init,
286 .sw_fini = pp_sw_fini,
287 .hw_init = pp_hw_init,
288 .hw_fini = pp_hw_fini,
289 .suspend = pp_suspend,
291 .is_idle = pp_is_idle,
292 .wait_for_idle = pp_wait_for_idle,
293 .soft_reset = pp_sw_reset,
294 .set_clockgating_state = NULL,
295 .set_powergating_state = pp_set_powergating_state,
298 static int pp_dpm_load_fw(void *handle)
303 static int pp_dpm_fw_loading_complete(void *handle)
308 static int pp_dpm_force_performance_level(void *handle,
309 enum amd_dpm_forced_level level)
311 struct pp_instance *pp_handle;
312 struct pp_hwmgr *hwmgr;
317 pp_handle = (struct pp_instance *)handle;
319 hwmgr = pp_handle->hwmgr;
323 if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
324 printk(KERN_INFO "%s was not implemented.\n", __func__);
328 hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
333 static enum amd_dpm_forced_level pp_dpm_get_performance_level(
336 struct pp_hwmgr *hwmgr;
341 hwmgr = ((struct pp_instance *)handle)->hwmgr;
346 return (((struct pp_instance *)handle)->hwmgr->dpm_level);
349 static int pp_dpm_get_sclk(void *handle, bool low)
351 struct pp_hwmgr *hwmgr;
356 hwmgr = ((struct pp_instance *)handle)->hwmgr;
360 if (hwmgr->hwmgr_func->get_sclk == NULL) {
361 printk(KERN_INFO "%s was not implemented.\n", __func__);
365 return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
368 static int pp_dpm_get_mclk(void *handle, bool low)
370 struct pp_hwmgr *hwmgr;
375 hwmgr = ((struct pp_instance *)handle)->hwmgr;
379 if (hwmgr->hwmgr_func->get_mclk == NULL) {
380 printk(KERN_INFO "%s was not implemented.\n", __func__);
384 return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
387 static int pp_dpm_powergate_vce(void *handle, bool gate)
389 struct pp_hwmgr *hwmgr;
394 hwmgr = ((struct pp_instance *)handle)->hwmgr;
398 if (hwmgr->hwmgr_func->powergate_vce == NULL) {
399 printk(KERN_INFO "%s was not implemented.\n", __func__);
403 return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
406 static int pp_dpm_powergate_uvd(void *handle, bool gate)
408 struct pp_hwmgr *hwmgr;
413 hwmgr = ((struct pp_instance *)handle)->hwmgr;
417 if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
418 printk(KERN_INFO "%s was not implemented.\n", __func__);
422 return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
425 static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state)
428 case POWER_STATE_TYPE_BATTERY:
429 return PP_StateUILabel_Battery;
430 case POWER_STATE_TYPE_BALANCED:
431 return PP_StateUILabel_Balanced;
432 case POWER_STATE_TYPE_PERFORMANCE:
433 return PP_StateUILabel_Performance;
435 return PP_StateUILabel_None;
439 int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output)
442 struct pp_instance *pp_handle;
443 struct pem_event_data data = { {0} };
445 pp_handle = (struct pp_instance *)handle;
447 if (pp_handle == NULL)
451 case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE:
452 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
454 case AMD_PP_EVENT_ENABLE_USER_STATE:
456 enum amd_pm_state_type ps;
460 ps = *(unsigned long *)input;
462 data.requested_ui_label = power_state_convert(ps);
463 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
466 case AMD_PP_EVENT_COMPLETE_INIT:
467 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
469 case AMD_PP_EVENT_READJUST_POWER_STATE:
470 ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
478 enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
480 struct pp_hwmgr *hwmgr;
481 struct pp_power_state *state;
486 hwmgr = ((struct pp_instance *)handle)->hwmgr;
488 if (hwmgr == NULL || hwmgr->current_ps == NULL)
491 state = hwmgr->current_ps;
493 switch (state->classification.ui_label) {
494 case PP_StateUILabel_Battery:
495 return POWER_STATE_TYPE_BATTERY;
496 case PP_StateUILabel_Balanced:
497 return POWER_STATE_TYPE_BALANCED;
498 case PP_StateUILabel_Performance:
499 return POWER_STATE_TYPE_PERFORMANCE;
501 if (state->classification.flags & PP_StateClassificationFlag_Boot)
502 return POWER_STATE_TYPE_INTERNAL_BOOT;
504 return POWER_STATE_TYPE_DEFAULT;
508 static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
510 struct pp_hwmgr *hwmgr;
515 hwmgr = ((struct pp_instance *)handle)->hwmgr;
519 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
520 printk(KERN_INFO "%s was not implemented.\n", __func__);
524 return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
527 static int pp_dpm_get_fan_control_mode(void *handle)
529 struct pp_hwmgr *hwmgr;
534 hwmgr = ((struct pp_instance *)handle)->hwmgr;
538 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
539 printk(KERN_INFO "%s was not implemented.\n", __func__);
543 return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
546 static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
548 struct pp_hwmgr *hwmgr;
553 hwmgr = ((struct pp_instance *)handle)->hwmgr;
557 if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
558 printk(KERN_INFO "%s was not implemented.\n", __func__);
562 return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
565 static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
567 struct pp_hwmgr *hwmgr;
572 hwmgr = ((struct pp_instance *)handle)->hwmgr;
576 if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
577 printk(KERN_INFO "%s was not implemented.\n", __func__);
581 return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
584 static int pp_dpm_get_temperature(void *handle)
586 struct pp_hwmgr *hwmgr;
591 hwmgr = ((struct pp_instance *)handle)->hwmgr;
595 if (hwmgr->hwmgr_func->get_temperature == NULL) {
596 printk(KERN_INFO "%s was not implemented.\n", __func__);
600 return hwmgr->hwmgr_func->get_temperature(hwmgr);
603 static int pp_dpm_get_pp_num_states(void *handle,
604 struct pp_states_info *data)
606 struct pp_hwmgr *hwmgr;
612 hwmgr = ((struct pp_instance *)handle)->hwmgr;
614 if (hwmgr == NULL || hwmgr->ps == NULL)
617 data->nums = hwmgr->num_ps;
619 for (i = 0; i < hwmgr->num_ps; i++) {
620 struct pp_power_state *state = (struct pp_power_state *)
621 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
622 switch (state->classification.ui_label) {
623 case PP_StateUILabel_Battery:
624 data->states[i] = POWER_STATE_TYPE_BATTERY;
626 case PP_StateUILabel_Balanced:
627 data->states[i] = POWER_STATE_TYPE_BALANCED;
629 case PP_StateUILabel_Performance:
630 data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
633 if (state->classification.flags & PP_StateClassificationFlag_Boot)
634 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
636 data->states[i] = POWER_STATE_TYPE_DEFAULT;
643 static int pp_dpm_get_pp_table(void *handle, char **table)
645 struct pp_hwmgr *hwmgr;
650 hwmgr = ((struct pp_instance *)handle)->hwmgr;
654 if (!hwmgr->soft_pp_table)
657 *table = (char *)hwmgr->soft_pp_table;
659 return hwmgr->soft_pp_table_size;
662 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
664 struct pp_hwmgr *hwmgr;
669 hwmgr = ((struct pp_instance *)handle)->hwmgr;
673 if (!hwmgr->hardcode_pp_table) {
674 hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
675 hwmgr->soft_pp_table_size,
678 if (!hwmgr->hardcode_pp_table)
682 memcpy(hwmgr->hardcode_pp_table, buf, size);
684 hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
686 return amd_powerplay_reset(handle);
689 static int pp_dpm_force_clock_level(void *handle,
690 enum pp_clock_type type, uint32_t mask)
692 struct pp_hwmgr *hwmgr;
697 hwmgr = ((struct pp_instance *)handle)->hwmgr;
701 if (hwmgr->hwmgr_func->force_clock_level == NULL) {
702 printk(KERN_INFO "%s was not implemented.\n", __func__);
706 return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
709 static int pp_dpm_print_clock_levels(void *handle,
710 enum pp_clock_type type, char *buf)
712 struct pp_hwmgr *hwmgr;
717 hwmgr = ((struct pp_instance *)handle)->hwmgr;
721 if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
722 printk(KERN_INFO "%s was not implemented.\n", __func__);
725 return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
728 static int pp_dpm_get_sclk_od(void *handle)
730 struct pp_hwmgr *hwmgr;
735 hwmgr = ((struct pp_instance *)handle)->hwmgr;
739 if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
740 printk(KERN_INFO "%s was not implemented.\n", __func__);
744 return hwmgr->hwmgr_func->get_sclk_od(hwmgr);
747 static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
749 struct pp_hwmgr *hwmgr;
754 hwmgr = ((struct pp_instance *)handle)->hwmgr;
758 if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
759 printk(KERN_INFO "%s was not implemented.\n", __func__);
763 return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
766 static int pp_dpm_get_mclk_od(void *handle)
768 struct pp_hwmgr *hwmgr;
773 hwmgr = ((struct pp_instance *)handle)->hwmgr;
777 if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
778 printk(KERN_INFO "%s was not implemented.\n", __func__);
782 return hwmgr->hwmgr_func->get_mclk_od(hwmgr);
785 static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
787 struct pp_hwmgr *hwmgr;
792 hwmgr = ((struct pp_instance *)handle)->hwmgr;
796 if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
797 printk(KERN_INFO "%s was not implemented.\n", __func__);
801 return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
804 static int pp_dpm_read_sensor(void *handle, int idx, int32_t *value)
806 struct pp_hwmgr *hwmgr;
811 hwmgr = ((struct pp_instance *)handle)->hwmgr;
815 if (hwmgr->hwmgr_func->read_sensor == NULL) {
816 printk(KERN_INFO "%s was not implemented.\n", __func__);
820 return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value);
823 const struct amd_powerplay_funcs pp_dpm_funcs = {
824 .get_temperature = pp_dpm_get_temperature,
825 .load_firmware = pp_dpm_load_fw,
826 .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
827 .force_performance_level = pp_dpm_force_performance_level,
828 .get_performance_level = pp_dpm_get_performance_level,
829 .get_current_power_state = pp_dpm_get_current_power_state,
830 .get_sclk = pp_dpm_get_sclk,
831 .get_mclk = pp_dpm_get_mclk,
832 .powergate_vce = pp_dpm_powergate_vce,
833 .powergate_uvd = pp_dpm_powergate_uvd,
834 .dispatch_tasks = pp_dpm_dispatch_tasks,
835 .set_fan_control_mode = pp_dpm_set_fan_control_mode,
836 .get_fan_control_mode = pp_dpm_get_fan_control_mode,
837 .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
838 .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
839 .get_pp_num_states = pp_dpm_get_pp_num_states,
840 .get_pp_table = pp_dpm_get_pp_table,
841 .set_pp_table = pp_dpm_set_pp_table,
842 .force_clock_level = pp_dpm_force_clock_level,
843 .print_clock_levels = pp_dpm_print_clock_levels,
844 .get_sclk_od = pp_dpm_get_sclk_od,
845 .set_sclk_od = pp_dpm_set_sclk_od,
846 .get_mclk_od = pp_dpm_get_mclk_od,
847 .set_mclk_od = pp_dpm_set_mclk_od,
848 .read_sensor = pp_dpm_read_sensor,
851 static int amd_pp_instance_init(struct amd_pp_init *pp_init,
852 struct amd_powerplay *amd_pp)
855 struct pp_instance *handle;
857 handle = kzalloc(sizeof(struct pp_instance), GFP_KERNEL);
861 handle->pp_valid = PP_VALID;
863 ret = smum_init(pp_init, handle);
867 ret = hwmgr_init(pp_init, handle);
871 ret = eventmgr_init(handle);
875 amd_pp->pp_handle = handle;
879 hwmgr_fini(handle->hwmgr);
881 smum_fini(handle->smu_mgr);
887 static int amd_pp_instance_fini(void *handle)
889 struct pp_instance *instance = (struct pp_instance *)handle;
891 if (instance == NULL)
894 eventmgr_fini(instance->eventmgr);
896 hwmgr_fini(instance->hwmgr);
898 smum_fini(instance->smu_mgr);
904 int amd_powerplay_init(struct amd_pp_init *pp_init,
905 struct amd_powerplay *amd_pp)
909 if (pp_init == NULL || amd_pp == NULL)
912 ret = amd_pp_instance_init(pp_init, amd_pp);
917 amd_pp->ip_funcs = &pp_ip_funcs;
918 amd_pp->pp_funcs = &pp_dpm_funcs;
923 int amd_powerplay_fini(void *handle)
925 amd_pp_instance_fini(handle);
930 int amd_powerplay_reset(void *handle)
932 struct pp_instance *instance = (struct pp_instance *)handle;
933 struct pp_eventmgr *eventmgr;
934 struct pem_event_data event_data = { {0} };
937 if (instance == NULL)
940 eventmgr = instance->eventmgr;
941 if (!eventmgr || !eventmgr->pp_eventmgr_fini)
944 eventmgr->pp_eventmgr_fini(eventmgr);
946 ret = pp_sw_fini(handle);
950 kfree(instance->hwmgr->ps);
952 ret = pp_sw_init(handle);
956 hw_init_power_state_table(instance->hwmgr);
958 if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
961 ret = eventmgr->pp_eventmgr_init(eventmgr);
965 return pem_handle_event(eventmgr, AMD_PP_EVENT_COMPLETE_INIT, &event_data);
968 /* export this function to DAL */
970 int amd_powerplay_display_configuration_change(void *handle,
971 const struct amd_pp_display_configuration *display_config)
973 struct pp_hwmgr *hwmgr;
975 PP_CHECK((struct pp_instance *)handle);
977 hwmgr = ((struct pp_instance *)handle)->hwmgr;
979 phm_store_dal_configuration_data(hwmgr, display_config);
984 int amd_powerplay_get_display_power_level(void *handle,
985 struct amd_pp_simple_clock_info *output)
987 struct pp_hwmgr *hwmgr;
989 PP_CHECK((struct pp_instance *)handle);
994 hwmgr = ((struct pp_instance *)handle)->hwmgr;
996 return phm_get_dal_power_level(hwmgr, output);
999 int amd_powerplay_get_current_clocks(void *handle,
1000 struct amd_pp_clock_info *clocks)
1002 struct pp_hwmgr *hwmgr;
1003 struct amd_pp_simple_clock_info simple_clocks;
1004 struct pp_clock_info hw_clocks;
1006 PP_CHECK((struct pp_instance *)handle);
1011 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1013 phm_get_dal_power_level(hwmgr, &simple_clocks);
1015 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) {
1016 if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment))
1017 PP_ASSERT_WITH_CODE(0, "Error in PHM_GetPowerContainmentClockInfo", return -1);
1019 if (0 != phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks, PHM_PerformanceLevelDesignation_Activity))
1020 PP_ASSERT_WITH_CODE(0, "Error in PHM_GetClockInfo", return -1);
1023 clocks->min_engine_clock = hw_clocks.min_eng_clk;
1024 clocks->max_engine_clock = hw_clocks.max_eng_clk;
1025 clocks->min_memory_clock = hw_clocks.min_mem_clk;
1026 clocks->max_memory_clock = hw_clocks.max_mem_clk;
1027 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1028 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1030 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1031 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1033 clocks->max_clocks_state = simple_clocks.level;
1035 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
1036 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1037 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1044 int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
1048 struct pp_hwmgr *hwmgr;
1050 PP_CHECK((struct pp_instance *)handle);
1055 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1057 result = phm_get_clock_by_type(hwmgr, type, clocks);
1062 int amd_powerplay_get_display_mode_validation_clocks(void *handle,
1063 struct amd_pp_simple_clock_info *clocks)
1066 struct pp_hwmgr *hwmgr;
1068 PP_CHECK((struct pp_instance *)handle);
1073 hwmgr = ((struct pp_instance *)handle)->hwmgr;
1075 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1076 result = phm_get_max_high_clocks(hwmgr, clocks);