2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "amd_shared.h"
32 * enum cgs_gpu_mem_type - GPU memory types
34 enum cgs_gpu_mem_type {
35 CGS_GPU_MEM_TYPE__VISIBLE_FB,
36 CGS_GPU_MEM_TYPE__INVISIBLE_FB,
37 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
38 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB,
39 CGS_GPU_MEM_TYPE__GART_CACHEABLE,
40 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
44 * enum cgs_ind_reg - Indirect register spaces
53 CGS_IND_REG__AUDIO_ENDPT
57 * enum cgs_clock - Clocks controlled by the SMU
71 * enum cgs_engine - Engines that can be statically power-gated
85 * enum cgs_voltage_planes - Voltage planes for external camera HW
87 enum cgs_voltage_planes {
88 CGS_VOLTAGE_PLANE__SENSOR0,
89 CGS_VOLTAGE_PLANE__SENSOR1,
94 * enum cgs_ucode_id - Firmware types for different IPs
105 CGS_UCODE_ID_CP_MEC_JT1,
106 CGS_UCODE_ID_CP_MEC_JT2,
107 CGS_UCODE_ID_GMCON_RENG,
109 CGS_UCODE_ID_MAXIMUM,
112 enum cgs_system_info_id {
113 CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
114 CGS_SYSTEM_INFO_PCIE_GEN_INFO,
115 CGS_SYSTEM_INFO_PCIE_MLW,
116 CGS_SYSTEM_INFO_PCIE_DEV,
117 CGS_SYSTEM_INFO_PCIE_REV,
118 CGS_SYSTEM_INFO_CG_FLAGS,
119 CGS_SYSTEM_INFO_PG_FLAGS,
120 CGS_SYSTEM_INFO_GFX_CU_INFO,
121 CGS_SYSTEM_INFO_GFX_SE_INFO,
122 CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID,
123 CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID,
124 CGS_SYSTEM_INFO_ID_MAXIMUM,
127 struct cgs_system_info {
129 enum cgs_system_info_id info_id;
134 uint64_t padding[13];
138 * enum cgs_resource_type - GPU resource type
140 enum cgs_resource_type {
141 CGS_RESOURCE_TYPE_MMIO = 0,
142 CGS_RESOURCE_TYPE_FB,
143 CGS_RESOURCE_TYPE_IO,
144 CGS_RESOURCE_TYPE_DOORBELL,
145 CGS_RESOURCE_TYPE_ROM,
149 * struct cgs_clock_limits - Clock limits
151 * Clocks are specified in 10KHz units.
153 struct cgs_clock_limits {
154 unsigned min; /**< Minimum supported frequency */
155 unsigned max; /**< Maxumim supported frequency */
156 unsigned sustainable; /**< Thermally sustainable frequency */
160 * struct cgs_firmware_info - Firmware information
162 struct cgs_firmware_info {
165 uint16_t feature_version;
169 /* only for smc firmware */
170 uint32_t ucode_start_address;
175 struct cgs_mode_info {
176 uint32_t refresh_rate;
178 uint32_t vblank_time_us;
181 struct cgs_display_info {
182 uint32_t display_count;
183 uint32_t active_display_mask;
184 struct cgs_mode_info *mode_info;
187 typedef unsigned long cgs_handle_t;
189 #define CGS_ACPI_METHOD_ATCS 0x53435441
190 #define CGS_ACPI_METHOD_ATIF 0x46495441
191 #define CGS_ACPI_METHOD_ATPX 0x58505441
192 #define CGS_ACPI_FIELD_METHOD_NAME 0x00000001
193 #define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002
194 #define CGS_ACPI_MAX_BUFFER_SIZE 256
195 #define CGS_ACPI_TYPE_ANY 0x00
196 #define CGS_ACPI_TYPE_INTEGER 0x01
197 #define CGS_ACPI_TYPE_STRING 0x02
198 #define CGS_ACPI_TYPE_BUFFER 0x03
199 #define CGS_ACPI_TYPE_PACKAGE 0x04
201 struct cgs_acpi_method_argument {
203 uint32_t data_length;
210 struct cgs_acpi_method_info {
213 uint32_t input_count;
215 struct cgs_acpi_method_argument *pinput_argument;
216 uint32_t output_count;
217 struct cgs_acpi_method_argument *poutput_argument;
222 * cgs_gpu_mem_info() - Return information about memory heaps
223 * @cgs_device: opaque device handle
225 * @mc_start: Start MC address of the heap (output)
226 * @mc_size: MC address space size (output)
227 * @mem_size: maximum amount of memory available for allocation (output)
229 * This function returns information about memory heaps. The type
230 * parameter is used to select the memory heap. The mc_start and
231 * mc_size for GART heaps may be bigger than the memory available for
234 * mc_start and mc_size are undefined for non-contiguous FB memory
235 * types, since buffers allocated with these types may or may not be
238 * Return: 0 on success, -errno otherwise
240 typedef int (*cgs_gpu_mem_info_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
241 uint64_t *mc_start, uint64_t *mc_size,
245 * cgs_gmap_kmem() - map kernel memory to GART aperture
246 * @cgs_device: opaque device handle
247 * @kmem: pointer to kernel memory
249 * @min_offset: minimum offset from start of GART aperture
250 * @max_offset: maximum offset from start of GART aperture
251 * @kmem_handle: kernel memory handle (output)
252 * @mcaddr: MC address (output)
254 * Return: 0 on success, -errno otherwise
256 typedef int (*cgs_gmap_kmem_t)(struct cgs_device *cgs_device, void *kmem, uint64_t size,
257 uint64_t min_offset, uint64_t max_offset,
258 cgs_handle_t *kmem_handle, uint64_t *mcaddr);
261 * cgs_gunmap_kmem() - unmap kernel memory
262 * @cgs_device: opaque device handle
263 * @kmem_handle: kernel memory handle returned by gmap_kmem
265 * Return: 0 on success, -errno otherwise
267 typedef int (*cgs_gunmap_kmem_t)(struct cgs_device *cgs_device, cgs_handle_t kmem_handle);
270 * cgs_alloc_gpu_mem() - Allocate GPU memory
271 * @cgs_device: opaque device handle
273 * @size: size in bytes
274 * @align: alignment in bytes
275 * @min_offset: minimum offset from start of heap
276 * @max_offset: maximum offset from start of heap
277 * @handle: memory handle (output)
279 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
280 * memory allocation. This guarantees that the MC address returned by
281 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous
282 * FB memory types may be GART mapped depending on memory
283 * fragmentation and memory allocator policies.
285 * If min/max_offset are non-0, the allocation will be forced to
286 * reside between these offsets in its respective memory heap. The
287 * base address that the offset relates to, depends on the memory
290 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address
291 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address
292 * - others: undefined, don't use with max_offset
294 * Return: 0 on success, -errno otherwise
296 typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
297 uint64_t size, uint64_t align,
298 uint64_t min_offset, uint64_t max_offset,
299 cgs_handle_t *handle);
302 * cgs_free_gpu_mem() - Free GPU memory
303 * @cgs_device: opaque device handle
304 * @handle: memory handle returned by alloc or import
306 * Return: 0 on success, -errno otherwise
308 typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
311 * cgs_gmap_gpu_mem() - GPU-map GPU memory
312 * @cgs_device: opaque device handle
313 * @handle: memory handle returned by alloc or import
314 * @mcaddr: MC address (output)
316 * Ensures that a buffer is GPU accessible and returns its MC address.
318 * Return: 0 on success, -errno otherwise
320 typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
324 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory
325 * @cgs_device: opaque device handle
326 * @handle: memory handle returned by alloc or import
328 * Allows the buffer to be migrated while it's not used by the GPU.
330 * Return: 0 on success, -errno otherwise
332 typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
335 * cgs_kmap_gpu_mem() - Kernel-map GPU memory
337 * @cgs_device: opaque device handle
338 * @handle: memory handle returned by alloc or import
339 * @map: Kernel virtual address the memory was mapped to (output)
341 * Return: 0 on success, -errno otherwise
343 typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
347 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory
348 * @cgs_device: opaque device handle
349 * @handle: memory handle returned by alloc or import
351 * Return: 0 on success, -errno otherwise
353 typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
356 * cgs_read_register() - Read an MMIO register
357 * @cgs_device: opaque device handle
358 * @offset: register offset
360 * Return: register value
362 typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
365 * cgs_write_register() - Write an MMIO register
366 * @cgs_device: opaque device handle
367 * @offset: register offset
368 * @value: register value
370 typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
374 * cgs_read_ind_register() - Read an indirect register
375 * @cgs_device: opaque device handle
376 * @offset: register offset
378 * Return: register value
380 typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
384 * cgs_write_ind_register() - Write an indirect register
385 * @cgs_device: opaque device handle
386 * @offset: register offset
387 * @value: register value
389 typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
390 unsigned index, uint32_t value);
393 * cgs_read_pci_config_byte() - Read byte from PCI configuration space
394 * @cgs_device: opaque device handle
399 typedef uint8_t (*cgs_read_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr);
402 * cgs_read_pci_config_word() - Read word from PCI configuration space
403 * @cgs_device: opaque device handle
404 * @addr: address, must be word-aligned
408 typedef uint16_t (*cgs_read_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr);
411 * cgs_read_pci_config_dword() - Read dword from PCI configuration space
412 * @cgs_device: opaque device handle
413 * @addr: address, must be dword-aligned
417 typedef uint32_t (*cgs_read_pci_config_dword_t)(struct cgs_device *cgs_device,
421 * cgs_write_pci_config_byte() - Write byte to PCI configuration space
422 * @cgs_device: opaque device handle
424 * @value: value to write
426 typedef void (*cgs_write_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr,
430 * cgs_write_pci_config_word() - Write byte to PCI configuration space
431 * @cgs_device: opaque device handle
432 * @addr: address, must be word-aligned
433 * @value: value to write
435 typedef void (*cgs_write_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr,
439 * cgs_write_pci_config_dword() - Write byte to PCI configuration space
440 * @cgs_device: opaque device handle
441 * @addr: address, must be dword-aligned
442 * @value: value to write
444 typedef void (*cgs_write_pci_config_dword_t)(struct cgs_device *cgs_device, unsigned addr,
449 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
450 * @cgs_device: opaque device handle
451 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL)
452 * @size: size of the region
453 * @offset: offset from the start of the region
454 * @resource_base: base address (not including offset) returned
456 * Return: 0 on success, -errno otherwise
458 typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device,
459 enum cgs_resource_type resource_type,
462 uint64_t *resource_base);
465 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
466 * @cgs_device: opaque device handle
467 * @table: data table index
468 * @size: size of the table (output, may be NULL)
469 * @frev: table format revision (output, may be NULL)
470 * @crev: table content revision (output, may be NULL)
472 * Return: Pointer to start of the table, or NULL on failure
474 typedef const void *(*cgs_atom_get_data_table_t)(
475 struct cgs_device *cgs_device, unsigned table,
476 uint16_t *size, uint8_t *frev, uint8_t *crev);
479 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
480 * @cgs_device: opaque device handle
481 * @table: data table index
482 * @frev: table format revision (output, may be NULL)
483 * @crev: table content revision (output, may be NULL)
485 * Return: 0 on success, -errno otherwise
487 typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table,
488 uint8_t *frev, uint8_t *crev);
491 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
492 * @cgs_device: opaque device handle
493 * @table: command table index
496 * Return: 0 on success, -errno otherwise
498 typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device,
499 unsigned table, void *args);
502 * cgs_create_pm_request() - Create a power management request
503 * @cgs_device: opaque device handle
504 * @request: handle of created PM request (output)
506 * Return: 0 on success, -errno otherwise
508 typedef int (*cgs_create_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t *request);
511 * cgs_destroy_pm_request() - Destroy a power management request
512 * @cgs_device: opaque device handle
513 * @request: handle of created PM request
515 * Return: 0 on success, -errno otherwise
517 typedef int (*cgs_destroy_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request);
520 * cgs_set_pm_request() - Activate or deactiveate a PM request
521 * @cgs_device: opaque device handle
522 * @request: PM request handle
523 * @active: 0 = deactivate, non-0 = activate
525 * While a PM request is active, its minimum clock requests are taken
526 * into account as the requested engines are powered up. When the
527 * request is inactive, the engines may be powered down and clocks may
528 * be lower, depending on other PM requests by other driver
531 * Return: 0 on success, -errno otherwise
533 typedef int (*cgs_set_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request,
537 * cgs_pm_request_clock() - Request a minimum frequency for a specific clock
538 * @cgs_device: opaque device handle
539 * @request: PM request handle
540 * @clock: which clock?
541 * @freq: requested min. frequency in 10KHz units (0 to clear request)
543 * Return: 0 on success, -errno otherwise
545 typedef int (*cgs_pm_request_clock_t)(struct cgs_device *cgs_device, cgs_handle_t request,
546 enum cgs_clock clock, unsigned freq);
549 * cgs_pm_request_engine() - Request an engine to be powered up
550 * @cgs_device: opaque device handle
551 * @request: PM request handle
552 * @engine: which engine?
553 * @powered: 0 = powered down, non-0 = powered up
555 * Return: 0 on success, -errno otherwise
557 typedef int (*cgs_pm_request_engine_t)(struct cgs_device *cgs_device, cgs_handle_t request,
558 enum cgs_engine engine, int powered);
561 * cgs_pm_query_clock_limits() - Query clock frequency limits
562 * @cgs_device: opaque device handle
563 * @clock: which clock?
564 * @limits: clock limits
566 * Return: 0 on success, -errno otherwise
568 typedef int (*cgs_pm_query_clock_limits_t)(struct cgs_device *cgs_device,
569 enum cgs_clock clock,
570 struct cgs_clock_limits *limits);
573 * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes
574 * @cgs_device: opaque device handle
575 * @mask: bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...)
576 * @voltages: pointer to array of voltage values in 1mV units
578 * Return: 0 on success, -errno otherwise
580 typedef int (*cgs_set_camera_voltages_t)(struct cgs_device *cgs_device, uint32_t mask,
581 const uint32_t *voltages);
583 * cgs_get_firmware_info - Get the firmware information from core driver
584 * @cgs_device: opaque device handle
585 * @type: the firmware type
586 * @info: returend firmware information
588 * Return: 0 on success, -errno otherwise
590 typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
591 enum cgs_ucode_id type,
592 struct cgs_firmware_info *info);
594 typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device,
595 enum cgs_ucode_id type);
597 typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
598 enum amd_ip_block_type block_type,
599 enum amd_powergating_state state);
601 typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device,
602 enum amd_ip_block_type block_type,
603 enum amd_clockgating_state state);
605 typedef int(*cgs_get_active_displays_info)(
606 struct cgs_device *cgs_device,
607 struct cgs_display_info *info);
609 typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
611 typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device,
612 uint32_t acpi_method,
613 uint32_t acpi_function,
614 void *pinput, void *poutput,
615 uint32_t output_count,
617 uint32_t output_size);
619 typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device,
620 struct cgs_system_info *sys_info);
623 /* memory management calls (similar to KFD interface) */
624 cgs_gpu_mem_info_t gpu_mem_info;
625 cgs_gmap_kmem_t gmap_kmem;
626 cgs_gunmap_kmem_t gunmap_kmem;
627 cgs_alloc_gpu_mem_t alloc_gpu_mem;
628 cgs_free_gpu_mem_t free_gpu_mem;
629 cgs_gmap_gpu_mem_t gmap_gpu_mem;
630 cgs_gunmap_gpu_mem_t gunmap_gpu_mem;
631 cgs_kmap_gpu_mem_t kmap_gpu_mem;
632 cgs_kunmap_gpu_mem_t kunmap_gpu_mem;
634 cgs_read_register_t read_register;
635 cgs_write_register_t write_register;
636 cgs_read_ind_register_t read_ind_register;
637 cgs_write_ind_register_t write_ind_register;
638 /* PCI configuration space access */
639 cgs_read_pci_config_byte_t read_pci_config_byte;
640 cgs_read_pci_config_word_t read_pci_config_word;
641 cgs_read_pci_config_dword_t read_pci_config_dword;
642 cgs_write_pci_config_byte_t write_pci_config_byte;
643 cgs_write_pci_config_word_t write_pci_config_word;
644 cgs_write_pci_config_dword_t write_pci_config_dword;
646 cgs_get_pci_resource_t get_pci_resource;
648 cgs_atom_get_data_table_t atom_get_data_table;
649 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
650 cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
651 /* Power management */
652 cgs_create_pm_request_t create_pm_request;
653 cgs_destroy_pm_request_t destroy_pm_request;
654 cgs_set_pm_request_t set_pm_request;
655 cgs_pm_request_clock_t pm_request_clock;
656 cgs_pm_request_engine_t pm_request_engine;
657 cgs_pm_query_clock_limits_t pm_query_clock_limits;
658 cgs_set_camera_voltages_t set_camera_voltages;
660 cgs_get_firmware_info get_firmware_info;
661 cgs_rel_firmware rel_firmware;
663 cgs_set_powergating_state set_powergating_state;
664 cgs_set_clockgating_state set_clockgating_state;
665 /* display manager */
666 cgs_get_active_displays_info get_active_displays_info;
667 /* notify dpm enabled */
668 cgs_notify_dpm_enabled notify_dpm_enabled;
670 cgs_call_acpi_method call_acpi_method;
671 /* get system info */
672 cgs_query_system_info query_system_info;
675 struct cgs_os_ops; /* To be define in OS-specific CGS header */
679 const struct cgs_ops *ops;
680 const struct cgs_os_ops *os_ops;
681 /* to be embedded at the start of driver private structure */
684 /* Convenience macros that make CGS indirect function calls look like
685 * normal function calls */
686 #define CGS_CALL(func,dev,...) \
687 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
688 #define CGS_OS_CALL(func,dev,...) \
689 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
691 #define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) \
692 CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size)
693 #define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \
694 CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr)
695 #define cgs_gunmap_kmem(dev,kmem_handle) \
696 CGS_CALL(gunmap_kmem,dev,keme_handle)
697 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \
698 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
699 #define cgs_free_gpu_mem(dev,handle) \
700 CGS_CALL(free_gpu_mem,dev,handle)
701 #define cgs_gmap_gpu_mem(dev,handle,mcaddr) \
702 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr)
703 #define cgs_gunmap_gpu_mem(dev,handle) \
704 CGS_CALL(gunmap_gpu_mem,dev,handle)
705 #define cgs_kmap_gpu_mem(dev,handle,map) \
706 CGS_CALL(kmap_gpu_mem,dev,handle,map)
707 #define cgs_kunmap_gpu_mem(dev,handle) \
708 CGS_CALL(kunmap_gpu_mem,dev,handle)
710 #define cgs_read_register(dev,offset) \
711 CGS_CALL(read_register,dev,offset)
712 #define cgs_write_register(dev,offset,value) \
713 CGS_CALL(write_register,dev,offset,value)
714 #define cgs_read_ind_register(dev,space,index) \
715 CGS_CALL(read_ind_register,dev,space,index)
716 #define cgs_write_ind_register(dev,space,index,value) \
717 CGS_CALL(write_ind_register,dev,space,index,value)
719 #define cgs_read_pci_config_byte(dev,addr) \
720 CGS_CALL(read_pci_config_byte,dev,addr)
721 #define cgs_read_pci_config_word(dev,addr) \
722 CGS_CALL(read_pci_config_word,dev,addr)
723 #define cgs_read_pci_config_dword(dev,addr) \
724 CGS_CALL(read_pci_config_dword,dev,addr)
725 #define cgs_write_pci_config_byte(dev,addr,value) \
726 CGS_CALL(write_pci_config_byte,dev,addr,value)
727 #define cgs_write_pci_config_word(dev,addr,value) \
728 CGS_CALL(write_pci_config_word,dev,addr,value)
729 #define cgs_write_pci_config_dword(dev,addr,value) \
730 CGS_CALL(write_pci_config_dword,dev,addr,value)
732 #define cgs_atom_get_data_table(dev,table,size,frev,crev) \
733 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
734 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \
735 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
736 #define cgs_atom_exec_cmd_table(dev,table,args) \
737 CGS_CALL(atom_exec_cmd_table,dev,table,args)
739 #define cgs_create_pm_request(dev,request) \
740 CGS_CALL(create_pm_request,dev,request)
741 #define cgs_destroy_pm_request(dev,request) \
742 CGS_CALL(destroy_pm_request,dev,request)
743 #define cgs_set_pm_request(dev,request,active) \
744 CGS_CALL(set_pm_request,dev,request,active)
745 #define cgs_pm_request_clock(dev,request,clock,freq) \
746 CGS_CALL(pm_request_clock,dev,request,clock,freq)
747 #define cgs_pm_request_engine(dev,request,engine,powered) \
748 CGS_CALL(pm_request_engine,dev,request,engine,powered)
749 #define cgs_pm_query_clock_limits(dev,clock,limits) \
750 CGS_CALL(pm_query_clock_limits,dev,clock,limits)
751 #define cgs_set_camera_voltages(dev,mask,voltages) \
752 CGS_CALL(set_camera_voltages,dev,mask,voltages)
753 #define cgs_get_firmware_info(dev, type, info) \
754 CGS_CALL(get_firmware_info, dev, type, info)
755 #define cgs_rel_firmware(dev, type) \
756 CGS_CALL(rel_firmware, dev, type)
757 #define cgs_set_powergating_state(dev, block_type, state) \
758 CGS_CALL(set_powergating_state, dev, block_type, state)
759 #define cgs_set_clockgating_state(dev, block_type, state) \
760 CGS_CALL(set_clockgating_state, dev, block_type, state)
761 #define cgs_notify_dpm_enabled(dev, enabled) \
762 CGS_CALL(notify_dpm_enabled, dev, enabled)
764 #define cgs_get_active_displays_info(dev, info) \
765 CGS_CALL(get_active_displays_info, dev, info)
767 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \
768 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
769 #define cgs_query_system_info(dev, sys_info) \
770 CGS_CALL(query_system_info, dev, sys_info)
771 #define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
773 CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
776 #endif /* _CGS_COMMON_H */