drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h

   1 /*
   2  * Copyright (C) 2017  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _uvd_7_0_DEFAULT_HEADER
  22 #define _uvd_7_0_DEFAULT_HEADER
  23
  24
  25 // addressBlock: uvd0_uvd_pg_dec
  26 #define mmUVD_POWER_STATUS_DEFAULT                                               0x00000000
  27 #define mmUVD_DPG_RBC_RB_CNTL_DEFAULT                                            0x01000101
  28 #define mmUVD_DPG_RBC_RB_BASE_LOW_DEFAULT                                        0x00000000
  29 #define mmUVD_DPG_RBC_RB_BASE_HIGH_DEFAULT                                       0x00000000
  30 #define mmUVD_DPG_RBC_RB_WPTR_CNTL_DEFAULT                                       0x00000000
  31 #define mmUVD_DPG_RBC_RB_RPTR_DEFAULT                                            0x00000000
  32 #define mmUVD_DPG_RBC_RB_WPTR_DEFAULT                                            0x00000000
  33 #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT                           0x00000000
  34 #define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT                          0x00000000
  35 #define mmUVD_DPG_VCPU_CACHE_OFFSET0_DEFAULT                                     0x00000000
  36
  37
  38 // addressBlock: uvd0_uvdnpdec
  39 #define mmUVD_JPEG_ADDR_CONFIG_DEFAULT                                           0x22010010
  40 #define mmUVD_GPCOM_VCPU_CMD_DEFAULT                                             0x00000000
  41 #define mmUVD_GPCOM_VCPU_DATA0_DEFAULT                                           0x00000000
  42 #define mmUVD_GPCOM_VCPU_DATA1_DEFAULT                                           0x00000000
  43 #define mmUVD_UDEC_ADDR_CONFIG_DEFAULT                                           0x22010010
  44 #define mmUVD_UDEC_DB_ADDR_CONFIG_DEFAULT                                        0x22010010
  45 #define mmUVD_UDEC_DBW_ADDR_CONFIG_DEFAULT                                       0x22010010
  46 #define mmUVD_SUVD_CGC_GATE_DEFAULT                                              0x00000000
  47 #define mmUVD_SUVD_CGC_CTRL_DEFAULT                                              0x00000000
  48 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_DEFAULT                              0x00000000
  49 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_DEFAULT                             0x00000000
  50 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_DEFAULT                              0x00000000
  51 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_DEFAULT                             0x00000000
  52 #define mmUVD_POWER_STATUS_U_DEFAULT                                             0x00000000
  53 #define mmUVD_NO_OP_DEFAULT                                                      0x00000000
  54 #define mmUVD_GP_SCRATCH8_DEFAULT                                                0x00000000
  55 #define mmUVD_RB_BASE_LO2_DEFAULT                                                0x00000000
  56 #define mmUVD_RB_BASE_HI2_DEFAULT                                                0x00000000
  57 #define mmUVD_RB_SIZE2_DEFAULT                                                   0x00000000
  58 #define mmUVD_RB_RPTR2_DEFAULT                                                   0x00000000
  59 #define mmUVD_RB_WPTR2_DEFAULT                                                   0x00000000
  60 #define mmUVD_RB_BASE_LO_DEFAULT                                                 0x00000000
  61 #define mmUVD_RB_BASE_HI_DEFAULT                                                 0x00000000
  62 #define mmUVD_RB_SIZE_DEFAULT                                                    0x00000000
  63 #define mmUVD_RB_RPTR_DEFAULT                                                    0x00000000
  64 #define mmUVD_RB_WPTR_DEFAULT                                                    0x00000000
  65 #define mmUVD_JRBC_RB_RPTR_DEFAULT                                               0x00000000
  66 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT                              0x00000000
  67 #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT                               0x00000000
  68 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_DEFAULT                                  0x00000000
  69 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_DEFAULT                                   0x00000000
  70 #define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_DEFAULT                                  0x00000000
  71 #define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_DEFAULT                                   0x00000000
  72
  73
  74 // addressBlock: uvd0_uvddec
  75 #define mmUVD_SEMA_CNTL_DEFAULT                                                  0x00000003
  76 #define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_DEFAULT                                  0x00000000
  77 #define mmUVD_JRBC_RB_WPTR_DEFAULT                                               0x00000000
  78 #define mmUVD_RB_RPTR3_DEFAULT                                                   0x00000000
  79 #define mmUVD_RB_WPTR3_DEFAULT                                                   0x00000000
  80 #define mmUVD_RB_BASE_LO3_DEFAULT                                                0x00000000
  81 #define mmUVD_RB_BASE_HI3_DEFAULT                                                0x00000000
  82 #define mmUVD_RB_SIZE3_DEFAULT                                                   0x00000000
  83 #define mmJPEG_CGC_GATE_DEFAULT                                                  0x00300000
  84 #define mmUVD_CTX_INDEX_DEFAULT                                                  0x00000000
  85 #define mmUVD_CTX_DATA_DEFAULT                                                   0x00000000
  86 #define mmUVD_CGC_GATE_DEFAULT                                                   0x000fffff
  87 #define mmUVD_CGC_CTRL_DEFAULT                                                   0x1fff018d
  88 #define mmUVD_GP_SCRATCH4_DEFAULT                                                0x00000000
  89 #define mmUVD_LMI_CTRL2_DEFAULT                                                  0x003e0000
  90 #define mmUVD_MASTINT_EN_DEFAULT                                                 0x00000000
  91 #define mmJPEG_CGC_CTRL_DEFAULT                                                  0x0000018d
  92 #define mmUVD_LMI_CTRL_DEFAULT                                                   0x00104340
  93 #define mmUVD_LMI_VM_CTRL_DEFAULT                                                0x00000000
  94 #define mmUVD_LMI_SWAP_CNTL_DEFAULT                                              0x00000000
  95 #define mmUVD_MP_SWAP_CNTL_DEFAULT                                               0x00000000
  96 #define mmUVD_MPC_SET_MUXA0_DEFAULT                                              0x00002040
  97 #define mmUVD_MPC_SET_MUXA1_DEFAULT                                              0x00000000
  98 #define mmUVD_MPC_SET_MUXB0_DEFAULT                                              0x00002040
  99 #define mmUVD_MPC_SET_MUXB1_DEFAULT                                              0x00000000
 100 #define mmUVD_MPC_SET_MUX_DEFAULT                                                0x00000088
 101 #define mmUVD_MPC_SET_ALU_DEFAULT                                                0x00000000
 102 #define mmUVD_VCPU_CACHE_OFFSET0_DEFAULT                                         0x00000000
 103 #define mmUVD_VCPU_CACHE_SIZE0_DEFAULT                                           0x00000000
 104 #define mmUVD_VCPU_CACHE_OFFSET1_DEFAULT                                         0x00000000
 105 #define mmUVD_VCPU_CACHE_SIZE1_DEFAULT                                           0x00000000
 106 #define mmUVD_VCPU_CACHE_OFFSET2_DEFAULT                                         0x00000000
 107 #define mmUVD_VCPU_CACHE_SIZE2_DEFAULT                                           0x00000000
 108 #define mmUVD_VCPU_CNTL_DEFAULT                                                  0x0ff20000
 109 #define mmUVD_SOFT_RESET_DEFAULT                                                 0x00000008
 110 #define mmUVD_LMI_RBC_IB_VMID_DEFAULT                                            0x00000000
 111 #define mmUVD_RBC_IB_SIZE_DEFAULT                                                0x00000000
 112 #define mmUVD_LMI_RBC_RB_VMID_DEFAULT                                            0x00000000
 113 #define mmUVD_RBC_RB_RPTR_DEFAULT                                                0x00000000
 114 #define mmUVD_RBC_RB_WPTR_DEFAULT                                                0x00000000
 115 #define mmUVD_RBC_RB_WPTR_CNTL_DEFAULT                                           0x00000000
 116 #define mmUVD_RBC_RB_CNTL_DEFAULT                                                0x01000101
 117 #define mmUVD_RBC_RB_RPTR_ADDR_DEFAULT                                           0x00000000
 118 #define mmUVD_STATUS_DEFAULT                                                     0x00000000
 119 #define mmUVD_SEMA_TIMEOUT_STATUS_DEFAULT                                        0x00000000
 120 #define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_DEFAULT                          0x02000000
 121 #define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_DEFAULT                               0x02000000
 122 #define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_DEFAULT                        0x02000000
 123 #define mmUVD_CONTEXT_ID_DEFAULT                                                 0x00000000
 124 #define mmUVD_CONTEXT_ID2_DEFAULT                                                0x00000000
 125
 126
 127 #endif