2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 #ifndef _vcn_1_0_SH_MASK_HEADER
22 #define _vcn_1_0_SH_MASK_HEADER
25 // addressBlock: uvd_uvd_pg_dec
27 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0
28 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2
29 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4
30 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6
31 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8
32 #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 0xa
33 #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 0xc
34 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe
35 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10
36 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12
37 #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT 0x14
38 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L
39 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL
40 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L
41 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L
42 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L
43 #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK 0x00000C00L
44 #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK 0x00003000L
45 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L
46 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L
47 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L
48 #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK 0x00300000L
50 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0
51 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2
52 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4
53 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6
54 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8
55 #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 0xa
56 #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 0xc
57 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe
58 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10
59 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12
60 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14
61 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L
62 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL
63 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L
64 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L
65 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L
66 #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK 0x00000C00L
67 #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK 0x00003000L
68 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L
69 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L
70 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L
71 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK 0x00300000L
73 #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0
74 #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2
75 #define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4
76 #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8
77 #define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9
78 #define UVD_POWER_STATUS__JRBC_SNOOP_DIS__SHIFT 0xa
79 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb
80 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L
81 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L
82 #define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L
83 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L
84 #define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L
85 #define UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK 0x00000400L
86 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L
88 #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1
89 #define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L
91 #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0
92 #define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL
94 #define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0
95 #define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL
97 #define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0
98 #define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL
100 #define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0
101 #define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL
103 #define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0
104 #define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL
106 #define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0
107 #define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL
109 #define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0
110 #define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL
112 #define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0
113 #define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL
115 #define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0
116 #define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL
118 #define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0
119 #define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL
121 #define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0
122 #define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL
124 #define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0
125 #define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL
127 #define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0
128 #define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL
130 #define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0
131 #define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL
132 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW
133 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
134 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
135 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH
136 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
137 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
138 //UVD_DPG_VCPU_CACHE_OFFSET0
139 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
140 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL
143 // addressBlock: uvd_uvdgendec
145 #define UVD_LCM_CGC_CNTRL__FORCE_OFF__SHIFT 0x12
146 #define UVD_LCM_CGC_CNTRL__FORCE_ON__SHIFT 0x13
147 #define UVD_LCM_CGC_CNTRL__OFF_DELAY__SHIFT 0x14
148 #define UVD_LCM_CGC_CNTRL__ON_DELAY__SHIFT 0x1c
149 #define UVD_LCM_CGC_CNTRL__FORCE_OFF_MASK 0x00040000L
150 #define UVD_LCM_CGC_CNTRL__FORCE_ON_MASK 0x00080000L
151 #define UVD_LCM_CGC_CNTRL__OFF_DELAY_MASK 0x0FF00000L
152 #define UVD_LCM_CGC_CNTRL__ON_DELAY_MASK 0xF0000000L
155 // addressBlock: uvd_uvdnpdec
157 #define UVD_JPEG_CNTL__SOFT_RESET__SHIFT 0x0
158 #define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1
159 #define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2
160 #define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3
161 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4
162 #define UVD_JPEG_CNTL__DBG_MUX_SEL__SHIFT 0x8
163 #define UVD_JPEG_CNTL__SOFT_RESET_MASK 0x00000001L
164 #define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L
165 #define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L
166 #define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L
167 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L
168 #define UVD_JPEG_CNTL__DBG_MUX_SEL_MASK 0x00007F00L
170 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0
171 #define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6
172 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL
173 #define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L
175 #define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4
176 #define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L
178 #define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4
179 #define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L
181 #define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4
182 #define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L
183 //UVD_JPEG_ADDR_CONFIG
184 #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
185 #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
186 #define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
187 #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
188 #define UVD_JPEG_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
189 #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
190 #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
191 #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
192 #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
193 #define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
194 #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
195 #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
196 #define UVD_JPEG_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
197 #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
198 #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
199 #define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
200 #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
201 #define UVD_JPEG_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
202 #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
203 #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
204 #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
205 #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
206 #define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
207 #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
208 #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
209 #define UVD_JPEG_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
211 #define UVD_JPEG_GPCOM_CMD__CMD_SEND__SHIFT 0x0
212 #define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1
213 #define UVD_JPEG_GPCOM_CMD__CMD_SOURCE__SHIFT 0x1f
214 #define UVD_JPEG_GPCOM_CMD__CMD_SEND_MASK 0x00000001L
215 #define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x7FFFFFFEL
216 #define UVD_JPEG_GPCOM_CMD__CMD_SOURCE_MASK 0x80000000L
217 //UVD_JPEG_GPCOM_DATA0
218 #define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0
219 #define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL
220 //UVD_JPEG_GPCOM_DATA1
221 #define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0
222 #define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL
223 //UVD_JPEG_JRB_BASE_LO
224 #define UVD_JPEG_JRB_BASE_LO__JRB_BASE_LO__SHIFT 0x6
225 #define UVD_JPEG_JRB_BASE_LO__JRB_BASE_LO_MASK 0xFFFFFFC0L
226 //UVD_JPEG_JRB_BASE_HI
227 #define UVD_JPEG_JRB_BASE_HI__JRB_BASE_HI__SHIFT 0x0
228 #define UVD_JPEG_JRB_BASE_HI__JRB_BASE_HI_MASK 0xFFFFFFFFL
230 #define UVD_JPEG_JRB_SIZE__JRB_SIZE__SHIFT 0x4
231 #define UVD_JPEG_JRB_SIZE__JRB_SIZE_MASK 0x007FFFF0L
233 #define UVD_JPEG_JRB_RPTR__JRB_RPTR__SHIFT 0x4
234 #define UVD_JPEG_JRB_RPTR__JRB_RPTR_MASK 0x007FFFF0L
236 #define UVD_JPEG_JRB_WPTR__JRB_WPTR__SHIFT 0x4
237 #define UVD_JPEG_JRB_WPTR__JRB_WPTR_MASK 0x007FFFF0L
238 //UVD_JPEG_UV_ADDR_CONFIG
239 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
240 #define UVD_JPEG_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
241 #define UVD_JPEG_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
242 #define UVD_JPEG_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
243 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
244 #define UVD_JPEG_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
245 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
246 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
247 #define UVD_JPEG_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
248 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
249 #define UVD_JPEG_UV_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
250 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
251 #define UVD_JPEG_UV_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
252 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
253 #define UVD_JPEG_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
254 #define UVD_JPEG_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
255 #define UVD_JPEG_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
256 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
257 #define UVD_JPEG_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
258 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
259 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
260 #define UVD_JPEG_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
261 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
262 #define UVD_JPEG_UV_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
263 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
264 #define UVD_JPEG_UV_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
266 #define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0
267 #define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL
269 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0
270 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL
272 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
273 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
274 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
275 #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
276 #define UVD_SEMA_CMD__VMID__SHIFT 0x8
277 #define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL
278 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L
279 #define UVD_SEMA_CMD__MODE_MASK 0x00000040L
280 #define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L
281 #define UVD_SEMA_CMD__VMID_MASK 0x00000F00L
283 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
284 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
285 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f
286 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L
287 #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL
288 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L
289 //UVD_GPCOM_VCPU_DATA0
290 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0
291 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL
292 //UVD_GPCOM_VCPU_DATA1
293 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
294 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL
295 //UVD_UDEC_DBW_UV_ADDR_CONFIG
296 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
297 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
298 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
299 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
300 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
301 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
302 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
303 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
304 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
305 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
306 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
307 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
308 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
309 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
310 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
311 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
312 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
313 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
314 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
315 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
316 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
317 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
318 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
319 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
320 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
321 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
322 //UVD_UDEC_ADDR_CONFIG
323 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
324 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
325 #define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
326 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
327 #define UVD_UDEC_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
328 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
329 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
330 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
331 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
332 #define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
333 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
334 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
335 #define UVD_UDEC_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
336 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
337 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
338 #define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
339 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
340 #define UVD_UDEC_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
341 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
342 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
343 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
344 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
345 #define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
346 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
347 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
348 #define UVD_UDEC_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
349 //UVD_UDEC_DB_ADDR_CONFIG
350 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
351 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
352 #define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
353 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
354 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
355 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
356 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
357 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
358 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
359 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
360 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
361 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
362 #define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
363 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
364 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
365 #define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
366 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
367 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
368 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
369 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
370 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
371 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
372 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
373 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
374 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
375 #define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
376 //UVD_UDEC_DBW_ADDR_CONFIG
377 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
378 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
379 #define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
380 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
381 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
382 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
383 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
384 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
385 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
386 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
387 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
388 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
389 #define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
390 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
391 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
392 #define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
393 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
394 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
395 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
396 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
397 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
398 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
399 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
400 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
401 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
402 #define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
404 #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0
405 #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1
406 #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2
407 #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3
408 #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4
409 #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
410 #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6
411 #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7
412 #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8
413 #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9
414 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
415 #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb
416 #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc
417 #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd
418 #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
419 #define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf
420 #define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10
421 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11
422 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12
423 #define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13
424 #define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14
425 #define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15
426 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16
427 #define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17
428 #define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18
429 #define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L
430 #define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L
431 #define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L
432 #define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L
433 #define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L
434 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L
435 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L
436 #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L
437 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L
438 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L
439 #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L
440 #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L
441 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L
442 #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L
443 #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L
444 #define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L
445 #define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L
446 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L
447 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L
448 #define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L
449 #define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L
450 #define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L
451 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L
452 #define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L
453 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L
454 //UVD_SUVD_CGC_STATUS
455 #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0
456 #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1
457 #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2
458 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3
459 #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4
460 #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5
461 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6
462 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7
463 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8
464 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9
465 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
466 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb
467 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc
468 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd
469 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe
470 #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf
471 #define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10
472 #define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11
473 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12
474 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13
475 #define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14
476 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15
477 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16
478 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17
479 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18
480 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19
481 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a
482 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b
483 #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L
484 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L
485 #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L
486 #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L
487 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L
488 #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L
489 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L
490 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L
491 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L
492 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L
493 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L
494 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L
495 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L
496 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L
497 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L
498 #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L
499 #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L
500 #define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L
501 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L
502 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L
503 #define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L
504 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L
505 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L
506 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L
507 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L
508 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L
509 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L
510 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L
512 #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0
513 #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1
514 #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2
515 #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3
516 #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4
517 #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
518 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6
519 #define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7
520 #define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8
521 #define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9
522 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L
523 #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L
524 #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L
525 #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L
526 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L
527 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L
528 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L
529 #define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L
530 #define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L
531 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L
532 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
533 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
534 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
535 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
536 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
537 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
538 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
539 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
540 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
541 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
542 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
543 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
545 #define UVD_NO_OP__NO_OP__SHIFT 0x0
546 #define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL
548 #define UVD_VERSION__MINOR_VERSION__SHIFT 0x0
549 #define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10
550 #define UVD_VERSION__MINOR_VERSION_MASK 0x0000FFFFL
551 #define UVD_VERSION__MAJOR_VERSION_MASK 0xFFFF0000L
553 #define UVD_GP_SCRATCH8__DATA__SHIFT 0x0
554 #define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL
556 #define UVD_GP_SCRATCH9__DATA__SHIFT 0x0
557 #define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL
559 #define UVD_GP_SCRATCH10__DATA__SHIFT 0x0
560 #define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL
562 #define UVD_GP_SCRATCH11__DATA__SHIFT 0x0
563 #define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL
565 #define UVD_GP_SCRATCH12__DATA__SHIFT 0x0
566 #define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL
568 #define UVD_GP_SCRATCH13__DATA__SHIFT 0x0
569 #define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL
571 #define UVD_GP_SCRATCH14__DATA__SHIFT 0x0
572 #define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL
574 #define UVD_GP_SCRATCH15__DATA__SHIFT 0x0
575 #define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL
577 #define UVD_GP_SCRATCH16__DATA__SHIFT 0x0
578 #define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL
580 #define UVD_GP_SCRATCH17__DATA__SHIFT 0x0
581 #define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL
583 #define UVD_GP_SCRATCH18__DATA__SHIFT 0x0
584 #define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL
586 #define UVD_GP_SCRATCH19__DATA__SHIFT 0x0
587 #define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL
589 #define UVD_GP_SCRATCH20__DATA__SHIFT 0x0
590 #define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL
592 #define UVD_GP_SCRATCH21__DATA__SHIFT 0x0
593 #define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL
595 #define UVD_GP_SCRATCH22__DATA__SHIFT 0x0
596 #define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL
598 #define UVD_GP_SCRATCH23__DATA__SHIFT 0x0
599 #define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL
601 #define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6
602 #define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L
604 #define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0
605 #define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL
607 #define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4
608 #define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L
610 #define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4
611 #define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L
613 #define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4
614 #define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L
616 #define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
617 #define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L
619 #define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
620 #define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL
622 #define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4
623 #define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L
625 #define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4
626 #define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
628 #define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4
629 #define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
631 #define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4
632 #define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L
634 #define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4
635 #define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
636 //UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
637 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
638 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
639 //UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
640 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
641 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
642 //UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH
643 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
644 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
645 //UVD_LMI_VCPU_NC1_64BIT_BAR_LOW
646 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
647 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
648 //UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH
649 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
650 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
651 //UVD_LMI_VCPU_NC0_64BIT_BAR_LOW
652 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
653 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
654 //UVD_LMI_LBSI_64BIT_BAR_HIGH
655 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
656 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
657 //UVD_LMI_LBSI_64BIT_BAR_LOW
658 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
659 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
660 //UVD_LMI_RBC_IB_64BIT_BAR_HIGH
661 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
662 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
663 //UVD_LMI_RBC_IB_64BIT_BAR_LOW
664 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
665 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
666 //UVD_LMI_RBC_RB_64BIT_BAR_HIGH
667 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
668 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
669 //UVD_LMI_RBC_RB_64BIT_BAR_LOW
670 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
671 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
674 // addressBlock: uvd_uvddec
676 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
677 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
678 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L
679 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L
680 //UVD_LMI_JRBC_RB_64BIT_BAR_LOW
681 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
682 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
683 //UVD_LMI_JRBC_RB_64BIT_BAR_HIGH
684 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
685 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
686 //UVD_LMI_JRBC_IB_64BIT_BAR_LOW
687 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
688 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL
689 //UVD_LMI_JRBC_IB_64BIT_BAR_HIGH
690 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
691 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL
692 //UVD_LMI_JRBC_IB_VMID
693 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0
694 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4
695 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL
696 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L
698 #define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4
699 #define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
701 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0
702 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1
703 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4
704 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L
705 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L
706 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L
708 #define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4
709 #define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L
710 //UVD_JRBC_LMI_SWAP_CNTL
711 #define UVD_JRBC_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
712 #define UVD_JRBC_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
713 #define UVD_JRBC_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L
714 #define UVD_JRBC_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL
715 //UVD_JRBC_SOFT_RESET
716 #define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0
717 #define UVD_JRBC_SOFT_RESET__VCLK_RESET_STATUS__SHIFT 0x10
718 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11
719 #define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L
720 #define UVD_JRBC_SOFT_RESET__VCLK_RESET_STATUS_MASK 0x00010000L
721 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L
723 #define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0
724 #define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1
725 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2
726 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3
727 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4
728 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5
729 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6
730 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7
731 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8
732 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9
733 #define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
734 #define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb
735 #define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc
736 #define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10
737 #define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11
738 #define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L
739 #define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L
740 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L
741 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L
742 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L
743 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L
744 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L
745 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L
746 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L
747 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L
748 #define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L
749 #define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L
750 #define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L
751 #define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L
752 #define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L
754 #define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4
755 #define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L
757 #define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4
758 #define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L
760 #define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6
761 #define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L
763 #define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0
764 #define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL
766 #define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4
767 #define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L
769 #define JPEG_CGC_GATE__JPEG__SHIFT 0x14
770 #define JPEG_CGC_GATE__JPEG2__SHIFT 0x15
771 #define JPEG_CGC_GATE__JPEG_MASK 0x00100000L
772 #define JPEG_CGC_GATE__JPEG2_MASK 0x00200000L
774 #define UVD_CTX_INDEX__INDEX__SHIFT 0x0
775 #define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL
777 #define UVD_CTX_DATA__DATA__SHIFT 0x0
778 #define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL
780 #define UVD_CGC_GATE__SYS__SHIFT 0x0
781 #define UVD_CGC_GATE__UDEC__SHIFT 0x1
782 #define UVD_CGC_GATE__MPEG2__SHIFT 0x2
783 #define UVD_CGC_GATE__REGS__SHIFT 0x3
784 #define UVD_CGC_GATE__RBC__SHIFT 0x4
785 #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5
786 #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6
787 #define UVD_CGC_GATE__IDCT__SHIFT 0x7
788 #define UVD_CGC_GATE__MPRD__SHIFT 0x8
789 #define UVD_CGC_GATE__MPC__SHIFT 0x9
790 #define UVD_CGC_GATE__LBSI__SHIFT 0xa
791 #define UVD_CGC_GATE__LRBBM__SHIFT 0xb
792 #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc
793 #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd
794 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
795 #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf
796 #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10
797 #define UVD_CGC_GATE__WCB__SHIFT 0x11
798 #define UVD_CGC_GATE__VCPU__SHIFT 0x12
799 #define UVD_CGC_GATE__SCPU__SHIFT 0x13
800 #define UVD_CGC_GATE__SYS_MASK 0x00000001L
801 #define UVD_CGC_GATE__UDEC_MASK 0x00000002L
802 #define UVD_CGC_GATE__MPEG2_MASK 0x00000004L
803 #define UVD_CGC_GATE__REGS_MASK 0x00000008L
804 #define UVD_CGC_GATE__RBC_MASK 0x00000010L
805 #define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L
806 #define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L
807 #define UVD_CGC_GATE__IDCT_MASK 0x00000080L
808 #define UVD_CGC_GATE__MPRD_MASK 0x00000100L
809 #define UVD_CGC_GATE__MPC_MASK 0x00000200L
810 #define UVD_CGC_GATE__LBSI_MASK 0x00000400L
811 #define UVD_CGC_GATE__LRBBM_MASK 0x00000800L
812 #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L
813 #define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L
814 #define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L
815 #define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L
816 #define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L
817 #define UVD_CGC_GATE__WCB_MASK 0x00020000L
818 #define UVD_CGC_GATE__VCPU_MASK 0x00040000L
819 #define UVD_CGC_GATE__SCPU_MASK 0x00080000L
821 #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0
822 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1
823 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2
824 #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3
825 #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4
826 #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5
827 #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6
828 #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7
829 #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8
830 #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9
831 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
832 #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb
833 #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc
834 #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd
835 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
836 #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf
837 #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10
838 #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11
839 #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12
840 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13
841 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
842 #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15
843 #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16
844 #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17
845 #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18
846 #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19
847 #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a
848 #define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b
849 #define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c
850 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d
851 #define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e
852 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f
853 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L
854 #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L
855 #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L
856 #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L
857 #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L
858 #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L
859 #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L
860 #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L
861 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L
862 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L
863 #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L
864 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L
865 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L
866 #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L
867 #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L
868 #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L
869 #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L
870 #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L
871 #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L
872 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L
873 #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L
874 #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L
875 #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L
876 #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L
877 #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L
878 #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L
879 #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L
880 #define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x08000000L
881 #define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000L
882 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L
883 #define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000L
884 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L
886 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
887 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
888 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
889 #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb
890 #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc
891 #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
892 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
893 #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf
894 #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
895 #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11
896 #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12
897 #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13
898 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
899 #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15
900 #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16
901 #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17
902 #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18
903 #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19
904 #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a
905 #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b
906 #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c
907 #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d
908 #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e
909 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L
910 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
911 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L
912 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L
913 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L
914 #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L
915 #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L
916 #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L
917 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L
918 #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L
919 #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L
920 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L
921 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L
922 #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L
923 #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L
924 #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L
925 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L
926 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L
927 #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L
928 #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L
929 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L
930 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L
931 #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L
933 #define UVD_GP_SCRATCH0__DATA__SHIFT 0x0
934 #define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL
936 #define UVD_GP_SCRATCH1__DATA__SHIFT 0x0
937 #define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL
939 #define UVD_GP_SCRATCH2__DATA__SHIFT 0x0
940 #define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL
942 #define UVD_GP_SCRATCH3__DATA__SHIFT 0x0
943 #define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL
945 #define UVD_GP_SCRATCH4__DATA__SHIFT 0x0
946 #define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL
948 #define UVD_GP_SCRATCH5__DATA__SHIFT 0x0
949 #define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL
951 #define UVD_GP_SCRATCH6__DATA__SHIFT 0x0
952 #define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL
954 #define UVD_GP_SCRATCH7__DATA__SHIFT 0x0
955 #define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL
956 //UVD_LMI_VCPU_CACHE_VMID
957 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0
958 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL
960 #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0
961 #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1
962 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
963 #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
964 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
965 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
966 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
967 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
968 #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L
969 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L
970 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L
971 #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L
972 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L
973 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
974 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L
975 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L
977 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
978 #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
979 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
980 #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
981 #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L
982 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L
983 #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L
984 #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L
986 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
987 #define JPEG_CGC_CTRL__JPEG2_MODE__SHIFT 0x1
988 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
989 #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
990 #define JPEG_CGC_CTRL__JPEG_MODE__SHIFT 0x1f
991 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L
992 #define JPEG_CGC_CTRL__JPEG2_MODE_MASK 0x00000002L
993 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
994 #define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L
995 #define JPEG_CGC_CTRL__JPEG_MODE_MASK 0x80000000L
997 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
998 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8
999 #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9
1000 #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
1001 #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
1002 #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
1003 #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
1004 #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
1005 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
1006 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16
1007 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17
1008 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18
1009 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19
1010 #define UVD_LMI_CTRL__RFU__SHIFT 0x1b
1011 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL
1012 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L
1013 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L
1014 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L
1015 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L
1016 #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L
1017 #define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L
1018 #define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L
1019 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L
1020 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L
1021 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L
1022 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L
1023 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L
1024 #define UVD_LMI_CTRL__RFU_MASK 0xF8000000L
1026 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
1027 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
1028 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4
1029 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6
1030 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8
1031 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
1032 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc
1033 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe
1034 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10
1035 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12
1036 #define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP__SHIFT 0x14
1037 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16
1038 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18
1039 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a
1040 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c
1041 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e
1042 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L
1043 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL
1044 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L
1045 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L
1046 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L
1047 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L
1048 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L
1049 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L
1050 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L
1051 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L
1052 #define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP_MASK 0x00300000L
1053 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0x00C00000L
1054 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L
1055 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L
1056 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L
1057 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L
1059 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
1060 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
1061 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
1062 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
1063 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
1064 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL
1065 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L
1066 #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L
1067 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L
1068 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L
1070 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
1071 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6
1072 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
1073 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL
1074 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L
1075 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L
1077 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0
1078 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
1079 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc
1080 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
1081 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18
1082 #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL
1083 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L
1084 #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L
1085 #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L
1086 #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L
1088 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
1089 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6
1090 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc
1091 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL
1092 #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L
1093 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L
1095 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0
1096 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
1097 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
1098 #define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L
1099 #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L
1100 #define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L
1102 #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0
1103 #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4
1104 #define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L
1105 #define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L
1107 #define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0
1108 #define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1
1109 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f
1110 #define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L
1111 #define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL
1112 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L
1113 //UVD_GPCOM_SYS_DATA0
1114 #define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0
1115 #define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL
1116 //UVD_GPCOM_SYS_DATA1
1117 #define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0
1118 #define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL
1119 //UVD_VCPU_CACHE_OFFSET0
1120 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
1121 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL
1122 //UVD_VCPU_CACHE_SIZE0
1123 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0
1124 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL
1125 //UVD_VCPU_CACHE_OFFSET1
1126 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
1127 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL
1128 //UVD_VCPU_CACHE_SIZE1
1129 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0
1130 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL
1131 //UVD_VCPU_CACHE_OFFSET2
1132 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0
1133 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL
1134 //UVD_VCPU_CACHE_SIZE2
1135 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
1136 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL
1138 #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9
1139 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L
1141 #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0
1142 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1
1143 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
1144 #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3
1145 #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4
1146 #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5
1147 #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6
1148 #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7
1149 #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8
1150 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
1151 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd
1152 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe
1153 #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf
1154 #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10
1155 #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11
1156 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12
1157 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13
1158 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14
1159 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15
1160 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16
1161 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a
1162 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b
1163 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c
1164 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d
1165 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e
1166 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f
1167 #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L
1168 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L
1169 #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L
1170 #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L
1171 #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L
1172 #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x00000020L
1173 #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L
1174 #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L
1175 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L
1176 #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L
1177 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L
1178 #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L
1179 #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L
1180 #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L
1181 #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L
1182 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L
1183 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L
1184 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L
1185 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L
1186 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L
1187 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L
1188 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L
1189 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L
1190 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L
1191 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L
1192 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L
1193 //UVD_LMI_RBC_IB_VMID
1194 #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0
1195 #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL
1197 #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4
1198 #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L
1200 #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4
1201 #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
1203 #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4
1204 #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
1205 //UVD_RBC_RB_WPTR_CNTL
1206 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0
1207 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL
1208 //UVD_RBC_WPTR_STATUS
1209 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4
1210 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L
1212 #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0
1213 #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8
1214 #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10
1215 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
1216 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18
1217 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c
1218 #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL
1219 #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L
1220 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L
1221 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L
1222 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L
1223 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L
1224 //UVD_RBC_RB_RPTR_ADDR
1225 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0
1226 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL
1228 #define UVD_STATUS__RBC_BUSY__SHIFT 0x0
1229 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
1230 #define UVD_STATUS__AVP_BUSY__SHIFT 0x8
1231 #define UVD_STATUS__IDCT_BUSY__SHIFT 0x9
1232 #define UVD_STATUS__IDCT_CTL_ACK__SHIFT 0xb
1233 #define UVD_STATUS__UVD_CTL_ACK__SHIFT 0xc
1234 #define UVD_STATUS__AVP_BLOCK_ACK__SHIFT 0xd
1235 #define UVD_STATUS__IDCT_BLOCK_ACK__SHIFT 0xe
1236 #define UVD_STATUS__UVD_BLOCK_ACK__SHIFT 0xf
1237 #define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10
1238 #define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f
1239 #define UVD_STATUS__RBC_BUSY_MASK 0x00000001L
1240 #define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL
1241 #define UVD_STATUS__AVP_BUSY_MASK 0x00000100L
1242 #define UVD_STATUS__IDCT_BUSY_MASK 0x00000200L
1243 #define UVD_STATUS__IDCT_CTL_ACK_MASK 0x00000800L
1244 #define UVD_STATUS__UVD_CTL_ACK_MASK 0x00001000L
1245 #define UVD_STATUS__AVP_BLOCK_ACK_MASK 0x00002000L
1246 #define UVD_STATUS__IDCT_BLOCK_ACK_MASK 0x00004000L
1247 #define UVD_STATUS__UVD_BLOCK_ACK_MASK 0x00008000L
1248 #define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L
1249 #define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L
1250 //UVD_SEMA_TIMEOUT_STATUS
1251 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0
1252 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1
1253 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
1254 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3
1255 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L
1256 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L
1257 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L
1258 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L
1259 //UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
1260 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0
1261 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1
1262 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
1263 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L
1264 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL
1265 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
1266 //UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
1267 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0
1268 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1
1269 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
1270 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L
1271 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL
1272 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
1273 //UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
1274 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0
1275 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1
1276 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
1277 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L
1278 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL
1279 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L
1281 #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0
1282 #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL
1284 #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0
1285 #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL
1286 //UVD_RBC_WPTR_POLL_CNTL
1287 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0
1288 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1289 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL
1290 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
1291 //UVD_RBC_WPTR_POLL_ADDR
1292 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2
1293 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL
1295 #define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6
1296 #define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L
1298 #define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0
1299 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL
1301 #define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4
1302 #define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L
1304 #define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4
1305 #define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L