2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 #ifndef _dcn_1_0_OFFSET_HEADER
22 #define _dcn_1_0_OFFSET_HEADER
26 // addressBlock: dce_dc_hda_azcontroller_azdec
27 // base address: 0x1300000
30 // addressBlock: dce_dc_hda_azendpoint_azdec
31 // base address: 0x1300000
34 // addressBlock: dce_dc_hda_azinputendpoint_azdec
35 // base address: 0x1300000
38 // addressBlock: dce_dc_hda_azroot_azdec
39 // base address: 0x1300000
42 // addressBlock: dce_dc_hda_azstream0_azdec
43 // base address: 0x1300000
46 // addressBlock: dce_dc_hda_azstream1_azdec
47 // base address: 0x1300020
50 // addressBlock: dce_dc_hda_azstream2_azdec
51 // base address: 0x1300040
54 // addressBlock: dce_dc_hda_azstream3_azdec
55 // base address: 0x1300060
58 // addressBlock: dce_dc_hda_azstream4_azdec
59 // base address: 0x1300080
62 // addressBlock: dce_dc_hda_azstream5_azdec
63 // base address: 0x13000a0
66 // addressBlock: dce_dc_hda_azstream6_azdec
67 // base address: 0x13000c0
70 // addressBlock: dce_dc_hda_azstream7_azdec
71 // base address: 0x13000e0
74 // addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
76 #define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
77 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
78 #define mmVGA_MEM_READ_PAGE_ADDR 0x0001
79 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
82 // addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
83 // base address: 0x3b4
84 #define mmCRTC8_IDX 0x002d
85 #define mmCRTC8_IDX_BASE_IDX 1
86 #define mmCRTC8_DATA 0x002d
87 #define mmCRTC8_DATA_BASE_IDX 1
88 #define mmGENFC_WT 0x002e
89 #define mmGENFC_WT_BASE_IDX 1
90 #define mmGENS1 0x002e
91 #define mmGENS1_BASE_IDX 1
92 #define mmATTRDW 0x0030
93 #define mmATTRDW_BASE_IDX 1
94 #define mmATTRX 0x0030
95 #define mmATTRX_BASE_IDX 1
96 #define mmATTRDR 0x0030
97 #define mmATTRDR_BASE_IDX 1
98 #define mmGENMO_WT 0x0030
99 #define mmGENMO_WT_BASE_IDX 1
100 #define mmGENS0 0x0030
101 #define mmGENS0_BASE_IDX 1
102 #define mmGENENB 0x0030
103 #define mmGENENB_BASE_IDX 1
104 #define mmSEQ8_IDX 0x0031
105 #define mmSEQ8_IDX_BASE_IDX 1
106 #define mmSEQ8_DATA 0x0031
107 #define mmSEQ8_DATA_BASE_IDX 1
108 #define mmDAC_MASK 0x0031
109 #define mmDAC_MASK_BASE_IDX 1
110 #define mmDAC_R_INDEX 0x0031
111 #define mmDAC_R_INDEX_BASE_IDX 1
112 #define mmDAC_W_INDEX 0x0032
113 #define mmDAC_W_INDEX_BASE_IDX 1
114 #define mmDAC_DATA 0x0032
115 #define mmDAC_DATA_BASE_IDX 1
116 #define mmGENFC_RD 0x0032
117 #define mmGENFC_RD_BASE_IDX 1
118 #define mmGENMO_RD 0x0033
119 #define mmGENMO_RD_BASE_IDX 1
120 #define mmGRPH8_IDX 0x0033
121 #define mmGRPH8_IDX_BASE_IDX 1
122 #define mmGRPH8_DATA 0x0033
123 #define mmGRPH8_DATA_BASE_IDX 1
124 #define mmCRTC8_IDX_1 0x0035
125 #define mmCRTC8_IDX_1_BASE_IDX 1
126 #define mmCRTC8_DATA_1 0x0035
127 #define mmCRTC8_DATA_1_BASE_IDX 1
128 #define mmGENFC_WT_1 0x0036
129 #define mmGENFC_WT_1_BASE_IDX 1
130 #define mmGENS1_1 0x0036
131 #define mmGENS1_1_BASE_IDX 1
134 // addressBlock: dce_dc_hda_azcontroller_azdec
136 #define mmCORB_WRITE_POINTER 0x0000
137 #define mmCORB_WRITE_POINTER_BASE_IDX 0
138 #define mmCORB_READ_POINTER 0x0000
139 #define mmCORB_READ_POINTER_BASE_IDX 0
140 #define mmCORB_CONTROL 0x0001
141 #define mmCORB_CONTROL_BASE_IDX 0
142 #define mmCORB_STATUS 0x0001
143 #define mmCORB_STATUS_BASE_IDX 0
144 #define mmCORB_SIZE 0x0001
145 #define mmCORB_SIZE_BASE_IDX 0
146 #define mmRIRB_LOWER_BASE_ADDRESS 0x0002
147 #define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
148 #define mmRIRB_UPPER_BASE_ADDRESS 0x0003
149 #define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
150 #define mmRIRB_WRITE_POINTER 0x0004
151 #define mmRIRB_WRITE_POINTER_BASE_IDX 0
152 #define mmRESPONSE_INTERRUPT_COUNT 0x0004
153 #define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0
154 #define mmRIRB_CONTROL 0x0005
155 #define mmRIRB_CONTROL_BASE_IDX 0
156 #define mmRIRB_STATUS 0x0005
157 #define mmRIRB_STATUS_BASE_IDX 0
158 #define mmRIRB_SIZE 0x0005
159 #define mmRIRB_SIZE_BASE_IDX 0
160 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
161 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
162 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
163 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
164 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
165 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
166 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
167 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
168 #define mmIMMEDIATE_COMMAND_STATUS 0x0008
169 #define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0
170 #define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a
171 #define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
172 #define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b
173 #define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
174 #define mmWALL_CLOCK_COUNTER_ALIAS 0x074c
175 #define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
178 // addressBlock: dce_dc_hda_azendpoint_azdec
180 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
181 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
182 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
183 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
186 // addressBlock: dce_dc_hda_azinputendpoint_azdec
188 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006
189 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0
190 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006
191 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0
194 // addressBlock: dce_dc_hda_azroot_azdec
196 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
197 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
198 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
199 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
202 // addressBlock: dce_dc_hda_azstream0_azdec
204 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e
205 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
206 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f
207 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
208 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010
209 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
210 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011
211 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
212 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012
213 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
214 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012
215 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
216 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014
217 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
218 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015
219 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
220 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761
221 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
224 // addressBlock: dce_dc_hda_azstream1_azdec
225 // base address: 0x20
226 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016
227 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
228 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017
229 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
230 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018
231 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
232 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019
233 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
234 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a
235 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
236 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a
237 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
238 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c
239 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
240 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d
241 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
242 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769
243 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
246 // addressBlock: dce_dc_hda_azstream2_azdec
247 // base address: 0x40
248 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e
249 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
250 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f
251 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
252 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020
253 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
254 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021
255 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
256 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022
257 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
258 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022
259 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
260 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024
261 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
262 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025
263 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
264 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771
265 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
268 // addressBlock: dce_dc_hda_azstream3_azdec
269 // base address: 0x60
270 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026
271 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
272 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027
273 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
274 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028
275 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
276 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029
277 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
278 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a
279 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
280 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a
281 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
282 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c
283 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
284 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d
285 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
286 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779
287 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
290 // addressBlock: dce_dc_hda_azstream4_azdec
291 // base address: 0x80
292 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e
293 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
294 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f
295 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
296 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030
297 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
298 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031
299 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
300 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032
301 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
302 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032
303 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
304 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034
305 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
306 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035
307 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
308 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781
309 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
312 // addressBlock: dce_dc_hda_azstream5_azdec
313 // base address: 0xa0
314 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036
315 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
316 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037
317 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
318 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038
319 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
320 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039
321 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
322 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a
323 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
324 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a
325 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
326 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c
327 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
328 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d
329 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
330 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789
331 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
334 // addressBlock: dce_dc_hda_azstream6_azdec
335 // base address: 0xc0
336 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e
337 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
338 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f
339 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
340 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040
341 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
342 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041
343 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
344 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042
345 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
346 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042
347 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
348 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044
349 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
350 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045
351 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
352 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791
353 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
356 // addressBlock: dce_dc_hda_azstream7_azdec
357 // base address: 0xe0
358 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046
359 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
360 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047
361 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
362 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048
363 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
364 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049
365 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
366 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a
367 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
368 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a
369 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
370 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c
371 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
372 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d
373 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
374 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799
375 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
378 // addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
379 // base address: 0x48
380 //#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000
381 //#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001
384 // addressBlock: dce_dc_mmhubbub_vga_dispdec
386 //#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000
387 //#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001
388 #define mmVGA_RENDER_CONTROL 0x0000
389 #define mmVGA_RENDER_CONTROL_BASE_IDX 1
390 #define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
391 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
392 #define mmVGA_MODE_CONTROL 0x0002
393 #define mmVGA_MODE_CONTROL_BASE_IDX 1
394 #define mmVGA_SURFACE_PITCH_SELECT 0x0003
395 #define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
396 #define mmVGA_MEMORY_BASE_ADDRESS 0x0004
397 #define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
398 #define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006
399 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
400 #define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008
401 #define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
402 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009
403 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
404 #define mmVGA_HDP_CONTROL 0x000a
405 #define mmVGA_HDP_CONTROL_BASE_IDX 1
406 #define mmVGA_CACHE_CONTROL 0x000b
407 #define mmVGA_CACHE_CONTROL_BASE_IDX 1
408 #define mmD1VGA_CONTROL 0x000c
409 #define mmD1VGA_CONTROL_BASE_IDX 1
410 #define mmD2VGA_CONTROL 0x000e
411 #define mmD2VGA_CONTROL_BASE_IDX 1
412 #define mmVGA_STATUS 0x0010
413 #define mmVGA_STATUS_BASE_IDX 1
414 #define mmVGA_INTERRUPT_CONTROL 0x0011
415 #define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1
416 #define mmVGA_STATUS_CLEAR 0x0012
417 #define mmVGA_STATUS_CLEAR_BASE_IDX 1
418 #define mmVGA_INTERRUPT_STATUS 0x0013
419 #define mmVGA_INTERRUPT_STATUS_BASE_IDX 1
420 #define mmVGA_MAIN_CONTROL 0x0014
421 #define mmVGA_MAIN_CONTROL_BASE_IDX 1
422 #define mmVGA_TEST_CONTROL 0x0015
423 #define mmVGA_TEST_CONTROL_BASE_IDX 1
424 #define mmVGA_QOS_CTRL 0x0018
425 #define mmVGA_QOS_CTRL_BASE_IDX 1
426 //#define mmVGA_CRTC8_IDX 0x002d
427 //#define mmVGA_CRTC8_DATA 0x002d
428 //#define mmVGA_GENFC_WT 0x002e
429 //#define mmVGA_GENS1 0x002e
430 //#define mmVGA_ATTRDW 0x0030
431 //#define mmVGA_ATTRX 0x0030
432 //#define mmVGA_ATTRDR 0x0030
433 //#define mmVGA_GENMO_WT 0x0030
434 //#define mmVGA_GENS0 0x0030
435 //#define mmVGA_GENENB 0x0030
436 //#define mmVGA_SEQ8_IDX 0x0031
437 //#define mmVGA_SEQ8_DATA 0x0031
438 //#define mmVGA_DAC_MASK 0x0031
439 //#define mmVGA_DAC_R_INDEX 0x0031
440 //#define mmVGA_DAC_W_INDEX 0x0032
441 //#define mmVGA_DAC_DATA 0x0032
442 //#define mmVGA_GENFC_RD 0x0032
443 //#define mmVGA_GENMO_RD 0x0033
444 //#define mmVGA_GRPH8_IDX 0x0033
445 //#define mmVGA_GRPH8_DATA 0x0033
446 //#define mmVGA_CRTC8_IDX_1 0x0035
447 //#define mmVGA_CRTC8_DATA_1 0x0035
448 //#define mmVGA_GENFC_WT_1 0x0036
449 //#define mmVGA_GENS1_1 0x0036
450 #define mmD3VGA_CONTROL 0x0038
451 #define mmD3VGA_CONTROL_BASE_IDX 1
452 #define mmD4VGA_CONTROL 0x0039
453 #define mmD4VGA_CONTROL_BASE_IDX 1
454 #define mmD5VGA_CONTROL 0x003a
455 #define mmD5VGA_CONTROL_BASE_IDX 1
456 #define mmD6VGA_CONTROL 0x003b
457 #define mmD6VGA_CONTROL_BASE_IDX 1
458 #define mmVGA_SOURCE_SELECT 0x003c
459 #define mmVGA_SOURCE_SELECT_BASE_IDX 1
462 // addressBlock: dce_dc_dccg_dccg_dispdec
464 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
465 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
466 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
467 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
468 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
469 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
470 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
471 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
472 #define mmDP_DTO_DBUF_EN 0x0044
473 #define mmDP_DTO_DBUF_EN_BASE_IDX 1
474 #define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
475 #define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
476 #define mmREFCLK_CNTL 0x0049
477 #define mmREFCLK_CNTL_BASE_IDX 1
478 #define mmMIPI_CLK_CNTL 0x004a
479 #define mmMIPI_CLK_CNTL_BASE_IDX 1
480 #define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
481 #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
482 #define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
483 #define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1
484 #define mmDCCG_PERFMON_CNTL2 0x004e
485 #define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
486 #define mmDSICLK_CGTT_BLK_CTRL_REG 0x004f
487 #define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
488 #define mmDCCG_CBUS_WRCMD_DELAY 0x0050
489 #define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX 1
490 #define mmDCCG_DS_DTO_INCR 0x0053
491 #define mmDCCG_DS_DTO_INCR_BASE_IDX 1
492 #define mmDCCG_DS_DTO_MODULO 0x0054
493 #define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
494 #define mmDCCG_DS_CNTL 0x0055
495 #define mmDCCG_DS_CNTL_BASE_IDX 1
496 #define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
497 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
498 #define mmSYMCLKG_CLOCK_ENABLE 0x0057
499 #define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX 1
500 #define mmDPREFCLK_CNTL 0x0058
501 #define mmDPREFCLK_CNTL_BASE_IDX 1
502 #define mmAOMCLK0_CNTL 0x0059
503 #define mmAOMCLK0_CNTL_BASE_IDX 1
504 #define mmAOMCLK1_CNTL 0x005a
505 #define mmAOMCLK1_CNTL_BASE_IDX 1
506 #define mmAOMCLK2_CNTL 0x005b
507 #define mmAOMCLK2_CNTL_BASE_IDX 1
508 #define mmDCCG_AUDIO_DTO2_PHASE 0x005c
509 #define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1
510 #define mmDCCG_AUDIO_DTO2_MODULO 0x005d
511 #define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1
512 #define mmDCE_VERSION 0x005e
513 #define mmDCE_VERSION_BASE_IDX 1
514 #define mmPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
515 #define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
516 #define mmDCCG_GTC_CNTL 0x0060
517 #define mmDCCG_GTC_CNTL_BASE_IDX 1
518 #define mmDCCG_GTC_DTO_INCR 0x0061
519 #define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
520 #define mmDCCG_GTC_DTO_MODULO 0x0062
521 #define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
522 #define mmDCCG_GTC_CURRENT 0x0063
523 #define mmDCCG_GTC_CURRENT_BASE_IDX 1
524 #define mmMIPI_DTO_CNTL 0x0065
525 #define mmMIPI_DTO_CNTL_BASE_IDX 1
526 #define mmMIPI_DTO_PHASE 0x0066
527 #define mmMIPI_DTO_PHASE_BASE_IDX 1
528 #define mmMIPI_DTO_MODULO 0x0067
529 #define mmMIPI_DTO_MODULO_BASE_IDX 1
530 #define mmDAC_CLK_ENABLE 0x0068
531 #define mmDAC_CLK_ENABLE_BASE_IDX 1
532 #define mmDVO_CLK_ENABLE 0x0069
533 #define mmDVO_CLK_ENABLE_BASE_IDX 1
534 #define mmAVSYNC_COUNTER_WRITE 0x006a
535 #define mmAVSYNC_COUNTER_WRITE_BASE_IDX 1
536 #define mmAVSYNC_COUNTER_CONTROL 0x006b
537 #define mmAVSYNC_COUNTER_CONTROL_BASE_IDX 1
538 #define mmAVSYNC_COUNTER_READ 0x006f
539 #define mmAVSYNC_COUNTER_READ_BASE_IDX 1
540 #define mmMILLISECOND_TIME_BASE_DIV 0x0070
541 #define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
542 #define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
543 #define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
544 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
545 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
546 #define mmDCCG_PERFMON_CNTL 0x0073
547 #define mmDCCG_PERFMON_CNTL_BASE_IDX 1
548 #define mmDCCG_GATE_DISABLE_CNTL 0x0074
549 #define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
550 #define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
551 #define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
552 #define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076
553 #define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
554 #define mmDCCG_CAC_STATUS 0x0077
555 #define mmDCCG_CAC_STATUS_BASE_IDX 1
556 #define mmPIXCLK1_RESYNC_CNTL 0x0078
557 #define mmPIXCLK1_RESYNC_CNTL_BASE_IDX 1
558 #define mmPIXCLK2_RESYNC_CNTL 0x0079
559 #define mmPIXCLK2_RESYNC_CNTL_BASE_IDX 1
560 #define mmPIXCLK0_RESYNC_CNTL 0x007a
561 #define mmPIXCLK0_RESYNC_CNTL_BASE_IDX 1
562 #define mmMICROSECOND_TIME_BASE_DIV 0x007b
563 #define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
564 #define mmDCCG_GATE_DISABLE_CNTL2 0x007c
565 #define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
566 #define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
567 #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
568 #define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
569 #define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
570 #define mmDCCG_DISP_CNTL_REG 0x007f
571 #define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
572 #define mmOTG0_PIXEL_RATE_CNTL 0x0080
573 #define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1
574 #define mmDP_DTO0_PHASE 0x0081
575 #define mmDP_DTO0_PHASE_BASE_IDX 1
576 #define mmDP_DTO0_MODULO 0x0082
577 #define mmDP_DTO0_MODULO_BASE_IDX 1
578 #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083
579 #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
580 #define mmOTG1_PIXEL_RATE_CNTL 0x0084
581 #define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1
582 #define mmDP_DTO1_PHASE 0x0085
583 #define mmDP_DTO1_PHASE_BASE_IDX 1
584 #define mmDP_DTO1_MODULO 0x0086
585 #define mmDP_DTO1_MODULO_BASE_IDX 1
586 #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087
587 #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
588 #define mmOTG2_PIXEL_RATE_CNTL 0x0088
589 #define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1
590 #define mmDP_DTO2_PHASE 0x0089
591 #define mmDP_DTO2_PHASE_BASE_IDX 1
592 #define mmDP_DTO2_MODULO 0x008a
593 #define mmDP_DTO2_MODULO_BASE_IDX 1
594 #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b
595 #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
596 #define mmOTG3_PIXEL_RATE_CNTL 0x008c
597 #define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1
598 #define mmDP_DTO3_PHASE 0x008d
599 #define mmDP_DTO3_PHASE_BASE_IDX 1
600 #define mmDP_DTO3_MODULO 0x008e
601 #define mmDP_DTO3_MODULO_BASE_IDX 1
602 #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f
603 #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
604 #define mmOTG4_PIXEL_RATE_CNTL 0x0090
605 #define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX 1
606 #define mmDP_DTO4_PHASE 0x0091
607 #define mmDP_DTO4_PHASE_BASE_IDX 1
608 #define mmDP_DTO4_MODULO 0x0092
609 #define mmDP_DTO4_MODULO_BASE_IDX 1
610 #define mmOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093
611 #define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
612 #define mmOTG5_PIXEL_RATE_CNTL 0x0094
613 #define mmOTG5_PIXEL_RATE_CNTL_BASE_IDX 1
614 #define mmDP_DTO5_PHASE 0x0095
615 #define mmDP_DTO5_PHASE_BASE_IDX 1
616 #define mmDP_DTO5_MODULO 0x0096
617 #define mmDP_DTO5_MODULO_BASE_IDX 1
618 #define mmOTG5_PHYPLL_PIXEL_RATE_CNTL 0x0097
619 #define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
620 #define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098
621 #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
622 #define mmSYMCLKA_CLOCK_ENABLE 0x00a0
623 #define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
624 #define mmSYMCLKB_CLOCK_ENABLE 0x00a1
625 #define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
626 #define mmSYMCLKC_CLOCK_ENABLE 0x00a2
627 #define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
628 #define mmSYMCLKD_CLOCK_ENABLE 0x00a3
629 #define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
630 #define mmSYMCLKE_CLOCK_ENABLE 0x00a4
631 #define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1
632 #define mmSYMCLKF_CLOCK_ENABLE 0x00a5
633 #define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1
634 #define mmDCCG_SOFT_RESET 0x00a6
635 #define mmDCCG_SOFT_RESET_BASE_IDX 1
636 #define mmDVOACLKD_CNTL 0x00a8
637 #define mmDVOACLKD_CNTL_BASE_IDX 1
638 #define mmDVOACLKC_MVP_CNTL 0x00a9
639 #define mmDVOACLKC_MVP_CNTL_BASE_IDX 1
640 #define mmDVOACLKC_CNTL 0x00aa
641 #define mmDVOACLKC_CNTL_BASE_IDX 1
642 #define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
643 #define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
644 #define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
645 #define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
646 #define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
647 #define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
648 #define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
649 #define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
650 #define mmDCCG_AUDIO_DTO1_MODULE 0x00af
651 #define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
652 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0
653 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1
654 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1
655 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1
656 #define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2
657 #define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1
658 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3
659 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1
660 #define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4
661 #define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1
662 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5
663 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1
664 #define mmDCCG_VSYNC_CNT_CTRL 0x00b8
665 #define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1
666 #define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9
667 #define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1
668 #define mmDCCG_TEST_CLK_SEL 0x00be
669 #define mmDCCG_TEST_CLK_SEL_BASE_IDX 1
672 // addressBlock: dce_dc_dccg_dccg_dfs_dispdec
674 #define mmDENTIST_DISPCLK_CNTL 0x0064
675 #define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
678 // addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
680 #define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000
681 #define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
682 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001
683 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
684 #define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002
685 #define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
686 #define mmDC_PERFMON0_PERFMON_CNTL 0x0003
687 #define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
688 #define mmDC_PERFMON0_PERFMON_CNTL2 0x0004
689 #define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
690 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005
691 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
692 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006
693 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
694 #define mmDC_PERFMON0_PERFMON_HI 0x0007
695 #define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
696 #define mmDC_PERFMON0_PERFMON_LOW 0x0008
697 #define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
700 // addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
701 // base address: 0x30
702 #define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c
703 #define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
704 #define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d
705 #define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2
706 #define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e
707 #define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2
708 #define mmDC_PERFMON1_PERFMON_CNTL 0x000f
709 #define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2
710 #define mmDC_PERFMON1_PERFMON_CNTL2 0x0010
711 #define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2
712 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011
713 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
714 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012
715 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2
716 #define mmDC_PERFMON1_PERFMON_HI 0x0013
717 #define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2
718 #define mmDC_PERFMON1_PERFMON_LOW 0x0014
719 #define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2
722 // addressBlock: dce_dc_dccg_dccg_pll_dispdec
724 #define mmPLL_MACRO_CNTL_RESERVED0 0x0018
725 #define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2
726 #define mmPLL_MACRO_CNTL_RESERVED1 0x0019
727 #define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2
728 #define mmPLL_MACRO_CNTL_RESERVED2 0x001a
729 #define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2
730 #define mmPLL_MACRO_CNTL_RESERVED3 0x001b
731 #define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2
732 #define mmPLL_MACRO_CNTL_RESERVED4 0x001c
733 #define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2
734 #define mmPLL_MACRO_CNTL_RESERVED5 0x001d
735 #define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2
736 #define mmPLL_MACRO_CNTL_RESERVED6 0x001e
737 #define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2
738 #define mmPLL_MACRO_CNTL_RESERVED7 0x001f
739 #define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2
740 #define mmPLL_MACRO_CNTL_RESERVED8 0x0020
741 #define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2
742 #define mmPLL_MACRO_CNTL_RESERVED9 0x0021
743 #define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2
744 #define mmPLL_MACRO_CNTL_RESERVED10 0x0022
745 #define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2
746 #define mmPLL_MACRO_CNTL_RESERVED11 0x0023
747 #define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2
748 #define mmPLL_MACRO_CNTL_RESERVED12 0x0024
749 #define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2
750 #define mmPLL_MACRO_CNTL_RESERVED13 0x0025
751 #define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2
752 #define mmPLL_MACRO_CNTL_RESERVED14 0x0026
753 #define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2
754 #define mmPLL_MACRO_CNTL_RESERVED15 0x0027
755 #define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2
756 #define mmPLL_MACRO_CNTL_RESERVED16 0x0028
757 #define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2
758 #define mmPLL_MACRO_CNTL_RESERVED17 0x0029
759 #define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2
760 #define mmPLL_MACRO_CNTL_RESERVED18 0x002a
761 #define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2
762 #define mmPLL_MACRO_CNTL_RESERVED19 0x002b
763 #define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2
764 #define mmPLL_MACRO_CNTL_RESERVED20 0x002c
765 #define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2
766 #define mmPLL_MACRO_CNTL_RESERVED21 0x002d
767 #define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2
768 #define mmPLL_MACRO_CNTL_RESERVED22 0x002e
769 #define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2
770 #define mmPLL_MACRO_CNTL_RESERVED23 0x002f
771 #define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2
772 #define mmPLL_MACRO_CNTL_RESERVED24 0x0030
773 #define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2
774 #define mmPLL_MACRO_CNTL_RESERVED25 0x0031
775 #define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2
776 #define mmPLL_MACRO_CNTL_RESERVED26 0x0032
777 #define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2
778 #define mmPLL_MACRO_CNTL_RESERVED27 0x0033
779 #define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2
780 #define mmPLL_MACRO_CNTL_RESERVED28 0x0034
781 #define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2
782 #define mmPLL_MACRO_CNTL_RESERVED29 0x0035
783 #define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2
784 #define mmPLL_MACRO_CNTL_RESERVED30 0x0036
785 #define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2
786 #define mmPLL_MACRO_CNTL_RESERVED31 0x0037
787 #define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2
788 #define mmPLL_MACRO_CNTL_RESERVED32 0x0038
789 #define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2
790 #define mmPLL_MACRO_CNTL_RESERVED33 0x0039
791 #define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2
792 #define mmPLL_MACRO_CNTL_RESERVED34 0x003a
793 #define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2
794 #define mmPLL_MACRO_CNTL_RESERVED35 0x003b
795 #define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2
796 #define mmPLL_MACRO_CNTL_RESERVED36 0x003c
797 #define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2
798 #define mmPLL_MACRO_CNTL_RESERVED37 0x003d
799 #define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2
800 #define mmPLL_MACRO_CNTL_RESERVED38 0x003e
801 #define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2
802 #define mmPLL_MACRO_CNTL_RESERVED39 0x003f
803 #define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2
804 #define mmPLL_MACRO_CNTL_RESERVED40 0x0040
805 #define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2
806 #define mmPLL_MACRO_CNTL_RESERVED41 0x0041
807 #define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2
810 // addressBlock: dce_dc_dmu_rbbmif_dispdec
812 #define mmRBBMIF_TIMEOUT 0x0055
813 #define mmRBBMIF_TIMEOUT_BASE_IDX 2
814 #define mmRBBMIF_STATUS 0x0056
815 #define mmRBBMIF_STATUS_BASE_IDX 2
816 #define mmRBBMIF_INT_STATUS 0x0057
817 #define mmRBBMIF_INT_STATUS_BASE_IDX 2
818 #define mmRBBMIF_TIMEOUT_DIS 0x0058
819 #define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
820 #define mmRBBMIF_STATUS_FLAG 0x0059
821 #define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
824 // addressBlock: dce_dc_dmu_dc_pg_dispdec
826 #define mmDOMAIN0_PG_CONFIG 0x008a
827 #define mmDOMAIN0_PG_CONFIG_BASE_IDX 2
828 #define mmDOMAIN0_PG_STATUS 0x008b
829 #define mmDOMAIN0_PG_STATUS_BASE_IDX 2
830 #define mmDOMAIN1_PG_CONFIG 0x008c
831 #define mmDOMAIN1_PG_CONFIG_BASE_IDX 2
832 #define mmDOMAIN1_PG_STATUS 0x008d
833 #define mmDOMAIN1_PG_STATUS_BASE_IDX 2
834 #define mmDOMAIN2_PG_CONFIG 0x008e
835 #define mmDOMAIN2_PG_CONFIG_BASE_IDX 2
836 #define mmDOMAIN2_PG_STATUS 0x008f
837 #define mmDOMAIN2_PG_STATUS_BASE_IDX 2
838 #define mmDOMAIN3_PG_CONFIG 0x0090
839 #define mmDOMAIN3_PG_CONFIG_BASE_IDX 2
840 #define mmDOMAIN3_PG_STATUS 0x0091
841 #define mmDOMAIN3_PG_STATUS_BASE_IDX 2
842 #define mmDOMAIN4_PG_CONFIG 0x0092
843 #define mmDOMAIN4_PG_CONFIG_BASE_IDX 2
844 #define mmDOMAIN4_PG_STATUS 0x0093
845 #define mmDOMAIN4_PG_STATUS_BASE_IDX 2
846 #define mmDOMAIN5_PG_CONFIG 0x0094
847 #define mmDOMAIN5_PG_CONFIG_BASE_IDX 2
848 #define mmDOMAIN5_PG_STATUS 0x0095
849 #define mmDOMAIN5_PG_STATUS_BASE_IDX 2
850 #define mmDOMAIN6_PG_CONFIG 0x0096
851 #define mmDOMAIN6_PG_CONFIG_BASE_IDX 2
852 #define mmDOMAIN6_PG_STATUS 0x0097
853 #define mmDOMAIN6_PG_STATUS_BASE_IDX 2
854 #define mmDOMAIN7_PG_CONFIG 0x0098
855 #define mmDOMAIN7_PG_CONFIG_BASE_IDX 2
856 #define mmDOMAIN7_PG_STATUS 0x0099
857 #define mmDOMAIN7_PG_STATUS_BASE_IDX 2
858 #define mmDOMAIN8_PG_CONFIG 0x009a
859 #define mmDOMAIN8_PG_CONFIG_BASE_IDX 2
860 #define mmDOMAIN8_PG_STATUS 0x009b
861 #define mmDOMAIN8_PG_STATUS_BASE_IDX 2
862 #define mmDOMAIN9_PG_CONFIG 0x009c
863 #define mmDOMAIN9_PG_CONFIG_BASE_IDX 2
864 #define mmDOMAIN9_PG_STATUS 0x009d
865 #define mmDOMAIN9_PG_STATUS_BASE_IDX 2
866 #define mmDOMAIN10_PG_CONFIG 0x009e
867 #define mmDOMAIN10_PG_CONFIG_BASE_IDX 2
868 #define mmDOMAIN10_PG_STATUS 0x009f
869 #define mmDOMAIN10_PG_STATUS_BASE_IDX 2
870 #define mmDOMAIN11_PG_CONFIG 0x00a0
871 #define mmDOMAIN11_PG_CONFIG_BASE_IDX 2
872 #define mmDOMAIN11_PG_STATUS 0x00a1
873 #define mmDOMAIN11_PG_STATUS_BASE_IDX 2
874 #define mmDOMAIN12_PG_CONFIG 0x00a2
875 #define mmDOMAIN12_PG_CONFIG_BASE_IDX 2
876 #define mmDOMAIN12_PG_STATUS 0x00a3
877 #define mmDOMAIN12_PG_STATUS_BASE_IDX 2
878 #define mmDOMAIN13_PG_CONFIG 0x00a4
879 #define mmDOMAIN13_PG_CONFIG_BASE_IDX 2
880 #define mmDOMAIN13_PG_STATUS 0x00a5
881 #define mmDOMAIN13_PG_STATUS_BASE_IDX 2
882 #define mmDOMAIN14_PG_CONFIG 0x00a6
883 #define mmDOMAIN14_PG_CONFIG_BASE_IDX 2
884 #define mmDOMAIN14_PG_STATUS 0x00a7
885 #define mmDOMAIN14_PG_STATUS_BASE_IDX 2
886 #define mmDOMAIN15_PG_CONFIG 0x00a8
887 #define mmDOMAIN15_PG_CONFIG_BASE_IDX 2
888 #define mmDOMAIN15_PG_STATUS 0x00a9
889 #define mmDOMAIN15_PG_STATUS_BASE_IDX 2
890 #define mmDCPG_INTERRUPT_STATUS 0x00aa
891 #define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2
892 #define mmDCPG_INTERRUPT_CONTROL_1 0x00ab
893 #define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2
894 #define mmDCPG_INTERRUPT_CONTROL_2 0x00ac
895 #define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2
896 #define mmDC_IP_REQUEST_CNTL 0x00ad
897 #define mmDC_IP_REQUEST_CNTL_BASE_IDX 2
898 #define mmDC_PGCNTL_STATUS_REG 0x00ae
899 #define mmDC_PGCNTL_STATUS_REG_BASE_IDX 2
902 // addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
903 // base address: 0x2f8
904 #define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be
905 #define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2
906 #define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf
907 #define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2
908 #define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0
909 #define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2
910 #define mmDC_PERFMON2_PERFMON_CNTL 0x00c1
911 #define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2
912 #define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2
913 #define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2
914 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3
915 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
916 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4
917 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2
918 #define mmDC_PERFMON2_PERFMON_HI 0x00c5
919 #define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2
920 #define mmDC_PERFMON2_PERFMON_LOW 0x00c6
921 #define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2
924 // addressBlock: dce_dc_dmu_dmu_misc_dispdec
926 #define mmCC_DC_PIPE_DIS 0x00ca
927 #define mmCC_DC_PIPE_DIS_BASE_IDX 2
928 #define mmDMU_CLK_CNTL 0x00cb
929 #define mmDMU_CLK_CNTL_BASE_IDX 2
930 #define mmDMU_MEM_PWR_CNTL 0x00cc
931 #define mmDMU_MEM_PWR_CNTL_BASE_IDX 2
932 #define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd
933 #define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2
934 #define mmSMU_INTERRUPT_CONTROL 0x00ce
935 #define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2
938 // addressBlock: dce_dc_dmu_dmcu_dispdec
940 #define mmDMCU_CTRL 0x00da
941 #define mmDMCU_CTRL_BASE_IDX 2
942 #define mmDMCU_STATUS 0x00db
943 #define mmDMCU_STATUS_BASE_IDX 2
944 #define mmDMCU_PC_START_ADDR 0x00dc
945 #define mmDMCU_PC_START_ADDR_BASE_IDX 2
946 #define mmDMCU_FW_START_ADDR 0x00dd
947 #define mmDMCU_FW_START_ADDR_BASE_IDX 2
948 #define mmDMCU_FW_END_ADDR 0x00de
949 #define mmDMCU_FW_END_ADDR_BASE_IDX 2
950 #define mmDMCU_FW_ISR_START_ADDR 0x00df
951 #define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2
952 #define mmDMCU_FW_CS_HI 0x00e0
953 #define mmDMCU_FW_CS_HI_BASE_IDX 2
954 #define mmDMCU_FW_CS_LO 0x00e1
955 #define mmDMCU_FW_CS_LO_BASE_IDX 2
956 #define mmDMCU_RAM_ACCESS_CTRL 0x00e2
957 #define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2
958 #define mmDMCU_ERAM_WR_CTRL 0x00e3
959 #define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2
960 #define mmDMCU_ERAM_WR_DATA 0x00e4
961 #define mmDMCU_ERAM_WR_DATA_BASE_IDX 2
962 #define mmDMCU_ERAM_RD_CTRL 0x00e5
963 #define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2
964 #define mmDMCU_ERAM_RD_DATA 0x00e6
965 #define mmDMCU_ERAM_RD_DATA_BASE_IDX 2
966 #define mmDMCU_IRAM_WR_CTRL 0x00e7
967 #define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2
968 #define mmDMCU_IRAM_WR_DATA 0x00e8
969 #define mmDMCU_IRAM_WR_DATA_BASE_IDX 2
970 #define mmDMCU_IRAM_RD_CTRL 0x00e9
971 #define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2
972 #define mmDMCU_IRAM_RD_DATA 0x00ea
973 #define mmDMCU_IRAM_RD_DATA_BASE_IDX 2
974 #define mmDMCU_EVENT_TRIGGER 0x00eb
975 #define mmDMCU_EVENT_TRIGGER_BASE_IDX 2
976 #define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec
977 #define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2
978 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed
979 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2
980 #define mmDMCU_INTERRUPT_STATUS 0x00ee
981 #define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2
982 #define mmDMCU_INTERRUPT_STATUS_1 0x00ef
983 #define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2
984 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0
985 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2
986 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1
987 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2
988 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2
989 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2
990 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3
991 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2
992 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4
993 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2
994 #define mmDC_DMCU_SCRATCH 0x00f5
995 #define mmDC_DMCU_SCRATCH_BASE_IDX 2
996 #define mmDMCU_INT_CNT 0x00f6
997 #define mmDMCU_INT_CNT_BASE_IDX 2
998 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7
999 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2
1000 #define mmDMCU_UC_CLK_GATING_CNTL 0x00f8
1001 #define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2
1002 #define mmMASTER_COMM_DATA_REG1 0x00f9
1003 #define mmMASTER_COMM_DATA_REG1_BASE_IDX 2
1004 #define mmMASTER_COMM_DATA_REG2 0x00fa
1005 #define mmMASTER_COMM_DATA_REG2_BASE_IDX 2
1006 #define mmMASTER_COMM_DATA_REG3 0x00fb
1007 #define mmMASTER_COMM_DATA_REG3_BASE_IDX 2
1008 #define mmMASTER_COMM_CMD_REG 0x00fc
1009 #define mmMASTER_COMM_CMD_REG_BASE_IDX 2
1010 #define mmMASTER_COMM_CNTL_REG 0x00fd
1011 #define mmMASTER_COMM_CNTL_REG_BASE_IDX 2
1012 #define mmSLAVE_COMM_DATA_REG1 0x00fe
1013 #define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2
1014 #define mmSLAVE_COMM_DATA_REG2 0x00ff
1015 #define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2
1016 #define mmSLAVE_COMM_DATA_REG3 0x0100
1017 #define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2
1018 #define mmSLAVE_COMM_CMD_REG 0x0101
1019 #define mmSLAVE_COMM_CMD_REG_BASE_IDX 2
1020 #define mmSLAVE_COMM_CNTL_REG 0x0102
1021 #define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2
1022 #define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105
1023 #define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2
1024 #define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106
1025 #define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2
1026 #define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107
1027 #define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2
1028 #define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108
1029 #define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2
1030 #define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109
1031 #define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2
1032 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a
1033 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
1034 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b
1035 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2
1036 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c
1037 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2
1038 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d
1039 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2
1040 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e
1041 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2
1042 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f
1043 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
1044 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110
1045 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2
1046 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111
1047 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2
1048 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112
1049 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2
1050 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113
1051 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2
1052 #define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114
1053 #define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2
1054 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115
1055 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
1056 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116
1057 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
1058 #define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119
1059 #define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
1060 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a
1061 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2
1062 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b
1063 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2
1064 #define mmDMCU_INT_CNT_CONTINUE 0x011c
1065 #define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2
1068 // addressBlock: dce_dc_dmu_ihc_dispdec
1069 // base address: 0x0
1070 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126
1071 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
1072 #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127
1073 #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2
1074 #define mmDC_GPU_TIMER_READ 0x0128
1075 #define mmDC_GPU_TIMER_READ_BASE_IDX 2
1076 #define mmDC_GPU_TIMER_READ_CNTL 0x0129
1077 #define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
1078 #define mmDISP_INTERRUPT_STATUS 0x012a
1079 #define mmDISP_INTERRUPT_STATUS_BASE_IDX 2
1080 #define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b
1081 #define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
1082 #define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c
1083 #define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
1084 #define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d
1085 #define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
1086 #define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e
1087 #define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
1088 #define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f
1089 #define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
1090 #define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130
1091 #define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
1092 #define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131
1093 #define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
1094 #define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132
1095 #define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
1096 #define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133
1097 #define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
1098 #define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134
1099 #define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
1100 #define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135
1101 #define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
1102 #define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136
1103 #define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2
1104 #define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137
1105 #define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2
1106 #define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138
1107 #define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2
1108 #define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139
1109 #define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2
1110 #define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a
1111 #define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2
1112 #define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b
1113 #define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2
1114 #define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c
1115 #define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2
1116 #define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d
1117 #define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2
1118 #define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e
1119 #define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2
1120 #define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f
1121 #define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2
1122 #define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140
1123 #define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2
1124 #define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141
1125 #define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2
1126 #define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142
1127 #define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2
1128 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143
1129 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2
1130 #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144
1131 #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2
1134 // addressBlock: dce_dc_wb0_dispdec_cnv_dispdec
1135 // base address: 0x0
1136 #define mmCNV0_WB_ENABLE 0x01da
1137 #define mmCNV0_WB_ENABLE_BASE_IDX 2
1138 #define mmCNV0_WB_EC_CONFIG 0x01db
1139 #define mmCNV0_WB_EC_CONFIG_BASE_IDX 2
1140 #define mmCNV0_CNV_MODE 0x01dc
1141 #define mmCNV0_CNV_MODE_BASE_IDX 2
1142 #define mmCNV0_CNV_WINDOW_START 0x01dd
1143 #define mmCNV0_CNV_WINDOW_START_BASE_IDX 2
1144 #define mmCNV0_CNV_WINDOW_SIZE 0x01de
1145 #define mmCNV0_CNV_WINDOW_SIZE_BASE_IDX 2
1146 #define mmCNV0_CNV_UPDATE 0x01df
1147 #define mmCNV0_CNV_UPDATE_BASE_IDX 2
1148 #define mmCNV0_CNV_SOURCE_SIZE 0x01e0
1149 #define mmCNV0_CNV_SOURCE_SIZE_BASE_IDX 2
1150 #define mmCNV0_CNV_CSC_CONTROL 0x01e1
1151 #define mmCNV0_CNV_CSC_CONTROL_BASE_IDX 2
1152 #define mmCNV0_CNV_CSC_C11_C12 0x01e2
1153 #define mmCNV0_CNV_CSC_C11_C12_BASE_IDX 2
1154 #define mmCNV0_CNV_CSC_C13_C14 0x01e3
1155 #define mmCNV0_CNV_CSC_C13_C14_BASE_IDX 2
1156 #define mmCNV0_CNV_CSC_C21_C22 0x01e4
1157 #define mmCNV0_CNV_CSC_C21_C22_BASE_IDX 2
1158 #define mmCNV0_CNV_CSC_C23_C24 0x01e5
1159 #define mmCNV0_CNV_CSC_C23_C24_BASE_IDX 2
1160 #define mmCNV0_CNV_CSC_C31_C32 0x01e6
1161 #define mmCNV0_CNV_CSC_C31_C32_BASE_IDX 2
1162 #define mmCNV0_CNV_CSC_C33_C34 0x01e7
1163 #define mmCNV0_CNV_CSC_C33_C34_BASE_IDX 2
1164 #define mmCNV0_CNV_CSC_ROUND_OFFSET_R 0x01e8
1165 #define mmCNV0_CNV_CSC_ROUND_OFFSET_R_BASE_IDX 2
1166 #define mmCNV0_CNV_CSC_ROUND_OFFSET_G 0x01e9
1167 #define mmCNV0_CNV_CSC_ROUND_OFFSET_G_BASE_IDX 2
1168 #define mmCNV0_CNV_CSC_ROUND_OFFSET_B 0x01ea
1169 #define mmCNV0_CNV_CSC_ROUND_OFFSET_B_BASE_IDX 2
1170 #define mmCNV0_CNV_CSC_CLAMP_R 0x01eb
1171 #define mmCNV0_CNV_CSC_CLAMP_R_BASE_IDX 2
1172 #define mmCNV0_CNV_CSC_CLAMP_G 0x01ec
1173 #define mmCNV0_CNV_CSC_CLAMP_G_BASE_IDX 2
1174 #define mmCNV0_CNV_CSC_CLAMP_B 0x01ed
1175 #define mmCNV0_CNV_CSC_CLAMP_B_BASE_IDX 2
1176 #define mmCNV0_CNV_TEST_CNTL 0x01ee
1177 #define mmCNV0_CNV_TEST_CNTL_BASE_IDX 2
1178 #define mmCNV0_CNV_TEST_CRC_RED 0x01ef
1179 #define mmCNV0_CNV_TEST_CRC_RED_BASE_IDX 2
1180 #define mmCNV0_CNV_TEST_CRC_GREEN 0x01f0
1181 #define mmCNV0_CNV_TEST_CRC_GREEN_BASE_IDX 2
1182 #define mmCNV0_CNV_TEST_CRC_BLUE 0x01f1
1183 #define mmCNV0_CNV_TEST_CRC_BLUE_BASE_IDX 2
1184 #define mmCNV0_CNV_INPUT_SELECT 0x01f5
1185 #define mmCNV0_CNV_INPUT_SELECT_BASE_IDX 2
1186 #define mmCNV0_WB_SOFT_RESET 0x01f8
1187 #define mmCNV0_WB_SOFT_RESET_BASE_IDX 2
1188 #define mmCNV0_WB_WARM_UP_MODE_CTL1 0x01f9
1189 #define mmCNV0_WB_WARM_UP_MODE_CTL1_BASE_IDX 2
1190 #define mmCNV0_WB_WARM_UP_MODE_CTL2 0x01fa
1191 #define mmCNV0_WB_WARM_UP_MODE_CTL2_BASE_IDX 2
1194 // addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec
1195 // base address: 0x0
1196 #define mmWBSCL0_WBSCL_COEF_RAM_SELECT 0x020a
1197 #define mmWBSCL0_WBSCL_COEF_RAM_SELECT_BASE_IDX 2
1198 #define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA 0x020b
1199 #define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2
1200 #define mmWBSCL0_WBSCL_MODE 0x020c
1201 #define mmWBSCL0_WBSCL_MODE_BASE_IDX 2
1202 #define mmWBSCL0_WBSCL_TAP_CONTROL 0x020d
1203 #define mmWBSCL0_WBSCL_TAP_CONTROL_BASE_IDX 2
1204 #define mmWBSCL0_WBSCL_DEST_SIZE 0x020e
1205 #define mmWBSCL0_WBSCL_DEST_SIZE_BASE_IDX 2
1206 #define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO 0x020f
1207 #define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
1208 #define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB 0x0210
1209 #define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2
1210 #define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR 0x0211
1211 #define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2
1212 #define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO 0x0212
1213 #define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
1214 #define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB 0x0213
1215 #define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2
1216 #define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR 0x0214
1217 #define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2
1218 #define mmWBSCL0_WBSCL_ROUND_OFFSET 0x0215
1219 #define mmWBSCL0_WBSCL_ROUND_OFFSET_BASE_IDX 2
1220 #define mmWBSCL0_WBSCL_CLAMP 0x0216
1221 #define mmWBSCL0_WBSCL_CLAMP_BASE_IDX 2
1222 #define mmWBSCL0_WBSCL_OVERFLOW_STATUS 0x0217
1223 #define mmWBSCL0_WBSCL_OVERFLOW_STATUS_BASE_IDX 2
1224 #define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS 0x0218
1225 #define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
1226 #define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY 0x0219
1227 #define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2
1228 #define mmWBSCL0_WBSCL_TEST_CNTL 0x021a
1229 #define mmWBSCL0_WBSCL_TEST_CNTL_BASE_IDX 2
1230 #define mmWBSCL0_WBSCL_TEST_CRC_RED 0x021b
1231 #define mmWBSCL0_WBSCL_TEST_CRC_RED_BASE_IDX 2
1232 #define mmWBSCL0_WBSCL_TEST_CRC_GREEN 0x021c
1233 #define mmWBSCL0_WBSCL_TEST_CRC_GREEN_BASE_IDX 2
1234 #define mmWBSCL0_WBSCL_TEST_CRC_BLUE 0x021d
1235 #define mmWBSCL0_WBSCL_TEST_CRC_BLUE_BASE_IDX 2
1236 #define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN 0x021e
1237 #define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2
1238 #define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT 0x021f
1239 #define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2
1240 #define mmWBSCL0_WBSCL_RAM_SHUTDOWN 0x0222
1241 #define mmWBSCL0_WBSCL_RAM_SHUTDOWN_BASE_IDX 2
1244 // addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
1245 // base address: 0x8e8
1246 #define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x023a
1247 #define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2
1248 #define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x023b
1249 #define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2
1250 #define mmDC_PERFMON3_PERFCOUNTER_STATE 0x023c
1251 #define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2
1252 #define mmDC_PERFMON3_PERFMON_CNTL 0x023d
1253 #define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2
1254 #define mmDC_PERFMON3_PERFMON_CNTL2 0x023e
1255 #define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2
1256 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x023f
1257 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
1258 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0240
1259 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2
1260 #define mmDC_PERFMON3_PERFMON_HI 0x0241
1261 #define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2
1262 #define mmDC_PERFMON3_PERFMON_LOW 0x0242
1263 #define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2
1266 // addressBlock: dce_dc_wb1_dispdec_cnv_dispdec
1267 // base address: 0x1b0
1268 #define mmCNV1_WB_ENABLE 0x0246
1269 #define mmCNV1_WB_ENABLE_BASE_IDX 2
1270 #define mmCNV1_WB_EC_CONFIG 0x0247
1271 #define mmCNV1_WB_EC_CONFIG_BASE_IDX 2
1272 #define mmCNV1_CNV_MODE 0x0248
1273 #define mmCNV1_CNV_MODE_BASE_IDX 2
1274 #define mmCNV1_CNV_WINDOW_START 0x0249
1275 #define mmCNV1_CNV_WINDOW_START_BASE_IDX 2
1276 #define mmCNV1_CNV_WINDOW_SIZE 0x024a
1277 #define mmCNV1_CNV_WINDOW_SIZE_BASE_IDX 2
1278 #define mmCNV1_CNV_UPDATE 0x024b
1279 #define mmCNV1_CNV_UPDATE_BASE_IDX 2
1280 #define mmCNV1_CNV_SOURCE_SIZE 0x024c
1281 #define mmCNV1_CNV_SOURCE_SIZE_BASE_IDX 2
1282 #define mmCNV1_CNV_CSC_CONTROL 0x024d
1283 #define mmCNV1_CNV_CSC_CONTROL_BASE_IDX 2
1284 #define mmCNV1_CNV_CSC_C11_C12 0x024e
1285 #define mmCNV1_CNV_CSC_C11_C12_BASE_IDX 2
1286 #define mmCNV1_CNV_CSC_C13_C14 0x024f
1287 #define mmCNV1_CNV_CSC_C13_C14_BASE_IDX 2
1288 #define mmCNV1_CNV_CSC_C21_C22 0x0250
1289 #define mmCNV1_CNV_CSC_C21_C22_BASE_IDX 2
1290 #define mmCNV1_CNV_CSC_C23_C24 0x0251
1291 #define mmCNV1_CNV_CSC_C23_C24_BASE_IDX 2
1292 #define mmCNV1_CNV_CSC_C31_C32 0x0252
1293 #define mmCNV1_CNV_CSC_C31_C32_BASE_IDX 2
1294 #define mmCNV1_CNV_CSC_C33_C34 0x0253
1295 #define mmCNV1_CNV_CSC_C33_C34_BASE_IDX 2
1296 #define mmCNV1_CNV_CSC_ROUND_OFFSET_R 0x0254
1297 #define mmCNV1_CNV_CSC_ROUND_OFFSET_R_BASE_IDX 2
1298 #define mmCNV1_CNV_CSC_ROUND_OFFSET_G 0x0255
1299 #define mmCNV1_CNV_CSC_ROUND_OFFSET_G_BASE_IDX 2
1300 #define mmCNV1_CNV_CSC_ROUND_OFFSET_B 0x0256
1301 #define mmCNV1_CNV_CSC_ROUND_OFFSET_B_BASE_IDX 2
1302 #define mmCNV1_CNV_CSC_CLAMP_R 0x0257
1303 #define mmCNV1_CNV_CSC_CLAMP_R_BASE_IDX 2
1304 #define mmCNV1_CNV_CSC_CLAMP_G 0x0258
1305 #define mmCNV1_CNV_CSC_CLAMP_G_BASE_IDX 2
1306 #define mmCNV1_CNV_CSC_CLAMP_B 0x0259
1307 #define mmCNV1_CNV_CSC_CLAMP_B_BASE_IDX 2
1308 #define mmCNV1_CNV_TEST_CNTL 0x025a
1309 #define mmCNV1_CNV_TEST_CNTL_BASE_IDX 2
1310 #define mmCNV1_CNV_TEST_CRC_RED 0x025b
1311 #define mmCNV1_CNV_TEST_CRC_RED_BASE_IDX 2
1312 #define mmCNV1_CNV_TEST_CRC_GREEN 0x025c
1313 #define mmCNV1_CNV_TEST_CRC_GREEN_BASE_IDX 2
1314 #define mmCNV1_CNV_TEST_CRC_BLUE 0x025d
1315 #define mmCNV1_CNV_TEST_CRC_BLUE_BASE_IDX 2
1316 #define mmCNV1_CNV_INPUT_SELECT 0x0261
1317 #define mmCNV1_CNV_INPUT_SELECT_BASE_IDX 2
1318 #define mmCNV1_WB_SOFT_RESET 0x0264
1319 #define mmCNV1_WB_SOFT_RESET_BASE_IDX 2
1320 #define mmCNV1_WB_WARM_UP_MODE_CTL1 0x0265
1321 #define mmCNV1_WB_WARM_UP_MODE_CTL1_BASE_IDX 2
1322 #define mmCNV1_WB_WARM_UP_MODE_CTL2 0x0266
1323 #define mmCNV1_WB_WARM_UP_MODE_CTL2_BASE_IDX 2
1326 // addressBlock: dce_dc_wb1_dispdec_wbscl_dispdec
1327 // base address: 0x1b0
1328 #define mmWBSCL1_WBSCL_COEF_RAM_SELECT 0x0276
1329 #define mmWBSCL1_WBSCL_COEF_RAM_SELECT_BASE_IDX 2
1330 #define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA 0x0277
1331 #define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2
1332 #define mmWBSCL1_WBSCL_MODE 0x0278
1333 #define mmWBSCL1_WBSCL_MODE_BASE_IDX 2
1334 #define mmWBSCL1_WBSCL_TAP_CONTROL 0x0279
1335 #define mmWBSCL1_WBSCL_TAP_CONTROL_BASE_IDX 2
1336 #define mmWBSCL1_WBSCL_DEST_SIZE 0x027a
1337 #define mmWBSCL1_WBSCL_DEST_SIZE_BASE_IDX 2
1338 #define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO 0x027b
1339 #define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
1340 #define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB 0x027c
1341 #define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2
1342 #define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR 0x027d
1343 #define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2
1344 #define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO 0x027e
1345 #define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
1346 #define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB 0x027f
1347 #define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2
1348 #define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR 0x0280
1349 #define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2
1350 #define mmWBSCL1_WBSCL_ROUND_OFFSET 0x0281
1351 #define mmWBSCL1_WBSCL_ROUND_OFFSET_BASE_IDX 2
1352 #define mmWBSCL1_WBSCL_CLAMP 0x0282
1353 #define mmWBSCL1_WBSCL_CLAMP_BASE_IDX 2
1354 #define mmWBSCL1_WBSCL_OVERFLOW_STATUS 0x0283
1355 #define mmWBSCL1_WBSCL_OVERFLOW_STATUS_BASE_IDX 2
1356 #define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS 0x0284
1357 #define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
1358 #define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY 0x0285
1359 #define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2
1360 #define mmWBSCL1_WBSCL_TEST_CNTL 0x0286
1361 #define mmWBSCL1_WBSCL_TEST_CNTL_BASE_IDX 2
1362 #define mmWBSCL1_WBSCL_TEST_CRC_RED 0x0287
1363 #define mmWBSCL1_WBSCL_TEST_CRC_RED_BASE_IDX 2
1364 #define mmWBSCL1_WBSCL_TEST_CRC_GREEN 0x0288
1365 #define mmWBSCL1_WBSCL_TEST_CRC_GREEN_BASE_IDX 2
1366 #define mmWBSCL1_WBSCL_TEST_CRC_BLUE 0x0289
1367 #define mmWBSCL1_WBSCL_TEST_CRC_BLUE_BASE_IDX 2
1368 #define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN 0x028a
1369 #define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2
1370 #define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT 0x028b
1371 #define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2
1372 #define mmWBSCL1_WBSCL_RAM_SHUTDOWN 0x028e
1373 #define mmWBSCL1_WBSCL_RAM_SHUTDOWN_BASE_IDX 2
1376 // addressBlock: dce_dc_wb1_dispdec_wb_dcperfmon_dc_perfmon_dispdec
1377 // base address: 0xa98
1378 #define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x02a6
1379 #define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2
1380 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x02a7
1381 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2
1382 #define mmDC_PERFMON4_PERFCOUNTER_STATE 0x02a8
1383 #define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2
1384 #define mmDC_PERFMON4_PERFMON_CNTL 0x02a9
1385 #define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2
1386 #define mmDC_PERFMON4_PERFMON_CNTL2 0x02aa
1387 #define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2
1388 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x02ab
1389 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
1390 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x02ac
1391 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2
1392 #define mmDC_PERFMON4_PERFMON_HI 0x02ad
1393 #define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2
1394 #define mmDC_PERFMON4_PERFMON_LOW 0x02ae
1395 #define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2
1398 // addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
1399 // base address: 0x0
1400 #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2
1401 #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
1402 #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3
1403 #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
1404 #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x02b4
1405 #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
1406 #define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x02b5
1407 #define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2
1408 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x02b6
1409 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
1410 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x02b7
1411 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
1412 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x02b8
1413 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
1414 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x02b9
1415 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
1416 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x02ba
1417 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
1418 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x02bb
1419 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
1420 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x02bc
1421 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
1422 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x02bd
1423 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
1424 #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x02be
1425 #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
1426 #define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x02bf
1427 #define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
1428 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x02c2
1429 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
1430 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3
1431 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
1432 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x02c4
1433 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
1434 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5
1435 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
1436 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x02c6
1437 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
1438 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7
1439 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
1440 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x02c8
1441 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
1442 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9
1443 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
1444 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x02ca
1445 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
1446 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb
1447 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
1448 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x02cc
1449 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
1450 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd
1451 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
1452 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x02ce
1453 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
1454 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf
1455 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
1456 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x02d0
1457 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
1458 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1
1459 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
1460 #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2
1461 #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
1462 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3
1463 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
1464 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x02d4
1465 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
1466 #define mmMCIF_WB0_MCIF_WB_WATERMARK 0x02d5
1467 #define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2
1468 #define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6
1469 #define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
1470 #define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x02d7
1471 #define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
1472 #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8
1473 #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
1474 #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x02d9
1475 #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
1476 #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x02db
1477 #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
1478 #define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x02dc
1479 #define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
1482 // addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec
1483 // base address: 0x100
1484 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2
1485 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
1486 #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3
1487 #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
1488 #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02f4
1489 #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
1490 #define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02f5
1491 #define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2
1492 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02f6
1493 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
1494 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02f7
1495 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
1496 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02f8
1497 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
1498 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02f9
1499 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
1500 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02fa
1501 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
1502 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02fb
1503 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
1504 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02fc
1505 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
1506 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02fd
1507 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
1508 #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02fe
1509 #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
1510 #define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02ff
1511 #define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
1512 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x0302
1513 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
1514 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303
1515 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
1516 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x0304
1517 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
1518 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305
1519 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
1520 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x0306
1521 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
1522 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307
1523 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
1524 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x0308
1525 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
1526 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309
1527 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
1528 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x030a
1529 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
1530 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b
1531 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
1532 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x030c
1533 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
1534 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d
1535 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
1536 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x030e
1537 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
1538 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f
1539 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
1540 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x0310
1541 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
1542 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311
1543 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
1544 #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312
1545 #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
1546 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313
1547 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
1548 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x0314
1549 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
1550 #define mmMCIF_WB1_MCIF_WB_WATERMARK 0x0315
1551 #define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2
1552 #define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x0316
1553 #define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
1554 #define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x0317
1555 #define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
1556 #define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x0318
1557 #define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
1558 #define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x0319
1559 #define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
1560 #define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x031b
1561 #define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
1562 #define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x031c
1563 #define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
1566 // addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
1567 // base address: 0x0
1568 #define mmWBIF0_MISC_CTRL 0x0333
1569 #define mmWBIF0_MISC_CTRL_BASE_IDX 2
1570 #define mmWBIF0_SMU_WM_CONTROL 0x0334
1571 #define mmWBIF0_SMU_WM_CONTROL_BASE_IDX 2
1572 #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335
1573 #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
1574 #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336
1575 #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
1576 #define mmWBIF1_MISC_CTRL 0x0337
1577 #define mmWBIF1_MISC_CTRL_BASE_IDX 2
1578 #define mmWBIF1_SMU_WM_CONTROL 0x0338
1579 #define mmWBIF1_SMU_WM_CONTROL_BASE_IDX 2
1580 #define mmWBIF1_PHASE0_OUTSTANDING_COUNTER 0x0339
1581 #define mmWBIF1_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
1582 #define mmWBIF1_PHASE1_OUTSTANDING_COUNTER 0x033a
1583 #define mmWBIF1_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
1584 #define mmVGA_SRC_SPLIT_CNTL 0x033b
1585 #define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2
1586 #define mmMMHUBBUB_MEM_PWR_STATUS 0x033c
1587 #define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2
1588 #define mmMMHUBBUB_MEM_PWR_CNTL 0x033d
1589 #define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2
1590 #define mmMMHUBBUB_CLOCK_CNTL 0x033e
1591 #define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2
1592 #define mmMMHUBBUB_SOFT_RESET 0x033f
1593 #define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2
1596 // addressBlock: dce_dc_mmhubbub_vgaif_dispdec
1597 // base address: 0x0
1598 #define mmMCIF_CONTROL 0x034a
1599 #define mmMCIF_CONTROL_BASE_IDX 2
1600 #define mmMCIF_WRITE_COMBINE_CONTROL 0x034b
1601 #define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2
1602 #define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e
1603 #define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
1604 #define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f
1605 #define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
1606 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350
1607 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2
1610 // addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
1611 // base address: 0xd48
1612 #define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x0352
1613 #define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2
1614 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x0353
1615 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2
1616 #define mmDC_PERFMON5_PERFCOUNTER_STATE 0x0354
1617 #define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2
1618 #define mmDC_PERFMON5_PERFMON_CNTL 0x0355
1619 #define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2
1620 #define mmDC_PERFMON5_PERFMON_CNTL2 0x0356
1621 #define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2
1622 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0357
1623 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
1624 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0358
1625 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2
1626 #define mmDC_PERFMON5_PERFMON_HI 0x0359
1627 #define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2
1628 #define mmDC_PERFMON5_PERFMON_LOW 0x035a
1629 #define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2
1632 // addressBlock: dce_dc_hda_azf0stream0_dispdec
1633 // base address: 0x0
1634 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e
1635 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2
1636 #define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f
1637 #define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2
1640 // addressBlock: dce_dc_hda_azf0stream1_dispdec
1641 // base address: 0x8
1642 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360
1643 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2
1644 #define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361
1645 #define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2
1648 // addressBlock: dce_dc_hda_azf0stream2_dispdec
1649 // base address: 0x10
1650 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362
1651 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2
1652 #define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363
1653 #define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2
1656 // addressBlock: dce_dc_hda_azf0stream3_dispdec
1657 // base address: 0x18
1658 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364
1659 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2
1660 #define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365
1661 #define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2
1664 // addressBlock: dce_dc_hda_azf0stream4_dispdec
1665 // base address: 0x20
1666 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366
1667 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2
1668 #define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367
1669 #define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2
1672 // addressBlock: dce_dc_hda_azf0stream5_dispdec
1673 // base address: 0x28
1674 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368
1675 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2
1676 #define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369
1677 #define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2
1680 // addressBlock: dce_dc_hda_azf0stream6_dispdec
1681 // base address: 0x30
1682 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a
1683 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2
1684 #define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b
1685 #define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2
1688 // addressBlock: dce_dc_hda_azf0stream7_dispdec
1689 // base address: 0x38
1690 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c
1691 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2
1692 #define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d
1693 #define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2
1696 // addressBlock: dce_dc_hda_az_misc_dispdec
1697 // base address: 0x0
1698 #define mmAZ_CLOCK_CNTL 0x0372
1699 #define mmAZ_CLOCK_CNTL_BASE_IDX 2
1702 // addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
1703 // base address: 0xde8
1704 #define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x037a
1705 #define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2
1706 #define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x037b
1707 #define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2
1708 #define mmDC_PERFMON6_PERFCOUNTER_STATE 0x037c
1709 #define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2
1710 #define mmDC_PERFMON6_PERFMON_CNTL 0x037d
1711 #define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2
1712 #define mmDC_PERFMON6_PERFMON_CNTL2 0x037e
1713 #define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2
1714 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x037f
1715 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
1716 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0380
1717 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2
1718 #define mmDC_PERFMON6_PERFMON_HI 0x0381
1719 #define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2
1720 #define mmDC_PERFMON6_PERFMON_LOW 0x0382
1721 #define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2
1724 // addressBlock: dce_dc_hda_azf0endpoint0_dispdec
1725 // base address: 0x0
1726 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386
1727 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1728 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387
1729 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1732 // addressBlock: dce_dc_hda_azf0endpoint1_dispdec
1733 // base address: 0x18
1734 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c
1735 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1736 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d
1737 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1740 // addressBlock: dce_dc_hda_azf0endpoint2_dispdec
1741 // base address: 0x30
1742 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392
1743 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1744 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393
1745 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1748 // addressBlock: dce_dc_hda_azf0endpoint3_dispdec
1749 // base address: 0x48
1750 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398
1751 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1752 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399
1753 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1756 // addressBlock: dce_dc_hda_azf0endpoint4_dispdec
1757 // base address: 0x60
1758 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e
1759 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1760 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f
1761 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1764 // addressBlock: dce_dc_hda_azf0endpoint5_dispdec
1765 // base address: 0x78
1766 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4
1767 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1768 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5
1769 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1772 // addressBlock: dce_dc_hda_azf0endpoint6_dispdec
1773 // base address: 0x90
1774 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa
1775 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1776 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab
1777 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1780 // addressBlock: dce_dc_hda_azf0endpoint7_dispdec
1781 // base address: 0xa8
1782 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0
1783 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
1784 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1
1785 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
1788 // addressBlock: dce_dc_hda_azf0controller_dispdec
1789 // base address: 0x0
1790 #define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2
1791 #define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
1792 #define mmAZALIA_AUDIO_DTO 0x03c3
1793 #define mmAZALIA_AUDIO_DTO_BASE_IDX 2
1794 #define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4
1795 #define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
1796 #define mmAZALIA_SOCCLK_CONTROL 0x03c5
1797 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
1798 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6
1799 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
1800 #define mmAZALIA_DATA_DMA_CONTROL 0x03c7
1801 #define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
1802 #define mmAZALIA_BDL_DMA_CONTROL 0x03c8
1803 #define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
1804 #define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9
1805 #define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
1806 #define mmAZALIA_CORB_DMA_CONTROL 0x03ca
1807 #define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
1808 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1
1809 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
1810 #define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2
1811 #define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
1812 #define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3
1813 #define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
1814 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4
1815 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
1816 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5
1817 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
1818 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6
1819 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
1820 #define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9
1821 #define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
1822 #define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da
1823 #define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
1824 #define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db
1825 #define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
1826 #define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc
1827 #define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
1828 #define mmAZALIA_INPUT_CRC0_RESULT 0x03dd
1829 #define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
1830 #define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de
1831 #define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
1832 #define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df
1833 #define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
1834 #define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0
1835 #define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
1836 #define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1
1837 #define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
1838 #define mmAZALIA_INPUT_CRC1_RESULT 0x03e2
1839 #define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
1840 #define mmAZALIA_CRC0_CONTROL0 0x03e3
1841 #define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2
1842 #define mmAZALIA_CRC0_CONTROL1 0x03e4
1843 #define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2
1844 #define mmAZALIA_CRC0_CONTROL2 0x03e5
1845 #define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2
1846 #define mmAZALIA_CRC0_CONTROL3 0x03e6
1847 #define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2
1848 #define mmAZALIA_CRC0_RESULT 0x03e7
1849 #define mmAZALIA_CRC0_RESULT_BASE_IDX 2
1850 #define mmAZALIA_CRC1_CONTROL0 0x03e8
1851 #define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2
1852 #define mmAZALIA_CRC1_CONTROL1 0x03e9
1853 #define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2
1854 #define mmAZALIA_CRC1_CONTROL2 0x03ea
1855 #define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2
1856 #define mmAZALIA_CRC1_CONTROL3 0x03eb
1857 #define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2
1858 #define mmAZALIA_CRC1_RESULT 0x03ec
1859 #define mmAZALIA_CRC1_RESULT_BASE_IDX 2
1860 #define mmAZALIA_MEM_PWR_CTRL 0x03ee
1861 #define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
1862 #define mmAZALIA_MEM_PWR_STATUS 0x03ef
1863 #define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
1866 // addressBlock: dce_dc_hda_azf0root_dispdec
1867 // base address: 0x0
1868 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406
1869 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
1870 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407
1871 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
1872 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408
1873 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
1874 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409
1875 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
1876 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a
1877 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
1878 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b
1879 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
1880 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c
1881 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
1882 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d
1883 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
1884 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e
1885 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
1886 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f
1887 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
1888 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410
1889 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
1890 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411
1891 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
1892 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412
1893 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
1894 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413
1895 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
1896 #define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415
1897 #define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2
1898 #define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416
1899 #define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2
1900 #define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417
1901 #define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2
1902 #define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418
1903 #define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2
1904 #define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419
1905 #define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2
1906 #define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a
1907 #define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2
1908 #define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b
1909 #define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2
1910 #define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c
1911 #define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
1912 #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d
1913 #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
1916 // addressBlock: dce_dc_hda_azf0stream8_dispdec
1917 // base address: 0x320
1918 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426
1919 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2
1920 #define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427
1921 #define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2
1924 // addressBlock: dce_dc_hda_azf0stream9_dispdec
1925 // base address: 0x328
1926 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428
1927 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2
1928 #define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429
1929 #define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2
1932 // addressBlock: dce_dc_hda_azf0stream10_dispdec
1933 // base address: 0x330
1934 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a
1935 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2
1936 #define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b
1937 #define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2
1940 // addressBlock: dce_dc_hda_azf0stream11_dispdec
1941 // base address: 0x338
1942 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c
1943 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2
1944 #define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d
1945 #define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2
1948 // addressBlock: dce_dc_hda_azf0stream12_dispdec
1949 // base address: 0x340
1950 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e
1951 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2
1952 #define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f
1953 #define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2
1956 // addressBlock: dce_dc_hda_azf0stream13_dispdec
1957 // base address: 0x348
1958 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430
1959 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2
1960 #define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431
1961 #define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2
1964 // addressBlock: dce_dc_hda_azf0stream14_dispdec
1965 // base address: 0x350
1966 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432
1967 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2
1968 #define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433
1969 #define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2
1972 // addressBlock: dce_dc_hda_azf0stream15_dispdec
1973 // base address: 0x358
1974 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434
1975 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2
1976 #define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435
1977 #define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2
1980 // addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
1981 // base address: 0x0
1982 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a
1983 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
1984 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b
1985 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
1988 // addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
1989 // base address: 0x10
1990 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e
1991 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
1992 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f
1993 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
1996 // addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
1997 // base address: 0x20
1998 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442
1999 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
2000 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443
2001 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
2004 // addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
2005 // base address: 0x30
2006 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446
2007 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
2008 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447
2009 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
2012 // addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
2013 // base address: 0x40
2014 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a
2015 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
2016 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b
2017 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
2020 // addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
2021 // base address: 0x50
2022 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e
2023 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
2024 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f
2025 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
2028 // addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
2029 // base address: 0x60
2030 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452
2031 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
2032 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453
2033 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
2036 // addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
2037 // base address: 0x70
2038 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456
2039 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
2040 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457
2041 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
2044 // addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
2045 // base address: 0x0
2046 #define mmDCHUBBUB_SDPIF_CFG0 0x048f
2047 #define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2
2048 #define mmDCHUBBUB_SDPIF_CFG1 0x0490
2049 #define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2
2050 #define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491
2051 #define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2
2052 #define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492
2053 #define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2
2054 #define mmDCHUBBUB_SDPIF_FB_BASE 0x0493
2055 #define mmDCHUBBUB_SDPIF_FB_BASE_BASE_IDX 2
2056 #define mmDCHUBBUB_SDPIF_FB_TOP 0x0494
2057 #define mmDCHUBBUB_SDPIF_FB_TOP_BASE_IDX 2
2058 #define mmDCHUBBUB_SDPIF_FB_OFFSET 0x0495
2059 #define mmDCHUBBUB_SDPIF_FB_OFFSET_BASE_IDX 2
2060 #define mmDCHUBBUB_SDPIF_AGP_BOT 0x0496
2061 #define mmDCHUBBUB_SDPIF_AGP_BOT_BASE_IDX 2
2062 #define mmDCHUBBUB_SDPIF_AGP_TOP 0x0497
2063 #define mmDCHUBBUB_SDPIF_AGP_TOP_BASE_IDX 2
2064 #define mmDCHUBBUB_SDPIF_AGP_BASE 0x0498
2065 #define mmDCHUBBUB_SDPIF_AGP_BASE_BASE_IDX 2
2066 #define mmDCHUBBUB_SDPIF_APER_BASE 0x0499
2067 #define mmDCHUBBUB_SDPIF_APER_BASE_BASE_IDX 2
2068 #define mmDCHUBBUB_SDPIF_APER_TOP 0x049a
2069 #define mmDCHUBBUB_SDPIF_APER_TOP_BASE_IDX 2
2070 #define mmDCHUBBUB_SDPIF_APER_DEF_0 0x049b
2071 #define mmDCHUBBUB_SDPIF_APER_DEF_0_BASE_IDX 2
2072 #define mmDCHUBBUB_SDPIF_APER_DEF_1 0x049c
2073 #define mmDCHUBBUB_SDPIF_APER_DEF_1_BASE_IDX 2
2074 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d
2075 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2
2076 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1 0x049e
2077 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1_BASE_IDX 2
2078 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W 0x049f
2079 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W_BASE_IDX 2
2080 #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0 0x04a0
2081 #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0_BASE_IDX 2
2082 #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0 0x04a1
2083 #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0_BASE_IDX 2
2084 #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0 0x04a2
2085 #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0_BASE_IDX 2
2086 #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0 0x04a3
2087 #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0_BASE_IDX 2
2088 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0 0x04a4
2089 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0_BASE_IDX 2
2090 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0 0x04a5
2091 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0_BASE_IDX 2
2092 #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1 0x04a6
2093 #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1_BASE_IDX 2
2094 #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1 0x04a7
2095 #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1_BASE_IDX 2
2096 #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1 0x04a8
2097 #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1_BASE_IDX 2
2098 #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1 0x04a9
2099 #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1_BASE_IDX 2
2100 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1 0x04aa
2101 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1_BASE_IDX 2
2102 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1 0x04ab
2103 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1_BASE_IDX 2
2104 #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2 0x04ac
2105 #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2_BASE_IDX 2
2106 #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2 0x04ad
2107 #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2_BASE_IDX 2
2108 #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2 0x04ae
2109 #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2_BASE_IDX 2
2110 #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2 0x04af
2111 #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2_BASE_IDX 2
2112 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2 0x04b0
2113 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2_BASE_IDX 2
2114 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2 0x04b1
2115 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2_BASE_IDX 2
2116 #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3 0x04b2
2117 #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3_BASE_IDX 2
2118 #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3 0x04b3
2119 #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3_BASE_IDX 2
2120 #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3 0x04b4
2121 #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3_BASE_IDX 2
2122 #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3 0x04b5
2123 #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3_BASE_IDX 2
2124 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3 0x04b6
2125 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3_BASE_IDX 2
2126 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3 0x04b7
2127 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3_BASE_IDX 2
2128 #define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x04b8
2129 #define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2
2130 #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04b9
2131 #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2
2132 #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04ba
2133 #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2
2136 // addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
2137 // base address: 0x0
2138 #define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf
2139 #define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2
2140 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0
2141 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2
2142 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1
2143 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2
2144 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2
2145 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2
2146 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3
2147 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2
2148 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4
2149 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2
2150 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5
2151 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2
2152 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6
2153 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2
2154 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7
2155 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2
2156 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8
2157 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2
2158 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9
2159 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2
2160 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da
2161 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2
2162 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db
2163 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2
2164 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc
2165 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2
2166 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd
2167 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2
2168 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de
2169 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2
2170 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df
2171 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2
2172 #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04e0
2173 #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2
2174 #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04e1
2175 #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2
2176 #define mmDCHUBBUB_CRC_CTRL 0x04e2
2177 #define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2
2178 #define mmDCHUBBUB_CRC0_VAL_R_G 0x04e3
2179 #define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2
2180 #define mmDCHUBBUB_CRC0_VAL_B_A 0x04e4
2181 #define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2
2182 #define mmDCHUBBUB_CRC1_VAL_R_G 0x04e5
2183 #define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2
2184 #define mmDCHUBBUB_CRC1_VAL_B_A 0x04e6
2185 #define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2
2188 // addressBlock: dce_dc_dchubbub_hubbub_dispdec
2189 // base address: 0x0
2190 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505
2191 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2
2192 #define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506
2193 #define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2
2194 #define mmDCHUBBUB_ARB_QOS_FORCE 0x0507
2195 #define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2
2196 #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508
2197 #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2
2198 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509
2199 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2
2200 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A 0x050a
2201 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_BASE_IDX 2
2202 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b
2203 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2
2204 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c
2205 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2
2206 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d
2207 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2
2208 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e
2209 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2
2210 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B 0x050f
2211 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_BASE_IDX 2
2212 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510
2213 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2
2214 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511
2215 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2
2216 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512
2217 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2
2218 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513
2219 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2
2220 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C 0x0514
2221 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_BASE_IDX 2
2222 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515
2223 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2
2224 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516
2225 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2
2226 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517
2227 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2
2228 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518
2229 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2
2230 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D 0x0519
2231 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_BASE_IDX 2
2232 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a
2233 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2
2234 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b
2235 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2
2236 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c
2237 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2
2238 #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d
2239 #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2
2240 #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e
2241 #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2
2242 #define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f
2243 #define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2
2244 #define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520
2245 #define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2
2246 #define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521
2247 #define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2
2248 #define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522
2249 #define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2
2250 #define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523
2251 #define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2
2252 #define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524
2253 #define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2
2254 #define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525
2255 #define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2
2256 #define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526
2257 #define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2
2258 #define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527
2259 #define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2
2260 #define mmVTG0_CONTROL 0x0528
2261 #define mmVTG0_CONTROL_BASE_IDX 2
2262 #define mmVTG1_CONTROL 0x0529
2263 #define mmVTG1_CONTROL_BASE_IDX 2
2264 #define mmVTG2_CONTROL 0x052a
2265 #define mmVTG2_CONTROL_BASE_IDX 2
2266 #define mmVTG3_CONTROL 0x052b
2267 #define mmVTG3_CONTROL_BASE_IDX 2
2268 #define mmVTG4_CONTROL 0x052c
2269 #define mmVTG4_CONTROL_BASE_IDX 2
2270 #define mmVTG5_CONTROL 0x052d
2271 #define mmVTG5_CONTROL_BASE_IDX 2
2272 #define mmDCHUBBUB_SOFT_RESET 0x052e
2273 #define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2
2274 #define mmDCHUBBUB_CLOCK_CNTL 0x052f
2275 #define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2
2276 #define mmDCFCLK_CNTL 0x0530
2277 #define mmDCFCLK_CNTL_BASE_IDX 2
2278 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531
2279 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2
2280 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532
2281 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2
2282 #define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533
2283 #define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2
2284 #define mmDCHUBBUB_SPARE 0x0534
2285 #define mmDCHUBBUB_SPARE_BASE_IDX 2
2288 // addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
2289 // base address: 0x1534
2290 #define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x054d
2291 #define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2
2292 #define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x054e
2293 #define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2
2294 #define mmDC_PERFMON7_PERFCOUNTER_STATE 0x054f
2295 #define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2
2296 #define mmDC_PERFMON7_PERFMON_CNTL 0x0550
2297 #define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2
2298 #define mmDC_PERFMON7_PERFMON_CNTL2 0x0551
2299 #define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2
2300 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x0552
2301 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
2302 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x0553
2303 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2
2304 #define mmDC_PERFMON7_PERFMON_HI 0x0554
2305 #define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2
2306 #define mmDC_PERFMON7_PERFMON_LOW 0x0555
2307 #define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2
2310 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
2311 // base address: 0x0
2312 #define mmHUBP0_DCSURF_SURFACE_CONFIG 0x0559
2313 #define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2
2314 #define mmHUBP0_DCSURF_ADDR_CONFIG 0x055a
2315 #define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2
2316 #define mmHUBP0_DCSURF_TILING_CONFIG 0x055b
2317 #define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2
2318 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x055c
2319 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
2320 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
2321 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
2322 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x055e
2323 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
2324 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x055f
2325 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
2326 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x0560
2327 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
2328 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x0561
2329 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
2330 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x0562
2331 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
2332 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0563
2333 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
2334 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x0564
2335 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
2336 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x0565
2337 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
2338 #define mmHUBP0_DCHUBP_CNTL 0x0566
2339 #define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2
2340 #define mmHUBP0_HUBP_CLK_CNTL 0x0567
2341 #define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2
2342 #define mmHUBP0_DCHUBP_VMPG_CONFIG 0x0568
2343 #define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2
2344 #define mmHUBP0_HUBPREQ_DEBUG_DB 0x0569
2345 #define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2
2346 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x056e
2347 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
2348 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x056f
2349 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
2352 // addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
2353 // base address: 0x0
2354 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x057b
2355 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2
2356 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x057c
2357 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
2358 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x057d
2359 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
2360 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x057e
2361 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2362 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x057f
2363 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
2364 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0580
2365 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2366 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0581
2367 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
2368 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0582
2369 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2370 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0583
2371 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
2372 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0584
2373 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2374 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0585
2375 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
2376 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0586
2377 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2378 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0587
2379 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
2380 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0588
2381 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2382 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0589
2383 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
2384 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x058a
2385 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2386 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x058b
2387 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
2388 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x058c
2389 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2390 #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x058d
2391 #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2
2392 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x058e
2393 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2
2394 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x058f
2395 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2
2396 #define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL 0x0590
2397 #define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2
2398 #define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME 0x0591
2399 #define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
2400 #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0592
2401 #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
2402 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0593
2403 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2
2404 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0594
2405 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
2406 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0595
2407 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
2408 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0596
2409 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
2410 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0597
2411 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
2412 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0598
2413 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
2414 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0599
2415 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
2416 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x059a
2417 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
2418 #define mmHUBPREQ0_DCN_EXPANSION_MODE 0x059b
2419 #define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2
2420 #define mmHUBPREQ0_DCN_TTU_QOS_WM 0x059c
2421 #define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2
2422 #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x059d
2423 #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
2424 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x059e
2425 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
2426 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x059f
2427 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
2428 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x05a0
2429 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
2430 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x05a1
2431 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
2432 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x05a2
2433 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
2434 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x05a3
2435 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
2436 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x05a4
2437 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2
2438 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x05a5
2439 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2
2440 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x05a6
2441 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2
2442 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x05a7
2443 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2
2444 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x05a8
2445 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
2446 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x05a9
2447 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
2448 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x05aa
2449 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
2450 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x05ab
2451 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
2452 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x05ac
2453 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
2454 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x05ad
2455 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
2456 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x05ae
2457 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
2458 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x05af
2459 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
2460 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x05b0
2461 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
2462 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x05b1
2463 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
2464 #define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS 0x05b2
2465 #define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2
2466 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x05b3
2467 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
2468 #define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL 0x05b4
2469 #define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2
2470 #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x05b5
2471 #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
2472 #define mmHUBPREQ0_BLANK_OFFSET_0 0x05b6
2473 #define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2
2474 #define mmHUBPREQ0_BLANK_OFFSET_1 0x05b7
2475 #define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2
2476 #define mmHUBPREQ0_DST_DIMENSIONS 0x05b8
2477 #define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2
2478 #define mmHUBPREQ0_DST_AFTER_SCALER 0x05b9
2479 #define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2
2480 #define mmHUBPREQ0_PREFETCH_SETTINS 0x05ba
2481 #define mmHUBPREQ0_PREFETCH_SETTINS_BASE_IDX 2
2482 #define mmHUBPREQ0_PREFETCH_SETTINS_C 0x05bb
2483 #define mmHUBPREQ0_PREFETCH_SETTINS_C_BASE_IDX 2
2484 #define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x05bc
2485 #define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2
2486 #define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x05bd
2487 #define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2
2488 #define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x05be
2489 #define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2
2490 #define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x05bf
2491 #define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2
2492 #define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x05c0
2493 #define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2
2494 #define mmHUBPREQ0_NOM_PARAMETERS_0 0x05c1
2495 #define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2
2496 #define mmHUBPREQ0_NOM_PARAMETERS_1 0x05c2
2497 #define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2
2498 #define mmHUBPREQ0_NOM_PARAMETERS_2 0x05c3
2499 #define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2
2500 #define mmHUBPREQ0_NOM_PARAMETERS_3 0x05c4
2501 #define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2
2502 #define mmHUBPREQ0_NOM_PARAMETERS_4 0x05c5
2503 #define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2
2504 #define mmHUBPREQ0_NOM_PARAMETERS_5 0x05c6
2505 #define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2
2506 #define mmHUBPREQ0_NOM_PARAMETERS_6 0x05c7
2507 #define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2
2508 #define mmHUBPREQ0_NOM_PARAMETERS_7 0x05c8
2509 #define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2
2510 #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x05c9
2511 #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2
2512 #define mmHUBPREQ0_PER_LINE_DELIVERY 0x05ca
2513 #define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2
2514 #define mmHUBPREQ0_CURSOR_SETTINS 0x05cb
2515 #define mmHUBPREQ0_CURSOR_SETTINS_BASE_IDX 2
2516 #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x05cc
2517 #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
2518 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x05cd
2519 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
2520 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x05ce
2521 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
2524 // addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
2525 // base address: 0x0
2526 #define mmHUBPRET0_HUBPRET_CONTROL 0x05e0
2527 #define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2
2528 #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x05e1
2529 #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
2530 #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x05e2
2531 #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
2532 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x05e3
2533 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
2534 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x05e4
2535 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
2536 #define mmHUBPRET0_HUBPRET_READ_LINE0 0x05e5
2537 #define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2
2538 #define mmHUBPRET0_HUBPRET_READ_LINE1 0x05e6
2539 #define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2
2540 #define mmHUBPRET0_HUBPRET_INTERRUPT 0x05e7
2541 #define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2
2542 #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x05e8
2543 #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
2544 #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x05e9
2545 #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
2548 // addressBlock: dce_dc_dcbubp0_dispdec_cursor_dispdec
2549 // base address: 0x0
2550 #define mmCURSOR0_CURSOR_CONTROL 0x05ec
2551 #define mmCURSOR0_CURSOR_CONTROL_BASE_IDX 2
2552 #define mmCURSOR0_CURSOR_SURFACE_ADDRESS 0x05ed
2553 #define mmCURSOR0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
2554 #define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH 0x05ee
2555 #define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2556 #define mmCURSOR0_CURSOR_SIZE 0x05ef
2557 #define mmCURSOR0_CURSOR_SIZE_BASE_IDX 2
2558 #define mmCURSOR0_CURSOR_POSITION 0x05f0
2559 #define mmCURSOR0_CURSOR_POSITION_BASE_IDX 2
2560 #define mmCURSOR0_CURSOR_HOT_SPOT 0x05f1
2561 #define mmCURSOR0_CURSOR_HOT_SPOT_BASE_IDX 2
2562 #define mmCURSOR0_CURSOR_STEREO_CONTROL 0x05f2
2563 #define mmCURSOR0_CURSOR_STEREO_CONTROL_BASE_IDX 2
2564 #define mmCURSOR0_CURSOR_DST_OFFSET 0x05f3
2565 #define mmCURSOR0_CURSOR_DST_OFFSET_BASE_IDX 2
2566 #define mmCURSOR0_CURSOR_MEM_PWR_CTRL 0x05f4
2567 #define mmCURSOR0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
2568 #define mmCURSOR0_CURSOR_MEM_PWR_STATUS 0x05f5
2569 #define mmCURSOR0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
2572 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
2573 // base address: 0x1844
2574 #define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0611
2575 #define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2
2576 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x0612
2577 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2
2578 #define mmDC_PERFMON8_PERFCOUNTER_STATE 0x0613
2579 #define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2
2580 #define mmDC_PERFMON8_PERFMON_CNTL 0x0614
2581 #define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2
2582 #define mmDC_PERFMON8_PERFMON_CNTL2 0x0615
2583 #define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2
2584 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x0616
2585 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
2586 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x0617
2587 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2
2588 #define mmDC_PERFMON8_PERFMON_HI 0x0618
2589 #define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2
2590 #define mmDC_PERFMON8_PERFMON_LOW 0x0619
2591 #define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2
2594 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
2595 // base address: 0x310
2596 #define mmHUBP1_DCSURF_SURFACE_CONFIG 0x061d
2597 #define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2
2598 #define mmHUBP1_DCSURF_ADDR_CONFIG 0x061e
2599 #define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2
2600 #define mmHUBP1_DCSURF_TILING_CONFIG 0x061f
2601 #define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2
2602 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x0620
2603 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
2604 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x0621
2605 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
2606 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x0622
2607 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
2608 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0623
2609 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
2610 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x0624
2611 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
2612 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x0625
2613 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
2614 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x0626
2615 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
2616 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0627
2617 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
2618 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x0628
2619 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
2620 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x0629
2621 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
2622 #define mmHUBP1_DCHUBP_CNTL 0x062a
2623 #define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2
2624 #define mmHUBP1_HUBP_CLK_CNTL 0x062b
2625 #define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2
2626 #define mmHUBP1_DCHUBP_VMPG_CONFIG 0x062c
2627 #define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2
2628 #define mmHUBP1_HUBPREQ_DEBUG_DB 0x062d
2629 #define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2
2630 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0632
2631 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
2632 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0633
2633 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
2636 // addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
2637 // base address: 0x310
2638 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x063f
2639 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2
2640 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x0640
2641 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
2642 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0641
2643 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
2644 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0642
2645 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2646 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0643
2647 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
2648 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0644
2649 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2650 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0645
2651 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
2652 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0646
2653 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2654 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0647
2655 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
2656 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0648
2657 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2658 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0649
2659 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
2660 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x064a
2661 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2662 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x064b
2663 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
2664 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x064c
2665 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2666 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x064d
2667 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
2668 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x064e
2669 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2670 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x064f
2671 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
2672 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0650
2673 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2674 #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x0651
2675 #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2
2676 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x0652
2677 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2
2678 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x0653
2679 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2
2680 #define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL 0x0654
2681 #define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2
2682 #define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME 0x0655
2683 #define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
2684 #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x0656
2685 #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
2686 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x0657
2687 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2
2688 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x0658
2689 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
2690 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x0659
2691 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
2692 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x065a
2693 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
2694 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x065b
2695 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
2696 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x065c
2697 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
2698 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x065d
2699 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
2700 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x065e
2701 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
2702 #define mmHUBPREQ1_DCN_EXPANSION_MODE 0x065f
2703 #define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2
2704 #define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0660
2705 #define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2
2706 #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0661
2707 #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
2708 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0662
2709 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
2710 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0663
2711 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
2712 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0664
2713 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
2714 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x0665
2715 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
2716 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x0666
2717 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
2718 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x0667
2719 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
2720 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x0668
2721 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2
2722 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x0669
2723 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2
2724 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x066a
2725 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2
2726 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x066b
2727 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2
2728 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x066c
2729 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
2730 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x066d
2731 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
2732 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x066e
2733 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
2734 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x066f
2735 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
2736 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0670
2737 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
2738 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x0671
2739 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
2740 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x0672
2741 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
2742 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0673
2743 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
2744 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0674
2745 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
2746 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0675
2747 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
2748 #define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS 0x0676
2749 #define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2
2750 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x0677
2751 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
2752 #define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL 0x0678
2753 #define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2
2754 #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x0679
2755 #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
2756 #define mmHUBPREQ1_BLANK_OFFSET_0 0x067a
2757 #define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2
2758 #define mmHUBPREQ1_BLANK_OFFSET_1 0x067b
2759 #define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2
2760 #define mmHUBPREQ1_DST_DIMENSIONS 0x067c
2761 #define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2
2762 #define mmHUBPREQ1_DST_AFTER_SCALER 0x067d
2763 #define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2
2764 #define mmHUBPREQ1_PREFETCH_SETTINS 0x067e
2765 #define mmHUBPREQ1_PREFETCH_SETTINS_BASE_IDX 2
2766 #define mmHUBPREQ1_PREFETCH_SETTINS_C 0x067f
2767 #define mmHUBPREQ1_PREFETCH_SETTINS_C_BASE_IDX 2
2768 #define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0680
2769 #define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2
2770 #define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0681
2771 #define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2
2772 #define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x0682
2773 #define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2
2774 #define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x0683
2775 #define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2
2776 #define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x0684
2777 #define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2
2778 #define mmHUBPREQ1_NOM_PARAMETERS_0 0x0685
2779 #define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2
2780 #define mmHUBPREQ1_NOM_PARAMETERS_1 0x0686
2781 #define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2
2782 #define mmHUBPREQ1_NOM_PARAMETERS_2 0x0687
2783 #define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2
2784 #define mmHUBPREQ1_NOM_PARAMETERS_3 0x0688
2785 #define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2
2786 #define mmHUBPREQ1_NOM_PARAMETERS_4 0x0689
2787 #define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2
2788 #define mmHUBPREQ1_NOM_PARAMETERS_5 0x068a
2789 #define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2
2790 #define mmHUBPREQ1_NOM_PARAMETERS_6 0x068b
2791 #define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2
2792 #define mmHUBPREQ1_NOM_PARAMETERS_7 0x068c
2793 #define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2
2794 #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x068d
2795 #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2
2796 #define mmHUBPREQ1_PER_LINE_DELIVERY 0x068e
2797 #define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2
2798 #define mmHUBPREQ1_CURSOR_SETTINS 0x068f
2799 #define mmHUBPREQ1_CURSOR_SETTINS_BASE_IDX 2
2800 #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0690
2801 #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
2802 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x0691
2803 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
2804 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x0692
2805 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
2808 // addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
2809 // base address: 0x310
2810 #define mmHUBPRET1_HUBPRET_CONTROL 0x06a4
2811 #define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2
2812 #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x06a5
2813 #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
2814 #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x06a6
2815 #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
2816 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x06a7
2817 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
2818 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x06a8
2819 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
2820 #define mmHUBPRET1_HUBPRET_READ_LINE0 0x06a9
2821 #define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2
2822 #define mmHUBPRET1_HUBPRET_READ_LINE1 0x06aa
2823 #define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2
2824 #define mmHUBPRET1_HUBPRET_INTERRUPT 0x06ab
2825 #define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2
2826 #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x06ac
2827 #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
2828 #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x06ad
2829 #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
2832 // addressBlock: dce_dc_dcbubp1_dispdec_cursor_dispdec
2833 // base address: 0x310
2834 #define mmCURSOR1_CURSOR_CONTROL 0x06b0
2835 #define mmCURSOR1_CURSOR_CONTROL_BASE_IDX 2
2836 #define mmCURSOR1_CURSOR_SURFACE_ADDRESS 0x06b1
2837 #define mmCURSOR1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
2838 #define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH 0x06b2
2839 #define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2840 #define mmCURSOR1_CURSOR_SIZE 0x06b3
2841 #define mmCURSOR1_CURSOR_SIZE_BASE_IDX 2
2842 #define mmCURSOR1_CURSOR_POSITION 0x06b4
2843 #define mmCURSOR1_CURSOR_POSITION_BASE_IDX 2
2844 #define mmCURSOR1_CURSOR_HOT_SPOT 0x06b5
2845 #define mmCURSOR1_CURSOR_HOT_SPOT_BASE_IDX 2
2846 #define mmCURSOR1_CURSOR_STEREO_CONTROL 0x06b6
2847 #define mmCURSOR1_CURSOR_STEREO_CONTROL_BASE_IDX 2
2848 #define mmCURSOR1_CURSOR_DST_OFFSET 0x06b7
2849 #define mmCURSOR1_CURSOR_DST_OFFSET_BASE_IDX 2
2850 #define mmCURSOR1_CURSOR_MEM_PWR_CTRL 0x06b8
2851 #define mmCURSOR1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
2852 #define mmCURSOR1_CURSOR_MEM_PWR_STATUS 0x06b9
2853 #define mmCURSOR1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
2856 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
2857 // base address: 0x1b54
2858 #define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x06d5
2859 #define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2
2860 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x06d6
2861 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2
2862 #define mmDC_PERFMON9_PERFCOUNTER_STATE 0x06d7
2863 #define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2
2864 #define mmDC_PERFMON9_PERFMON_CNTL 0x06d8
2865 #define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2
2866 #define mmDC_PERFMON9_PERFMON_CNTL2 0x06d9
2867 #define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2
2868 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x06da
2869 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
2870 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x06db
2871 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2
2872 #define mmDC_PERFMON9_PERFMON_HI 0x06dc
2873 #define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2
2874 #define mmDC_PERFMON9_PERFMON_LOW 0x06dd
2875 #define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2
2878 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
2879 // base address: 0x620
2880 #define mmHUBP2_DCSURF_SURFACE_CONFIG 0x06e1
2881 #define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2
2882 #define mmHUBP2_DCSURF_ADDR_CONFIG 0x06e2
2883 #define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2
2884 #define mmHUBP2_DCSURF_TILING_CONFIG 0x06e3
2885 #define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2
2886 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x06e4
2887 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
2888 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x06e5
2889 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
2890 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x06e6
2891 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
2892 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06e7
2893 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
2894 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x06e8
2895 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
2896 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x06e9
2897 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
2898 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x06ea
2899 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
2900 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06eb
2901 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
2902 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x06ec
2903 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
2904 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x06ed
2905 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
2906 #define mmHUBP2_DCHUBP_CNTL 0x06ee
2907 #define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2
2908 #define mmHUBP2_HUBP_CLK_CNTL 0x06ef
2909 #define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2
2910 #define mmHUBP2_DCHUBP_VMPG_CONFIG 0x06f0
2911 #define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2
2912 #define mmHUBP2_HUBPREQ_DEBUG_DB 0x06f1
2913 #define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2
2914 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06f6
2915 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
2916 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06f7
2917 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
2920 // addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
2921 // base address: 0x620
2922 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x0703
2923 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2
2924 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x0704
2925 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
2926 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0705
2927 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
2928 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0706
2929 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2930 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0707
2931 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
2932 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0708
2933 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2934 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0709
2935 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
2936 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x070a
2937 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2938 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x070b
2939 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
2940 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x070c
2941 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2942 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x070d
2943 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
2944 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x070e
2945 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2946 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x070f
2947 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
2948 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0710
2949 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2950 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0711
2951 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
2952 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0712
2953 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
2954 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0713
2955 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
2956 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0714
2957 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
2958 #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x0715
2959 #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2
2960 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x0716
2961 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2
2962 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x0717
2963 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2
2964 #define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL 0x0718
2965 #define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2
2966 #define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME 0x0719
2967 #define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
2968 #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x071a
2969 #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
2970 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x071b
2971 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2
2972 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x071c
2973 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
2974 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x071d
2975 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
2976 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x071e
2977 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
2978 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x071f
2979 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
2980 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0720
2981 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
2982 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0721
2983 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
2984 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0722
2985 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
2986 #define mmHUBPREQ2_DCN_EXPANSION_MODE 0x0723
2987 #define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2
2988 #define mmHUBPREQ2_DCN_TTU_QOS_WM 0x0724
2989 #define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2
2990 #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x0725
2991 #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
2992 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x0726
2993 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
2994 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x0727
2995 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
2996 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x0728
2997 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
2998 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x0729
2999 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
3000 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x072a
3001 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
3002 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x072b
3003 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
3004 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x072c
3005 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2
3006 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x072d
3007 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2
3008 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x072e
3009 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2
3010 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x072f
3011 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2
3012 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0730
3013 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
3014 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0731
3015 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
3016 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x0732
3017 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
3018 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x0733
3019 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
3020 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0734
3021 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
3022 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x0735
3023 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
3024 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x0736
3025 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
3026 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0737
3027 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
3028 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0738
3029 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
3030 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0739
3031 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
3032 #define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS 0x073a
3033 #define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2
3034 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x073b
3035 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
3036 #define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL 0x073c
3037 #define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2
3038 #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x073d
3039 #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
3040 #define mmHUBPREQ2_BLANK_OFFSET_0 0x073e
3041 #define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2
3042 #define mmHUBPREQ2_BLANK_OFFSET_1 0x073f
3043 #define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2
3044 #define mmHUBPREQ2_DST_DIMENSIONS 0x0740
3045 #define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2
3046 #define mmHUBPREQ2_DST_AFTER_SCALER 0x0741
3047 #define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2
3048 #define mmHUBPREQ2_PREFETCH_SETTINS 0x0742
3049 #define mmHUBPREQ2_PREFETCH_SETTINS_BASE_IDX 2
3050 #define mmHUBPREQ2_PREFETCH_SETTINS_C 0x0743
3051 #define mmHUBPREQ2_PREFETCH_SETTINS_C_BASE_IDX 2
3052 #define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0744
3053 #define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2
3054 #define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0745
3055 #define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2
3056 #define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0746
3057 #define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2
3058 #define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0747
3059 #define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2
3060 #define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0748
3061 #define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2
3062 #define mmHUBPREQ2_NOM_PARAMETERS_0 0x0749
3063 #define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2
3064 #define mmHUBPREQ2_NOM_PARAMETERS_1 0x074a
3065 #define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2
3066 #define mmHUBPREQ2_NOM_PARAMETERS_2 0x074b
3067 #define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2
3068 #define mmHUBPREQ2_NOM_PARAMETERS_3 0x074c
3069 #define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2
3070 #define mmHUBPREQ2_NOM_PARAMETERS_4 0x074d
3071 #define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2
3072 #define mmHUBPREQ2_NOM_PARAMETERS_5 0x074e
3073 #define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2
3074 #define mmHUBPREQ2_NOM_PARAMETERS_6 0x074f
3075 #define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2
3076 #define mmHUBPREQ2_NOM_PARAMETERS_7 0x0750
3077 #define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2
3078 #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0751
3079 #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2
3080 #define mmHUBPREQ2_PER_LINE_DELIVERY 0x0752
3081 #define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2
3082 #define mmHUBPREQ2_CURSOR_SETTINS 0x0753
3083 #define mmHUBPREQ2_CURSOR_SETTINS_BASE_IDX 2
3084 #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0754
3085 #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
3086 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0755
3087 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
3088 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0756
3089 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
3092 // addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
3093 // base address: 0x620
3094 #define mmHUBPRET2_HUBPRET_CONTROL 0x0768
3095 #define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2
3096 #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0769
3097 #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
3098 #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x076a
3099 #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
3100 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x076b
3101 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
3102 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x076c
3103 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
3104 #define mmHUBPRET2_HUBPRET_READ_LINE0 0x076d
3105 #define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2
3106 #define mmHUBPRET2_HUBPRET_READ_LINE1 0x076e
3107 #define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2
3108 #define mmHUBPRET2_HUBPRET_INTERRUPT 0x076f
3109 #define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2
3110 #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x0770
3111 #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
3112 #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x0771
3113 #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
3116 // addressBlock: dce_dc_dcbubp2_dispdec_cursor_dispdec
3117 // base address: 0x620
3118 #define mmCURSOR2_CURSOR_CONTROL 0x0774
3119 #define mmCURSOR2_CURSOR_CONTROL_BASE_IDX 2
3120 #define mmCURSOR2_CURSOR_SURFACE_ADDRESS 0x0775
3121 #define mmCURSOR2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
3122 #define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH 0x0776
3123 #define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3124 #define mmCURSOR2_CURSOR_SIZE 0x0777
3125 #define mmCURSOR2_CURSOR_SIZE_BASE_IDX 2
3126 #define mmCURSOR2_CURSOR_POSITION 0x0778
3127 #define mmCURSOR2_CURSOR_POSITION_BASE_IDX 2
3128 #define mmCURSOR2_CURSOR_HOT_SPOT 0x0779
3129 #define mmCURSOR2_CURSOR_HOT_SPOT_BASE_IDX 2
3130 #define mmCURSOR2_CURSOR_STEREO_CONTROL 0x077a
3131 #define mmCURSOR2_CURSOR_STEREO_CONTROL_BASE_IDX 2
3132 #define mmCURSOR2_CURSOR_DST_OFFSET 0x077b
3133 #define mmCURSOR2_CURSOR_DST_OFFSET_BASE_IDX 2
3134 #define mmCURSOR2_CURSOR_MEM_PWR_CTRL 0x077c
3135 #define mmCURSOR2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
3136 #define mmCURSOR2_CURSOR_MEM_PWR_STATUS 0x077d
3137 #define mmCURSOR2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
3140 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
3141 // base address: 0x1e64
3142 #define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x0799
3143 #define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2
3144 #define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x079a
3145 #define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2
3146 #define mmDC_PERFMON10_PERFCOUNTER_STATE 0x079b
3147 #define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2
3148 #define mmDC_PERFMON10_PERFMON_CNTL 0x079c
3149 #define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2
3150 #define mmDC_PERFMON10_PERFMON_CNTL2 0x079d
3151 #define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2
3152 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x079e
3153 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
3154 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x079f
3155 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2
3156 #define mmDC_PERFMON10_PERFMON_HI 0x07a0
3157 #define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2
3158 #define mmDC_PERFMON10_PERFMON_LOW 0x07a1
3159 #define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2
3162 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
3163 // base address: 0x930
3164 #define mmHUBP3_DCSURF_SURFACE_CONFIG 0x07a5
3165 #define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2
3166 #define mmHUBP3_DCSURF_ADDR_CONFIG 0x07a6
3167 #define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2
3168 #define mmHUBP3_DCSURF_TILING_CONFIG 0x07a7
3169 #define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2
3170 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x07a8
3171 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
3172 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a9
3173 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
3174 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x07aa
3175 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
3176 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07ab
3177 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
3178 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x07ac
3179 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
3180 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x07ad
3181 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
3182 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x07ae
3183 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
3184 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07af
3185 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
3186 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x07b0
3187 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
3188 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x07b1
3189 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
3190 #define mmHUBP3_DCHUBP_CNTL 0x07b2
3191 #define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2
3192 #define mmHUBP3_HUBP_CLK_CNTL 0x07b3
3193 #define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2
3194 #define mmHUBP3_DCHUBP_VMPG_CONFIG 0x07b4
3195 #define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2
3196 #define mmHUBP3_HUBPREQ_DEBUG_DB 0x07b5
3197 #define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2
3198 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07ba
3199 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
3200 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07bb
3201 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
3204 // addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
3205 // base address: 0x930
3206 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x07c7
3207 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2
3208 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x07c8
3209 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
3210 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c9
3211 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
3212 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07ca
3213 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3214 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07cb
3215 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
3216 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07cc
3217 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3218 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07cd
3219 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
3220 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07ce
3221 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3222 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07cf
3223 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
3224 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07d0
3225 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3226 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07d1
3227 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
3228 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07d2
3229 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3230 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07d3
3231 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
3232 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07d4
3233 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3234 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07d5
3235 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
3236 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07d6
3237 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3238 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d7
3239 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
3240 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d8
3241 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
3242 #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x07d9
3243 #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2
3244 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x07da
3245 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2
3246 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x07db
3247 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2
3248 #define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL 0x07dc
3249 #define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2
3250 #define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME 0x07dd
3251 #define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
3252 #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x07de
3253 #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
3254 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x07df
3255 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2
3256 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x07e0
3257 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
3258 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x07e1
3259 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
3260 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x07e2
3261 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
3262 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x07e3
3263 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
3264 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07e4
3265 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
3266 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07e5
3267 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
3268 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e6
3269 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
3270 #define mmHUBPREQ3_DCN_EXPANSION_MODE 0x07e7
3271 #define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2
3272 #define mmHUBPREQ3_DCN_TTU_QOS_WM 0x07e8
3273 #define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2
3274 #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x07e9
3275 #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
3276 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x07ea
3277 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
3278 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x07eb
3279 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
3280 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x07ec
3281 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
3282 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x07ed
3283 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
3284 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x07ee
3285 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
3286 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x07ef
3287 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
3288 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x07f0
3289 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2
3290 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x07f1
3291 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2
3292 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x07f2
3293 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2
3294 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x07f3
3295 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2
3296 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x07f4
3297 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
3298 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x07f5
3299 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
3300 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x07f6
3301 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
3302 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x07f7
3303 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
3304 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x07f8
3305 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
3306 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x07f9
3307 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
3308 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x07fa
3309 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
3310 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x07fb
3311 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
3312 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x07fc
3313 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
3314 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x07fd
3315 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
3316 #define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS 0x07fe
3317 #define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2
3318 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x07ff
3319 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
3320 #define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL 0x0800
3321 #define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2
3322 #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x0801
3323 #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
3324 #define mmHUBPREQ3_BLANK_OFFSET_0 0x0802
3325 #define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2
3326 #define mmHUBPREQ3_BLANK_OFFSET_1 0x0803
3327 #define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2
3328 #define mmHUBPREQ3_DST_DIMENSIONS 0x0804
3329 #define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2
3330 #define mmHUBPREQ3_DST_AFTER_SCALER 0x0805
3331 #define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2
3332 #define mmHUBPREQ3_PREFETCH_SETTINS 0x0806
3333 #define mmHUBPREQ3_PREFETCH_SETTINS_BASE_IDX 2
3334 #define mmHUBPREQ3_PREFETCH_SETTINS_C 0x0807
3335 #define mmHUBPREQ3_PREFETCH_SETTINS_C_BASE_IDX 2
3336 #define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x0808
3337 #define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2
3338 #define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x0809
3339 #define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2
3340 #define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x080a
3341 #define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2
3342 #define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x080b
3343 #define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2
3344 #define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x080c
3345 #define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2
3346 #define mmHUBPREQ3_NOM_PARAMETERS_0 0x080d
3347 #define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2
3348 #define mmHUBPREQ3_NOM_PARAMETERS_1 0x080e
3349 #define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2
3350 #define mmHUBPREQ3_NOM_PARAMETERS_2 0x080f
3351 #define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2
3352 #define mmHUBPREQ3_NOM_PARAMETERS_3 0x0810
3353 #define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2
3354 #define mmHUBPREQ3_NOM_PARAMETERS_4 0x0811
3355 #define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2
3356 #define mmHUBPREQ3_NOM_PARAMETERS_5 0x0812
3357 #define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2
3358 #define mmHUBPREQ3_NOM_PARAMETERS_6 0x0813
3359 #define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2
3360 #define mmHUBPREQ3_NOM_PARAMETERS_7 0x0814
3361 #define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2
3362 #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x0815
3363 #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2
3364 #define mmHUBPREQ3_PER_LINE_DELIVERY 0x0816
3365 #define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2
3366 #define mmHUBPREQ3_CURSOR_SETTINS 0x0817
3367 #define mmHUBPREQ3_CURSOR_SETTINS_BASE_IDX 2
3368 #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x0818
3369 #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
3370 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x0819
3371 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
3372 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x081a
3373 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
3376 // addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
3377 // base address: 0x930
3378 #define mmHUBPRET3_HUBPRET_CONTROL 0x082c
3379 #define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2
3380 #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x082d
3381 #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
3382 #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x082e
3383 #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
3384 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x082f
3385 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
3386 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0830
3387 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
3388 #define mmHUBPRET3_HUBPRET_READ_LINE0 0x0831
3389 #define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2
3390 #define mmHUBPRET3_HUBPRET_READ_LINE1 0x0832
3391 #define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2
3392 #define mmHUBPRET3_HUBPRET_INTERRUPT 0x0833
3393 #define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2
3394 #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0834
3395 #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
3396 #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0835
3397 #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
3400 // addressBlock: dce_dc_dcbubp3_dispdec_cursor_dispdec
3401 // base address: 0x930
3402 #define mmCURSOR3_CURSOR_CONTROL 0x0838
3403 #define mmCURSOR3_CURSOR_CONTROL_BASE_IDX 2
3404 #define mmCURSOR3_CURSOR_SURFACE_ADDRESS 0x0839
3405 #define mmCURSOR3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
3406 #define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH 0x083a
3407 #define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
3408 #define mmCURSOR3_CURSOR_SIZE 0x083b
3409 #define mmCURSOR3_CURSOR_SIZE_BASE_IDX 2
3410 #define mmCURSOR3_CURSOR_POSITION 0x083c
3411 #define mmCURSOR3_CURSOR_POSITION_BASE_IDX 2
3412 #define mmCURSOR3_CURSOR_HOT_SPOT 0x083d
3413 #define mmCURSOR3_CURSOR_HOT_SPOT_BASE_IDX 2
3414 #define mmCURSOR3_CURSOR_STEREO_CONTROL 0x083e
3415 #define mmCURSOR3_CURSOR_STEREO_CONTROL_BASE_IDX 2
3416 #define mmCURSOR3_CURSOR_DST_OFFSET 0x083f
3417 #define mmCURSOR3_CURSOR_DST_OFFSET_BASE_IDX 2
3418 #define mmCURSOR3_CURSOR_MEM_PWR_CTRL 0x0840
3419 #define mmCURSOR3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
3420 #define mmCURSOR3_CURSOR_MEM_PWR_STATUS 0x0841
3421 #define mmCURSOR3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
3424 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
3425 // base address: 0x2174
3426 #define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x085d
3427 #define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2
3428 #define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x085e
3429 #define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2
3430 #define mmDC_PERFMON11_PERFCOUNTER_STATE 0x085f
3431 #define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2
3432 #define mmDC_PERFMON11_PERFMON_CNTL 0x0860
3433 #define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2
3434 #define mmDC_PERFMON11_PERFMON_CNTL2 0x0861
3435 #define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2
3436 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0862
3437 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
3438 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x0863
3439 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2
3440 #define mmDC_PERFMON11_PERFMON_HI 0x0864
3441 #define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2
3442 #define mmDC_PERFMON11_PERFMON_LOW 0x0865
3443 #define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2
3446 // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
3447 // base address: 0x0
3448 #define mmDPP_TOP0_DPP_CONTROL 0x0c3d
3449 #define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2
3450 #define mmDPP_TOP0_DPP_SOFT_RESET 0x0c3e
3451 #define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2
3452 #define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0c3f
3453 #define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2
3454 #define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0c40
3455 #define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2
3456 #define mmDPP_TOP0_DPP_CRC_CTRL 0x0c41
3457 #define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2
3458 #define mmDPP_TOP0_HOST_READ_CONTROL 0x0c42
3459 #define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2
3462 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
3463 // base address: 0x0
3464 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0c47
3465 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
3466 #define mmCNVC_CFG0_FORMAT_CONTROL 0x0c48
3467 #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2
3468 #define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS 0x0c49
3469 #define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS_BASE_IDX 2
3470 #define mmCNVC_CFG0_DENORM_CONTROL 0x0c4a
3471 #define mmCNVC_CFG0_DENORM_CONTROL_BASE_IDX 2
3472 #define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0c4c
3473 #define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2
3474 #define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0c4d
3475 #define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2
3476 #define mmCNVC_CFG0_COLOR_KEYER_RED 0x0c4e
3477 #define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2
3478 #define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0c4f
3479 #define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2
3480 #define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0c50
3481 #define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2
3484 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
3485 // base address: 0x0
3486 #define mmCNVC_CUR0_CURSOR0_CONTROL 0x0c58
3487 #define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2
3488 #define mmCNVC_CUR0_CURSOR0_COLOR0 0x0c59
3489 #define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2
3490 #define mmCNVC_CUR0_CURSOR0_COLOR1 0x0c5a
3491 #define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2
3492 #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0c5b
3493 #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
3496 // addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
3497 // base address: 0x0
3498 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0c62
3499 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
3500 #define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0c63
3501 #define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
3502 #define mmDSCL0_SCL_MODE 0x0c64
3503 #define mmDSCL0_SCL_MODE_BASE_IDX 2
3504 #define mmDSCL0_SCL_TAP_CONTROL 0x0c65
3505 #define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2
3506 #define mmDSCL0_DSCL_CONTROL 0x0c66
3507 #define mmDSCL0_DSCL_CONTROL_BASE_IDX 2
3508 #define mmDSCL0_DSCL_2TAP_CONTROL 0x0c67
3509 #define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2
3510 #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0c68
3511 #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
3512 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0c69
3513 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
3514 #define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0c6a
3515 #define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2
3516 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0c6b
3517 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
3518 #define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0c6c
3519 #define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
3520 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0c6d
3521 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
3522 #define mmDSCL0_SCL_VERT_FILTER_INIT 0x0c6e
3523 #define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2
3524 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0c6f
3525 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
3526 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0c70
3527 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
3528 #define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0c71
3529 #define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
3530 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0c72
3531 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
3532 #define mmDSCL0_SCL_BLACK_OFFSET 0x0c73
3533 #define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX 2
3534 #define mmDSCL0_DSCL_UPDATE 0x0c74
3535 #define mmDSCL0_DSCL_UPDATE_BASE_IDX 2
3536 #define mmDSCL0_DSCL_AUTOCAL 0x0c75
3537 #define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2
3538 #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0c76
3539 #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
3540 #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0c77
3541 #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
3542 #define mmDSCL0_OTG_H_BLANK 0x0c78
3543 #define mmDSCL0_OTG_H_BLANK_BASE_IDX 2
3544 #define mmDSCL0_OTG_V_BLANK 0x0c79
3545 #define mmDSCL0_OTG_V_BLANK_BASE_IDX 2
3546 #define mmDSCL0_RECOUT_START 0x0c7a
3547 #define mmDSCL0_RECOUT_START_BASE_IDX 2
3548 #define mmDSCL0_RECOUT_SIZE 0x0c7b
3549 #define mmDSCL0_RECOUT_SIZE_BASE_IDX 2
3550 #define mmDSCL0_MPC_SIZE 0x0c7c
3551 #define mmDSCL0_MPC_SIZE_BASE_IDX 2
3552 #define mmDSCL0_LB_DATA_FORMAT 0x0c7d
3553 #define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2
3554 #define mmDSCL0_LB_MEMORY_CTRL 0x0c7e
3555 #define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2
3556 #define mmDSCL0_LB_V_COUNTER 0x0c7f
3557 #define mmDSCL0_LB_V_COUNTER_BASE_IDX 2
3558 #define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0c80
3559 #define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2
3560 #define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0c81
3561 #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2
3562 #define mmDSCL0_OBUF_CONTROL 0x0c82
3563 #define mmDSCL0_OBUF_CONTROL_BASE_IDX 2
3564 #define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0c83
3565 #define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2
3568 // addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
3569 // base address: 0x0
3570 #define mmCM0_CM_CONTROL 0x0c92
3571 #define mmCM0_CM_CONTROL_BASE_IDX 2
3572 #define mmCM0_CM_COMA_C11_C12 0x0c93
3573 #define mmCM0_CM_COMA_C11_C12_BASE_IDX 2
3574 #define mmCM0_CM_COMA_C13_C14 0x0c94
3575 #define mmCM0_CM_COMA_C13_C14_BASE_IDX 2
3576 #define mmCM0_CM_COMA_C21_C22 0x0c95
3577 #define mmCM0_CM_COMA_C21_C22_BASE_IDX 2
3578 #define mmCM0_CM_COMA_C23_C24 0x0c96
3579 #define mmCM0_CM_COMA_C23_C24_BASE_IDX 2
3580 #define mmCM0_CM_COMA_C31_C32 0x0c97
3581 #define mmCM0_CM_COMA_C31_C32_BASE_IDX 2
3582 #define mmCM0_CM_COMA_C33_C34 0x0c98
3583 #define mmCM0_CM_COMA_C33_C34_BASE_IDX 2
3584 #define mmCM0_CM_COMB_C11_C12 0x0c99
3585 #define mmCM0_CM_COMB_C11_C12_BASE_IDX 2
3586 #define mmCM0_CM_COMB_C13_C14 0x0c9a
3587 #define mmCM0_CM_COMB_C13_C14_BASE_IDX 2
3588 #define mmCM0_CM_COMB_C21_C22 0x0c9b
3589 #define mmCM0_CM_COMB_C21_C22_BASE_IDX 2
3590 #define mmCM0_CM_COMB_C23_C24 0x0c9c
3591 #define mmCM0_CM_COMB_C23_C24_BASE_IDX 2
3592 #define mmCM0_CM_COMB_C31_C32 0x0c9d
3593 #define mmCM0_CM_COMB_C31_C32_BASE_IDX 2
3594 #define mmCM0_CM_COMB_C33_C34 0x0c9e
3595 #define mmCM0_CM_COMB_C33_C34_BASE_IDX 2
3596 #define mmCM0_CM_IGAM_CONTROL 0x0c9f
3597 #define mmCM0_CM_IGAM_CONTROL_BASE_IDX 2
3598 #define mmCM0_CM_IGAM_LUT_RW_CONTROL 0x0ca0
3599 #define mmCM0_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2
3600 #define mmCM0_CM_IGAM_LUT_RW_INDEX 0x0ca1
3601 #define mmCM0_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2
3602 #define mmCM0_CM_IGAM_LUT_SEQ_COLOR 0x0ca2
3603 #define mmCM0_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2
3604 #define mmCM0_CM_IGAM_LUT_30_COLOR 0x0ca3
3605 #define mmCM0_CM_IGAM_LUT_30_COLOR_BASE_IDX 2
3606 #define mmCM0_CM_IGAM_LUT_PWL_DATA 0x0ca4
3607 #define mmCM0_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2
3608 #define mmCM0_CM_IGAM_LUT_AUTOFILL 0x0ca5
3609 #define mmCM0_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2
3610 #define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0ca6
3611 #define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2
3612 #define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0ca7
3613 #define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2
3614 #define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED 0x0ca8
3615 #define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2
3616 #define mmCM0_CM_ICSC_CONTROL 0x0ca9
3617 #define mmCM0_CM_ICSC_CONTROL_BASE_IDX 2
3618 #define mmCM0_CM_ICSC_C11_C12 0x0caa
3619 #define mmCM0_CM_ICSC_C11_C12_BASE_IDX 2
3620 #define mmCM0_CM_ICSC_C13_C14 0x0cab
3621 #define mmCM0_CM_ICSC_C13_C14_BASE_IDX 2
3622 #define mmCM0_CM_ICSC_C21_C22 0x0cac
3623 #define mmCM0_CM_ICSC_C21_C22_BASE_IDX 2
3624 #define mmCM0_CM_ICSC_C23_C24 0x0cad
3625 #define mmCM0_CM_ICSC_C23_C24_BASE_IDX 2
3626 #define mmCM0_CM_ICSC_C31_C32 0x0cae
3627 #define mmCM0_CM_ICSC_C31_C32_BASE_IDX 2
3628 #define mmCM0_CM_ICSC_C33_C34 0x0caf
3629 #define mmCM0_CM_ICSC_C33_C34_BASE_IDX 2
3630 #define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0cb0
3631 #define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
3632 #define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0cb1
3633 #define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
3634 #define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0cb2
3635 #define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
3636 #define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0cb3
3637 #define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
3638 #define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0cb4
3639 #define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
3640 #define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0cb5
3641 #define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
3642 #define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0cb6
3643 #define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
3644 #define mmCM0_CM_OCSC_CONTROL 0x0cb7
3645 #define mmCM0_CM_OCSC_CONTROL_BASE_IDX 2
3646 #define mmCM0_CM_OCSC_C11_C12 0x0cb8
3647 #define mmCM0_CM_OCSC_C11_C12_BASE_IDX 2
3648 #define mmCM0_CM_OCSC_C13_C14 0x0cb9
3649 #define mmCM0_CM_OCSC_C13_C14_BASE_IDX 2
3650 #define mmCM0_CM_OCSC_C21_C22 0x0cba
3651 #define mmCM0_CM_OCSC_C21_C22_BASE_IDX 2
3652 #define mmCM0_CM_OCSC_C23_C24 0x0cbb
3653 #define mmCM0_CM_OCSC_C23_C24_BASE_IDX 2
3654 #define mmCM0_CM_OCSC_C31_C32 0x0cbc
3655 #define mmCM0_CM_OCSC_C31_C32_BASE_IDX 2
3656 #define mmCM0_CM_OCSC_C33_C34 0x0cbd
3657 #define mmCM0_CM_OCSC_C33_C34_BASE_IDX 2
3658 #define mmCM0_CM_BNS_VALUES_R 0x0cbe
3659 #define mmCM0_CM_BNS_VALUES_R_BASE_IDX 2
3660 #define mmCM0_CM_BNS_VALUES_G 0x0cbf
3661 #define mmCM0_CM_BNS_VALUES_G_BASE_IDX 2
3662 #define mmCM0_CM_BNS_VALUES_B 0x0cc0
3663 #define mmCM0_CM_BNS_VALUES_B_BASE_IDX 2
3664 #define mmCM0_CM_DGAM_CONTROL 0x0cc1
3665 #define mmCM0_CM_DGAM_CONTROL_BASE_IDX 2
3666 #define mmCM0_CM_DGAM_LUT_INDEX 0x0cc2
3667 #define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX 2
3668 #define mmCM0_CM_DGAM_LUT_DATA 0x0cc3
3669 #define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX 2
3670 #define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 0x0cc4
3671 #define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
3672 #define mmCM0_CM_DGAM_RAMA_START_CNTL_B 0x0cc5
3673 #define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
3674 #define mmCM0_CM_DGAM_RAMA_START_CNTL_G 0x0cc6
3675 #define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
3676 #define mmCM0_CM_DGAM_RAMA_START_CNTL_R 0x0cc7
3677 #define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
3678 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0cc8
3679 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
3680 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0cc9
3681 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
3682 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0cca
3683 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
3684 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_B 0x0ccb
3685 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
3686 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_B 0x0ccc
3687 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
3688 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_G 0x0ccd
3689 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
3690 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_G 0x0cce
3691 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
3692 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R 0x0ccf
3693 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
3694 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_R 0x0cd0
3695 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
3696 #define mmCM0_CM_DGAM_RAMA_REGION_0_1 0x0cd1
3697 #define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
3698 #define mmCM0_CM_DGAM_RAMA_REGION_2_3 0x0cd2
3699 #define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
3700 #define mmCM0_CM_DGAM_RAMA_REGION_4_5 0x0cd3
3701 #define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
3702 #define mmCM0_CM_DGAM_RAMA_REGION_6_7 0x0cd4
3703 #define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
3704 #define mmCM0_CM_DGAM_RAMA_REGION_8_9 0x0cd5
3705 #define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
3706 #define mmCM0_CM_DGAM_RAMA_REGION_10_11 0x0cd6
3707 #define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
3708 #define mmCM0_CM_DGAM_RAMA_REGION_12_13 0x0cd7
3709 #define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
3710 #define mmCM0_CM_DGAM_RAMA_REGION_14_15 0x0cd8
3711 #define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
3712 #define mmCM0_CM_DGAM_RAMB_START_CNTL_B 0x0cd9
3713 #define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
3714 #define mmCM0_CM_DGAM_RAMB_START_CNTL_G 0x0cda
3715 #define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
3716 #define mmCM0_CM_DGAM_RAMB_START_CNTL_R 0x0cdb
3717 #define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
3718 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0cdc
3719 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
3720 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0cdd
3721 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
3722 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0cde
3723 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
3724 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_B 0x0cdf
3725 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
3726 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_B 0x0ce0
3727 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
3728 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_G 0x0ce1
3729 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
3730 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_G 0x0ce2
3731 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
3732 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_R 0x0ce3
3733 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
3734 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_R 0x0ce4
3735 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
3736 #define mmCM0_CM_DGAM_RAMB_REGION_0_1 0x0ce5
3737 #define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
3738 #define mmCM0_CM_DGAM_RAMB_REGION_2_3 0x0ce6
3739 #define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
3740 #define mmCM0_CM_DGAM_RAMB_REGION_4_5 0x0ce7
3741 #define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
3742 #define mmCM0_CM_DGAM_RAMB_REGION_6_7 0x0ce8
3743 #define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
3744 #define mmCM0_CM_DGAM_RAMB_REGION_8_9 0x0ce9
3745 #define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
3746 #define mmCM0_CM_DGAM_RAMB_REGION_10_11 0x0cea
3747 #define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
3748 #define mmCM0_CM_DGAM_RAMB_REGION_12_13 0x0ceb
3749 #define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
3750 #define mmCM0_CM_DGAM_RAMB_REGION_14_15 0x0cec
3751 #define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
3752 #define mmCM0_CM_RGAM_CONTROL 0x0ced
3753 #define mmCM0_CM_RGAM_CONTROL_BASE_IDX 2
3754 #define mmCM0_CM_RGAM_LUT_INDEX 0x0cee
3755 #define mmCM0_CM_RGAM_LUT_INDEX_BASE_IDX 2
3756 #define mmCM0_CM_RGAM_LUT_DATA 0x0cef
3757 #define mmCM0_CM_RGAM_LUT_DATA_BASE_IDX 2
3758 #define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK 0x0cf0
3759 #define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
3760 #define mmCM0_CM_RGAM_RAMA_START_CNTL_B 0x0cf1
3761 #define mmCM0_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2
3762 #define mmCM0_CM_RGAM_RAMA_START_CNTL_G 0x0cf2
3763 #define mmCM0_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2
3764 #define mmCM0_CM_RGAM_RAMA_START_CNTL_R 0x0cf3
3765 #define mmCM0_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2
3766 #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0cf4
3767 #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
3768 #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0cf5
3769 #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
3770 #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0cf6
3771 #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
3772 #define mmCM0_CM_RGAM_RAMA_END_CNTL1_B 0x0cf7
3773 #define mmCM0_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2
3774 #define mmCM0_CM_RGAM_RAMA_END_CNTL2_B 0x0cf8
3775 #define mmCM0_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2
3776 #define mmCM0_CM_RGAM_RAMA_END_CNTL1_G 0x0cf9
3777 #define mmCM0_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2
3778 #define mmCM0_CM_RGAM_RAMA_END_CNTL2_G 0x0cfa
3779 #define mmCM0_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2
3780 #define mmCM0_CM_RGAM_RAMA_END_CNTL1_R 0x0cfb
3781 #define mmCM0_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2
3782 #define mmCM0_CM_RGAM_RAMA_END_CNTL2_R 0x0cfc
3783 #define mmCM0_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2
3784 #define mmCM0_CM_RGAM_RAMA_REGION_0_1 0x0cfd
3785 #define mmCM0_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2
3786 #define mmCM0_CM_RGAM_RAMA_REGION_2_3 0x0cfe
3787 #define mmCM0_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2
3788 #define mmCM0_CM_RGAM_RAMA_REGION_4_5 0x0cff
3789 #define mmCM0_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2
3790 #define mmCM0_CM_RGAM_RAMA_REGION_6_7 0x0d00
3791 #define mmCM0_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2
3792 #define mmCM0_CM_RGAM_RAMA_REGION_8_9 0x0d01
3793 #define mmCM0_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2
3794 #define mmCM0_CM_RGAM_RAMA_REGION_10_11 0x0d02
3795 #define mmCM0_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2
3796 #define mmCM0_CM_RGAM_RAMA_REGION_12_13 0x0d03
3797 #define mmCM0_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2
3798 #define mmCM0_CM_RGAM_RAMA_REGION_14_15 0x0d04
3799 #define mmCM0_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2
3800 #define mmCM0_CM_RGAM_RAMA_REGION_16_17 0x0d05
3801 #define mmCM0_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2
3802 #define mmCM0_CM_RGAM_RAMA_REGION_18_19 0x0d06
3803 #define mmCM0_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2
3804 #define mmCM0_CM_RGAM_RAMA_REGION_20_21 0x0d07
3805 #define mmCM0_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2
3806 #define mmCM0_CM_RGAM_RAMA_REGION_22_23 0x0d08
3807 #define mmCM0_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2
3808 #define mmCM0_CM_RGAM_RAMA_REGION_24_25 0x0d09
3809 #define mmCM0_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2
3810 #define mmCM0_CM_RGAM_RAMA_REGION_26_27 0x0d0a
3811 #define mmCM0_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2
3812 #define mmCM0_CM_RGAM_RAMA_REGION_28_29 0x0d0b
3813 #define mmCM0_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2
3814 #define mmCM0_CM_RGAM_RAMA_REGION_30_31 0x0d0c
3815 #define mmCM0_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2
3816 #define mmCM0_CM_RGAM_RAMA_REGION_32_33 0x0d0d
3817 #define mmCM0_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2
3818 #define mmCM0_CM_RGAM_RAMB_START_CNTL_B 0x0d0e
3819 #define mmCM0_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2
3820 #define mmCM0_CM_RGAM_RAMB_START_CNTL_G 0x0d0f
3821 #define mmCM0_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2
3822 #define mmCM0_CM_RGAM_RAMB_START_CNTL_R 0x0d10
3823 #define mmCM0_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2
3824 #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0d11
3825 #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
3826 #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0d12
3827 #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
3828 #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0d13
3829 #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
3830 #define mmCM0_CM_RGAM_RAMB_END_CNTL1_B 0x0d14
3831 #define mmCM0_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2
3832 #define mmCM0_CM_RGAM_RAMB_END_CNTL2_B 0x0d15
3833 #define mmCM0_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2
3834 #define mmCM0_CM_RGAM_RAMB_END_CNTL1_G 0x0d16
3835 #define mmCM0_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2
3836 #define mmCM0_CM_RGAM_RAMB_END_CNTL2_G 0x0d17
3837 #define mmCM0_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2
3838 #define mmCM0_CM_RGAM_RAMB_END_CNTL1_R 0x0d18
3839 #define mmCM0_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2
3840 #define mmCM0_CM_RGAM_RAMB_END_CNTL2_R 0x0d19
3841 #define mmCM0_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2
3842 #define mmCM0_CM_RGAM_RAMB_REGION_0_1 0x0d1a
3843 #define mmCM0_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2
3844 #define mmCM0_CM_RGAM_RAMB_REGION_2_3 0x0d1b
3845 #define mmCM0_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2
3846 #define mmCM0_CM_RGAM_RAMB_REGION_4_5 0x0d1c
3847 #define mmCM0_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2
3848 #define mmCM0_CM_RGAM_RAMB_REGION_6_7 0x0d1d
3849 #define mmCM0_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2
3850 #define mmCM0_CM_RGAM_RAMB_REGION_8_9 0x0d1e
3851 #define mmCM0_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2
3852 #define mmCM0_CM_RGAM_RAMB_REGION_10_11 0x0d1f
3853 #define mmCM0_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2
3854 #define mmCM0_CM_RGAM_RAMB_REGION_12_13 0x0d20
3855 #define mmCM0_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2
3856 #define mmCM0_CM_RGAM_RAMB_REGION_14_15 0x0d21
3857 #define mmCM0_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2
3858 #define mmCM0_CM_RGAM_RAMB_REGION_16_17 0x0d22
3859 #define mmCM0_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2
3860 #define mmCM0_CM_RGAM_RAMB_REGION_18_19 0x0d23
3861 #define mmCM0_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2
3862 #define mmCM0_CM_RGAM_RAMB_REGION_20_21 0x0d24
3863 #define mmCM0_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2
3864 #define mmCM0_CM_RGAM_RAMB_REGION_22_23 0x0d25
3865 #define mmCM0_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2
3866 #define mmCM0_CM_RGAM_RAMB_REGION_24_25 0x0d26
3867 #define mmCM0_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2
3868 #define mmCM0_CM_RGAM_RAMB_REGION_26_27 0x0d27
3869 #define mmCM0_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2
3870 #define mmCM0_CM_RGAM_RAMB_REGION_28_29 0x0d28
3871 #define mmCM0_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2
3872 #define mmCM0_CM_RGAM_RAMB_REGION_30_31 0x0d29
3873 #define mmCM0_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2
3874 #define mmCM0_CM_RGAM_RAMB_REGION_32_33 0x0d2a
3875 #define mmCM0_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2
3876 #define mmCM0_CM_HDR_MULT_COEF 0x0d2b
3877 #define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2
3878 #define mmCM0_CM_RANGE_CLAMP_CONTROL_R 0x0d2c
3879 #define mmCM0_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2
3880 #define mmCM0_CM_RANGE_CLAMP_CONTROL_G 0x0d2d
3881 #define mmCM0_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2
3882 #define mmCM0_CM_RANGE_CLAMP_CONTROL_B 0x0d2e
3883 #define mmCM0_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2
3884 #define mmCM0_CM_DENORM_CONTROL 0x0d2f
3885 #define mmCM0_CM_DENORM_CONTROL_BASE_IDX 2
3886 #define mmCM0_CM_CMOUT_CONTROL 0x0d30
3887 #define mmCM0_CM_CMOUT_CONTROL_BASE_IDX 2
3888 #define mmCM0_CM_CMOUT_RANDOM_SEEDS 0x0d31
3889 #define mmCM0_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2
3890 #define mmCM0_CM_MEM_PWR_CTRL 0x0d32
3891 #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
3892 #define mmCM0_CM_MEM_PWR_STATUS 0x0d33
3893 #define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
3896 // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
3897 // base address: 0x3530
3898 #define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x0d4c
3899 #define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2
3900 #define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x0d4d
3901 #define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2
3902 #define mmDC_PERFMON12_PERFCOUNTER_STATE 0x0d4e
3903 #define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2
3904 #define mmDC_PERFMON12_PERFMON_CNTL 0x0d4f
3905 #define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2
3906 #define mmDC_PERFMON12_PERFMON_CNTL2 0x0d50
3907 #define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2
3908 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0d51
3909 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
3910 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x0d52
3911 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2
3912 #define mmDC_PERFMON12_PERFMON_HI 0x0d53
3913 #define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2
3914 #define mmDC_PERFMON12_PERFMON_LOW 0x0d54
3915 #define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2
3918 // addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
3919 // base address: 0x46c
3920 #define mmDPP_TOP1_DPP_CONTROL 0x0d58
3921 #define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2
3922 #define mmDPP_TOP1_DPP_SOFT_RESET 0x0d59
3923 #define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2
3924 #define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0d5a
3925 #define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2
3926 #define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0d5b
3927 #define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2
3928 #define mmDPP_TOP1_DPP_CRC_CTRL 0x0d5c
3929 #define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2
3930 #define mmDPP_TOP1_HOST_READ_CONTROL 0x0d5d
3931 #define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2
3934 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
3935 // base address: 0x46c
3936 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0d62
3937 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
3938 #define mmCNVC_CFG1_FORMAT_CONTROL 0x0d63
3939 #define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2
3940 #define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS 0x0d64
3941 #define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS_BASE_IDX 2
3942 #define mmCNVC_CFG1_DENORM_CONTROL 0x0d65
3943 #define mmCNVC_CFG1_DENORM_CONTROL_BASE_IDX 2
3944 #define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0d67
3945 #define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2
3946 #define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0d68
3947 #define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2
3948 #define mmCNVC_CFG1_COLOR_KEYER_RED 0x0d69
3949 #define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2
3950 #define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0d6a
3951 #define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2
3952 #define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0d6b
3953 #define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2
3956 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
3957 // base address: 0x46c
3958 #define mmCNVC_CUR1_CURSOR0_CONTROL 0x0d73
3959 #define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2
3960 #define mmCNVC_CUR1_CURSOR0_COLOR0 0x0d74
3961 #define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2
3962 #define mmCNVC_CUR1_CURSOR0_COLOR1 0x0d75
3963 #define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2
3964 #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0d76
3965 #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
3968 // addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
3969 // base address: 0x46c
3970 #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0d7d
3971 #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
3972 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0d7e
3973 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
3974 #define mmDSCL1_SCL_MODE 0x0d7f
3975 #define mmDSCL1_SCL_MODE_BASE_IDX 2
3976 #define mmDSCL1_SCL_TAP_CONTROL 0x0d80
3977 #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2
3978 #define mmDSCL1_DSCL_CONTROL 0x0d81
3979 #define mmDSCL1_DSCL_CONTROL_BASE_IDX 2
3980 #define mmDSCL1_DSCL_2TAP_CONTROL 0x0d82
3981 #define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2
3982 #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0d83
3983 #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
3984 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0d84
3985 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
3986 #define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0d85
3987 #define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2
3988 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d86
3989 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
3990 #define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0d87
3991 #define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
3992 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0d88
3993 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
3994 #define mmDSCL1_SCL_VERT_FILTER_INIT 0x0d89
3995 #define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2
3996 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0d8a
3997 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
3998 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d8b
3999 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
4000 #define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0d8c
4001 #define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
4002 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0d8d
4003 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
4004 #define mmDSCL1_SCL_BLACK_OFFSET 0x0d8e
4005 #define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX 2
4006 #define mmDSCL1_DSCL_UPDATE 0x0d8f
4007 #define mmDSCL1_DSCL_UPDATE_BASE_IDX 2
4008 #define mmDSCL1_DSCL_AUTOCAL 0x0d90
4009 #define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2
4010 #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d91
4011 #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
4012 #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d92
4013 #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
4014 #define mmDSCL1_OTG_H_BLANK 0x0d93
4015 #define mmDSCL1_OTG_H_BLANK_BASE_IDX 2
4016 #define mmDSCL1_OTG_V_BLANK 0x0d94
4017 #define mmDSCL1_OTG_V_BLANK_BASE_IDX 2
4018 #define mmDSCL1_RECOUT_START 0x0d95
4019 #define mmDSCL1_RECOUT_START_BASE_IDX 2
4020 #define mmDSCL1_RECOUT_SIZE 0x0d96
4021 #define mmDSCL1_RECOUT_SIZE_BASE_IDX 2
4022 #define mmDSCL1_MPC_SIZE 0x0d97
4023 #define mmDSCL1_MPC_SIZE_BASE_IDX 2
4024 #define mmDSCL1_LB_DATA_FORMAT 0x0d98
4025 #define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2
4026 #define mmDSCL1_LB_MEMORY_CTRL 0x0d99
4027 #define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2
4028 #define mmDSCL1_LB_V_COUNTER 0x0d9a
4029 #define mmDSCL1_LB_V_COUNTER_BASE_IDX 2
4030 #define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0d9b
4031 #define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2
4032 #define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0d9c
4033 #define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2
4034 #define mmDSCL1_OBUF_CONTROL 0x0d9d
4035 #define mmDSCL1_OBUF_CONTROL_BASE_IDX 2
4036 #define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0d9e
4037 #define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2
4040 // addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
4041 // base address: 0x46c
4042 #define mmCM1_CM_CONTROL 0x0dad
4043 #define mmCM1_CM_CONTROL_BASE_IDX 2
4044 #define mmCM1_CM_COMA_C11_C12 0x0dae
4045 #define mmCM1_CM_COMA_C11_C12_BASE_IDX 2
4046 #define mmCM1_CM_COMA_C13_C14 0x0daf
4047 #define mmCM1_CM_COMA_C13_C14_BASE_IDX 2
4048 #define mmCM1_CM_COMA_C21_C22 0x0db0
4049 #define mmCM1_CM_COMA_C21_C22_BASE_IDX 2
4050 #define mmCM1_CM_COMA_C23_C24 0x0db1
4051 #define mmCM1_CM_COMA_C23_C24_BASE_IDX 2
4052 #define mmCM1_CM_COMA_C31_C32 0x0db2
4053 #define mmCM1_CM_COMA_C31_C32_BASE_IDX 2
4054 #define mmCM1_CM_COMA_C33_C34 0x0db3
4055 #define mmCM1_CM_COMA_C33_C34_BASE_IDX 2
4056 #define mmCM1_CM_COMB_C11_C12 0x0db4
4057 #define mmCM1_CM_COMB_C11_C12_BASE_IDX 2
4058 #define mmCM1_CM_COMB_C13_C14 0x0db5
4059 #define mmCM1_CM_COMB_C13_C14_BASE_IDX 2
4060 #define mmCM1_CM_COMB_C21_C22 0x0db6
4061 #define mmCM1_CM_COMB_C21_C22_BASE_IDX 2
4062 #define mmCM1_CM_COMB_C23_C24 0x0db7
4063 #define mmCM1_CM_COMB_C23_C24_BASE_IDX 2
4064 #define mmCM1_CM_COMB_C31_C32 0x0db8
4065 #define mmCM1_CM_COMB_C31_C32_BASE_IDX 2
4066 #define mmCM1_CM_COMB_C33_C34 0x0db9
4067 #define mmCM1_CM_COMB_C33_C34_BASE_IDX 2
4068 #define mmCM1_CM_IGAM_CONTROL 0x0dba
4069 #define mmCM1_CM_IGAM_CONTROL_BASE_IDX 2
4070 #define mmCM1_CM_IGAM_LUT_RW_CONTROL 0x0dbb
4071 #define mmCM1_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2
4072 #define mmCM1_CM_IGAM_LUT_RW_INDEX 0x0dbc
4073 #define mmCM1_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2
4074 #define mmCM1_CM_IGAM_LUT_SEQ_COLOR 0x0dbd
4075 #define mmCM1_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2
4076 #define mmCM1_CM_IGAM_LUT_30_COLOR 0x0dbe
4077 #define mmCM1_CM_IGAM_LUT_30_COLOR_BASE_IDX 2
4078 #define mmCM1_CM_IGAM_LUT_PWL_DATA 0x0dbf
4079 #define mmCM1_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2
4080 #define mmCM1_CM_IGAM_LUT_AUTOFILL 0x0dc0
4081 #define mmCM1_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2
4082 #define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0dc1
4083 #define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2
4084 #define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0dc2
4085 #define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2
4086 #define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED 0x0dc3
4087 #define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2
4088 #define mmCM1_CM_ICSC_CONTROL 0x0dc4
4089 #define mmCM1_CM_ICSC_CONTROL_BASE_IDX 2
4090 #define mmCM1_CM_ICSC_C11_C12 0x0dc5
4091 #define mmCM1_CM_ICSC_C11_C12_BASE_IDX 2
4092 #define mmCM1_CM_ICSC_C13_C14 0x0dc6
4093 #define mmCM1_CM_ICSC_C13_C14_BASE_IDX 2
4094 #define mmCM1_CM_ICSC_C21_C22 0x0dc7
4095 #define mmCM1_CM_ICSC_C21_C22_BASE_IDX 2
4096 #define mmCM1_CM_ICSC_C23_C24 0x0dc8
4097 #define mmCM1_CM_ICSC_C23_C24_BASE_IDX 2
4098 #define mmCM1_CM_ICSC_C31_C32 0x0dc9
4099 #define mmCM1_CM_ICSC_C31_C32_BASE_IDX 2
4100 #define mmCM1_CM_ICSC_C33_C34 0x0dca
4101 #define mmCM1_CM_ICSC_C33_C34_BASE_IDX 2
4102 #define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0dcb
4103 #define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
4104 #define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0dcc
4105 #define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
4106 #define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0dcd
4107 #define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
4108 #define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0dce
4109 #define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
4110 #define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0dcf
4111 #define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
4112 #define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0dd0
4113 #define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
4114 #define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0dd1
4115 #define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
4116 #define mmCM1_CM_OCSC_CONTROL 0x0dd2
4117 #define mmCM1_CM_OCSC_CONTROL_BASE_IDX 2
4118 #define mmCM1_CM_OCSC_C11_C12 0x0dd3
4119 #define mmCM1_CM_OCSC_C11_C12_BASE_IDX 2
4120 #define mmCM1_CM_OCSC_C13_C14 0x0dd4
4121 #define mmCM1_CM_OCSC_C13_C14_BASE_IDX 2
4122 #define mmCM1_CM_OCSC_C21_C22 0x0dd5
4123 #define mmCM1_CM_OCSC_C21_C22_BASE_IDX 2
4124 #define mmCM1_CM_OCSC_C23_C24 0x0dd6
4125 #define mmCM1_CM_OCSC_C23_C24_BASE_IDX 2
4126 #define mmCM1_CM_OCSC_C31_C32 0x0dd7
4127 #define mmCM1_CM_OCSC_C31_C32_BASE_IDX 2
4128 #define mmCM1_CM_OCSC_C33_C34 0x0dd8
4129 #define mmCM1_CM_OCSC_C33_C34_BASE_IDX 2
4130 #define mmCM1_CM_BNS_VALUES_R 0x0dd9
4131 #define mmCM1_CM_BNS_VALUES_R_BASE_IDX 2
4132 #define mmCM1_CM_BNS_VALUES_G 0x0dda
4133 #define mmCM1_CM_BNS_VALUES_G_BASE_IDX 2
4134 #define mmCM1_CM_BNS_VALUES_B 0x0ddb
4135 #define mmCM1_CM_BNS_VALUES_B_BASE_IDX 2
4136 #define mmCM1_CM_DGAM_CONTROL 0x0ddc
4137 #define mmCM1_CM_DGAM_CONTROL_BASE_IDX 2
4138 #define mmCM1_CM_DGAM_LUT_INDEX 0x0ddd
4139 #define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX 2
4140 #define mmCM1_CM_DGAM_LUT_DATA 0x0dde
4141 #define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX 2
4142 #define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 0x0ddf
4143 #define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
4144 #define mmCM1_CM_DGAM_RAMA_START_CNTL_B 0x0de0
4145 #define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
4146 #define mmCM1_CM_DGAM_RAMA_START_CNTL_G 0x0de1
4147 #define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
4148 #define mmCM1_CM_DGAM_RAMA_START_CNTL_R 0x0de2
4149 #define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
4150 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0de3
4151 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
4152 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0de4
4153 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
4154 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0de5
4155 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
4156 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_B 0x0de6
4157 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
4158 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_B 0x0de7
4159 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
4160 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G 0x0de8
4161 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
4162 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_G 0x0de9
4163 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
4164 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_R 0x0dea
4165 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
4166 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_R 0x0deb
4167 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
4168 #define mmCM1_CM_DGAM_RAMA_REGION_0_1 0x0dec
4169 #define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
4170 #define mmCM1_CM_DGAM_RAMA_REGION_2_3 0x0ded
4171 #define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
4172 #define mmCM1_CM_DGAM_RAMA_REGION_4_5 0x0dee
4173 #define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
4174 #define mmCM1_CM_DGAM_RAMA_REGION_6_7 0x0def
4175 #define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
4176 #define mmCM1_CM_DGAM_RAMA_REGION_8_9 0x0df0
4177 #define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
4178 #define mmCM1_CM_DGAM_RAMA_REGION_10_11 0x0df1
4179 #define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
4180 #define mmCM1_CM_DGAM_RAMA_REGION_12_13 0x0df2
4181 #define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
4182 #define mmCM1_CM_DGAM_RAMA_REGION_14_15 0x0df3
4183 #define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
4184 #define mmCM1_CM_DGAM_RAMB_START_CNTL_B 0x0df4
4185 #define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
4186 #define mmCM1_CM_DGAM_RAMB_START_CNTL_G 0x0df5
4187 #define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
4188 #define mmCM1_CM_DGAM_RAMB_START_CNTL_R 0x0df6
4189 #define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
4190 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0df7
4191 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
4192 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0df8
4193 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
4194 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0df9
4195 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
4196 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_B 0x0dfa
4197 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
4198 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_B 0x0dfb
4199 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
4200 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_G 0x0dfc
4201 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
4202 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_G 0x0dfd
4203 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
4204 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_R 0x0dfe
4205 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
4206 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_R 0x0dff
4207 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
4208 #define mmCM1_CM_DGAM_RAMB_REGION_0_1 0x0e00
4209 #define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
4210 #define mmCM1_CM_DGAM_RAMB_REGION_2_3 0x0e01
4211 #define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
4212 #define mmCM1_CM_DGAM_RAMB_REGION_4_5 0x0e02
4213 #define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
4214 #define mmCM1_CM_DGAM_RAMB_REGION_6_7 0x0e03
4215 #define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
4216 #define mmCM1_CM_DGAM_RAMB_REGION_8_9 0x0e04
4217 #define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
4218 #define mmCM1_CM_DGAM_RAMB_REGION_10_11 0x0e05
4219 #define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
4220 #define mmCM1_CM_DGAM_RAMB_REGION_12_13 0x0e06
4221 #define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
4222 #define mmCM1_CM_DGAM_RAMB_REGION_14_15 0x0e07
4223 #define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
4224 #define mmCM1_CM_RGAM_CONTROL 0x0e08
4225 #define mmCM1_CM_RGAM_CONTROL_BASE_IDX 2
4226 #define mmCM1_CM_RGAM_LUT_INDEX 0x0e09
4227 #define mmCM1_CM_RGAM_LUT_INDEX_BASE_IDX 2
4228 #define mmCM1_CM_RGAM_LUT_DATA 0x0e0a
4229 #define mmCM1_CM_RGAM_LUT_DATA_BASE_IDX 2
4230 #define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK 0x0e0b
4231 #define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
4232 #define mmCM1_CM_RGAM_RAMA_START_CNTL_B 0x0e0c
4233 #define mmCM1_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2
4234 #define mmCM1_CM_RGAM_RAMA_START_CNTL_G 0x0e0d
4235 #define mmCM1_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2
4236 #define mmCM1_CM_RGAM_RAMA_START_CNTL_R 0x0e0e
4237 #define mmCM1_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2
4238 #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0e0f
4239 #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
4240 #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0e10
4241 #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
4242 #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0e11
4243 #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
4244 #define mmCM1_CM_RGAM_RAMA_END_CNTL1_B 0x0e12
4245 #define mmCM1_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2
4246 #define mmCM1_CM_RGAM_RAMA_END_CNTL2_B 0x0e13
4247 #define mmCM1_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2
4248 #define mmCM1_CM_RGAM_RAMA_END_CNTL1_G 0x0e14
4249 #define mmCM1_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2
4250 #define mmCM1_CM_RGAM_RAMA_END_CNTL2_G 0x0e15
4251 #define mmCM1_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2
4252 #define mmCM1_CM_RGAM_RAMA_END_CNTL1_R 0x0e16
4253 #define mmCM1_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2
4254 #define mmCM1_CM_RGAM_RAMA_END_CNTL2_R 0x0e17
4255 #define mmCM1_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2
4256 #define mmCM1_CM_RGAM_RAMA_REGION_0_1 0x0e18
4257 #define mmCM1_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2
4258 #define mmCM1_CM_RGAM_RAMA_REGION_2_3 0x0e19
4259 #define mmCM1_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2
4260 #define mmCM1_CM_RGAM_RAMA_REGION_4_5 0x0e1a
4261 #define mmCM1_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2
4262 #define mmCM1_CM_RGAM_RAMA_REGION_6_7 0x0e1b
4263 #define mmCM1_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2
4264 #define mmCM1_CM_RGAM_RAMA_REGION_8_9 0x0e1c
4265 #define mmCM1_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2
4266 #define mmCM1_CM_RGAM_RAMA_REGION_10_11 0x0e1d
4267 #define mmCM1_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2
4268 #define mmCM1_CM_RGAM_RAMA_REGION_12_13 0x0e1e
4269 #define mmCM1_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2
4270 #define mmCM1_CM_RGAM_RAMA_REGION_14_15 0x0e1f
4271 #define mmCM1_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2
4272 #define mmCM1_CM_RGAM_RAMA_REGION_16_17 0x0e20
4273 #define mmCM1_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2
4274 #define mmCM1_CM_RGAM_RAMA_REGION_18_19 0x0e21
4275 #define mmCM1_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2
4276 #define mmCM1_CM_RGAM_RAMA_REGION_20_21 0x0e22
4277 #define mmCM1_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2
4278 #define mmCM1_CM_RGAM_RAMA_REGION_22_23 0x0e23
4279 #define mmCM1_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2
4280 #define mmCM1_CM_RGAM_RAMA_REGION_24_25 0x0e24
4281 #define mmCM1_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2
4282 #define mmCM1_CM_RGAM_RAMA_REGION_26_27 0x0e25
4283 #define mmCM1_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2
4284 #define mmCM1_CM_RGAM_RAMA_REGION_28_29 0x0e26
4285 #define mmCM1_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2
4286 #define mmCM1_CM_RGAM_RAMA_REGION_30_31 0x0e27
4287 #define mmCM1_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2
4288 #define mmCM1_CM_RGAM_RAMA_REGION_32_33 0x0e28
4289 #define mmCM1_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2
4290 #define mmCM1_CM_RGAM_RAMB_START_CNTL_B 0x0e29
4291 #define mmCM1_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2
4292 #define mmCM1_CM_RGAM_RAMB_START_CNTL_G 0x0e2a
4293 #define mmCM1_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2
4294 #define mmCM1_CM_RGAM_RAMB_START_CNTL_R 0x0e2b
4295 #define mmCM1_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2
4296 #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0e2c
4297 #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
4298 #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0e2d
4299 #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
4300 #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0e2e
4301 #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
4302 #define mmCM1_CM_RGAM_RAMB_END_CNTL1_B 0x0e2f
4303 #define mmCM1_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2
4304 #define mmCM1_CM_RGAM_RAMB_END_CNTL2_B 0x0e30
4305 #define mmCM1_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2
4306 #define mmCM1_CM_RGAM_RAMB_END_CNTL1_G 0x0e31
4307 #define mmCM1_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2
4308 #define mmCM1_CM_RGAM_RAMB_END_CNTL2_G 0x0e32
4309 #define mmCM1_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2
4310 #define mmCM1_CM_RGAM_RAMB_END_CNTL1_R 0x0e33
4311 #define mmCM1_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2
4312 #define mmCM1_CM_RGAM_RAMB_END_CNTL2_R 0x0e34
4313 #define mmCM1_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2
4314 #define mmCM1_CM_RGAM_RAMB_REGION_0_1 0x0e35
4315 #define mmCM1_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2
4316 #define mmCM1_CM_RGAM_RAMB_REGION_2_3 0x0e36
4317 #define mmCM1_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2
4318 #define mmCM1_CM_RGAM_RAMB_REGION_4_5 0x0e37
4319 #define mmCM1_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2
4320 #define mmCM1_CM_RGAM_RAMB_REGION_6_7 0x0e38
4321 #define mmCM1_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2
4322 #define mmCM1_CM_RGAM_RAMB_REGION_8_9 0x0e39
4323 #define mmCM1_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2
4324 #define mmCM1_CM_RGAM_RAMB_REGION_10_11 0x0e3a
4325 #define mmCM1_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2
4326 #define mmCM1_CM_RGAM_RAMB_REGION_12_13 0x0e3b
4327 #define mmCM1_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2
4328 #define mmCM1_CM_RGAM_RAMB_REGION_14_15 0x0e3c
4329 #define mmCM1_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2
4330 #define mmCM1_CM_RGAM_RAMB_REGION_16_17 0x0e3d
4331 #define mmCM1_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2
4332 #define mmCM1_CM_RGAM_RAMB_REGION_18_19 0x0e3e
4333 #define mmCM1_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2
4334 #define mmCM1_CM_RGAM_RAMB_REGION_20_21 0x0e3f
4335 #define mmCM1_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2
4336 #define mmCM1_CM_RGAM_RAMB_REGION_22_23 0x0e40
4337 #define mmCM1_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2
4338 #define mmCM1_CM_RGAM_RAMB_REGION_24_25 0x0e41
4339 #define mmCM1_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2
4340 #define mmCM1_CM_RGAM_RAMB_REGION_26_27 0x0e42
4341 #define mmCM1_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2
4342 #define mmCM1_CM_RGAM_RAMB_REGION_28_29 0x0e43
4343 #define mmCM1_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2
4344 #define mmCM1_CM_RGAM_RAMB_REGION_30_31 0x0e44
4345 #define mmCM1_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2
4346 #define mmCM1_CM_RGAM_RAMB_REGION_32_33 0x0e45
4347 #define mmCM1_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2
4348 #define mmCM1_CM_HDR_MULT_COEF 0x0e46
4349 #define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2
4350 #define mmCM1_CM_RANGE_CLAMP_CONTROL_R 0x0e47
4351 #define mmCM1_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2
4352 #define mmCM1_CM_RANGE_CLAMP_CONTROL_G 0x0e48
4353 #define mmCM1_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2
4354 #define mmCM1_CM_RANGE_CLAMP_CONTROL_B 0x0e49
4355 #define mmCM1_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2
4356 #define mmCM1_CM_DENORM_CONTROL 0x0e4a
4357 #define mmCM1_CM_DENORM_CONTROL_BASE_IDX 2
4358 #define mmCM1_CM_CMOUT_CONTROL 0x0e4b
4359 #define mmCM1_CM_CMOUT_CONTROL_BASE_IDX 2
4360 #define mmCM1_CM_CMOUT_RANDOM_SEEDS 0x0e4c
4361 #define mmCM1_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2
4362 #define mmCM1_CM_MEM_PWR_CTRL 0x0e4d
4363 #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
4364 #define mmCM1_CM_MEM_PWR_STATUS 0x0e4e
4365 #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
4368 // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
4369 // base address: 0x399c
4370 #define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x0e67
4371 #define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
4372 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x0e68
4373 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2
4374 #define mmDC_PERFMON13_PERFCOUNTER_STATE 0x0e69
4375 #define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2
4376 #define mmDC_PERFMON13_PERFMON_CNTL 0x0e6a
4377 #define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2
4378 #define mmDC_PERFMON13_PERFMON_CNTL2 0x0e6b
4379 #define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2
4380 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0e6c
4381 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
4382 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0e6d
4383 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2
4384 #define mmDC_PERFMON13_PERFMON_HI 0x0e6e
4385 #define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2
4386 #define mmDC_PERFMON13_PERFMON_LOW 0x0e6f
4387 #define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2
4390 // addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
4391 // base address: 0x8d8
4392 #define mmDPP_TOP2_DPP_CONTROL 0x0e73
4393 #define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2
4394 #define mmDPP_TOP2_DPP_SOFT_RESET 0x0e74
4395 #define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2
4396 #define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0e75
4397 #define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2
4398 #define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0e76
4399 #define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2
4400 #define mmDPP_TOP2_DPP_CRC_CTRL 0x0e77
4401 #define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2
4402 #define mmDPP_TOP2_HOST_READ_CONTROL 0x0e78
4403 #define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2
4406 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
4407 // base address: 0x8d8
4408 #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0e7d
4409 #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
4410 #define mmCNVC_CFG2_FORMAT_CONTROL 0x0e7e
4411 #define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2
4412 #define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS 0x0e7f
4413 #define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS_BASE_IDX 2
4414 #define mmCNVC_CFG2_DENORM_CONTROL 0x0e80
4415 #define mmCNVC_CFG2_DENORM_CONTROL_BASE_IDX 2
4416 #define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0e82
4417 #define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2
4418 #define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0e83
4419 #define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2
4420 #define mmCNVC_CFG2_COLOR_KEYER_RED 0x0e84
4421 #define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2
4422 #define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0e85
4423 #define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2
4424 #define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0e86
4425 #define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2
4428 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
4429 // base address: 0x8d8
4430 #define mmCNVC_CUR2_CURSOR0_CONTROL 0x0e8e
4431 #define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2
4432 #define mmCNVC_CUR2_CURSOR0_COLOR0 0x0e8f
4433 #define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2
4434 #define mmCNVC_CUR2_CURSOR0_COLOR1 0x0e90
4435 #define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2
4436 #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0e91
4437 #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
4440 // addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
4441 // base address: 0x8d8
4442 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0e98
4443 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
4444 #define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0e99
4445 #define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
4446 #define mmDSCL2_SCL_MODE 0x0e9a
4447 #define mmDSCL2_SCL_MODE_BASE_IDX 2
4448 #define mmDSCL2_SCL_TAP_CONTROL 0x0e9b
4449 #define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2
4450 #define mmDSCL2_DSCL_CONTROL 0x0e9c
4451 #define mmDSCL2_DSCL_CONTROL_BASE_IDX 2
4452 #define mmDSCL2_DSCL_2TAP_CONTROL 0x0e9d
4453 #define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2
4454 #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0e9e
4455 #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
4456 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0e9f
4457 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
4458 #define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0ea0
4459 #define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2
4460 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0ea1
4461 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
4462 #define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0ea2
4463 #define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
4464 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0ea3
4465 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
4466 #define mmDSCL2_SCL_VERT_FILTER_INIT 0x0ea4
4467 #define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2
4468 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0ea5
4469 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
4470 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0ea6
4471 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
4472 #define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0ea7
4473 #define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
4474 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0ea8
4475 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
4476 #define mmDSCL2_SCL_BLACK_OFFSET 0x0ea9
4477 #define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX 2
4478 #define mmDSCL2_DSCL_UPDATE 0x0eaa
4479 #define mmDSCL2_DSCL_UPDATE_BASE_IDX 2
4480 #define mmDSCL2_DSCL_AUTOCAL 0x0eab
4481 #define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2
4482 #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0eac
4483 #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
4484 #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0ead
4485 #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
4486 #define mmDSCL2_OTG_H_BLANK 0x0eae
4487 #define mmDSCL2_OTG_H_BLANK_BASE_IDX 2
4488 #define mmDSCL2_OTG_V_BLANK 0x0eaf
4489 #define mmDSCL2_OTG_V_BLANK_BASE_IDX 2
4490 #define mmDSCL2_RECOUT_START 0x0eb0
4491 #define mmDSCL2_RECOUT_START_BASE_IDX 2
4492 #define mmDSCL2_RECOUT_SIZE 0x0eb1
4493 #define mmDSCL2_RECOUT_SIZE_BASE_IDX 2
4494 #define mmDSCL2_MPC_SIZE 0x0eb2
4495 #define mmDSCL2_MPC_SIZE_BASE_IDX 2
4496 #define mmDSCL2_LB_DATA_FORMAT 0x0eb3
4497 #define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2
4498 #define mmDSCL2_LB_MEMORY_CTRL 0x0eb4
4499 #define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2
4500 #define mmDSCL2_LB_V_COUNTER 0x0eb5
4501 #define mmDSCL2_LB_V_COUNTER_BASE_IDX 2
4502 #define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0eb6
4503 #define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2
4504 #define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0eb7
4505 #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2
4506 #define mmDSCL2_OBUF_CONTROL 0x0eb8
4507 #define mmDSCL2_OBUF_CONTROL_BASE_IDX 2
4508 #define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0eb9
4509 #define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2
4512 // addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
4513 // base address: 0x8d8
4514 #define mmCM2_CM_CONTROL 0x0ec8
4515 #define mmCM2_CM_CONTROL_BASE_IDX 2
4516 #define mmCM2_CM_COMA_C11_C12 0x0ec9
4517 #define mmCM2_CM_COMA_C11_C12_BASE_IDX 2
4518 #define mmCM2_CM_COMA_C13_C14 0x0eca
4519 #define mmCM2_CM_COMA_C13_C14_BASE_IDX 2
4520 #define mmCM2_CM_COMA_C21_C22 0x0ecb
4521 #define mmCM2_CM_COMA_C21_C22_BASE_IDX 2
4522 #define mmCM2_CM_COMA_C23_C24 0x0ecc
4523 #define mmCM2_CM_COMA_C23_C24_BASE_IDX 2
4524 #define mmCM2_CM_COMA_C31_C32 0x0ecd
4525 #define mmCM2_CM_COMA_C31_C32_BASE_IDX 2
4526 #define mmCM2_CM_COMA_C33_C34 0x0ece
4527 #define mmCM2_CM_COMA_C33_C34_BASE_IDX 2
4528 #define mmCM2_CM_COMB_C11_C12 0x0ecf
4529 #define mmCM2_CM_COMB_C11_C12_BASE_IDX 2
4530 #define mmCM2_CM_COMB_C13_C14 0x0ed0
4531 #define mmCM2_CM_COMB_C13_C14_BASE_IDX 2
4532 #define mmCM2_CM_COMB_C21_C22 0x0ed1
4533 #define mmCM2_CM_COMB_C21_C22_BASE_IDX 2
4534 #define mmCM2_CM_COMB_C23_C24 0x0ed2
4535 #define mmCM2_CM_COMB_C23_C24_BASE_IDX 2
4536 #define mmCM2_CM_COMB_C31_C32 0x0ed3
4537 #define mmCM2_CM_COMB_C31_C32_BASE_IDX 2
4538 #define mmCM2_CM_COMB_C33_C34 0x0ed4
4539 #define mmCM2_CM_COMB_C33_C34_BASE_IDX 2
4540 #define mmCM2_CM_IGAM_CONTROL 0x0ed5
4541 #define mmCM2_CM_IGAM_CONTROL_BASE_IDX 2
4542 #define mmCM2_CM_IGAM_LUT_RW_CONTROL 0x0ed6
4543 #define mmCM2_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2
4544 #define mmCM2_CM_IGAM_LUT_RW_INDEX 0x0ed7
4545 #define mmCM2_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2
4546 #define mmCM2_CM_IGAM_LUT_SEQ_COLOR 0x0ed8
4547 #define mmCM2_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2
4548 #define mmCM2_CM_IGAM_LUT_30_COLOR 0x0ed9
4549 #define mmCM2_CM_IGAM_LUT_30_COLOR_BASE_IDX 2
4550 #define mmCM2_CM_IGAM_LUT_PWL_DATA 0x0eda
4551 #define mmCM2_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2
4552 #define mmCM2_CM_IGAM_LUT_AUTOFILL 0x0edb
4553 #define mmCM2_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2
4554 #define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0edc
4555 #define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2
4556 #define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0edd
4557 #define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2
4558 #define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED 0x0ede
4559 #define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2
4560 #define mmCM2_CM_ICSC_CONTROL 0x0edf
4561 #define mmCM2_CM_ICSC_CONTROL_BASE_IDX 2
4562 #define mmCM2_CM_ICSC_C11_C12 0x0ee0
4563 #define mmCM2_CM_ICSC_C11_C12_BASE_IDX 2
4564 #define mmCM2_CM_ICSC_C13_C14 0x0ee1
4565 #define mmCM2_CM_ICSC_C13_C14_BASE_IDX 2
4566 #define mmCM2_CM_ICSC_C21_C22 0x0ee2
4567 #define mmCM2_CM_ICSC_C21_C22_BASE_IDX 2
4568 #define mmCM2_CM_ICSC_C23_C24 0x0ee3
4569 #define mmCM2_CM_ICSC_C23_C24_BASE_IDX 2
4570 #define mmCM2_CM_ICSC_C31_C32 0x0ee4
4571 #define mmCM2_CM_ICSC_C31_C32_BASE_IDX 2
4572 #define mmCM2_CM_ICSC_C33_C34 0x0ee5
4573 #define mmCM2_CM_ICSC_C33_C34_BASE_IDX 2
4574 #define mmCM2_CM_GAMUT_REMAP_CONTROL 0x0ee6
4575 #define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
4576 #define mmCM2_CM_GAMUT_REMAP_C11_C12 0x0ee7
4577 #define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
4578 #define mmCM2_CM_GAMUT_REMAP_C13_C14 0x0ee8
4579 #define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
4580 #define mmCM2_CM_GAMUT_REMAP_C21_C22 0x0ee9
4581 #define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
4582 #define mmCM2_CM_GAMUT_REMAP_C23_C24 0x0eea
4583 #define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
4584 #define mmCM2_CM_GAMUT_REMAP_C31_C32 0x0eeb
4585 #define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
4586 #define mmCM2_CM_GAMUT_REMAP_C33_C34 0x0eec
4587 #define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
4588 #define mmCM2_CM_OCSC_CONTROL 0x0eed
4589 #define mmCM2_CM_OCSC_CONTROL_BASE_IDX 2
4590 #define mmCM2_CM_OCSC_C11_C12 0x0eee
4591 #define mmCM2_CM_OCSC_C11_C12_BASE_IDX 2
4592 #define mmCM2_CM_OCSC_C13_C14 0x0eef
4593 #define mmCM2_CM_OCSC_C13_C14_BASE_IDX 2
4594 #define mmCM2_CM_OCSC_C21_C22 0x0ef0
4595 #define mmCM2_CM_OCSC_C21_C22_BASE_IDX 2
4596 #define mmCM2_CM_OCSC_C23_C24 0x0ef1
4597 #define mmCM2_CM_OCSC_C23_C24_BASE_IDX 2
4598 #define mmCM2_CM_OCSC_C31_C32 0x0ef2
4599 #define mmCM2_CM_OCSC_C31_C32_BASE_IDX 2
4600 #define mmCM2_CM_OCSC_C33_C34 0x0ef3
4601 #define mmCM2_CM_OCSC_C33_C34_BASE_IDX 2
4602 #define mmCM2_CM_BNS_VALUES_R 0x0ef4
4603 #define mmCM2_CM_BNS_VALUES_R_BASE_IDX 2
4604 #define mmCM2_CM_BNS_VALUES_G 0x0ef5
4605 #define mmCM2_CM_BNS_VALUES_G_BASE_IDX 2
4606 #define mmCM2_CM_BNS_VALUES_B 0x0ef6
4607 #define mmCM2_CM_BNS_VALUES_B_BASE_IDX 2
4608 #define mmCM2_CM_DGAM_CONTROL 0x0ef7
4609 #define mmCM2_CM_DGAM_CONTROL_BASE_IDX 2
4610 #define mmCM2_CM_DGAM_LUT_INDEX 0x0ef8
4611 #define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX 2
4612 #define mmCM2_CM_DGAM_LUT_DATA 0x0ef9
4613 #define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX 2
4614 #define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK 0x0efa
4615 #define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
4616 #define mmCM2_CM_DGAM_RAMA_START_CNTL_B 0x0efb
4617 #define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
4618 #define mmCM2_CM_DGAM_RAMA_START_CNTL_G 0x0efc
4619 #define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
4620 #define mmCM2_CM_DGAM_RAMA_START_CNTL_R 0x0efd
4621 #define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
4622 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0efe
4623 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
4624 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0eff
4625 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
4626 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0f00
4627 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
4628 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B 0x0f01
4629 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
4630 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_B 0x0f02
4631 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
4632 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_G 0x0f03
4633 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
4634 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_G 0x0f04
4635 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
4636 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_R 0x0f05
4637 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
4638 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_R 0x0f06
4639 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
4640 #define mmCM2_CM_DGAM_RAMA_REGION_0_1 0x0f07
4641 #define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
4642 #define mmCM2_CM_DGAM_RAMA_REGION_2_3 0x0f08
4643 #define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
4644 #define mmCM2_CM_DGAM_RAMA_REGION_4_5 0x0f09
4645 #define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
4646 #define mmCM2_CM_DGAM_RAMA_REGION_6_7 0x0f0a
4647 #define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
4648 #define mmCM2_CM_DGAM_RAMA_REGION_8_9 0x0f0b
4649 #define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
4650 #define mmCM2_CM_DGAM_RAMA_REGION_10_11 0x0f0c
4651 #define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
4652 #define mmCM2_CM_DGAM_RAMA_REGION_12_13 0x0f0d
4653 #define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
4654 #define mmCM2_CM_DGAM_RAMA_REGION_14_15 0x0f0e
4655 #define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
4656 #define mmCM2_CM_DGAM_RAMB_START_CNTL_B 0x0f0f
4657 #define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
4658 #define mmCM2_CM_DGAM_RAMB_START_CNTL_G 0x0f10
4659 #define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
4660 #define mmCM2_CM_DGAM_RAMB_START_CNTL_R 0x0f11
4661 #define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
4662 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0f12
4663 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
4664 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0f13
4665 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
4666 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0f14
4667 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
4668 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_B 0x0f15
4669 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
4670 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_B 0x0f16
4671 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
4672 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_G 0x0f17
4673 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
4674 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_G 0x0f18
4675 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
4676 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_R 0x0f19
4677 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
4678 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_R 0x0f1a
4679 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
4680 #define mmCM2_CM_DGAM_RAMB_REGION_0_1 0x0f1b
4681 #define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
4682 #define mmCM2_CM_DGAM_RAMB_REGION_2_3 0x0f1c
4683 #define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
4684 #define mmCM2_CM_DGAM_RAMB_REGION_4_5 0x0f1d
4685 #define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
4686 #define mmCM2_CM_DGAM_RAMB_REGION_6_7 0x0f1e
4687 #define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
4688 #define mmCM2_CM_DGAM_RAMB_REGION_8_9 0x0f1f
4689 #define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
4690 #define mmCM2_CM_DGAM_RAMB_REGION_10_11 0x0f20
4691 #define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
4692 #define mmCM2_CM_DGAM_RAMB_REGION_12_13 0x0f21
4693 #define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
4694 #define mmCM2_CM_DGAM_RAMB_REGION_14_15 0x0f22
4695 #define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
4696 #define mmCM2_CM_RGAM_CONTROL 0x0f23
4697 #define mmCM2_CM_RGAM_CONTROL_BASE_IDX 2
4698 #define mmCM2_CM_RGAM_LUT_INDEX 0x0f24
4699 #define mmCM2_CM_RGAM_LUT_INDEX_BASE_IDX 2
4700 #define mmCM2_CM_RGAM_LUT_DATA 0x0f25
4701 #define mmCM2_CM_RGAM_LUT_DATA_BASE_IDX 2
4702 #define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK 0x0f26
4703 #define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
4704 #define mmCM2_CM_RGAM_RAMA_START_CNTL_B 0x0f27
4705 #define mmCM2_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2
4706 #define mmCM2_CM_RGAM_RAMA_START_CNTL_G 0x0f28
4707 #define mmCM2_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2
4708 #define mmCM2_CM_RGAM_RAMA_START_CNTL_R 0x0f29
4709 #define mmCM2_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2
4710 #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0f2a
4711 #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
4712 #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0f2b
4713 #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
4714 #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0f2c
4715 #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
4716 #define mmCM2_CM_RGAM_RAMA_END_CNTL1_B 0x0f2d
4717 #define mmCM2_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2
4718 #define mmCM2_CM_RGAM_RAMA_END_CNTL2_B 0x0f2e
4719 #define mmCM2_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2
4720 #define mmCM2_CM_RGAM_RAMA_END_CNTL1_G 0x0f2f
4721 #define mmCM2_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2
4722 #define mmCM2_CM_RGAM_RAMA_END_CNTL2_G 0x0f30
4723 #define mmCM2_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2
4724 #define mmCM2_CM_RGAM_RAMA_END_CNTL1_R 0x0f31
4725 #define mmCM2_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2
4726 #define mmCM2_CM_RGAM_RAMA_END_CNTL2_R 0x0f32
4727 #define mmCM2_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2
4728 #define mmCM2_CM_RGAM_RAMA_REGION_0_1 0x0f33
4729 #define mmCM2_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2
4730 #define mmCM2_CM_RGAM_RAMA_REGION_2_3 0x0f34
4731 #define mmCM2_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2
4732 #define mmCM2_CM_RGAM_RAMA_REGION_4_5 0x0f35
4733 #define mmCM2_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2
4734 #define mmCM2_CM_RGAM_RAMA_REGION_6_7 0x0f36
4735 #define mmCM2_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2
4736 #define mmCM2_CM_RGAM_RAMA_REGION_8_9 0x0f37
4737 #define mmCM2_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2
4738 #define mmCM2_CM_RGAM_RAMA_REGION_10_11 0x0f38
4739 #define mmCM2_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2
4740 #define mmCM2_CM_RGAM_RAMA_REGION_12_13 0x0f39
4741 #define mmCM2_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2
4742 #define mmCM2_CM_RGAM_RAMA_REGION_14_15 0x0f3a
4743 #define mmCM2_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2
4744 #define mmCM2_CM_RGAM_RAMA_REGION_16_17 0x0f3b
4745 #define mmCM2_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2
4746 #define mmCM2_CM_RGAM_RAMA_REGION_18_19 0x0f3c
4747 #define mmCM2_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2
4748 #define mmCM2_CM_RGAM_RAMA_REGION_20_21 0x0f3d
4749 #define mmCM2_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2
4750 #define mmCM2_CM_RGAM_RAMA_REGION_22_23 0x0f3e
4751 #define mmCM2_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2
4752 #define mmCM2_CM_RGAM_RAMA_REGION_24_25 0x0f3f
4753 #define mmCM2_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2
4754 #define mmCM2_CM_RGAM_RAMA_REGION_26_27 0x0f40
4755 #define mmCM2_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2
4756 #define mmCM2_CM_RGAM_RAMA_REGION_28_29 0x0f41
4757 #define mmCM2_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2
4758 #define mmCM2_CM_RGAM_RAMA_REGION_30_31 0x0f42
4759 #define mmCM2_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2
4760 #define mmCM2_CM_RGAM_RAMA_REGION_32_33 0x0f43
4761 #define mmCM2_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2
4762 #define mmCM2_CM_RGAM_RAMB_START_CNTL_B 0x0f44
4763 #define mmCM2_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2
4764 #define mmCM2_CM_RGAM_RAMB_START_CNTL_G 0x0f45
4765 #define mmCM2_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2
4766 #define mmCM2_CM_RGAM_RAMB_START_CNTL_R 0x0f46
4767 #define mmCM2_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2
4768 #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0f47
4769 #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
4770 #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0f48
4771 #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
4772 #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0f49
4773 #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
4774 #define mmCM2_CM_RGAM_RAMB_END_CNTL1_B 0x0f4a
4775 #define mmCM2_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2
4776 #define mmCM2_CM_RGAM_RAMB_END_CNTL2_B 0x0f4b
4777 #define mmCM2_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2
4778 #define mmCM2_CM_RGAM_RAMB_END_CNTL1_G 0x0f4c
4779 #define mmCM2_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2
4780 #define mmCM2_CM_RGAM_RAMB_END_CNTL2_G 0x0f4d
4781 #define mmCM2_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2
4782 #define mmCM2_CM_RGAM_RAMB_END_CNTL1_R 0x0f4e
4783 #define mmCM2_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2
4784 #define mmCM2_CM_RGAM_RAMB_END_CNTL2_R 0x0f4f
4785 #define mmCM2_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2
4786 #define mmCM2_CM_RGAM_RAMB_REGION_0_1 0x0f50
4787 #define mmCM2_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2
4788 #define mmCM2_CM_RGAM_RAMB_REGION_2_3 0x0f51
4789 #define mmCM2_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2
4790 #define mmCM2_CM_RGAM_RAMB_REGION_4_5 0x0f52
4791 #define mmCM2_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2
4792 #define mmCM2_CM_RGAM_RAMB_REGION_6_7 0x0f53
4793 #define mmCM2_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2
4794 #define mmCM2_CM_RGAM_RAMB_REGION_8_9 0x0f54
4795 #define mmCM2_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2
4796 #define mmCM2_CM_RGAM_RAMB_REGION_10_11 0x0f55
4797 #define mmCM2_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2
4798 #define mmCM2_CM_RGAM_RAMB_REGION_12_13 0x0f56
4799 #define mmCM2_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2
4800 #define mmCM2_CM_RGAM_RAMB_REGION_14_15 0x0f57
4801 #define mmCM2_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2
4802 #define mmCM2_CM_RGAM_RAMB_REGION_16_17 0x0f58
4803 #define mmCM2_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2
4804 #define mmCM2_CM_RGAM_RAMB_REGION_18_19 0x0f59
4805 #define mmCM2_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2
4806 #define mmCM2_CM_RGAM_RAMB_REGION_20_21 0x0f5a
4807 #define mmCM2_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2
4808 #define mmCM2_CM_RGAM_RAMB_REGION_22_23 0x0f5b
4809 #define mmCM2_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2
4810 #define mmCM2_CM_RGAM_RAMB_REGION_24_25 0x0f5c
4811 #define mmCM2_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2
4812 #define mmCM2_CM_RGAM_RAMB_REGION_26_27 0x0f5d
4813 #define mmCM2_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2
4814 #define mmCM2_CM_RGAM_RAMB_REGION_28_29 0x0f5e
4815 #define mmCM2_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2
4816 #define mmCM2_CM_RGAM_RAMB_REGION_30_31 0x0f5f
4817 #define mmCM2_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2
4818 #define mmCM2_CM_RGAM_RAMB_REGION_32_33 0x0f60
4819 #define mmCM2_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2
4820 #define mmCM2_CM_HDR_MULT_COEF 0x0f61
4821 #define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2
4822 #define mmCM2_CM_RANGE_CLAMP_CONTROL_R 0x0f62
4823 #define mmCM2_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2
4824 #define mmCM2_CM_RANGE_CLAMP_CONTROL_G 0x0f63
4825 #define mmCM2_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2
4826 #define mmCM2_CM_RANGE_CLAMP_CONTROL_B 0x0f64
4827 #define mmCM2_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2
4828 #define mmCM2_CM_DENORM_CONTROL 0x0f65
4829 #define mmCM2_CM_DENORM_CONTROL_BASE_IDX 2
4830 #define mmCM2_CM_CMOUT_CONTROL 0x0f66
4831 #define mmCM2_CM_CMOUT_CONTROL_BASE_IDX 2
4832 #define mmCM2_CM_CMOUT_RANDOM_SEEDS 0x0f67
4833 #define mmCM2_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2
4834 #define mmCM2_CM_MEM_PWR_CTRL 0x0f68
4835 #define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
4836 #define mmCM2_CM_MEM_PWR_STATUS 0x0f69
4837 #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
4840 // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
4841 // base address: 0x3e08
4842 #define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x0f82
4843 #define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2
4844 #define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x0f83
4845 #define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2
4846 #define mmDC_PERFMON14_PERFCOUNTER_STATE 0x0f84
4847 #define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2
4848 #define mmDC_PERFMON14_PERFMON_CNTL 0x0f85
4849 #define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2
4850 #define mmDC_PERFMON14_PERFMON_CNTL2 0x0f86
4851 #define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2
4852 #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x0f87
4853 #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
4854 #define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x0f88
4855 #define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2
4856 #define mmDC_PERFMON14_PERFMON_HI 0x0f89
4857 #define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2
4858 #define mmDC_PERFMON14_PERFMON_LOW 0x0f8a
4859 #define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2
4862 // addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
4863 // base address: 0xd44
4864 #define mmDPP_TOP3_DPP_CONTROL 0x0f8e
4865 #define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2
4866 #define mmDPP_TOP3_DPP_SOFT_RESET 0x0f8f
4867 #define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2
4868 #define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x0f90
4869 #define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2
4870 #define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x0f91
4871 #define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2
4872 #define mmDPP_TOP3_DPP_CRC_CTRL 0x0f92
4873 #define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2
4874 #define mmDPP_TOP3_HOST_READ_CONTROL 0x0f93
4875 #define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2
4878 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
4879 // base address: 0xd44
4880 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x0f98
4881 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
4882 #define mmCNVC_CFG3_FORMAT_CONTROL 0x0f99
4883 #define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2
4884 #define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS 0x0f9a
4885 #define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS_BASE_IDX 2
4886 #define mmCNVC_CFG3_DENORM_CONTROL 0x0f9b
4887 #define mmCNVC_CFG3_DENORM_CONTROL_BASE_IDX 2
4888 #define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x0f9d
4889 #define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2
4890 #define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x0f9e
4891 #define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2
4892 #define mmCNVC_CFG3_COLOR_KEYER_RED 0x0f9f
4893 #define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2
4894 #define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x0fa0
4895 #define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2
4896 #define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x0fa1
4897 #define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2
4900 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
4901 // base address: 0xd44
4902 #define mmCNVC_CUR3_CURSOR0_CONTROL 0x0fa9
4903 #define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2
4904 #define mmCNVC_CUR3_CURSOR0_COLOR0 0x0faa
4905 #define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2
4906 #define mmCNVC_CUR3_CURSOR0_COLOR1 0x0fab
4907 #define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2
4908 #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x0fac
4909 #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
4912 // addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
4913 // base address: 0xd44
4914 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x0fb3
4915 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
4916 #define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x0fb4
4917 #define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
4918 #define mmDSCL3_SCL_MODE 0x0fb5
4919 #define mmDSCL3_SCL_MODE_BASE_IDX 2
4920 #define mmDSCL3_SCL_TAP_CONTROL 0x0fb6
4921 #define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2
4922 #define mmDSCL3_DSCL_CONTROL 0x0fb7
4923 #define mmDSCL3_DSCL_CONTROL_BASE_IDX 2
4924 #define mmDSCL3_DSCL_2TAP_CONTROL 0x0fb8
4925 #define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2
4926 #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x0fb9
4927 #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
4928 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x0fba
4929 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
4930 #define mmDSCL3_SCL_HORZ_FILTER_INIT 0x0fbb
4931 #define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2
4932 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fbc
4933 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
4934 #define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x0fbd
4935 #define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
4936 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x0fbe
4937 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
4938 #define mmDSCL3_SCL_VERT_FILTER_INIT 0x0fbf
4939 #define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2
4940 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x0fc0
4941 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
4942 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fc1
4943 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
4944 #define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x0fc2
4945 #define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
4946 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x0fc3
4947 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
4948 #define mmDSCL3_SCL_BLACK_OFFSET 0x0fc4
4949 #define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX 2
4950 #define mmDSCL3_DSCL_UPDATE 0x0fc5
4951 #define mmDSCL3_DSCL_UPDATE_BASE_IDX 2
4952 #define mmDSCL3_DSCL_AUTOCAL 0x0fc6
4953 #define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2
4954 #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fc7
4955 #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
4956 #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fc8
4957 #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
4958 #define mmDSCL3_OTG_H_BLANK 0x0fc9
4959 #define mmDSCL3_OTG_H_BLANK_BASE_IDX 2
4960 #define mmDSCL3_OTG_V_BLANK 0x0fca
4961 #define mmDSCL3_OTG_V_BLANK_BASE_IDX 2
4962 #define mmDSCL3_RECOUT_START 0x0fcb
4963 #define mmDSCL3_RECOUT_START_BASE_IDX 2
4964 #define mmDSCL3_RECOUT_SIZE 0x0fcc
4965 #define mmDSCL3_RECOUT_SIZE_BASE_IDX 2
4966 #define mmDSCL3_MPC_SIZE 0x0fcd
4967 #define mmDSCL3_MPC_SIZE_BASE_IDX 2
4968 #define mmDSCL3_LB_DATA_FORMAT 0x0fce
4969 #define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2
4970 #define mmDSCL3_LB_MEMORY_CTRL 0x0fcf
4971 #define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2
4972 #define mmDSCL3_LB_V_COUNTER 0x0fd0
4973 #define mmDSCL3_LB_V_COUNTER_BASE_IDX 2
4974 #define mmDSCL3_DSCL_MEM_PWR_CTRL 0x0fd1
4975 #define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2
4976 #define mmDSCL3_DSCL_MEM_PWR_STATUS 0x0fd2
4977 #define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2
4978 #define mmDSCL3_OBUF_CONTROL 0x0fd3
4979 #define mmDSCL3_OBUF_CONTROL_BASE_IDX 2
4980 #define mmDSCL3_OBUF_MEM_PWR_CTRL 0x0fd4
4981 #define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2
4984 // addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
4985 // base address: 0xd44
4986 #define mmCM3_CM_CONTROL 0x0fe3
4987 #define mmCM3_CM_CONTROL_BASE_IDX 2
4988 #define mmCM3_CM_COMA_C11_C12 0x0fe4
4989 #define mmCM3_CM_COMA_C11_C12_BASE_IDX 2
4990 #define mmCM3_CM_COMA_C13_C14 0x0fe5
4991 #define mmCM3_CM_COMA_C13_C14_BASE_IDX 2
4992 #define mmCM3_CM_COMA_C21_C22 0x0fe6
4993 #define mmCM3_CM_COMA_C21_C22_BASE_IDX 2
4994 #define mmCM3_CM_COMA_C23_C24 0x0fe7
4995 #define mmCM3_CM_COMA_C23_C24_BASE_IDX 2
4996 #define mmCM3_CM_COMA_C31_C32 0x0fe8
4997 #define mmCM3_CM_COMA_C31_C32_BASE_IDX 2
4998 #define mmCM3_CM_COMA_C33_C34 0x0fe9
4999 #define mmCM3_CM_COMA_C33_C34_BASE_IDX 2
5000 #define mmCM3_CM_COMB_C11_C12 0x0fea
5001 #define mmCM3_CM_COMB_C11_C12_BASE_IDX 2
5002 #define mmCM3_CM_COMB_C13_C14 0x0feb
5003 #define mmCM3_CM_COMB_C13_C14_BASE_IDX 2
5004 #define mmCM3_CM_COMB_C21_C22 0x0fec
5005 #define mmCM3_CM_COMB_C21_C22_BASE_IDX 2
5006 #define mmCM3_CM_COMB_C23_C24 0x0fed
5007 #define mmCM3_CM_COMB_C23_C24_BASE_IDX 2
5008 #define mmCM3_CM_COMB_C31_C32 0x0fee
5009 #define mmCM3_CM_COMB_C31_C32_BASE_IDX 2
5010 #define mmCM3_CM_COMB_C33_C34 0x0fef
5011 #define mmCM3_CM_COMB_C33_C34_BASE_IDX 2
5012 #define mmCM3_CM_IGAM_CONTROL 0x0ff0
5013 #define mmCM3_CM_IGAM_CONTROL_BASE_IDX 2
5014 #define mmCM3_CM_IGAM_LUT_RW_CONTROL 0x0ff1
5015 #define mmCM3_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2
5016 #define mmCM3_CM_IGAM_LUT_RW_INDEX 0x0ff2
5017 #define mmCM3_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2
5018 #define mmCM3_CM_IGAM_LUT_SEQ_COLOR 0x0ff3
5019 #define mmCM3_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2
5020 #define mmCM3_CM_IGAM_LUT_30_COLOR 0x0ff4
5021 #define mmCM3_CM_IGAM_LUT_30_COLOR_BASE_IDX 2
5022 #define mmCM3_CM_IGAM_LUT_PWL_DATA 0x0ff5
5023 #define mmCM3_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2
5024 #define mmCM3_CM_IGAM_LUT_AUTOFILL 0x0ff6
5025 #define mmCM3_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2
5026 #define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0ff7
5027 #define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2
5028 #define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0ff8
5029 #define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2
5030 #define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED 0x0ff9
5031 #define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2
5032 #define mmCM3_CM_ICSC_CONTROL 0x0ffa
5033 #define mmCM3_CM_ICSC_CONTROL_BASE_IDX 2
5034 #define mmCM3_CM_ICSC_C11_C12 0x0ffb
5035 #define mmCM3_CM_ICSC_C11_C12_BASE_IDX 2
5036 #define mmCM3_CM_ICSC_C13_C14 0x0ffc
5037 #define mmCM3_CM_ICSC_C13_C14_BASE_IDX 2
5038 #define mmCM3_CM_ICSC_C21_C22 0x0ffd
5039 #define mmCM3_CM_ICSC_C21_C22_BASE_IDX 2
5040 #define mmCM3_CM_ICSC_C23_C24 0x0ffe
5041 #define mmCM3_CM_ICSC_C23_C24_BASE_IDX 2
5042 #define mmCM3_CM_ICSC_C31_C32 0x0fff
5043 #define mmCM3_CM_ICSC_C31_C32_BASE_IDX 2
5044 #define mmCM3_CM_ICSC_C33_C34 0x1000
5045 #define mmCM3_CM_ICSC_C33_C34_BASE_IDX 2
5046 #define mmCM3_CM_GAMUT_REMAP_CONTROL 0x1001
5047 #define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
5048 #define mmCM3_CM_GAMUT_REMAP_C11_C12 0x1002
5049 #define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
5050 #define mmCM3_CM_GAMUT_REMAP_C13_C14 0x1003
5051 #define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
5052 #define mmCM3_CM_GAMUT_REMAP_C21_C22 0x1004
5053 #define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
5054 #define mmCM3_CM_GAMUT_REMAP_C23_C24 0x1005
5055 #define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
5056 #define mmCM3_CM_GAMUT_REMAP_C31_C32 0x1006
5057 #define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
5058 #define mmCM3_CM_GAMUT_REMAP_C33_C34 0x1007
5059 #define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
5060 #define mmCM3_CM_OCSC_CONTROL 0x1008
5061 #define mmCM3_CM_OCSC_CONTROL_BASE_IDX 2
5062 #define mmCM3_CM_OCSC_C11_C12 0x1009
5063 #define mmCM3_CM_OCSC_C11_C12_BASE_IDX 2
5064 #define mmCM3_CM_OCSC_C13_C14 0x100a
5065 #define mmCM3_CM_OCSC_C13_C14_BASE_IDX 2
5066 #define mmCM3_CM_OCSC_C21_C22 0x100b
5067 #define mmCM3_CM_OCSC_C21_C22_BASE_IDX 2
5068 #define mmCM3_CM_OCSC_C23_C24 0x100c
5069 #define mmCM3_CM_OCSC_C23_C24_BASE_IDX 2
5070 #define mmCM3_CM_OCSC_C31_C32 0x100d
5071 #define mmCM3_CM_OCSC_C31_C32_BASE_IDX 2
5072 #define mmCM3_CM_OCSC_C33_C34 0x100e
5073 #define mmCM3_CM_OCSC_C33_C34_BASE_IDX 2
5074 #define mmCM3_CM_BNS_VALUES_R 0x100f
5075 #define mmCM3_CM_BNS_VALUES_R_BASE_IDX 2
5076 #define mmCM3_CM_BNS_VALUES_G 0x1010
5077 #define mmCM3_CM_BNS_VALUES_G_BASE_IDX 2
5078 #define mmCM3_CM_BNS_VALUES_B 0x1011
5079 #define mmCM3_CM_BNS_VALUES_B_BASE_IDX 2
5080 #define mmCM3_CM_DGAM_CONTROL 0x1012
5081 #define mmCM3_CM_DGAM_CONTROL_BASE_IDX 2
5082 #define mmCM3_CM_DGAM_LUT_INDEX 0x1013
5083 #define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX 2
5084 #define mmCM3_CM_DGAM_LUT_DATA 0x1014
5085 #define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX 2
5086 #define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK 0x1015
5087 #define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
5088 #define mmCM3_CM_DGAM_RAMA_START_CNTL_B 0x1016
5089 #define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
5090 #define mmCM3_CM_DGAM_RAMA_START_CNTL_G 0x1017
5091 #define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
5092 #define mmCM3_CM_DGAM_RAMA_START_CNTL_R 0x1018
5093 #define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
5094 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B 0x1019
5095 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
5096 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G 0x101a
5097 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
5098 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R 0x101b
5099 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
5100 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_B 0x101c
5101 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
5102 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_B 0x101d
5103 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
5104 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_G 0x101e
5105 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
5106 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_G 0x101f
5107 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
5108 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_R 0x1020
5109 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
5110 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_R 0x1021
5111 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
5112 #define mmCM3_CM_DGAM_RAMA_REGION_0_1 0x1022
5113 #define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
5114 #define mmCM3_CM_DGAM_RAMA_REGION_2_3 0x1023
5115 #define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
5116 #define mmCM3_CM_DGAM_RAMA_REGION_4_5 0x1024
5117 #define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
5118 #define mmCM3_CM_DGAM_RAMA_REGION_6_7 0x1025
5119 #define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
5120 #define mmCM3_CM_DGAM_RAMA_REGION_8_9 0x1026
5121 #define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
5122 #define mmCM3_CM_DGAM_RAMA_REGION_10_11 0x1027
5123 #define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
5124 #define mmCM3_CM_DGAM_RAMA_REGION_12_13 0x1028
5125 #define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
5126 #define mmCM3_CM_DGAM_RAMA_REGION_14_15 0x1029
5127 #define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
5128 #define mmCM3_CM_DGAM_RAMB_START_CNTL_B 0x102a
5129 #define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
5130 #define mmCM3_CM_DGAM_RAMB_START_CNTL_G 0x102b
5131 #define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
5132 #define mmCM3_CM_DGAM_RAMB_START_CNTL_R 0x102c
5133 #define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
5134 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B 0x102d
5135 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
5136 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G 0x102e
5137 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
5138 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R 0x102f
5139 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
5140 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_B 0x1030
5141 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
5142 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_B 0x1031
5143 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
5144 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_G 0x1032
5145 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
5146 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_G 0x1033
5147 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
5148 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_R 0x1034
5149 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
5150 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_R 0x1035
5151 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
5152 #define mmCM3_CM_DGAM_RAMB_REGION_0_1 0x1036
5153 #define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
5154 #define mmCM3_CM_DGAM_RAMB_REGION_2_3 0x1037
5155 #define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
5156 #define mmCM3_CM_DGAM_RAMB_REGION_4_5 0x1038
5157 #define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
5158 #define mmCM3_CM_DGAM_RAMB_REGION_6_7 0x1039
5159 #define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
5160 #define mmCM3_CM_DGAM_RAMB_REGION_8_9 0x103a
5161 #define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
5162 #define mmCM3_CM_DGAM_RAMB_REGION_10_11 0x103b
5163 #define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
5164 #define mmCM3_CM_DGAM_RAMB_REGION_12_13 0x103c
5165 #define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
5166 #define mmCM3_CM_DGAM_RAMB_REGION_14_15 0x103d
5167 #define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
5168 #define mmCM3_CM_RGAM_CONTROL 0x103e
5169 #define mmCM3_CM_RGAM_CONTROL_BASE_IDX 2
5170 #define mmCM3_CM_RGAM_LUT_INDEX 0x103f
5171 #define mmCM3_CM_RGAM_LUT_INDEX_BASE_IDX 2
5172 #define mmCM3_CM_RGAM_LUT_DATA 0x1040
5173 #define mmCM3_CM_RGAM_LUT_DATA_BASE_IDX 2
5174 #define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK 0x1041
5175 #define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
5176 #define mmCM3_CM_RGAM_RAMA_START_CNTL_B 0x1042
5177 #define mmCM3_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2
5178 #define mmCM3_CM_RGAM_RAMA_START_CNTL_G 0x1043
5179 #define mmCM3_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2
5180 #define mmCM3_CM_RGAM_RAMA_START_CNTL_R 0x1044
5181 #define mmCM3_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2
5182 #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B 0x1045
5183 #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
5184 #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G 0x1046
5185 #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
5186 #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R 0x1047
5187 #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
5188 #define mmCM3_CM_RGAM_RAMA_END_CNTL1_B 0x1048
5189 #define mmCM3_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2
5190 #define mmCM3_CM_RGAM_RAMA_END_CNTL2_B 0x1049
5191 #define mmCM3_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2
5192 #define mmCM3_CM_RGAM_RAMA_END_CNTL1_G 0x104a
5193 #define mmCM3_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2
5194 #define mmCM3_CM_RGAM_RAMA_END_CNTL2_G 0x104b
5195 #define mmCM3_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2
5196 #define mmCM3_CM_RGAM_RAMA_END_CNTL1_R 0x104c
5197 #define mmCM3_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2
5198 #define mmCM3_CM_RGAM_RAMA_END_CNTL2_R 0x104d
5199 #define mmCM3_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2
5200 #define mmCM3_CM_RGAM_RAMA_REGION_0_1 0x104e
5201 #define mmCM3_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2
5202 #define mmCM3_CM_RGAM_RAMA_REGION_2_3 0x104f
5203 #define mmCM3_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2
5204 #define mmCM3_CM_RGAM_RAMA_REGION_4_5 0x1050
5205 #define mmCM3_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2
5206 #define mmCM3_CM_RGAM_RAMA_REGION_6_7 0x1051
5207 #define mmCM3_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2
5208 #define mmCM3_CM_RGAM_RAMA_REGION_8_9 0x1052
5209 #define mmCM3_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2
5210 #define mmCM3_CM_RGAM_RAMA_REGION_10_11 0x1053
5211 #define mmCM3_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2
5212 #define mmCM3_CM_RGAM_RAMA_REGION_12_13 0x1054
5213 #define mmCM3_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2
5214 #define mmCM3_CM_RGAM_RAMA_REGION_14_15 0x1055
5215 #define mmCM3_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2
5216 #define mmCM3_CM_RGAM_RAMA_REGION_16_17 0x1056
5217 #define mmCM3_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2
5218 #define mmCM3_CM_RGAM_RAMA_REGION_18_19 0x1057
5219 #define mmCM3_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2
5220 #define mmCM3_CM_RGAM_RAMA_REGION_20_21 0x1058
5221 #define mmCM3_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2
5222 #define mmCM3_CM_RGAM_RAMA_REGION_22_23 0x1059
5223 #define mmCM3_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2
5224 #define mmCM3_CM_RGAM_RAMA_REGION_24_25 0x105a
5225 #define mmCM3_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2
5226 #define mmCM3_CM_RGAM_RAMA_REGION_26_27 0x105b
5227 #define mmCM3_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2
5228 #define mmCM3_CM_RGAM_RAMA_REGION_28_29 0x105c
5229 #define mmCM3_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2
5230 #define mmCM3_CM_RGAM_RAMA_REGION_30_31 0x105d
5231 #define mmCM3_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2
5232 #define mmCM3_CM_RGAM_RAMA_REGION_32_33 0x105e
5233 #define mmCM3_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2
5234 #define mmCM3_CM_RGAM_RAMB_START_CNTL_B 0x105f
5235 #define mmCM3_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2
5236 #define mmCM3_CM_RGAM_RAMB_START_CNTL_G 0x1060
5237 #define mmCM3_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2
5238 #define mmCM3_CM_RGAM_RAMB_START_CNTL_R 0x1061
5239 #define mmCM3_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2
5240 #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B 0x1062
5241 #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
5242 #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G 0x1063
5243 #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
5244 #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R 0x1064
5245 #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
5246 #define mmCM3_CM_RGAM_RAMB_END_CNTL1_B 0x1065
5247 #define mmCM3_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2
5248 #define mmCM3_CM_RGAM_RAMB_END_CNTL2_B 0x1066
5249 #define mmCM3_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2
5250 #define mmCM3_CM_RGAM_RAMB_END_CNTL1_G 0x1067
5251 #define mmCM3_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2
5252 #define mmCM3_CM_RGAM_RAMB_END_CNTL2_G 0x1068
5253 #define mmCM3_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2
5254 #define mmCM3_CM_RGAM_RAMB_END_CNTL1_R 0x1069
5255 #define mmCM3_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2
5256 #define mmCM3_CM_RGAM_RAMB_END_CNTL2_R 0x106a
5257 #define mmCM3_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2
5258 #define mmCM3_CM_RGAM_RAMB_REGION_0_1 0x106b
5259 #define mmCM3_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2
5260 #define mmCM3_CM_RGAM_RAMB_REGION_2_3 0x106c
5261 #define mmCM3_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2
5262 #define mmCM3_CM_RGAM_RAMB_REGION_4_5 0x106d
5263 #define mmCM3_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2
5264 #define mmCM3_CM_RGAM_RAMB_REGION_6_7 0x106e
5265 #define mmCM3_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2
5266 #define mmCM3_CM_RGAM_RAMB_REGION_8_9 0x106f
5267 #define mmCM3_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2
5268 #define mmCM3_CM_RGAM_RAMB_REGION_10_11 0x1070
5269 #define mmCM3_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2
5270 #define mmCM3_CM_RGAM_RAMB_REGION_12_13 0x1071
5271 #define mmCM3_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2
5272 #define mmCM3_CM_RGAM_RAMB_REGION_14_15 0x1072
5273 #define mmCM3_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2
5274 #define mmCM3_CM_RGAM_RAMB_REGION_16_17 0x1073
5275 #define mmCM3_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2
5276 #define mmCM3_CM_RGAM_RAMB_REGION_18_19 0x1074
5277 #define mmCM3_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2
5278 #define mmCM3_CM_RGAM_RAMB_REGION_20_21 0x1075
5279 #define mmCM3_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2
5280 #define mmCM3_CM_RGAM_RAMB_REGION_22_23 0x1076
5281 #define mmCM3_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2
5282 #define mmCM3_CM_RGAM_RAMB_REGION_24_25 0x1077
5283 #define mmCM3_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2
5284 #define mmCM3_CM_RGAM_RAMB_REGION_26_27 0x1078
5285 #define mmCM3_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2
5286 #define mmCM3_CM_RGAM_RAMB_REGION_28_29 0x1079
5287 #define mmCM3_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2
5288 #define mmCM3_CM_RGAM_RAMB_REGION_30_31 0x107a
5289 #define mmCM3_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2
5290 #define mmCM3_CM_RGAM_RAMB_REGION_32_33 0x107b
5291 #define mmCM3_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2
5292 #define mmCM3_CM_HDR_MULT_COEF 0x107c
5293 #define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2
5294 #define mmCM3_CM_RANGE_CLAMP_CONTROL_R 0x107d
5295 #define mmCM3_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2
5296 #define mmCM3_CM_RANGE_CLAMP_CONTROL_G 0x107e
5297 #define mmCM3_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2
5298 #define mmCM3_CM_RANGE_CLAMP_CONTROL_B 0x107f
5299 #define mmCM3_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2
5300 #define mmCM3_CM_DENORM_CONTROL 0x1080
5301 #define mmCM3_CM_DENORM_CONTROL_BASE_IDX 2
5302 #define mmCM3_CM_CMOUT_CONTROL 0x1081
5303 #define mmCM3_CM_CMOUT_CONTROL_BASE_IDX 2
5304 #define mmCM3_CM_CMOUT_RANDOM_SEEDS 0x1082
5305 #define mmCM3_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2
5306 #define mmCM3_CM_MEM_PWR_CTRL 0x1083
5307 #define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
5308 #define mmCM3_CM_MEM_PWR_STATUS 0x1084
5309 #define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
5312 // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
5313 // base address: 0x4274
5314 #define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x109d
5315 #define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2
5316 #define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x109e
5317 #define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2
5318 #define mmDC_PERFMON15_PERFCOUNTER_STATE 0x109f
5319 #define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2
5320 #define mmDC_PERFMON15_PERFMON_CNTL 0x10a0
5321 #define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2
5322 #define mmDC_PERFMON15_PERFMON_CNTL2 0x10a1
5323 #define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2
5324 #define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x10a2
5325 #define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
5326 #define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x10a3
5327 #define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2
5328 #define mmDC_PERFMON15_PERFMON_HI 0x10a4
5329 #define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 2
5330 #define mmDC_PERFMON15_PERFMON_LOW 0x10a5
5331 #define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 2
5334 // addressBlock: dce_dc_mpc_mpcc0_dispdec
5335 // base address: 0x0
5336 #define mmMPCC0_MPCC_TOP_SEL 0x1630
5337 #define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 2
5338 #define mmMPCC0_MPCC_BOT_SEL 0x1631
5339 #define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 2
5340 #define mmMPCC0_MPCC_OPP_ID 0x1632
5341 #define mmMPCC0_MPCC_OPP_ID_BASE_IDX 2
5342 #define mmMPCC0_MPCC_CONTROL 0x1633
5343 #define mmMPCC0_MPCC_CONTROL_BASE_IDX 2
5344 #define mmMPCC0_MPCC_SM_CONTROL 0x1634
5345 #define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 2
5346 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x1635
5347 #define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
5348 #define mmMPCC0_MPCC_TOP_OFFSET 0x1636
5349 #define mmMPCC0_MPCC_TOP_OFFSET_BASE_IDX 2
5350 #define mmMPCC0_MPCC_BOT_OFFSET 0x1637
5351 #define mmMPCC0_MPCC_BOT_OFFSET_BASE_IDX 2
5352 #define mmMPCC0_MPCC_OFFSET 0x1638
5353 #define mmMPCC0_MPCC_OFFSET_BASE_IDX 2
5354 #define mmMPCC0_MPCC_BG_R_CR 0x1639
5355 #define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 2
5356 #define mmMPCC0_MPCC_BG_G_Y 0x163a
5357 #define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 2
5358 #define mmMPCC0_MPCC_BG_B_CB 0x163b
5359 #define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 2
5360 #define mmMPCC0_MPCC_STALL_STATUS 0x163c
5361 #define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX 2
5362 #define mmMPCC0_MPCC_STATUS 0x163d
5363 #define mmMPCC0_MPCC_STATUS_BASE_IDX 2
5366 // addressBlock: dce_dc_mpc_mpcc1_dispdec
5367 // base address: 0x6c
5368 #define mmMPCC1_MPCC_TOP_SEL 0x164b
5369 #define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 2
5370 #define mmMPCC1_MPCC_BOT_SEL 0x164c
5371 #define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 2
5372 #define mmMPCC1_MPCC_OPP_ID 0x164d
5373 #define mmMPCC1_MPCC_OPP_ID_BASE_IDX 2
5374 #define mmMPCC1_MPCC_CONTROL 0x164e
5375 #define mmMPCC1_MPCC_CONTROL_BASE_IDX 2
5376 #define mmMPCC1_MPCC_SM_CONTROL 0x164f
5377 #define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 2
5378 #define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x1650
5379 #define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
5380 #define mmMPCC1_MPCC_TOP_OFFSET 0x1651
5381 #define mmMPCC1_MPCC_TOP_OFFSET_BASE_IDX 2
5382 #define mmMPCC1_MPCC_BOT_OFFSET 0x1652
5383 #define mmMPCC1_MPCC_BOT_OFFSET_BASE_IDX 2
5384 #define mmMPCC1_MPCC_OFFSET 0x1653
5385 #define mmMPCC1_MPCC_OFFSET_BASE_IDX 2
5386 #define mmMPCC1_MPCC_BG_R_CR 0x1654
5387 #define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 2
5388 #define mmMPCC1_MPCC_BG_G_Y 0x1655
5389 #define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 2
5390 #define mmMPCC1_MPCC_BG_B_CB 0x1656
5391 #define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 2
5392 #define mmMPCC1_MPCC_STALL_STATUS 0x1657
5393 #define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX 2
5394 #define mmMPCC1_MPCC_STATUS 0x1658
5395 #define mmMPCC1_MPCC_STATUS_BASE_IDX 2
5398 // addressBlock: dce_dc_mpc_mpcc2_dispdec
5399 // base address: 0xd8
5400 #define mmMPCC2_MPCC_TOP_SEL 0x1666
5401 #define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 2
5402 #define mmMPCC2_MPCC_BOT_SEL 0x1667
5403 #define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 2
5404 #define mmMPCC2_MPCC_OPP_ID 0x1668
5405 #define mmMPCC2_MPCC_OPP_ID_BASE_IDX 2
5406 #define mmMPCC2_MPCC_CONTROL 0x1669
5407 #define mmMPCC2_MPCC_CONTROL_BASE_IDX 2
5408 #define mmMPCC2_MPCC_SM_CONTROL 0x166a
5409 #define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 2
5410 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x166b
5411 #define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
5412 #define mmMPCC2_MPCC_TOP_OFFSET 0x166c
5413 #define mmMPCC2_MPCC_TOP_OFFSET_BASE_IDX 2
5414 #define mmMPCC2_MPCC_BOT_OFFSET 0x166d
5415 #define mmMPCC2_MPCC_BOT_OFFSET_BASE_IDX 2
5416 #define mmMPCC2_MPCC_OFFSET 0x166e
5417 #define mmMPCC2_MPCC_OFFSET_BASE_IDX 2
5418 #define mmMPCC2_MPCC_BG_R_CR 0x166f
5419 #define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 2
5420 #define mmMPCC2_MPCC_BG_G_Y 0x1670
5421 #define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 2
5422 #define mmMPCC2_MPCC_BG_B_CB 0x1671
5423 #define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 2
5424 #define mmMPCC2_MPCC_STALL_STATUS 0x1672
5425 #define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX 2
5426 #define mmMPCC2_MPCC_STATUS 0x1673
5427 #define mmMPCC2_MPCC_STATUS_BASE_IDX 2
5430 // addressBlock: dce_dc_mpc_mpcc3_dispdec
5431 // base address: 0x144
5432 #define mmMPCC3_MPCC_TOP_SEL 0x1681
5433 #define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 2
5434 #define mmMPCC3_MPCC_BOT_SEL 0x1682
5435 #define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 2
5436 #define mmMPCC3_MPCC_OPP_ID 0x1683
5437 #define mmMPCC3_MPCC_OPP_ID_BASE_IDX 2
5438 #define mmMPCC3_MPCC_CONTROL 0x1684
5439 #define mmMPCC3_MPCC_CONTROL_BASE_IDX 2
5440 #define mmMPCC3_MPCC_SM_CONTROL 0x1685
5441 #define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 2
5442 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x1686
5443 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
5444 #define mmMPCC3_MPCC_TOP_OFFSET 0x1687
5445 #define mmMPCC3_MPCC_TOP_OFFSET_BASE_IDX 2
5446 #define mmMPCC3_MPCC_BOT_OFFSET 0x1688
5447 #define mmMPCC3_MPCC_BOT_OFFSET_BASE_IDX 2
5448 #define mmMPCC3_MPCC_OFFSET 0x1689
5449 #define mmMPCC3_MPCC_OFFSET_BASE_IDX 2
5450 #define mmMPCC3_MPCC_BG_R_CR 0x168a
5451 #define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 2
5452 #define mmMPCC3_MPCC_BG_G_Y 0x168b
5453 #define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 2
5454 #define mmMPCC3_MPCC_BG_B_CB 0x168c
5455 #define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 2
5456 #define mmMPCC3_MPCC_STALL_STATUS 0x168d
5457 #define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX 2
5458 #define mmMPCC3_MPCC_STATUS 0x168e
5459 #define mmMPCC3_MPCC_STATUS_BASE_IDX 2
5462 // addressBlock: dce_dc_mpc_mpc_cfg_dispdec
5463 // base address: 0x0
5464 #define mmMPC_CLOCK_CONTROL 0x1723
5465 #define mmMPC_CLOCK_CONTROL_BASE_IDX 2
5466 #define mmMPC_SOFT_RESET 0x1724
5467 #define mmMPC_SOFT_RESET_BASE_IDX 2
5468 #define mmMPC_CRC_CTRL 0x1725
5469 #define mmMPC_CRC_CTRL_BASE_IDX 2
5470 #define mmMPC_CRC_SEL_CONTROL 0x1726
5471 #define mmMPC_CRC_SEL_CONTROL_BASE_IDX 2
5472 #define mmMPC_CRC_RESULT_AR 0x1727
5473 #define mmMPC_CRC_RESULT_AR_BASE_IDX 2
5474 #define mmMPC_CRC_RESULT_GB 0x1728
5475 #define mmMPC_CRC_RESULT_GB_BASE_IDX 2
5476 #define mmMPC_CRC_RESULT_C 0x1729
5477 #define mmMPC_CRC_RESULT_C_BASE_IDX 2
5478 #define mmMPC_PERFMON_EVENT_CTRL 0x172c
5479 #define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 2
5480 #define mmMPC_BYPASS_BG_AR 0x172d
5481 #define mmMPC_BYPASS_BG_AR_BASE_IDX 2
5482 #define mmMPC_BYPASS_BG_GB 0x172e
5483 #define mmMPC_BYPASS_BG_GB_BASE_IDX 2
5484 #define mmMPC_OUT0_MUX 0x172f
5485 #define mmMPC_OUT0_MUX_BASE_IDX 2
5486 #define mmMPC_OUT1_MUX 0x1730
5487 #define mmMPC_OUT1_MUX_BASE_IDX 2
5488 #define mmMPC_OUT2_MUX 0x1731
5489 #define mmMPC_OUT2_MUX_BASE_IDX 2
5490 #define mmMPC_OUT3_MUX 0x1732
5491 #define mmMPC_OUT3_MUX_BASE_IDX 2
5492 #define mmMPC_STALL_GRACE_WINDOW 0x1756
5493 #define mmMPC_STALL_GRACE_WINDOW_BASE_IDX 2
5494 #define mmADR_CFG_VUPDATE_LOCK_SET0 0x175b
5495 #define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 2
5496 #define mmADR_VUPDATE_LOCK_SET0 0x175c
5497 #define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 2
5498 #define mmCUR0_VUPDATE_LOCK_SET0 0x175d
5499 #define mmCUR0_VUPDATE_LOCK_SET0_BASE_IDX 2
5500 #define mmCUR1_VUPDATE_LOCK_SET0 0x175e
5501 #define mmCUR1_VUPDATE_LOCK_SET0_BASE_IDX 2
5502 #define mmADR_CFG_VUPDATE_LOCK_SET1 0x175f
5503 #define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 2
5504 #define mmADR_VUPDATE_LOCK_SET1 0x1760
5505 #define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 2
5506 #define mmCUR0_VUPDATE_LOCK_SET1 0x1761
5507 #define mmCUR0_VUPDATE_LOCK_SET1_BASE_IDX 2
5508 #define mmCUR1_VUPDATE_LOCK_SET1 0x1762
5509 #define mmCUR1_VUPDATE_LOCK_SET1_BASE_IDX 2
5510 #define mmADR_CFG_VUPDATE_LOCK_SET2 0x1763
5511 #define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 2
5512 #define mmADR_VUPDATE_LOCK_SET2 0x1764
5513 #define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 2
5514 #define mmCUR0_VUPDATE_LOCK_SET2 0x1765
5515 #define mmCUR0_VUPDATE_LOCK_SET2_BASE_IDX 2
5516 #define mmCUR1_VUPDATE_LOCK_SET2 0x1766
5517 #define mmCUR1_VUPDATE_LOCK_SET2_BASE_IDX 2
5518 #define mmADR_CFG_VUPDATE_LOCK_SET3 0x1767
5519 #define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 2
5520 #define mmADR_VUPDATE_LOCK_SET3 0x1768
5521 #define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 2
5522 #define mmCUR0_VUPDATE_LOCK_SET3 0x1769
5523 #define mmCUR0_VUPDATE_LOCK_SET3_BASE_IDX 2
5524 #define mmCUR1_VUPDATE_LOCK_SET3 0x176a
5525 #define mmCUR1_VUPDATE_LOCK_SET3_BASE_IDX 2
5528 // addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
5529 // base address: 0x5e90
5530 #define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x17a4
5531 #define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2
5532 #define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x17a5
5533 #define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2
5534 #define mmDC_PERFMON16_PERFCOUNTER_STATE 0x17a6
5535 #define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2
5536 #define mmDC_PERFMON16_PERFMON_CNTL 0x17a7
5537 #define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2
5538 #define mmDC_PERFMON16_PERFMON_CNTL2 0x17a8
5539 #define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2
5540 #define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x17a9
5541 #define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
5542 #define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x17aa
5543 #define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2
5544 #define mmDC_PERFMON16_PERFMON_HI 0x17ab
5545 #define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 2
5546 #define mmDC_PERFMON16_PERFMON_LOW 0x17ac
5547 #define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 2
5550 // addressBlock: dce_dc_opp_abm0_dispdec
5551 // base address: 0x0
5552 #define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x17b0
5553 #define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2
5554 #define mmABM0_BL1_PWM_USER_LEVEL 0x17b1
5555 #define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX 2
5556 #define mmABM0_BL1_PWM_TARGET_ABM_LEVEL 0x17b2
5557 #define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2
5558 #define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x17b3
5559 #define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2
5560 #define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x17b4
5561 #define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2
5562 #define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x17b5
5563 #define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2
5564 #define mmABM0_BL1_PWM_ABM_CNTL 0x17b6
5565 #define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX 2
5566 #define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x17b7
5567 #define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2
5568 #define mmABM0_BL1_PWM_GRP2_REG_LOCK 0x17b8
5569 #define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 2
5570 #define mmABM0_DC_ABM1_CNTL 0x17b9
5571 #define mmABM0_DC_ABM1_CNTL_BASE_IDX 2
5572 #define mmABM0_DC_ABM1_IPCSC_COEFF_SEL 0x17ba
5573 #define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2
5574 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x17bb
5575 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2
5576 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x17bc
5577 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2
5578 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x17bd
5579 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2
5580 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x17be
5581 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2
5582 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x17bf
5583 #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2
5584 #define mmABM0_DC_ABM1_ACE_THRES_12 0x17c0
5585 #define mmABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 2
5586 #define mmABM0_DC_ABM1_ACE_THRES_34 0x17c1
5587 #define mmABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 2
5588 #define mmABM0_DC_ABM1_ACE_CNTL_MISC 0x17c2
5589 #define mmABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 2
5590 #define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x17c4
5591 #define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2
5592 #define mmABM0_DC_ABM1_HG_MISC_CTRL 0x17c5
5593 #define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 2
5594 #define mmABM0_DC_ABM1_LS_SUM_OF_LUMA 0x17c6
5595 #define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2
5596 #define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x17c7
5597 #define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2
5598 #define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x17c8
5599 #define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2
5600 #define mmABM0_DC_ABM1_LS_PIXEL_COUNT 0x17c9
5601 #define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2
5602 #define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x17ca
5603 #define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2
5604 #define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x17cb
5605 #define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2
5606 #define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x17cc
5607 #define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2
5608 #define mmABM0_DC_ABM1_HG_SAMPLE_RATE 0x17cd
5609 #define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2
5610 #define mmABM0_DC_ABM1_LS_SAMPLE_RATE 0x17ce
5611 #define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2
5612 #define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x17cf
5613 #define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2
5614 #define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x17d0
5615 #define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2
5616 #define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x17d1
5617 #define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2
5618 #define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x17d2
5619 #define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2
5620 #define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x17d3
5621 #define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2
5622 #define mmABM0_DC_ABM1_HG_RESULT_1 0x17d4
5623 #define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 2
5624 #define mmABM0_DC_ABM1_HG_RESULT_2 0x17d5
5625 #define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 2
5626 #define mmABM0_DC_ABM1_HG_RESULT_3 0x17d6
5627 #define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 2
5628 #define mmABM0_DC_ABM1_HG_RESULT_4 0x17d7
5629 #define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 2
5630 #define mmABM0_DC_ABM1_HG_RESULT_5 0x17d8
5631 #define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 2
5632 #define mmABM0_DC_ABM1_HG_RESULT_6 0x17d9
5633 #define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 2
5634 #define mmABM0_DC_ABM1_HG_RESULT_7 0x17da
5635 #define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 2
5636 #define mmABM0_DC_ABM1_HG_RESULT_8 0x17db
5637 #define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 2
5638 #define mmABM0_DC_ABM1_HG_RESULT_9 0x17dc
5639 #define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 2
5640 #define mmABM0_DC_ABM1_HG_RESULT_10 0x17dd
5641 #define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 2
5642 #define mmABM0_DC_ABM1_HG_RESULT_11 0x17de
5643 #define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 2
5644 #define mmABM0_DC_ABM1_HG_RESULT_12 0x17df
5645 #define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 2
5646 #define mmABM0_DC_ABM1_HG_RESULT_13 0x17e0
5647 #define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 2
5648 #define mmABM0_DC_ABM1_HG_RESULT_14 0x17e1
5649 #define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 2
5650 #define mmABM0_DC_ABM1_HG_RESULT_15 0x17e2
5651 #define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 2
5652 #define mmABM0_DC_ABM1_HG_RESULT_16 0x17e3
5653 #define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 2
5654 #define mmABM0_DC_ABM1_HG_RESULT_17 0x17e4
5655 #define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 2
5656 #define mmABM0_DC_ABM1_HG_RESULT_18 0x17e5
5657 #define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 2
5658 #define mmABM0_DC_ABM1_HG_RESULT_19 0x17e6
5659 #define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 2
5660 #define mmABM0_DC_ABM1_HG_RESULT_20 0x17e7
5661 #define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 2
5662 #define mmABM0_DC_ABM1_HG_RESULT_21 0x17e8
5663 #define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 2
5664 #define mmABM0_DC_ABM1_HG_RESULT_22 0x17e9
5665 #define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 2
5666 #define mmABM0_DC_ABM1_HG_RESULT_23 0x17ea
5667 #define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 2
5668 #define mmABM0_DC_ABM1_HG_RESULT_24 0x17eb
5669 #define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 2
5670 #define mmABM0_DC_ABM1_BL_MASTER_LOCK 0x17ec
5671 #define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 2
5674 // addressBlock: dce_dc_opp_abm1_dispdec
5675 // base address: 0x118
5676 #define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x17f6
5677 #define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2
5678 #define mmABM1_BL1_PWM_USER_LEVEL 0x17f7
5679 #define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX 2
5680 #define mmABM1_BL1_PWM_TARGET_ABM_LEVEL 0x17f8
5681 #define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2
5682 #define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x17f9
5683 #define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2
5684 #define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x17fa
5685 #define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2
5686 #define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x17fb
5687 #define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2
5688 #define mmABM1_BL1_PWM_ABM_CNTL 0x17fc
5689 #define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX 2
5690 #define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x17fd
5691 #define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2
5692 #define mmABM1_BL1_PWM_GRP2_REG_LOCK 0x17fe
5693 #define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 2
5694 #define mmABM1_DC_ABM1_CNTL 0x17ff
5695 #define mmABM1_DC_ABM1_CNTL_BASE_IDX 2
5696 #define mmABM1_DC_ABM1_IPCSC_COEFF_SEL 0x1800
5697 #define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2
5698 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x1801
5699 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2
5700 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x1802
5701 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2
5702 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x1803
5703 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2
5704 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x1804
5705 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2
5706 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x1805
5707 #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2
5708 #define mmABM1_DC_ABM1_ACE_THRES_12 0x1806
5709 #define mmABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 2
5710 #define mmABM1_DC_ABM1_ACE_THRES_34 0x1807
5711 #define mmABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 2
5712 #define mmABM1_DC_ABM1_ACE_CNTL_MISC 0x1808
5713 #define mmABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 2
5714 #define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x180a
5715 #define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2
5716 #define mmABM1_DC_ABM1_HG_MISC_CTRL 0x180b
5717 #define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 2
5718 #define mmABM1_DC_ABM1_LS_SUM_OF_LUMA 0x180c
5719 #define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2
5720 #define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x180d
5721 #define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2
5722 #define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x180e
5723 #define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2
5724 #define mmABM1_DC_ABM1_LS_PIXEL_COUNT 0x180f
5725 #define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2
5726 #define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1810
5727 #define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2
5728 #define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1811
5729 #define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2
5730 #define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1812
5731 #define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2
5732 #define mmABM1_DC_ABM1_HG_SAMPLE_RATE 0x1813
5733 #define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2
5734 #define mmABM1_DC_ABM1_LS_SAMPLE_RATE 0x1814
5735 #define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2
5736 #define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1815
5737 #define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2
5738 #define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1816
5739 #define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2
5740 #define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1817
5741 #define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2
5742 #define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1818
5743 #define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2
5744 #define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x1819
5745 #define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2
5746 #define mmABM1_DC_ABM1_HG_RESULT_1 0x181a
5747 #define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 2
5748 #define mmABM1_DC_ABM1_HG_RESULT_2 0x181b
5749 #define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 2
5750 #define mmABM1_DC_ABM1_HG_RESULT_3 0x181c
5751 #define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 2
5752 #define mmABM1_DC_ABM1_HG_RESULT_4 0x181d
5753 #define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 2
5754 #define mmABM1_DC_ABM1_HG_RESULT_5 0x181e
5755 #define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 2
5756 #define mmABM1_DC_ABM1_HG_RESULT_6 0x181f
5757 #define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 2
5758 #define mmABM1_DC_ABM1_HG_RESULT_7 0x1820
5759 #define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 2
5760 #define mmABM1_DC_ABM1_HG_RESULT_8 0x1821
5761 #define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 2
5762 #define mmABM1_DC_ABM1_HG_RESULT_9 0x1822
5763 #define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 2
5764 #define mmABM1_DC_ABM1_HG_RESULT_10 0x1823
5765 #define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 2
5766 #define mmABM1_DC_ABM1_HG_RESULT_11 0x1824
5767 #define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 2
5768 #define mmABM1_DC_ABM1_HG_RESULT_12 0x1825
5769 #define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 2
5770 #define mmABM1_DC_ABM1_HG_RESULT_13 0x1826
5771 #define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 2
5772 #define mmABM1_DC_ABM1_HG_RESULT_14 0x1827
5773 #define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 2
5774 #define mmABM1_DC_ABM1_HG_RESULT_15 0x1828
5775 #define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 2
5776 #define mmABM1_DC_ABM1_HG_RESULT_16 0x1829
5777 #define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 2
5778 #define mmABM1_DC_ABM1_HG_RESULT_17 0x182a
5779 #define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 2
5780 #define mmABM1_DC_ABM1_HG_RESULT_18 0x182b
5781 #define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 2
5782 #define mmABM1_DC_ABM1_HG_RESULT_19 0x182c
5783 #define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 2
5784 #define mmABM1_DC_ABM1_HG_RESULT_20 0x182d
5785 #define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 2
5786 #define mmABM1_DC_ABM1_HG_RESULT_21 0x182e
5787 #define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 2
5788 #define mmABM1_DC_ABM1_HG_RESULT_22 0x182f
5789 #define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 2
5790 #define mmABM1_DC_ABM1_HG_RESULT_23 0x1830
5791 #define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 2
5792 #define mmABM1_DC_ABM1_HG_RESULT_24 0x1831
5793 #define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 2
5794 #define mmABM1_DC_ABM1_BL_MASTER_LOCK 0x1832
5795 #define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 2
5798 // addressBlock: dce_dc_opp_fmt0_dispdec
5799 // base address: 0x0
5800 #define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c
5801 #define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
5802 #define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d
5803 #define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
5804 #define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e
5805 #define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
5806 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f
5807 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
5808 #define mmFMT0_FMT_CONTROL 0x1840
5809 #define mmFMT0_FMT_CONTROL_BASE_IDX 2
5810 #define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841
5811 #define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
5812 #define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842
5813 #define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
5814 #define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843
5815 #define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
5816 #define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844
5817 #define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
5818 #define mmFMT0_FMT_CLAMP_CNTL 0x1848
5819 #define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2
5820 #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1849
5821 #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
5822 #define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x184a
5823 #define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
5826 // addressBlock: dce_dc_opp_oppbuf0_dispdec
5827 // base address: 0x0
5828 #define mmOPPBUF0_OPPBUF_CONTROL 0x1884
5829 #define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2
5830 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885
5831 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
5832 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886
5833 #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
5836 // addressBlock: dce_dc_opp_opp_pipe0_dispdec
5837 // base address: 0x0
5838 #define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c
5839 #define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2
5842 // addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
5843 // base address: 0x0
5844 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891
5845 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
5846 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892
5847 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2
5848 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893
5849 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
5850 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894
5851 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
5852 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895
5853 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
5856 // addressBlock: dce_dc_opp_fmt1_dispdec
5857 // base address: 0x168
5858 #define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896
5859 #define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
5860 #define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897
5861 #define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
5862 #define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898
5863 #define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
5864 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899
5865 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
5866 #define mmFMT1_FMT_CONTROL 0x189a
5867 #define mmFMT1_FMT_CONTROL_BASE_IDX 2
5868 #define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b
5869 #define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
5870 #define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c
5871 #define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
5872 #define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d
5873 #define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
5874 #define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e
5875 #define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
5876 #define mmFMT1_FMT_CLAMP_CNTL 0x18a2
5877 #define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2
5878 #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a3
5879 #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
5880 #define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a4
5881 #define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
5884 // addressBlock: dce_dc_opp_oppbuf1_dispdec
5885 // base address: 0x168
5886 #define mmOPPBUF1_OPPBUF_CONTROL 0x18de
5887 #define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2
5888 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df
5889 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
5890 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0
5891 #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
5894 // addressBlock: dce_dc_opp_opp_pipe1_dispdec
5895 // base address: 0x168
5896 #define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6
5897 #define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2
5900 // addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
5901 // base address: 0x168
5902 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb
5903 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
5904 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec
5905 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2
5906 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed
5907 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
5908 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee
5909 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
5910 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef
5911 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
5914 // addressBlock: dce_dc_opp_fmt2_dispdec
5915 // base address: 0x2d0
5916 #define mmFMT2_FMT_CLAMP_COMPONENT_R 0x18f0
5917 #define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
5918 #define mmFMT2_FMT_CLAMP_COMPONENT_G 0x18f1
5919 #define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
5920 #define mmFMT2_FMT_CLAMP_COMPONENT_B 0x18f2
5921 #define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
5922 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3
5923 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
5924 #define mmFMT2_FMT_CONTROL 0x18f4
5925 #define mmFMT2_FMT_CONTROL_BASE_IDX 2
5926 #define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5
5927 #define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
5928 #define mmFMT2_FMT_DITHER_RAND_R_SEED 0x18f6
5929 #define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
5930 #define mmFMT2_FMT_DITHER_RAND_G_SEED 0x18f7
5931 #define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
5932 #define mmFMT2_FMT_DITHER_RAND_B_SEED 0x18f8
5933 #define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
5934 #define mmFMT2_FMT_CLAMP_CNTL 0x18fc
5935 #define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2
5936 #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fd
5937 #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
5938 #define mmFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fe
5939 #define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
5942 // addressBlock: dce_dc_opp_oppbuf2_dispdec
5943 // base address: 0x2d0
5944 #define mmOPPBUF2_OPPBUF_CONTROL 0x1938
5945 #define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2
5946 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939
5947 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
5948 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a
5949 #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
5952 // addressBlock: dce_dc_opp_opp_pipe2_dispdec
5953 // base address: 0x2d0
5954 #define mmOPP_PIPE2_OPP_PIPE_CONTROL 0x1940
5955 #define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2
5958 // addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
5959 // base address: 0x2d0
5960 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945
5961 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
5962 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946
5963 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2
5964 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947
5965 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
5966 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948
5967 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
5968 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949
5969 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
5972 // addressBlock: dce_dc_opp_fmt3_dispdec
5973 // base address: 0x438
5974 #define mmFMT3_FMT_CLAMP_COMPONENT_R 0x194a
5975 #define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
5976 #define mmFMT3_FMT_CLAMP_COMPONENT_G 0x194b
5977 #define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
5978 #define mmFMT3_FMT_CLAMP_COMPONENT_B 0x194c
5979 #define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
5980 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d
5981 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
5982 #define mmFMT3_FMT_CONTROL 0x194e
5983 #define mmFMT3_FMT_CONTROL_BASE_IDX 2
5984 #define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x194f
5985 #define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
5986 #define mmFMT3_FMT_DITHER_RAND_R_SEED 0x1950
5987 #define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
5988 #define mmFMT3_FMT_DITHER_RAND_G_SEED 0x1951
5989 #define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
5990 #define mmFMT3_FMT_DITHER_RAND_B_SEED 0x1952
5991 #define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
5992 #define mmFMT3_FMT_CLAMP_CNTL 0x1956
5993 #define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2
5994 #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1957
5995 #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
5996 #define mmFMT3_FMT_MAP420_MEMORY_CONTROL 0x1958
5997 #define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
6000 // addressBlock: dce_dc_opp_oppbuf3_dispdec
6001 // base address: 0x438
6002 #define mmOPPBUF3_OPPBUF_CONTROL 0x1992
6003 #define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2
6004 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993
6005 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
6006 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994
6007 #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
6010 // addressBlock: dce_dc_opp_opp_pipe3_dispdec
6011 // base address: 0x438
6012 #define mmOPP_PIPE3_OPP_PIPE_CONTROL 0x199a
6013 #define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2
6016 // addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
6017 // base address: 0x438
6018 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f
6019 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
6020 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0
6021 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2
6022 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1
6023 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
6024 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2
6025 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
6026 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3
6027 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
6030 // addressBlock: dce_dc_opp_fmt4_dispdec
6031 // base address: 0x5a0
6032 #define mmFMT4_FMT_CLAMP_COMPONENT_R 0x19a4
6033 #define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
6034 #define mmFMT4_FMT_CLAMP_COMPONENT_G 0x19a5
6035 #define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
6036 #define mmFMT4_FMT_CLAMP_COMPONENT_B 0x19a6
6037 #define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
6038 #define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x19a7
6039 #define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
6040 #define mmFMT4_FMT_CONTROL 0x19a8
6041 #define mmFMT4_FMT_CONTROL_BASE_IDX 2
6042 #define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x19a9
6043 #define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
6044 #define mmFMT4_FMT_DITHER_RAND_R_SEED 0x19aa
6045 #define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
6046 #define mmFMT4_FMT_DITHER_RAND_G_SEED 0x19ab
6047 #define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
6048 #define mmFMT4_FMT_DITHER_RAND_B_SEED 0x19ac
6049 #define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
6050 #define mmFMT4_FMT_CLAMP_CNTL 0x19b0
6051 #define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2
6052 #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x19b1
6053 #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
6054 #define mmFMT4_FMT_MAP420_MEMORY_CONTROL 0x19b2
6055 #define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
6058 // addressBlock: dce_dc_opp_oppbuf4_dispdec
6059 // base address: 0x5a0
6060 #define mmOPPBUF4_OPPBUF_CONTROL 0x19ec
6061 #define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX 2
6062 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 0x19ed
6063 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
6064 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 0x19ee
6065 #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
6068 // addressBlock: dce_dc_opp_opp_pipe4_dispdec
6069 // base address: 0x5a0
6070 #define mmOPP_PIPE4_OPP_PIPE_CONTROL 0x19f4
6071 #define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX 2
6074 // addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec
6075 // base address: 0x5a0
6076 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL 0x19f9
6077 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
6078 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK 0x19fa
6079 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX 2
6080 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 0x19fb
6081 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
6082 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 0x19fc
6083 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
6084 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 0x19fd
6085 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
6088 // addressBlock: dce_dc_opp_fmt5_dispdec
6089 // base address: 0x708
6090 #define mmFMT5_FMT_CLAMP_COMPONENT_R 0x19fe
6091 #define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
6092 #define mmFMT5_FMT_CLAMP_COMPONENT_G 0x19ff
6093 #define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
6094 #define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1a00
6095 #define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
6096 #define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1a01
6097 #define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
6098 #define mmFMT5_FMT_CONTROL 0x1a02
6099 #define mmFMT5_FMT_CONTROL_BASE_IDX 2
6100 #define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1a03
6101 #define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
6102 #define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1a04
6103 #define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
6104 #define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1a05
6105 #define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
6106 #define mmFMT5_FMT_DITHER_RAND_B_SEED 0x1a06
6107 #define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
6108 #define mmFMT5_FMT_CLAMP_CNTL 0x1a0a
6109 #define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2
6110 #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1a0b
6111 #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
6112 #define mmFMT5_FMT_MAP420_MEMORY_CONTROL 0x1a0c
6113 #define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
6116 // addressBlock: dce_dc_opp_oppbuf5_dispdec
6117 // base address: 0x708
6118 #define mmOPPBUF5_OPPBUF_CONTROL 0x1a46
6119 #define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX 2
6120 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0 0x1a47
6121 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
6122 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1 0x1a48
6123 #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
6126 // addressBlock: dce_dc_opp_opp_pipe5_dispdec
6127 // base address: 0x708
6128 #define mmOPP_PIPE5_OPP_PIPE_CONTROL 0x1a4e
6129 #define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 2
6132 // addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec
6133 // base address: 0x708
6134 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL 0x1a53
6135 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
6136 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK 0x1a54
6137 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX 2
6138 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 0x1a55
6139 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
6140 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 0x1a56
6141 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
6142 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 0x1a57
6143 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
6146 // addressBlock: dce_dc_opp_opp_top_dispdec
6147 // base address: 0x0
6148 #define mmOPP_TOP_CLK_CONTROL 0x1a5e
6149 #define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2
6152 // addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
6153 // base address: 0x6af8
6154 #define mmDC_PERFMON17_PERFCOUNTER_CNTL 0x1abe
6155 #define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2
6156 #define mmDC_PERFMON17_PERFCOUNTER_CNTL2 0x1abf
6157 #define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2
6158 #define mmDC_PERFMON17_PERFCOUNTER_STATE 0x1ac0
6159 #define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2
6160 #define mmDC_PERFMON17_PERFMON_CNTL 0x1ac1
6161 #define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2
6162 #define mmDC_PERFMON17_PERFMON_CNTL2 0x1ac2
6163 #define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2
6164 #define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1ac3
6165 #define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
6166 #define mmDC_PERFMON17_PERFMON_CVALUE_LOW 0x1ac4
6167 #define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2
6168 #define mmDC_PERFMON17_PERFMON_HI 0x1ac5
6169 #define mmDC_PERFMON17_PERFMON_HI_BASE_IDX 2
6170 #define mmDC_PERFMON17_PERFMON_LOW 0x1ac6
6171 #define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX 2
6174 // addressBlock: dce_dc_optc_odm0_dispdec
6175 // base address: 0x0
6176 #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca
6177 #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
6178 #define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb
6179 #define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
6180 #define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acd
6181 #define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
6182 #define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1acf
6183 #define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
6186 // addressBlock: dce_dc_optc_odm1_dispdec
6187 // base address: 0x40
6188 #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada
6189 #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
6190 #define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb
6191 #define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
6192 #define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1add
6193 #define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
6194 #define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1adf
6195 #define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
6198 // addressBlock: dce_dc_optc_odm2_dispdec
6199 // base address: 0x80
6200 #define mmODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea
6201 #define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
6202 #define mmODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb
6203 #define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
6204 #define mmODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aed
6205 #define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
6206 #define mmODM2_OPTC_INPUT_SPARE_REGISTER 0x1aef
6207 #define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
6210 // addressBlock: dce_dc_optc_odm3_dispdec
6211 // base address: 0xc0
6212 #define mmODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa
6213 #define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
6214 #define mmODM3_OPTC_DATA_SOURCE_SELECT 0x1afb
6215 #define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
6216 #define mmODM3_OPTC_INPUT_CLOCK_CONTROL 0x1afd
6217 #define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
6218 #define mmODM3_OPTC_INPUT_SPARE_REGISTER 0x1aff
6219 #define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
6222 // addressBlock: dce_dc_optc_odm4_dispdec
6223 // base address: 0x100
6224 #define mmODM4_OPTC_INPUT_GLOBAL_CONTROL 0x1b0a
6225 #define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
6226 #define mmODM4_OPTC_DATA_SOURCE_SELECT 0x1b0b
6227 #define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
6228 #define mmODM4_OPTC_INPUT_CLOCK_CONTROL 0x1b0d
6229 #define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
6230 #define mmODM4_OPTC_INPUT_SPARE_REGISTER 0x1b0f
6231 #define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
6234 // addressBlock: dce_dc_optc_odm5_dispdec
6235 // base address: 0x140
6236 #define mmODM5_OPTC_INPUT_GLOBAL_CONTROL 0x1b1a
6237 #define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
6238 #define mmODM5_OPTC_DATA_SOURCE_SELECT 0x1b1b
6239 #define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
6240 #define mmODM5_OPTC_INPUT_CLOCK_CONTROL 0x1b1d
6241 #define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
6242 #define mmODM5_OPTC_INPUT_SPARE_REGISTER 0x1b1f
6243 #define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
6246 // addressBlock: dce_dc_optc_otg0_dispdec
6247 // base address: 0x0
6248 #define mmOTG0_OTG_H_TOTAL 0x1b2a
6249 #define mmOTG0_OTG_H_TOTAL_BASE_IDX 2
6250 #define mmOTG0_OTG_H_BLANK_START_END 0x1b2b
6251 #define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2
6252 #define mmOTG0_OTG_H_SYNC_A 0x1b2c
6253 #define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2
6254 #define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d
6255 #define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2
6256 #define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e
6257 #define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2
6258 #define mmOTG0_OTG_V_TOTAL 0x1b2f
6259 #define mmOTG0_OTG_V_TOTAL_BASE_IDX 2
6260 #define mmOTG0_OTG_V_TOTAL_MIN 0x1b30
6261 #define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2
6262 #define mmOTG0_OTG_V_TOTAL_MAX 0x1b31
6263 #define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2
6264 #define mmOTG0_OTG_V_TOTAL_MID 0x1b32
6265 #define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2
6266 #define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33
6267 #define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2
6268 #define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34
6269 #define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
6270 #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35
6271 #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
6272 #define mmOTG0_OTG_V_BLANK_START_END 0x1b36
6273 #define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2
6274 #define mmOTG0_OTG_V_SYNC_A 0x1b37
6275 #define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2
6276 #define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38
6277 #define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2
6278 #define mmOTG0_OTG_TRIGA_CNTL 0x1b39
6279 #define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2
6280 #define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a
6281 #define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
6282 #define mmOTG0_OTG_TRIGB_CNTL 0x1b3b
6283 #define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2
6284 #define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c
6285 #define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
6286 #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d
6287 #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
6288 #define mmOTG0_OTG_FLOW_CONTROL 0x1b3e
6289 #define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2
6290 #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f
6291 #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
6292 #define mmOTG0_OTG_AVSYNC_COUNTER 0x1b40
6293 #define mmOTG0_OTG_AVSYNC_COUNTER_BASE_IDX 2
6294 #define mmOTG0_OTG_CONTROL 0x1b41
6295 #define mmOTG0_OTG_CONTROL_BASE_IDX 2
6296 #define mmOTG0_OTG_BLANK_CONTROL 0x1b42
6297 #define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX 2
6298 #define mmOTG0_OTG_PIPE_ABORT_CONTROL 0x1b43
6299 #define mmOTG0_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
6300 #define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44
6301 #define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2
6302 #define mmOTG0_OTG_INTERLACE_STATUS 0x1b45
6303 #define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2
6304 #define mmOTG0_OTG_FIELD_INDICATION_CONTROL 0x1b46
6305 #define mmOTG0_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
6306 #define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47
6307 #define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
6308 #define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48
6309 #define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
6310 #define mmOTG0_OTG_STATUS 0x1b49
6311 #define mmOTG0_OTG_STATUS_BASE_IDX 2
6312 #define mmOTG0_OTG_STATUS_POSITION 0x1b4a
6313 #define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2
6314 #define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b
6315 #define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2
6316 #define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c
6317 #define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
6318 #define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d
6319 #define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2
6320 #define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e
6321 #define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2
6322 #define mmOTG0_OTG_COUNT_CONTROL 0x1b4f
6323 #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2
6324 #define mmOTG0_OTG_COUNT_RESET 0x1b50
6325 #define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2
6326 #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51
6327 #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
6328 #define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52
6329 #define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
6330 #define mmOTG0_OTG_STEREO_STATUS 0x1b53
6331 #define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2
6332 #define mmOTG0_OTG_STEREO_CONTROL 0x1b54
6333 #define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2
6334 #define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55
6335 #define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2
6336 #define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56
6337 #define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
6338 #define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57
6339 #define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2
6340 #define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58
6341 #define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2
6342 #define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59
6343 #define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2
6344 #define mmOTG0_OTG_UPDATE_LOCK 0x1b5a
6345 #define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2
6346 #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b
6347 #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
6348 #define mmOTG0_OTG_TEST_PATTERN_CONTROL 0x1b5c
6349 #define mmOTG0_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
6350 #define mmOTG0_OTG_TEST_PATTERN_PARAMETERS 0x1b5d
6351 #define mmOTG0_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
6352 #define mmOTG0_OTG_TEST_PATTERN_COLOR 0x1b5e
6353 #define mmOTG0_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
6354 #define mmOTG0_OTG_MASTER_EN 0x1b5f
6355 #define mmOTG0_OTG_MASTER_EN_BASE_IDX 2
6356 #define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b61
6357 #define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2
6358 #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b62
6359 #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
6360 #define mmOTG0_OTG_BLACK_COLOR 0x1b63
6361 #define mmOTG0_OTG_BLACK_COLOR_BASE_IDX 2
6362 #define mmOTG0_OTG_BLACK_COLOR_EXT 0x1b64
6363 #define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX 2
6364 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b65
6365 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
6366 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b66
6367 #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
6368 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b67
6369 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
6370 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b68
6371 #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
6372 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b69
6373 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
6374 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b6a
6375 #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
6376 #define mmOTG0_OTG_CRC_CNTL 0x1b6b
6377 #define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2
6378 #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6c
6379 #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
6380 #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6d
6381 #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
6382 #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6e
6383 #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
6384 #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6f
6385 #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
6386 #define mmOTG0_OTG_CRC0_DATA_RG 0x1b70
6387 #define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2
6388 #define mmOTG0_OTG_CRC0_DATA_B 0x1b71
6389 #define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2
6390 #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b72
6391 #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
6392 #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b73
6393 #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
6394 #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b74
6395 #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
6396 #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b75
6397 #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
6398 #define mmOTG0_OTG_CRC1_DATA_RG 0x1b76
6399 #define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2
6400 #define mmOTG0_OTG_CRC1_DATA_B 0x1b77
6401 #define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2
6402 #define mmOTG0_OTG_CRC2_DATA_RG 0x1b78
6403 #define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2
6404 #define mmOTG0_OTG_CRC2_DATA_B 0x1b79
6405 #define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2
6406 #define mmOTG0_OTG_CRC3_DATA_RG 0x1b7a
6407 #define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2
6408 #define mmOTG0_OTG_CRC3_DATA_B 0x1b7b
6409 #define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2
6410 #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7c
6411 #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
6412 #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7d
6413 #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
6414 #define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b84
6415 #define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
6416 #define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b85
6417 #define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
6418 #define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b86
6419 #define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2
6420 #define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b87
6421 #define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
6422 #define mmOTG0_OTG_CLOCK_CONTROL 0x1b88
6423 #define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2
6424 #define mmOTG0_OTG_VSTARTUP_PARAM 0x1b89
6425 #define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2
6426 #define mmOTG0_OTG_VUPDATE_PARAM 0x1b8a
6427 #define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2
6428 #define mmOTG0_OTG_VREADY_PARAM 0x1b8b
6429 #define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2
6430 #define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8c
6431 #define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
6432 #define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8d
6433 #define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
6434 #define mmOTG0_OTG_GSL_CONTROL 0x1b8e
6435 #define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2
6436 #define mmOTG0_OTG_GSL_WINDOW_X 0x1b8f
6437 #define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2
6438 #define mmOTG0_OTG_GSL_WINDOW_Y 0x1b90
6439 #define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2
6440 #define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b91
6441 #define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
6442 #define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b92
6443 #define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2
6444 #define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b93
6445 #define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2
6446 #define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b94
6447 #define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2
6448 #define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b95
6449 #define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2
6450 #define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b96
6451 #define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
6452 #define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b97
6453 #define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
6454 #define mmOTG0_OTG_RANGE_TIMING_INT_STATUS 0x1b98
6455 #define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
6456 #define mmOTG0_OTG_DRR_CONTROL 0x1b99
6457 #define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2
6458 #define mmOTG0_OTG_REQUEST_CONTROL 0x1b9a
6459 #define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2
6460 #define mmOTG0_OTG_SPARE_REGISTER 0x1b9b
6461 #define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2
6464 // addressBlock: dce_dc_optc_otg1_dispdec
6465 // base address: 0x200
6466 #define mmOTG1_OTG_H_TOTAL 0x1baa
6467 #define mmOTG1_OTG_H_TOTAL_BASE_IDX 2
6468 #define mmOTG1_OTG_H_BLANK_START_END 0x1bab
6469 #define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2
6470 #define mmOTG1_OTG_H_SYNC_A 0x1bac
6471 #define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2
6472 #define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad
6473 #define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2
6474 #define mmOTG1_OTG_H_TIMING_CNTL 0x1bae
6475 #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2
6476 #define mmOTG1_OTG_V_TOTAL 0x1baf
6477 #define mmOTG1_OTG_V_TOTAL_BASE_IDX 2
6478 #define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0
6479 #define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2
6480 #define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1
6481 #define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2
6482 #define mmOTG1_OTG_V_TOTAL_MID 0x1bb2
6483 #define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2
6484 #define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3
6485 #define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2
6486 #define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4
6487 #define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
6488 #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5
6489 #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
6490 #define mmOTG1_OTG_V_BLANK_START_END 0x1bb6
6491 #define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2
6492 #define mmOTG1_OTG_V_SYNC_A 0x1bb7
6493 #define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2
6494 #define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8
6495 #define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2
6496 #define mmOTG1_OTG_TRIGA_CNTL 0x1bb9
6497 #define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2
6498 #define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba
6499 #define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
6500 #define mmOTG1_OTG_TRIGB_CNTL 0x1bbb
6501 #define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2
6502 #define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc
6503 #define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
6504 #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd
6505 #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
6506 #define mmOTG1_OTG_FLOW_CONTROL 0x1bbe
6507 #define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2
6508 #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf
6509 #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
6510 #define mmOTG1_OTG_AVSYNC_COUNTER 0x1bc0
6511 #define mmOTG1_OTG_AVSYNC_COUNTER_BASE_IDX 2
6512 #define mmOTG1_OTG_CONTROL 0x1bc1
6513 #define mmOTG1_OTG_CONTROL_BASE_IDX 2
6514 #define mmOTG1_OTG_BLANK_CONTROL 0x1bc2
6515 #define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2
6516 #define mmOTG1_OTG_PIPE_ABORT_CONTROL 0x1bc3
6517 #define mmOTG1_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
6518 #define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4
6519 #define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2
6520 #define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5
6521 #define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2
6522 #define mmOTG1_OTG_FIELD_INDICATION_CONTROL 0x1bc6
6523 #define mmOTG1_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
6524 #define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7
6525 #define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
6526 #define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8
6527 #define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
6528 #define mmOTG1_OTG_STATUS 0x1bc9
6529 #define mmOTG1_OTG_STATUS_BASE_IDX 2
6530 #define mmOTG1_OTG_STATUS_POSITION 0x1bca
6531 #define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2
6532 #define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb
6533 #define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2
6534 #define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc
6535 #define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
6536 #define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd
6537 #define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2
6538 #define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce
6539 #define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2
6540 #define mmOTG1_OTG_COUNT_CONTROL 0x1bcf
6541 #define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2
6542 #define mmOTG1_OTG_COUNT_RESET 0x1bd0
6543 #define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2
6544 #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1
6545 #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
6546 #define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2
6547 #define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
6548 #define mmOTG1_OTG_STEREO_STATUS 0x1bd3
6549 #define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2
6550 #define mmOTG1_OTG_STEREO_CONTROL 0x1bd4
6551 #define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2
6552 #define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5
6553 #define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2
6554 #define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6
6555 #define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
6556 #define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7
6557 #define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2
6558 #define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8
6559 #define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2
6560 #define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9
6561 #define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2
6562 #define mmOTG1_OTG_UPDATE_LOCK 0x1bda
6563 #define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2
6564 #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb
6565 #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
6566 #define mmOTG1_OTG_TEST_PATTERN_CONTROL 0x1bdc
6567 #define mmOTG1_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
6568 #define mmOTG1_OTG_TEST_PATTERN_PARAMETERS 0x1bdd
6569 #define mmOTG1_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
6570 #define mmOTG1_OTG_TEST_PATTERN_COLOR 0x1bde
6571 #define mmOTG1_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
6572 #define mmOTG1_OTG_MASTER_EN 0x1bdf
6573 #define mmOTG1_OTG_MASTER_EN_BASE_IDX 2
6574 #define mmOTG1_OTG_BLANK_DATA_COLOR 0x1be1
6575 #define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2
6576 #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1be2
6577 #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
6578 #define mmOTG1_OTG_BLACK_COLOR 0x1be3
6579 #define mmOTG1_OTG_BLACK_COLOR_BASE_IDX 2
6580 #define mmOTG1_OTG_BLACK_COLOR_EXT 0x1be4
6581 #define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX 2
6582 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be5
6583 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
6584 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be6
6585 #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
6586 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be7
6587 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
6588 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be8
6589 #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
6590 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be9
6591 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
6592 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1bea
6593 #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
6594 #define mmOTG1_OTG_CRC_CNTL 0x1beb
6595 #define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2
6596 #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bec
6597 #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
6598 #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1bed
6599 #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
6600 #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bee
6601 #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
6602 #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bef
6603 #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
6604 #define mmOTG1_OTG_CRC0_DATA_RG 0x1bf0
6605 #define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2
6606 #define mmOTG1_OTG_CRC0_DATA_B 0x1bf1
6607 #define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2
6608 #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf2
6609 #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
6610 #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf3
6611 #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
6612 #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf4
6613 #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
6614 #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf5
6615 #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
6616 #define mmOTG1_OTG_CRC1_DATA_RG 0x1bf6
6617 #define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2
6618 #define mmOTG1_OTG_CRC1_DATA_B 0x1bf7
6619 #define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2
6620 #define mmOTG1_OTG_CRC2_DATA_RG 0x1bf8
6621 #define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2
6622 #define mmOTG1_OTG_CRC2_DATA_B 0x1bf9
6623 #define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2
6624 #define mmOTG1_OTG_CRC3_DATA_RG 0x1bfa
6625 #define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2
6626 #define mmOTG1_OTG_CRC3_DATA_B 0x1bfb
6627 #define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2
6628 #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfc
6629 #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
6630 #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfd
6631 #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
6632 #define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c04
6633 #define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
6634 #define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c05
6635 #define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
6636 #define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c06
6637 #define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2
6638 #define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c07
6639 #define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
6640 #define mmOTG1_OTG_CLOCK_CONTROL 0x1c08
6641 #define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2
6642 #define mmOTG1_OTG_VSTARTUP_PARAM 0x1c09
6643 #define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2
6644 #define mmOTG1_OTG_VUPDATE_PARAM 0x1c0a
6645 #define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2
6646 #define mmOTG1_OTG_VREADY_PARAM 0x1c0b
6647 #define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2
6648 #define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0c
6649 #define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
6650 #define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0d
6651 #define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
6652 #define mmOTG1_OTG_GSL_CONTROL 0x1c0e
6653 #define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2
6654 #define mmOTG1_OTG_GSL_WINDOW_X 0x1c0f
6655 #define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2
6656 #define mmOTG1_OTG_GSL_WINDOW_Y 0x1c10
6657 #define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2
6658 #define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c11
6659 #define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
6660 #define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c12
6661 #define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2
6662 #define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c13
6663 #define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2
6664 #define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c14
6665 #define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2
6666 #define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c15
6667 #define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2
6668 #define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c16
6669 #define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
6670 #define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c17
6671 #define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
6672 #define mmOTG1_OTG_RANGE_TIMING_INT_STATUS 0x1c18
6673 #define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
6674 #define mmOTG1_OTG_DRR_CONTROL 0x1c19
6675 #define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2
6676 #define mmOTG1_OTG_REQUEST_CONTROL 0x1c1a
6677 #define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2
6678 #define mmOTG1_OTG_SPARE_REGISTER 0x1c1b
6679 #define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2
6682 // addressBlock: dce_dc_optc_otg2_dispdec
6683 // base address: 0x400
6684 #define mmOTG2_OTG_H_TOTAL 0x1c2a
6685 #define mmOTG2_OTG_H_TOTAL_BASE_IDX 2
6686 #define mmOTG2_OTG_H_BLANK_START_END 0x1c2b
6687 #define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX 2
6688 #define mmOTG2_OTG_H_SYNC_A 0x1c2c
6689 #define mmOTG2_OTG_H_SYNC_A_BASE_IDX 2
6690 #define mmOTG2_OTG_H_SYNC_A_CNTL 0x1c2d
6691 #define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2
6692 #define mmOTG2_OTG_H_TIMING_CNTL 0x1c2e
6693 #define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2
6694 #define mmOTG2_OTG_V_TOTAL 0x1c2f
6695 #define mmOTG2_OTG_V_TOTAL_BASE_IDX 2
6696 #define mmOTG2_OTG_V_TOTAL_MIN 0x1c30
6697 #define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2
6698 #define mmOTG2_OTG_V_TOTAL_MAX 0x1c31
6699 #define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2
6700 #define mmOTG2_OTG_V_TOTAL_MID 0x1c32
6701 #define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX 2
6702 #define mmOTG2_OTG_V_TOTAL_CONTROL 0x1c33
6703 #define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2
6704 #define mmOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34
6705 #define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
6706 #define mmOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35
6707 #define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
6708 #define mmOTG2_OTG_V_BLANK_START_END 0x1c36
6709 #define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX 2
6710 #define mmOTG2_OTG_V_SYNC_A 0x1c37
6711 #define mmOTG2_OTG_V_SYNC_A_BASE_IDX 2
6712 #define mmOTG2_OTG_V_SYNC_A_CNTL 0x1c38
6713 #define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2
6714 #define mmOTG2_OTG_TRIGA_CNTL 0x1c39
6715 #define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX 2
6716 #define mmOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a
6717 #define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
6718 #define mmOTG2_OTG_TRIGB_CNTL 0x1c3b
6719 #define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX 2
6720 #define mmOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c
6721 #define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
6722 #define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d
6723 #define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
6724 #define mmOTG2_OTG_FLOW_CONTROL 0x1c3e
6725 #define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX 2
6726 #define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f
6727 #define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
6728 #define mmOTG2_OTG_AVSYNC_COUNTER 0x1c40
6729 #define mmOTG2_OTG_AVSYNC_COUNTER_BASE_IDX 2
6730 #define mmOTG2_OTG_CONTROL 0x1c41
6731 #define mmOTG2_OTG_CONTROL_BASE_IDX 2
6732 #define mmOTG2_OTG_BLANK_CONTROL 0x1c42
6733 #define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX 2
6734 #define mmOTG2_OTG_PIPE_ABORT_CONTROL 0x1c43
6735 #define mmOTG2_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
6736 #define mmOTG2_OTG_INTERLACE_CONTROL 0x1c44
6737 #define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2
6738 #define mmOTG2_OTG_INTERLACE_STATUS 0x1c45
6739 #define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2
6740 #define mmOTG2_OTG_FIELD_INDICATION_CONTROL 0x1c46
6741 #define mmOTG2_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
6742 #define mmOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47
6743 #define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
6744 #define mmOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48
6745 #define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
6746 #define mmOTG2_OTG_STATUS 0x1c49
6747 #define mmOTG2_OTG_STATUS_BASE_IDX 2
6748 #define mmOTG2_OTG_STATUS_POSITION 0x1c4a
6749 #define mmOTG2_OTG_STATUS_POSITION_BASE_IDX 2
6750 #define mmOTG2_OTG_NOM_VERT_POSITION 0x1c4b
6751 #define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2
6752 #define mmOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c
6753 #define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
6754 #define mmOTG2_OTG_STATUS_VF_COUNT 0x1c4d
6755 #define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2
6756 #define mmOTG2_OTG_STATUS_HV_COUNT 0x1c4e
6757 #define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2
6758 #define mmOTG2_OTG_COUNT_CONTROL 0x1c4f
6759 #define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX 2
6760 #define mmOTG2_OTG_COUNT_RESET 0x1c50
6761 #define mmOTG2_OTG_COUNT_RESET_BASE_IDX 2
6762 #define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51
6763 #define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
6764 #define mmOTG2_OTG_VERT_SYNC_CONTROL 0x1c52
6765 #define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
6766 #define mmOTG2_OTG_STEREO_STATUS 0x1c53
6767 #define mmOTG2_OTG_STEREO_STATUS_BASE_IDX 2
6768 #define mmOTG2_OTG_STEREO_CONTROL 0x1c54
6769 #define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX 2
6770 #define mmOTG2_OTG_SNAPSHOT_STATUS 0x1c55
6771 #define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2
6772 #define mmOTG2_OTG_SNAPSHOT_CONTROL 0x1c56
6773 #define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
6774 #define mmOTG2_OTG_SNAPSHOT_POSITION 0x1c57
6775 #define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2
6776 #define mmOTG2_OTG_SNAPSHOT_FRAME 0x1c58
6777 #define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2
6778 #define mmOTG2_OTG_INTERRUPT_CONTROL 0x1c59
6779 #define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2
6780 #define mmOTG2_OTG_UPDATE_LOCK 0x1c5a
6781 #define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX 2
6782 #define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b
6783 #define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
6784 #define mmOTG2_OTG_TEST_PATTERN_CONTROL 0x1c5c
6785 #define mmOTG2_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
6786 #define mmOTG2_OTG_TEST_PATTERN_PARAMETERS 0x1c5d
6787 #define mmOTG2_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
6788 #define mmOTG2_OTG_TEST_PATTERN_COLOR 0x1c5e
6789 #define mmOTG2_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
6790 #define mmOTG2_OTG_MASTER_EN 0x1c5f
6791 #define mmOTG2_OTG_MASTER_EN_BASE_IDX 2
6792 #define mmOTG2_OTG_BLANK_DATA_COLOR 0x1c61
6793 #define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX 2
6794 #define mmOTG2_OTG_BLANK_DATA_COLOR_EXT 0x1c62
6795 #define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
6796 #define mmOTG2_OTG_BLACK_COLOR 0x1c63
6797 #define mmOTG2_OTG_BLACK_COLOR_BASE_IDX 2
6798 #define mmOTG2_OTG_BLACK_COLOR_EXT 0x1c64
6799 #define mmOTG2_OTG_BLACK_COLOR_EXT_BASE_IDX 2
6800 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c65
6801 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
6802 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c66
6803 #define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
6804 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c67
6805 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
6806 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c68
6807 #define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
6808 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c69
6809 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
6810 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c6a
6811 #define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
6812 #define mmOTG2_OTG_CRC_CNTL 0x1c6b
6813 #define mmOTG2_OTG_CRC_CNTL_BASE_IDX 2
6814 #define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6c
6815 #define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
6816 #define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6d
6817 #define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
6818 #define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6e
6819 #define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
6820 #define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6f
6821 #define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
6822 #define mmOTG2_OTG_CRC0_DATA_RG 0x1c70
6823 #define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2
6824 #define mmOTG2_OTG_CRC0_DATA_B 0x1c71
6825 #define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX 2
6826 #define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c72
6827 #define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
6828 #define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c73
6829 #define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
6830 #define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c74
6831 #define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
6832 #define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c75
6833 #define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
6834 #define mmOTG2_OTG_CRC1_DATA_RG 0x1c76
6835 #define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2
6836 #define mmOTG2_OTG_CRC1_DATA_B 0x1c77
6837 #define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX 2
6838 #define mmOTG2_OTG_CRC2_DATA_RG 0x1c78
6839 #define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2
6840 #define mmOTG2_OTG_CRC2_DATA_B 0x1c79
6841 #define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX 2
6842 #define mmOTG2_OTG_CRC3_DATA_RG 0x1c7a
6843 #define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2
6844 #define mmOTG2_OTG_CRC3_DATA_B 0x1c7b
6845 #define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX 2
6846 #define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7c
6847 #define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
6848 #define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7d
6849 #define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
6850 #define mmOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c84
6851 #define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
6852 #define mmOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c85
6853 #define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
6854 #define mmOTG2_OTG_GSL_VSYNC_GAP 0x1c86
6855 #define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2
6856 #define mmOTG2_OTG_MASTER_UPDATE_MODE 0x1c87
6857 #define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
6858 #define mmOTG2_OTG_CLOCK_CONTROL 0x1c88
6859 #define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2
6860 #define mmOTG2_OTG_VSTARTUP_PARAM 0x1c89
6861 #define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2
6862 #define mmOTG2_OTG_VUPDATE_PARAM 0x1c8a
6863 #define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2
6864 #define mmOTG2_OTG_VREADY_PARAM 0x1c8b
6865 #define mmOTG2_OTG_VREADY_PARAM_BASE_IDX 2
6866 #define mmOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8c
6867 #define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
6868 #define mmOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8d
6869 #define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
6870 #define mmOTG2_OTG_GSL_CONTROL 0x1c8e
6871 #define mmOTG2_OTG_GSL_CONTROL_BASE_IDX 2
6872 #define mmOTG2_OTG_GSL_WINDOW_X 0x1c8f
6873 #define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2
6874 #define mmOTG2_OTG_GSL_WINDOW_Y 0x1c90
6875 #define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2
6876 #define mmOTG2_OTG_VUPDATE_KEEPOUT 0x1c91
6877 #define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
6878 #define mmOTG2_OTG_GLOBAL_CONTROL0 0x1c92
6879 #define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2
6880 #define mmOTG2_OTG_GLOBAL_CONTROL1 0x1c93
6881 #define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2
6882 #define mmOTG2_OTG_GLOBAL_CONTROL2 0x1c94
6883 #define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2
6884 #define mmOTG2_OTG_GLOBAL_CONTROL3 0x1c95
6885 #define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2
6886 #define mmOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c96
6887 #define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
6888 #define mmOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c97
6889 #define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
6890 #define mmOTG2_OTG_RANGE_TIMING_INT_STATUS 0x1c98
6891 #define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
6892 #define mmOTG2_OTG_DRR_CONTROL 0x1c99
6893 #define mmOTG2_OTG_DRR_CONTROL_BASE_IDX 2
6894 #define mmOTG2_OTG_REQUEST_CONTROL 0x1c9a
6895 #define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2
6896 #define mmOTG2_OTG_SPARE_REGISTER 0x1c9b
6897 #define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX 2
6900 // addressBlock: dce_dc_optc_otg3_dispdec
6901 // base address: 0x600
6902 #define mmOTG3_OTG_H_TOTAL 0x1caa
6903 #define mmOTG3_OTG_H_TOTAL_BASE_IDX 2
6904 #define mmOTG3_OTG_H_BLANK_START_END 0x1cab
6905 #define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX 2
6906 #define mmOTG3_OTG_H_SYNC_A 0x1cac
6907 #define mmOTG3_OTG_H_SYNC_A_BASE_IDX 2
6908 #define mmOTG3_OTG_H_SYNC_A_CNTL 0x1cad
6909 #define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2
6910 #define mmOTG3_OTG_H_TIMING_CNTL 0x1cae
6911 #define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2
6912 #define mmOTG3_OTG_V_TOTAL 0x1caf
6913 #define mmOTG3_OTG_V_TOTAL_BASE_IDX 2
6914 #define mmOTG3_OTG_V_TOTAL_MIN 0x1cb0
6915 #define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2
6916 #define mmOTG3_OTG_V_TOTAL_MAX 0x1cb1
6917 #define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2
6918 #define mmOTG3_OTG_V_TOTAL_MID 0x1cb2
6919 #define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX 2
6920 #define mmOTG3_OTG_V_TOTAL_CONTROL 0x1cb3
6921 #define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2
6922 #define mmOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4
6923 #define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
6924 #define mmOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5
6925 #define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
6926 #define mmOTG3_OTG_V_BLANK_START_END 0x1cb6
6927 #define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX 2
6928 #define mmOTG3_OTG_V_SYNC_A 0x1cb7
6929 #define mmOTG3_OTG_V_SYNC_A_BASE_IDX 2
6930 #define mmOTG3_OTG_V_SYNC_A_CNTL 0x1cb8
6931 #define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2
6932 #define mmOTG3_OTG_TRIGA_CNTL 0x1cb9
6933 #define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX 2
6934 #define mmOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba
6935 #define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
6936 #define mmOTG3_OTG_TRIGB_CNTL 0x1cbb
6937 #define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX 2
6938 #define mmOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc
6939 #define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
6940 #define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd
6941 #define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
6942 #define mmOTG3_OTG_FLOW_CONTROL 0x1cbe
6943 #define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX 2
6944 #define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf
6945 #define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
6946 #define mmOTG3_OTG_AVSYNC_COUNTER 0x1cc0
6947 #define mmOTG3_OTG_AVSYNC_COUNTER_BASE_IDX 2
6948 #define mmOTG3_OTG_CONTROL 0x1cc1
6949 #define mmOTG3_OTG_CONTROL_BASE_IDX 2
6950 #define mmOTG3_OTG_BLANK_CONTROL 0x1cc2
6951 #define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX 2
6952 #define mmOTG3_OTG_PIPE_ABORT_CONTROL 0x1cc3
6953 #define mmOTG3_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
6954 #define mmOTG3_OTG_INTERLACE_CONTROL 0x1cc4
6955 #define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2
6956 #define mmOTG3_OTG_INTERLACE_STATUS 0x1cc5
6957 #define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2
6958 #define mmOTG3_OTG_FIELD_INDICATION_CONTROL 0x1cc6
6959 #define mmOTG3_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
6960 #define mmOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7
6961 #define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
6962 #define mmOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8
6963 #define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
6964 #define mmOTG3_OTG_STATUS 0x1cc9
6965 #define mmOTG3_OTG_STATUS_BASE_IDX 2
6966 #define mmOTG3_OTG_STATUS_POSITION 0x1cca
6967 #define mmOTG3_OTG_STATUS_POSITION_BASE_IDX 2
6968 #define mmOTG3_OTG_NOM_VERT_POSITION 0x1ccb
6969 #define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2
6970 #define mmOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc
6971 #define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
6972 #define mmOTG3_OTG_STATUS_VF_COUNT 0x1ccd
6973 #define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2
6974 #define mmOTG3_OTG_STATUS_HV_COUNT 0x1cce
6975 #define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2
6976 #define mmOTG3_OTG_COUNT_CONTROL 0x1ccf
6977 #define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX 2
6978 #define mmOTG3_OTG_COUNT_RESET 0x1cd0
6979 #define mmOTG3_OTG_COUNT_RESET_BASE_IDX 2
6980 #define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1
6981 #define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
6982 #define mmOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2
6983 #define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
6984 #define mmOTG3_OTG_STEREO_STATUS 0x1cd3
6985 #define mmOTG3_OTG_STEREO_STATUS_BASE_IDX 2
6986 #define mmOTG3_OTG_STEREO_CONTROL 0x1cd4
6987 #define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX 2
6988 #define mmOTG3_OTG_SNAPSHOT_STATUS 0x1cd5
6989 #define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2
6990 #define mmOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6
6991 #define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
6992 #define mmOTG3_OTG_SNAPSHOT_POSITION 0x1cd7
6993 #define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2
6994 #define mmOTG3_OTG_SNAPSHOT_FRAME 0x1cd8
6995 #define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2
6996 #define mmOTG3_OTG_INTERRUPT_CONTROL 0x1cd9
6997 #define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2
6998 #define mmOTG3_OTG_UPDATE_LOCK 0x1cda
6999 #define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX 2
7000 #define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb
7001 #define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
7002 #define mmOTG3_OTG_TEST_PATTERN_CONTROL 0x1cdc
7003 #define mmOTG3_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
7004 #define mmOTG3_OTG_TEST_PATTERN_PARAMETERS 0x1cdd
7005 #define mmOTG3_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
7006 #define mmOTG3_OTG_TEST_PATTERN_COLOR 0x1cde
7007 #define mmOTG3_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
7008 #define mmOTG3_OTG_MASTER_EN 0x1cdf
7009 #define mmOTG3_OTG_MASTER_EN_BASE_IDX 2
7010 #define mmOTG3_OTG_BLANK_DATA_COLOR 0x1ce1
7011 #define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX 2
7012 #define mmOTG3_OTG_BLANK_DATA_COLOR_EXT 0x1ce2
7013 #define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
7014 #define mmOTG3_OTG_BLACK_COLOR 0x1ce3
7015 #define mmOTG3_OTG_BLACK_COLOR_BASE_IDX 2
7016 #define mmOTG3_OTG_BLACK_COLOR_EXT 0x1ce4
7017 #define mmOTG3_OTG_BLACK_COLOR_EXT_BASE_IDX 2
7018 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce5
7019 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
7020 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce6
7021 #define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
7022 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce7
7023 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
7024 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce8
7025 #define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
7026 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce9
7027 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
7028 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1cea
7029 #define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
7030 #define mmOTG3_OTG_CRC_CNTL 0x1ceb
7031 #define mmOTG3_OTG_CRC_CNTL_BASE_IDX 2
7032 #define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cec
7033 #define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
7034 #define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ced
7035 #define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
7036 #define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cee
7037 #define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
7038 #define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1cef
7039 #define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
7040 #define mmOTG3_OTG_CRC0_DATA_RG 0x1cf0
7041 #define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2
7042 #define mmOTG3_OTG_CRC0_DATA_B 0x1cf1
7043 #define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX 2
7044 #define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf2
7045 #define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
7046 #define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf3
7047 #define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
7048 #define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf4
7049 #define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
7050 #define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf5
7051 #define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
7052 #define mmOTG3_OTG_CRC1_DATA_RG 0x1cf6
7053 #define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2
7054 #define mmOTG3_OTG_CRC1_DATA_B 0x1cf7
7055 #define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX 2
7056 #define mmOTG3_OTG_CRC2_DATA_RG 0x1cf8
7057 #define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2
7058 #define mmOTG3_OTG_CRC2_DATA_B 0x1cf9
7059 #define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX 2
7060 #define mmOTG3_OTG_CRC3_DATA_RG 0x1cfa
7061 #define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2
7062 #define mmOTG3_OTG_CRC3_DATA_B 0x1cfb
7063 #define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX 2
7064 #define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfc
7065 #define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
7066 #define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfd
7067 #define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
7068 #define mmOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d04
7069 #define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
7070 #define mmOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d05
7071 #define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
7072 #define mmOTG3_OTG_GSL_VSYNC_GAP 0x1d06
7073 #define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2
7074 #define mmOTG3_OTG_MASTER_UPDATE_MODE 0x1d07
7075 #define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
7076 #define mmOTG3_OTG_CLOCK_CONTROL 0x1d08
7077 #define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2
7078 #define mmOTG3_OTG_VSTARTUP_PARAM 0x1d09
7079 #define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2
7080 #define mmOTG3_OTG_VUPDATE_PARAM 0x1d0a
7081 #define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2
7082 #define mmOTG3_OTG_VREADY_PARAM 0x1d0b
7083 #define mmOTG3_OTG_VREADY_PARAM_BASE_IDX 2
7084 #define mmOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0c
7085 #define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
7086 #define mmOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0d
7087 #define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
7088 #define mmOTG3_OTG_GSL_CONTROL 0x1d0e
7089 #define mmOTG3_OTG_GSL_CONTROL_BASE_IDX 2
7090 #define mmOTG3_OTG_GSL_WINDOW_X 0x1d0f
7091 #define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2
7092 #define mmOTG3_OTG_GSL_WINDOW_Y 0x1d10
7093 #define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2
7094 #define mmOTG3_OTG_VUPDATE_KEEPOUT 0x1d11
7095 #define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
7096 #define mmOTG3_OTG_GLOBAL_CONTROL0 0x1d12
7097 #define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2
7098 #define mmOTG3_OTG_GLOBAL_CONTROL1 0x1d13
7099 #define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2
7100 #define mmOTG3_OTG_GLOBAL_CONTROL2 0x1d14
7101 #define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2
7102 #define mmOTG3_OTG_GLOBAL_CONTROL3 0x1d15
7103 #define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2
7104 #define mmOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d16
7105 #define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
7106 #define mmOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d17
7107 #define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
7108 #define mmOTG3_OTG_RANGE_TIMING_INT_STATUS 0x1d18
7109 #define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
7110 #define mmOTG3_OTG_DRR_CONTROL 0x1d19
7111 #define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2
7112 #define mmOTG3_OTG_REQUEST_CONTROL 0x1d1a
7113 #define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2
7114 #define mmOTG3_OTG_SPARE_REGISTER 0x1d1b
7115 #define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX 2
7118 // addressBlock: dce_dc_optc_otg4_dispdec
7119 // base address: 0x800
7120 #define mmOTG4_OTG_H_TOTAL 0x1d2a
7121 #define mmOTG4_OTG_H_TOTAL_BASE_IDX 2
7122 #define mmOTG4_OTG_H_BLANK_START_END 0x1d2b
7123 #define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX 2
7124 #define mmOTG4_OTG_H_SYNC_A 0x1d2c
7125 #define mmOTG4_OTG_H_SYNC_A_BASE_IDX 2
7126 #define mmOTG4_OTG_H_SYNC_A_CNTL 0x1d2d
7127 #define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX 2
7128 #define mmOTG4_OTG_H_TIMING_CNTL 0x1d2e
7129 #define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX 2
7130 #define mmOTG4_OTG_V_TOTAL 0x1d2f
7131 #define mmOTG4_OTG_V_TOTAL_BASE_IDX 2
7132 #define mmOTG4_OTG_V_TOTAL_MIN 0x1d30
7133 #define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX 2
7134 #define mmOTG4_OTG_V_TOTAL_MAX 0x1d31
7135 #define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX 2
7136 #define mmOTG4_OTG_V_TOTAL_MID 0x1d32
7137 #define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX 2
7138 #define mmOTG4_OTG_V_TOTAL_CONTROL 0x1d33
7139 #define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX 2
7140 #define mmOTG4_OTG_V_TOTAL_INT_STATUS 0x1d34
7141 #define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
7142 #define mmOTG4_OTG_VSYNC_NOM_INT_STATUS 0x1d35
7143 #define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
7144 #define mmOTG4_OTG_V_BLANK_START_END 0x1d36
7145 #define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX 2
7146 #define mmOTG4_OTG_V_SYNC_A 0x1d37
7147 #define mmOTG4_OTG_V_SYNC_A_BASE_IDX 2
7148 #define mmOTG4_OTG_V_SYNC_A_CNTL 0x1d38
7149 #define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX 2
7150 #define mmOTG4_OTG_TRIGA_CNTL 0x1d39
7151 #define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX 2
7152 #define mmOTG4_OTG_TRIGA_MANUAL_TRIG 0x1d3a
7153 #define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
7154 #define mmOTG4_OTG_TRIGB_CNTL 0x1d3b
7155 #define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX 2
7156 #define mmOTG4_OTG_TRIGB_MANUAL_TRIG 0x1d3c
7157 #define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
7158 #define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL 0x1d3d
7159 #define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
7160 #define mmOTG4_OTG_FLOW_CONTROL 0x1d3e
7161 #define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX 2
7162 #define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE 0x1d3f
7163 #define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
7164 #define mmOTG4_OTG_AVSYNC_COUNTER 0x1d40
7165 #define mmOTG4_OTG_AVSYNC_COUNTER_BASE_IDX 2
7166 #define mmOTG4_OTG_CONTROL 0x1d41
7167 #define mmOTG4_OTG_CONTROL_BASE_IDX 2
7168 #define mmOTG4_OTG_BLANK_CONTROL 0x1d42
7169 #define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX 2
7170 #define mmOTG4_OTG_PIPE_ABORT_CONTROL 0x1d43
7171 #define mmOTG4_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
7172 #define mmOTG4_OTG_INTERLACE_CONTROL 0x1d44
7173 #define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX 2
7174 #define mmOTG4_OTG_INTERLACE_STATUS 0x1d45
7175 #define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX 2
7176 #define mmOTG4_OTG_FIELD_INDICATION_CONTROL 0x1d46
7177 #define mmOTG4_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
7178 #define mmOTG4_OTG_PIXEL_DATA_READBACK0 0x1d47
7179 #define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
7180 #define mmOTG4_OTG_PIXEL_DATA_READBACK1 0x1d48
7181 #define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
7182 #define mmOTG4_OTG_STATUS 0x1d49
7183 #define mmOTG4_OTG_STATUS_BASE_IDX 2
7184 #define mmOTG4_OTG_STATUS_POSITION 0x1d4a
7185 #define mmOTG4_OTG_STATUS_POSITION_BASE_IDX 2
7186 #define mmOTG4_OTG_NOM_VERT_POSITION 0x1d4b
7187 #define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX 2
7188 #define mmOTG4_OTG_STATUS_FRAME_COUNT 0x1d4c
7189 #define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
7190 #define mmOTG4_OTG_STATUS_VF_COUNT 0x1d4d
7191 #define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX 2
7192 #define mmOTG4_OTG_STATUS_HV_COUNT 0x1d4e
7193 #define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX 2
7194 #define mmOTG4_OTG_COUNT_CONTROL 0x1d4f
7195 #define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2
7196 #define mmOTG4_OTG_COUNT_RESET 0x1d50
7197 #define mmOTG4_OTG_COUNT_RESET_BASE_IDX 2
7198 #define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1d51
7199 #define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
7200 #define mmOTG4_OTG_VERT_SYNC_CONTROL 0x1d52
7201 #define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
7202 #define mmOTG4_OTG_STEREO_STATUS 0x1d53
7203 #define mmOTG4_OTG_STEREO_STATUS_BASE_IDX 2
7204 #define mmOTG4_OTG_STEREO_CONTROL 0x1d54
7205 #define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX 2
7206 #define mmOTG4_OTG_SNAPSHOT_STATUS 0x1d55
7207 #define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX 2
7208 #define mmOTG4_OTG_SNAPSHOT_CONTROL 0x1d56
7209 #define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
7210 #define mmOTG4_OTG_SNAPSHOT_POSITION 0x1d57
7211 #define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX 2
7212 #define mmOTG4_OTG_SNAPSHOT_FRAME 0x1d58
7213 #define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX 2
7214 #define mmOTG4_OTG_INTERRUPT_CONTROL 0x1d59
7215 #define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX 2
7216 #define mmOTG4_OTG_UPDATE_LOCK 0x1d5a
7217 #define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX 2
7218 #define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL 0x1d5b
7219 #define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
7220 #define mmOTG4_OTG_TEST_PATTERN_CONTROL 0x1d5c
7221 #define mmOTG4_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
7222 #define mmOTG4_OTG_TEST_PATTERN_PARAMETERS 0x1d5d
7223 #define mmOTG4_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
7224 #define mmOTG4_OTG_TEST_PATTERN_COLOR 0x1d5e
7225 #define mmOTG4_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
7226 #define mmOTG4_OTG_MASTER_EN 0x1d5f
7227 #define mmOTG4_OTG_MASTER_EN_BASE_IDX 2
7228 #define mmOTG4_OTG_BLANK_DATA_COLOR 0x1d61
7229 #define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX 2
7230 #define mmOTG4_OTG_BLANK_DATA_COLOR_EXT 0x1d62
7231 #define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
7232 #define mmOTG4_OTG_BLACK_COLOR 0x1d63
7233 #define mmOTG4_OTG_BLACK_COLOR_BASE_IDX 2
7234 #define mmOTG4_OTG_BLACK_COLOR_EXT 0x1d64
7235 #define mmOTG4_OTG_BLACK_COLOR_EXT_BASE_IDX 2
7236 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION 0x1d65
7237 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
7238 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1d66
7239 #define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
7240 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION 0x1d67
7241 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
7242 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1d68
7243 #define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
7244 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION 0x1d69
7245 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
7246 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1d6a
7247 #define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
7248 #define mmOTG4_OTG_CRC_CNTL 0x1d6b
7249 #define mmOTG4_OTG_CRC_CNTL_BASE_IDX 2
7250 #define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL 0x1d6c
7251 #define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
7252 #define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d6d
7253 #define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
7254 #define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL 0x1d6e
7255 #define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
7256 #define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d6f
7257 #define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
7258 #define mmOTG4_OTG_CRC0_DATA_RG 0x1d70
7259 #define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX 2
7260 #define mmOTG4_OTG_CRC0_DATA_B 0x1d71
7261 #define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX 2
7262 #define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL 0x1d72
7263 #define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
7264 #define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d73
7265 #define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
7266 #define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL 0x1d74
7267 #define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
7268 #define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d75
7269 #define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
7270 #define mmOTG4_OTG_CRC1_DATA_RG 0x1d76
7271 #define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX 2
7272 #define mmOTG4_OTG_CRC1_DATA_B 0x1d77
7273 #define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX 2
7274 #define mmOTG4_OTG_CRC2_DATA_RG 0x1d78
7275 #define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX 2
7276 #define mmOTG4_OTG_CRC2_DATA_B 0x1d79
7277 #define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX 2
7278 #define mmOTG4_OTG_CRC3_DATA_RG 0x1d7a
7279 #define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX 2
7280 #define mmOTG4_OTG_CRC3_DATA_B 0x1d7b
7281 #define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX 2
7282 #define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK 0x1d7c
7283 #define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
7284 #define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d7d
7285 #define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
7286 #define mmOTG4_OTG_STATIC_SCREEN_CONTROL 0x1d84
7287 #define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
7288 #define mmOTG4_OTG_3D_STRUCTURE_CONTROL 0x1d85
7289 #define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
7290 #define mmOTG4_OTG_GSL_VSYNC_GAP 0x1d86
7291 #define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX 2
7292 #define mmOTG4_OTG_MASTER_UPDATE_MODE 0x1d87
7293 #define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
7294 #define mmOTG4_OTG_CLOCK_CONTROL 0x1d88
7295 #define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX 2
7296 #define mmOTG4_OTG_VSTARTUP_PARAM 0x1d89
7297 #define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX 2
7298 #define mmOTG4_OTG_VUPDATE_PARAM 0x1d8a
7299 #define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX 2
7300 #define mmOTG4_OTG_VREADY_PARAM 0x1d8b
7301 #define mmOTG4_OTG_VREADY_PARAM_BASE_IDX 2
7302 #define mmOTG4_OTG_GLOBAL_SYNC_STATUS 0x1d8c
7303 #define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
7304 #define mmOTG4_OTG_MASTER_UPDATE_LOCK 0x1d8d
7305 #define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
7306 #define mmOTG4_OTG_GSL_CONTROL 0x1d8e
7307 #define mmOTG4_OTG_GSL_CONTROL_BASE_IDX 2
7308 #define mmOTG4_OTG_GSL_WINDOW_X 0x1d8f
7309 #define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX 2
7310 #define mmOTG4_OTG_GSL_WINDOW_Y 0x1d90
7311 #define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX 2
7312 #define mmOTG4_OTG_VUPDATE_KEEPOUT 0x1d91
7313 #define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
7314 #define mmOTG4_OTG_GLOBAL_CONTROL0 0x1d92
7315 #define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX 2
7316 #define mmOTG4_OTG_GLOBAL_CONTROL1 0x1d93
7317 #define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX 2
7318 #define mmOTG4_OTG_GLOBAL_CONTROL2 0x1d94
7319 #define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX 2
7320 #define mmOTG4_OTG_GLOBAL_CONTROL3 0x1d95
7321 #define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX 2
7322 #define mmOTG4_OTG_TRIG_MANUAL_CONTROL 0x1d96
7323 #define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
7324 #define mmOTG4_OTG_MANUAL_FLOW_CONTROL 0x1d97
7325 #define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
7326 #define mmOTG4_OTG_RANGE_TIMING_INT_STATUS 0x1d98
7327 #define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
7328 #define mmOTG4_OTG_DRR_CONTROL 0x1d99
7329 #define mmOTG4_OTG_DRR_CONTROL_BASE_IDX 2
7330 #define mmOTG4_OTG_REQUEST_CONTROL 0x1d9a
7331 #define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX 2
7332 #define mmOTG4_OTG_SPARE_REGISTER 0x1d9b
7333 #define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX 2
7336 // addressBlock: dce_dc_optc_otg5_dispdec
7337 // base address: 0xa00
7338 #define mmOTG5_OTG_H_TOTAL 0x1daa
7339 #define mmOTG5_OTG_H_TOTAL_BASE_IDX 2
7340 #define mmOTG5_OTG_H_BLANK_START_END 0x1dab
7341 #define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX 2
7342 #define mmOTG5_OTG_H_SYNC_A 0x1dac
7343 #define mmOTG5_OTG_H_SYNC_A_BASE_IDX 2
7344 #define mmOTG5_OTG_H_SYNC_A_CNTL 0x1dad
7345 #define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX 2
7346 #define mmOTG5_OTG_H_TIMING_CNTL 0x1dae
7347 #define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 2
7348 #define mmOTG5_OTG_V_TOTAL 0x1daf
7349 #define mmOTG5_OTG_V_TOTAL_BASE_IDX 2
7350 #define mmOTG5_OTG_V_TOTAL_MIN 0x1db0
7351 #define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX 2
7352 #define mmOTG5_OTG_V_TOTAL_MAX 0x1db1
7353 #define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX 2
7354 #define mmOTG5_OTG_V_TOTAL_MID 0x1db2
7355 #define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX 2
7356 #define mmOTG5_OTG_V_TOTAL_CONTROL 0x1db3
7357 #define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX 2
7358 #define mmOTG5_OTG_V_TOTAL_INT_STATUS 0x1db4
7359 #define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
7360 #define mmOTG5_OTG_VSYNC_NOM_INT_STATUS 0x1db5
7361 #define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
7362 #define mmOTG5_OTG_V_BLANK_START_END 0x1db6
7363 #define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX 2
7364 #define mmOTG5_OTG_V_SYNC_A 0x1db7
7365 #define mmOTG5_OTG_V_SYNC_A_BASE_IDX 2
7366 #define mmOTG5_OTG_V_SYNC_A_CNTL 0x1db8
7367 #define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX 2
7368 #define mmOTG5_OTG_TRIGA_CNTL 0x1db9
7369 #define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX 2
7370 #define mmOTG5_OTG_TRIGA_MANUAL_TRIG 0x1dba
7371 #define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
7372 #define mmOTG5_OTG_TRIGB_CNTL 0x1dbb
7373 #define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX 2
7374 #define mmOTG5_OTG_TRIGB_MANUAL_TRIG 0x1dbc
7375 #define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
7376 #define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL 0x1dbd
7377 #define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
7378 #define mmOTG5_OTG_FLOW_CONTROL 0x1dbe
7379 #define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX 2
7380 #define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE 0x1dbf
7381 #define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
7382 #define mmOTG5_OTG_AVSYNC_COUNTER 0x1dc0
7383 #define mmOTG5_OTG_AVSYNC_COUNTER_BASE_IDX 2
7384 #define mmOTG5_OTG_CONTROL 0x1dc1
7385 #define mmOTG5_OTG_CONTROL_BASE_IDX 2
7386 #define mmOTG5_OTG_BLANK_CONTROL 0x1dc2
7387 #define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX 2
7388 #define mmOTG5_OTG_PIPE_ABORT_CONTROL 0x1dc3
7389 #define mmOTG5_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
7390 #define mmOTG5_OTG_INTERLACE_CONTROL 0x1dc4
7391 #define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX 2
7392 #define mmOTG5_OTG_INTERLACE_STATUS 0x1dc5
7393 #define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX 2
7394 #define mmOTG5_OTG_FIELD_INDICATION_CONTROL 0x1dc6
7395 #define mmOTG5_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
7396 #define mmOTG5_OTG_PIXEL_DATA_READBACK0 0x1dc7
7397 #define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
7398 #define mmOTG5_OTG_PIXEL_DATA_READBACK1 0x1dc8
7399 #define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
7400 #define mmOTG5_OTG_STATUS 0x1dc9
7401 #define mmOTG5_OTG_STATUS_BASE_IDX 2
7402 #define mmOTG5_OTG_STATUS_POSITION 0x1dca
7403 #define mmOTG5_OTG_STATUS_POSITION_BASE_IDX 2
7404 #define mmOTG5_OTG_NOM_VERT_POSITION 0x1dcb
7405 #define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX 2
7406 #define mmOTG5_OTG_STATUS_FRAME_COUNT 0x1dcc
7407 #define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
7408 #define mmOTG5_OTG_STATUS_VF_COUNT 0x1dcd
7409 #define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 2
7410 #define mmOTG5_OTG_STATUS_HV_COUNT 0x1dce
7411 #define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX 2
7412 #define mmOTG5_OTG_COUNT_CONTROL 0x1dcf
7413 #define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2
7414 #define mmOTG5_OTG_COUNT_RESET 0x1dd0
7415 #define mmOTG5_OTG_COUNT_RESET_BASE_IDX 2
7416 #define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dd1
7417 #define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
7418 #define mmOTG5_OTG_VERT_SYNC_CONTROL 0x1dd2
7419 #define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
7420 #define mmOTG5_OTG_STEREO_STATUS 0x1dd3
7421 #define mmOTG5_OTG_STEREO_STATUS_BASE_IDX 2
7422 #define mmOTG5_OTG_STEREO_CONTROL 0x1dd4
7423 #define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX 2
7424 #define mmOTG5_OTG_SNAPSHOT_STATUS 0x1dd5
7425 #define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX 2
7426 #define mmOTG5_OTG_SNAPSHOT_CONTROL 0x1dd6
7427 #define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
7428 #define mmOTG5_OTG_SNAPSHOT_POSITION 0x1dd7
7429 #define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX 2
7430 #define mmOTG5_OTG_SNAPSHOT_FRAME 0x1dd8
7431 #define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX 2
7432 #define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9
7433 #define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX 2
7434 #define mmOTG5_OTG_UPDATE_LOCK 0x1dda
7435 #define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX 2
7436 #define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL 0x1ddb
7437 #define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
7438 #define mmOTG5_OTG_TEST_PATTERN_CONTROL 0x1ddc
7439 #define mmOTG5_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
7440 #define mmOTG5_OTG_TEST_PATTERN_PARAMETERS 0x1ddd
7441 #define mmOTG5_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
7442 #define mmOTG5_OTG_TEST_PATTERN_COLOR 0x1dde
7443 #define mmOTG5_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
7444 #define mmOTG5_OTG_MASTER_EN 0x1ddf
7445 #define mmOTG5_OTG_MASTER_EN_BASE_IDX 2
7446 #define mmOTG5_OTG_BLANK_DATA_COLOR 0x1de1
7447 #define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX 2
7448 #define mmOTG5_OTG_BLANK_DATA_COLOR_EXT 0x1de2
7449 #define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
7450 #define mmOTG5_OTG_BLACK_COLOR 0x1de3
7451 #define mmOTG5_OTG_BLACK_COLOR_BASE_IDX 2
7452 #define mmOTG5_OTG_BLACK_COLOR_EXT 0x1de4
7453 #define mmOTG5_OTG_BLACK_COLOR_EXT_BASE_IDX 2
7454 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION 0x1de5
7455 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
7456 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1de6
7457 #define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
7458 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION 0x1de7
7459 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
7460 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1de8
7461 #define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
7462 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION 0x1de9
7463 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
7464 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1dea
7465 #define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
7466 #define mmOTG5_OTG_CRC_CNTL 0x1deb
7467 #define mmOTG5_OTG_CRC_CNTL_BASE_IDX 2
7468 #define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL 0x1dec
7469 #define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
7470 #define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ded
7471 #define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
7472 #define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL 0x1dee
7473 #define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
7474 #define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL 0x1def
7475 #define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
7476 #define mmOTG5_OTG_CRC0_DATA_RG 0x1df0
7477 #define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX 2
7478 #define mmOTG5_OTG_CRC0_DATA_B 0x1df1
7479 #define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX 2
7480 #define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL 0x1df2
7481 #define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
7482 #define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL 0x1df3
7483 #define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
7484 #define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL 0x1df4
7485 #define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
7486 #define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL 0x1df5
7487 #define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
7488 #define mmOTG5_OTG_CRC1_DATA_RG 0x1df6
7489 #define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX 2
7490 #define mmOTG5_OTG_CRC1_DATA_B 0x1df7
7491 #define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX 2
7492 #define mmOTG5_OTG_CRC2_DATA_RG 0x1df8
7493 #define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX 2
7494 #define mmOTG5_OTG_CRC2_DATA_B 0x1df9
7495 #define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX 2
7496 #define mmOTG5_OTG_CRC3_DATA_RG 0x1dfa
7497 #define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX 2
7498 #define mmOTG5_OTG_CRC3_DATA_B 0x1dfb
7499 #define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX 2
7500 #define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK 0x1dfc
7501 #define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
7502 #define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1dfd
7503 #define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
7504 #define mmOTG5_OTG_STATIC_SCREEN_CONTROL 0x1e04
7505 #define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
7506 #define mmOTG5_OTG_3D_STRUCTURE_CONTROL 0x1e05
7507 #define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
7508 #define mmOTG5_OTG_GSL_VSYNC_GAP 0x1e06
7509 #define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX 2
7510 #define mmOTG5_OTG_MASTER_UPDATE_MODE 0x1e07
7511 #define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
7512 #define mmOTG5_OTG_CLOCK_CONTROL 0x1e08
7513 #define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX 2
7514 #define mmOTG5_OTG_VSTARTUP_PARAM 0x1e09
7515 #define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX 2
7516 #define mmOTG5_OTG_VUPDATE_PARAM 0x1e0a
7517 #define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX 2
7518 #define mmOTG5_OTG_VREADY_PARAM 0x1e0b
7519 #define mmOTG5_OTG_VREADY_PARAM_BASE_IDX 2
7520 #define mmOTG5_OTG_GLOBAL_SYNC_STATUS 0x1e0c
7521 #define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
7522 #define mmOTG5_OTG_MASTER_UPDATE_LOCK 0x1e0d
7523 #define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
7524 #define mmOTG5_OTG_GSL_CONTROL 0x1e0e
7525 #define mmOTG5_OTG_GSL_CONTROL_BASE_IDX 2
7526 #define mmOTG5_OTG_GSL_WINDOW_X 0x1e0f
7527 #define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX 2
7528 #define mmOTG5_OTG_GSL_WINDOW_Y 0x1e10
7529 #define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX 2
7530 #define mmOTG5_OTG_VUPDATE_KEEPOUT 0x1e11
7531 #define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
7532 #define mmOTG5_OTG_GLOBAL_CONTROL0 0x1e12
7533 #define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX 2
7534 #define mmOTG5_OTG_GLOBAL_CONTROL1 0x1e13
7535 #define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX 2
7536 #define mmOTG5_OTG_GLOBAL_CONTROL2 0x1e14
7537 #define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX 2
7538 #define mmOTG5_OTG_GLOBAL_CONTROL3 0x1e15
7539 #define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX 2
7540 #define mmOTG5_OTG_TRIG_MANUAL_CONTROL 0x1e16
7541 #define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
7542 #define mmOTG5_OTG_MANUAL_FLOW_CONTROL 0x1e17
7543 #define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
7544 #define mmOTG5_OTG_RANGE_TIMING_INT_STATUS 0x1e18
7545 #define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
7546 #define mmOTG5_OTG_DRR_CONTROL 0x1e19
7547 #define mmOTG5_OTG_DRR_CONTROL_BASE_IDX 2
7548 #define mmOTG5_OTG_REQUEST_CONTROL 0x1e1a
7549 #define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX 2
7550 #define mmOTG5_OTG_SPARE_REGISTER 0x1e1b
7551 #define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX 2
7554 // addressBlock: dce_dc_optc_optc_misc_dispdec
7555 // base address: 0x0
7556 #define mmDWB_SOURCE_SELECT 0x1e2a
7557 #define mmDWB_SOURCE_SELECT_BASE_IDX 2
7558 #define mmGSL_SOURCE_SELECT 0x1e2b
7559 #define mmGSL_SOURCE_SELECT_BASE_IDX 2
7560 #define mmOPTC_CLOCK_CONTROL 0x1e2c
7561 #define mmOPTC_CLOCK_CONTROL_BASE_IDX 2
7562 #define mmOPTC_MISC_SPARE_REGISTER 0x1e2d
7563 #define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2
7566 // addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
7567 // base address: 0x79a8
7568 #define mmDC_PERFMON18_PERFCOUNTER_CNTL 0x1e6a
7569 #define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2
7570 #define mmDC_PERFMON18_PERFCOUNTER_CNTL2 0x1e6b
7571 #define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2
7572 #define mmDC_PERFMON18_PERFCOUNTER_STATE 0x1e6c
7573 #define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2
7574 #define mmDC_PERFMON18_PERFMON_CNTL 0x1e6d
7575 #define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2
7576 #define mmDC_PERFMON18_PERFMON_CNTL2 0x1e6e
7577 #define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2
7578 #define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1e6f
7579 #define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
7580 #define mmDC_PERFMON18_PERFMON_CVALUE_LOW 0x1e70
7581 #define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2
7582 #define mmDC_PERFMON18_PERFMON_HI 0x1e71
7583 #define mmDC_PERFMON18_PERFMON_HI_BASE_IDX 2
7584 #define mmDC_PERFMON18_PERFMON_LOW 0x1e72
7585 #define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX 2
7588 // addressBlock: dce_dc_dio_dac_dispdec
7589 // base address: 0x0
7590 #define mmDAC_ENABLE 0x1e76
7591 #define mmDAC_ENABLE_BASE_IDX 2
7592 #define mmDAC_SOURCE_SELECT 0x1e77
7593 #define mmDAC_SOURCE_SELECT_BASE_IDX 2
7594 #define mmDAC_CRC_EN 0x1e78
7595 #define mmDAC_CRC_EN_BASE_IDX 2
7596 #define mmDAC_CRC_CONTROL 0x1e79
7597 #define mmDAC_CRC_CONTROL_BASE_IDX 2
7598 #define mmDAC_CRC_SIG_RGB_MASK 0x1e7a
7599 #define mmDAC_CRC_SIG_RGB_MASK_BASE_IDX 2
7600 #define mmDAC_CRC_SIG_CONTROL_MASK 0x1e7b
7601 #define mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX 2
7602 #define mmDAC_CRC_SIG_RGB 0x1e7c
7603 #define mmDAC_CRC_SIG_RGB_BASE_IDX 2
7604 #define mmDAC_CRC_SIG_CONTROL 0x1e7d
7605 #define mmDAC_CRC_SIG_CONTROL_BASE_IDX 2
7606 #define mmDAC_SYNC_TRISTATE_CONTROL 0x1e7e
7607 #define mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX 2
7608 #define mmDAC_STEREOSYNC_SELECT 0x1e7f
7609 #define mmDAC_STEREOSYNC_SELECT_BASE_IDX 2
7610 #define mmDAC_AUTODETECT_CONTROL 0x1e80
7611 #define mmDAC_AUTODETECT_CONTROL_BASE_IDX 2
7612 #define mmDAC_AUTODETECT_CONTROL2 0x1e81
7613 #define mmDAC_AUTODETECT_CONTROL2_BASE_IDX 2
7614 #define mmDAC_AUTODETECT_CONTROL3 0x1e82
7615 #define mmDAC_AUTODETECT_CONTROL3_BASE_IDX 2
7616 #define mmDAC_AUTODETECT_STATUS 0x1e83
7617 #define mmDAC_AUTODETECT_STATUS_BASE_IDX 2
7618 #define mmDAC_AUTODETECT_INT_CONTROL 0x1e84
7619 #define mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX 2
7620 #define mmDAC_FORCE_OUTPUT_CNTL 0x1e85
7621 #define mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX 2
7622 #define mmDAC_FORCE_DATA 0x1e86
7623 #define mmDAC_FORCE_DATA_BASE_IDX 2
7624 #define mmDAC_POWERDOWN 0x1e87
7625 #define mmDAC_POWERDOWN_BASE_IDX 2
7626 #define mmDAC_CONTROL 0x1e88
7627 #define mmDAC_CONTROL_BASE_IDX 2
7628 #define mmDAC_COMPARATOR_ENABLE 0x1e89
7629 #define mmDAC_COMPARATOR_ENABLE_BASE_IDX 2
7630 #define mmDAC_COMPARATOR_OUTPUT 0x1e8a
7631 #define mmDAC_COMPARATOR_OUTPUT_BASE_IDX 2
7632 #define mmDAC_PWR_CNTL 0x1e8b
7633 #define mmDAC_PWR_CNTL_BASE_IDX 2
7634 #define mmDAC_DFT_CONFIG 0x1e8c
7635 #define mmDAC_DFT_CONFIG_BASE_IDX 2
7636 #define mmDAC_FIFO_STATUS 0x1e8d
7637 #define mmDAC_FIFO_STATUS_BASE_IDX 2
7640 // addressBlock: dce_dc_dio_dout_i2c_dispdec
7641 // base address: 0x0
7642 #define mmDC_I2C_CONTROL 0x1e98
7643 #define mmDC_I2C_CONTROL_BASE_IDX 2
7644 #define mmDC_I2C_ARBITRATION 0x1e99
7645 #define mmDC_I2C_ARBITRATION_BASE_IDX 2
7646 #define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a
7647 #define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
7648 #define mmDC_I2C_SW_STATUS 0x1e9b
7649 #define mmDC_I2C_SW_STATUS_BASE_IDX 2
7650 #define mmDC_I2C_DDC1_HW_STATUS 0x1e9c
7651 #define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
7652 #define mmDC_I2C_DDC2_HW_STATUS 0x1e9d
7653 #define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
7654 #define mmDC_I2C_DDC3_HW_STATUS 0x1e9e
7655 #define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2
7656 #define mmDC_I2C_DDC4_HW_STATUS 0x1e9f
7657 #define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2
7658 #define mmDC_I2C_DDC5_HW_STATUS 0x1ea0
7659 #define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2
7660 #define mmDC_I2C_DDC6_HW_STATUS 0x1ea1
7661 #define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2
7662 #define mmDC_I2C_DDC1_SPEED 0x1ea2
7663 #define mmDC_I2C_DDC1_SPEED_BASE_IDX 2
7664 #define mmDC_I2C_DDC1_SETUP 0x1ea3
7665 #define mmDC_I2C_DDC1_SETUP_BASE_IDX 2
7666 #define mmDC_I2C_DDC2_SPEED 0x1ea4
7667 #define mmDC_I2C_DDC2_SPEED_BASE_IDX 2
7668 #define mmDC_I2C_DDC2_SETUP 0x1ea5
7669 #define mmDC_I2C_DDC2_SETUP_BASE_IDX 2
7670 #define mmDC_I2C_DDC3_SPEED 0x1ea6
7671 #define mmDC_I2C_DDC3_SPEED_BASE_IDX 2
7672 #define mmDC_I2C_DDC3_SETUP 0x1ea7
7673 #define mmDC_I2C_DDC3_SETUP_BASE_IDX 2
7674 #define mmDC_I2C_DDC4_SPEED 0x1ea8
7675 #define mmDC_I2C_DDC4_SPEED_BASE_IDX 2
7676 #define mmDC_I2C_DDC4_SETUP 0x1ea9
7677 #define mmDC_I2C_DDC4_SETUP_BASE_IDX 2
7678 #define mmDC_I2C_DDC5_SPEED 0x1eaa
7679 #define mmDC_I2C_DDC5_SPEED_BASE_IDX 2
7680 #define mmDC_I2C_DDC5_SETUP 0x1eab
7681 #define mmDC_I2C_DDC5_SETUP_BASE_IDX 2
7682 #define mmDC_I2C_DDC6_SPEED 0x1eac
7683 #define mmDC_I2C_DDC6_SPEED_BASE_IDX 2
7684 #define mmDC_I2C_DDC6_SETUP 0x1ead
7685 #define mmDC_I2C_DDC6_SETUP_BASE_IDX 2
7686 #define mmDC_I2C_TRANSACTION0 0x1eae
7687 #define mmDC_I2C_TRANSACTION0_BASE_IDX 2
7688 #define mmDC_I2C_TRANSACTION1 0x1eaf
7689 #define mmDC_I2C_TRANSACTION1_BASE_IDX 2
7690 #define mmDC_I2C_TRANSACTION2 0x1eb0
7691 #define mmDC_I2C_TRANSACTION2_BASE_IDX 2
7692 #define mmDC_I2C_TRANSACTION3 0x1eb1
7693 #define mmDC_I2C_TRANSACTION3_BASE_IDX 2
7694 #define mmDC_I2C_DATA 0x1eb2
7695 #define mmDC_I2C_DATA_BASE_IDX 2
7696 #define mmDC_I2C_DDCVGA_HW_STATUS 0x1eb3
7697 #define mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX 2
7698 #define mmDC_I2C_DDCVGA_SPEED 0x1eb4
7699 #define mmDC_I2C_DDCVGA_SPEED_BASE_IDX 2
7700 #define mmDC_I2C_DDCVGA_SETUP 0x1eb5
7701 #define mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2
7702 #define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6
7703 #define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
7704 #define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7
7705 #define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
7708 // addressBlock: dce_dc_dio_generic_i2c_dispdec
7709 // base address: 0x0
7710 #define mmGENERIC_I2C_CONTROL 0x1eb8
7711 #define mmGENERIC_I2C_CONTROL_BASE_IDX 2
7712 #define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1eb9
7713 #define mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
7714 #define mmGENERIC_I2C_STATUS 0x1eba
7715 #define mmGENERIC_I2C_STATUS_BASE_IDX 2
7716 #define mmGENERIC_I2C_SPEED 0x1ebb
7717 #define mmGENERIC_I2C_SPEED_BASE_IDX 2
7718 #define mmGENERIC_I2C_SETUP 0x1ebc
7719 #define mmGENERIC_I2C_SETUP_BASE_IDX 2
7720 #define mmGENERIC_I2C_TRANSACTION 0x1ebd
7721 #define mmGENERIC_I2C_TRANSACTION_BASE_IDX 2
7722 #define mmGENERIC_I2C_DATA 0x1ebe
7723 #define mmGENERIC_I2C_DATA_BASE_IDX 2
7724 #define mmGENERIC_I2C_PIN_SELECTION 0x1ebf
7725 #define mmGENERIC_I2C_PIN_SELECTION_BASE_IDX 2
7728 // addressBlock: dce_dc_dio_dio_misc_dispdec
7729 // base address: 0x0
7730 #define mmDIO_SCRATCH0 0x1eca
7731 #define mmDIO_SCRATCH0_BASE_IDX 2
7732 #define mmDIO_SCRATCH1 0x1ecb
7733 #define mmDIO_SCRATCH1_BASE_IDX 2
7734 #define mmDIO_SCRATCH2 0x1ecc
7735 #define mmDIO_SCRATCH2_BASE_IDX 2
7736 #define mmDIO_SCRATCH3 0x1ecd
7737 #define mmDIO_SCRATCH3_BASE_IDX 2
7738 #define mmDIO_SCRATCH4 0x1ece
7739 #define mmDIO_SCRATCH4_BASE_IDX 2
7740 #define mmDIO_SCRATCH5 0x1ecf
7741 #define mmDIO_SCRATCH5_BASE_IDX 2
7742 #define mmDIO_SCRATCH6 0x1ed0
7743 #define mmDIO_SCRATCH6_BASE_IDX 2
7744 #define mmDIO_SCRATCH7 0x1ed1
7745 #define mmDIO_SCRATCH7_BASE_IDX 2
7746 #define mmDCE_VCE_CONTROL 0x1ed2
7747 #define mmDCE_VCE_CONTROL_BASE_IDX 2
7748 #define mmDIO_MEM_PWR_STATUS 0x1edd
7749 #define mmDIO_MEM_PWR_STATUS_BASE_IDX 2
7750 #define mmDIO_MEM_PWR_CTRL 0x1ede
7751 #define mmDIO_MEM_PWR_CTRL_BASE_IDX 2
7752 #define mmDIO_MEM_PWR_CTRL2 0x1edf
7753 #define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2
7754 #define mmDIO_CLK_CNTL 0x1ee0
7755 #define mmDIO_CLK_CNTL_BASE_IDX 2
7756 #define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4
7757 #define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
7758 #define mmDIO_STEREOSYNC_SEL 0x1eea
7759 #define mmDIO_STEREOSYNC_SEL_BASE_IDX 2
7760 #define mmDIO_SOFT_RESET 0x1eed
7761 #define mmDIO_SOFT_RESET_BASE_IDX 2
7762 #define mmDIG_SOFT_RESET 0x1eee
7763 #define mmDIG_SOFT_RESET_BASE_IDX 2
7764 #define mmDIO_MEM_PWR_STATUS1 0x1ef0
7765 #define mmDIO_MEM_PWR_STATUS1_BASE_IDX 2
7766 #define mmDIO_CLK_CNTL2 0x1ef2
7767 #define mmDIO_CLK_CNTL2_BASE_IDX 2
7768 #define mmDIO_CLK_CNTL3 0x1ef3
7769 #define mmDIO_CLK_CNTL3_BASE_IDX 2
7770 #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff
7771 #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
7772 #define mmDIO_PSP_INTERRUPT_STATUS 0x1f00
7773 #define mmDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2
7774 #define mmDIO_PSP_INTERRUPT_CLEAR 0x1f01
7775 #define mmDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2
7776 #define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02
7777 #define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2
7778 #define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03
7779 #define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2
7782 // addressBlock: dce_dc_dio_hpd0_dispdec
7783 // base address: 0x0
7784 #define mmHPD0_DC_HPD_INT_STATUS 0x1f14
7785 #define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2
7786 #define mmHPD0_DC_HPD_INT_CONTROL 0x1f15
7787 #define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2
7788 #define mmHPD0_DC_HPD_CONTROL 0x1f16
7789 #define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2
7790 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17
7791 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
7792 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18
7793 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
7796 // addressBlock: dce_dc_dio_hpd1_dispdec
7797 // base address: 0x20
7798 #define mmHPD1_DC_HPD_INT_STATUS 0x1f1c
7799 #define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2
7800 #define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d
7801 #define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2
7802 #define mmHPD1_DC_HPD_CONTROL 0x1f1e
7803 #define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2
7804 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f
7805 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
7806 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20
7807 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
7810 // addressBlock: dce_dc_dio_hpd2_dispdec
7811 // base address: 0x40
7812 #define mmHPD2_DC_HPD_INT_STATUS 0x1f24
7813 #define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2
7814 #define mmHPD2_DC_HPD_INT_CONTROL 0x1f25
7815 #define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2
7816 #define mmHPD2_DC_HPD_CONTROL 0x1f26
7817 #define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2
7818 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27
7819 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
7820 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28
7821 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
7824 // addressBlock: dce_dc_dio_hpd3_dispdec
7825 // base address: 0x60
7826 #define mmHPD3_DC_HPD_INT_STATUS 0x1f2c
7827 #define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2
7828 #define mmHPD3_DC_HPD_INT_CONTROL 0x1f2d
7829 #define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2
7830 #define mmHPD3_DC_HPD_CONTROL 0x1f2e
7831 #define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2
7832 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f
7833 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
7834 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30
7835 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
7838 // addressBlock: dce_dc_dio_hpd4_dispdec
7839 // base address: 0x80
7840 #define mmHPD4_DC_HPD_INT_STATUS 0x1f34
7841 #define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2
7842 #define mmHPD4_DC_HPD_INT_CONTROL 0x1f35
7843 #define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2
7844 #define mmHPD4_DC_HPD_CONTROL 0x1f36
7845 #define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2
7846 #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37
7847 #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
7848 #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38
7849 #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
7852 // addressBlock: dce_dc_dio_hpd5_dispdec
7853 // base address: 0xa0
7854 #define mmHPD5_DC_HPD_INT_STATUS 0x1f3c
7855 #define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2
7856 #define mmHPD5_DC_HPD_INT_CONTROL 0x1f3d
7857 #define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2
7858 #define mmHPD5_DC_HPD_CONTROL 0x1f3e
7859 #define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2
7860 #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x1f3f
7861 #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
7862 #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x1f40
7863 #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
7866 // addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
7867 // base address: 0x7d10
7868 #define mmDC_PERFMON19_PERFCOUNTER_CNTL 0x1f44
7869 #define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2
7870 #define mmDC_PERFMON19_PERFCOUNTER_CNTL2 0x1f45
7871 #define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2
7872 #define mmDC_PERFMON19_PERFCOUNTER_STATE 0x1f46
7873 #define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2
7874 #define mmDC_PERFMON19_PERFMON_CNTL 0x1f47
7875 #define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2
7876 #define mmDC_PERFMON19_PERFMON_CNTL2 0x1f48
7877 #define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2
7878 #define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x1f49
7879 #define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
7880 #define mmDC_PERFMON19_PERFMON_CVALUE_LOW 0x1f4a
7881 #define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2
7882 #define mmDC_PERFMON19_PERFMON_HI 0x1f4b
7883 #define mmDC_PERFMON19_PERFMON_HI_BASE_IDX 2
7884 #define mmDC_PERFMON19_PERFMON_LOW 0x1f4c
7885 #define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX 2
7888 // addressBlock: dce_dc_dio_dp_aux0_dispdec
7889 // base address: 0x0
7890 #define mmDP_AUX0_AUX_CONTROL 0x1f50
7891 #define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2
7892 #define mmDP_AUX0_AUX_SW_CONTROL 0x1f51
7893 #define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2
7894 #define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52
7895 #define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2
7896 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53
7897 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2
7898 #define mmDP_AUX0_AUX_SW_STATUS 0x1f54
7899 #define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2
7900 #define mmDP_AUX0_AUX_LS_STATUS 0x1f55
7901 #define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2
7902 #define mmDP_AUX0_AUX_SW_DATA 0x1f56
7903 #define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2
7904 #define mmDP_AUX0_AUX_LS_DATA 0x1f57
7905 #define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2
7906 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58
7907 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
7908 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59
7909 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2
7910 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a
7911 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
7912 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b
7913 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
7914 #define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c
7915 #define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2
7916 #define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d
7917 #define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2
7918 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f
7919 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
7920 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60
7921 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
7922 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61
7923 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2
7926 // addressBlock: dce_dc_dio_dp_aux1_dispdec
7927 // base address: 0x70
7928 #define mmDP_AUX1_AUX_CONTROL 0x1f6c
7929 #define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2
7930 #define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d
7931 #define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2
7932 #define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e
7933 #define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2
7934 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f
7935 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2
7936 #define mmDP_AUX1_AUX_SW_STATUS 0x1f70
7937 #define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2
7938 #define mmDP_AUX1_AUX_LS_STATUS 0x1f71
7939 #define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2
7940 #define mmDP_AUX1_AUX_SW_DATA 0x1f72
7941 #define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2
7942 #define mmDP_AUX1_AUX_LS_DATA 0x1f73
7943 #define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2
7944 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74
7945 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
7946 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75
7947 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2
7948 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76
7949 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
7950 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77
7951 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
7952 #define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78
7953 #define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2
7954 #define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79
7955 #define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2
7956 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b
7957 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
7958 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c
7959 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
7960 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d
7961 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2
7964 // addressBlock: dce_dc_dio_dp_aux2_dispdec
7965 // base address: 0xe0
7966 #define mmDP_AUX2_AUX_CONTROL 0x1f88
7967 #define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2
7968 #define mmDP_AUX2_AUX_SW_CONTROL 0x1f89
7969 #define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2
7970 #define mmDP_AUX2_AUX_ARB_CONTROL 0x1f8a
7971 #define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2
7972 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b
7973 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2
7974 #define mmDP_AUX2_AUX_SW_STATUS 0x1f8c
7975 #define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2
7976 #define mmDP_AUX2_AUX_LS_STATUS 0x1f8d
7977 #define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2
7978 #define mmDP_AUX2_AUX_SW_DATA 0x1f8e
7979 #define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2
7980 #define mmDP_AUX2_AUX_LS_DATA 0x1f8f
7981 #define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2
7982 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90
7983 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
7984 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91
7985 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2
7986 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92
7987 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
7988 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93
7989 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
7990 #define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94
7991 #define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2
7992 #define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95
7993 #define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2
7994 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97
7995 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
7996 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98
7997 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
7998 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99
7999 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2
8002 // addressBlock: dce_dc_dio_dp_aux3_dispdec
8003 // base address: 0x150
8004 #define mmDP_AUX3_AUX_CONTROL 0x1fa4
8005 #define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2
8006 #define mmDP_AUX3_AUX_SW_CONTROL 0x1fa5
8007 #define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2
8008 #define mmDP_AUX3_AUX_ARB_CONTROL 0x1fa6
8009 #define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2
8010 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7
8011 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2
8012 #define mmDP_AUX3_AUX_SW_STATUS 0x1fa8
8013 #define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2
8014 #define mmDP_AUX3_AUX_LS_STATUS 0x1fa9
8015 #define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2
8016 #define mmDP_AUX3_AUX_SW_DATA 0x1faa
8017 #define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2
8018 #define mmDP_AUX3_AUX_LS_DATA 0x1fab
8019 #define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2
8020 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac
8021 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
8022 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad
8023 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2
8024 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae
8025 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
8026 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf
8027 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
8028 #define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0
8029 #define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2
8030 #define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1
8031 #define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2
8032 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3
8033 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
8034 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4
8035 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
8036 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5
8037 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2
8040 // addressBlock: dce_dc_dio_dp_aux4_dispdec
8041 // base address: 0x1c0
8042 #define mmDP_AUX4_AUX_CONTROL 0x1fc0
8043 #define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2
8044 #define mmDP_AUX4_AUX_SW_CONTROL 0x1fc1
8045 #define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2
8046 #define mmDP_AUX4_AUX_ARB_CONTROL 0x1fc2
8047 #define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2
8048 #define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3
8049 #define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2
8050 #define mmDP_AUX4_AUX_SW_STATUS 0x1fc4
8051 #define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2
8052 #define mmDP_AUX4_AUX_LS_STATUS 0x1fc5
8053 #define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2
8054 #define mmDP_AUX4_AUX_SW_DATA 0x1fc6
8055 #define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2
8056 #define mmDP_AUX4_AUX_LS_DATA 0x1fc7
8057 #define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2
8058 #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8
8059 #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
8060 #define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9
8061 #define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2
8062 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca
8063 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
8064 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb
8065 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
8066 #define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc
8067 #define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2
8068 #define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd
8069 #define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2
8070 #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf
8071 #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
8072 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0
8073 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
8074 #define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1
8075 #define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2
8078 // addressBlock: dce_dc_dio_dp_aux5_dispdec
8079 // base address: 0x230
8080 #define mmDP_AUX5_AUX_CONTROL 0x1fdc
8081 #define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2
8082 #define mmDP_AUX5_AUX_SW_CONTROL 0x1fdd
8083 #define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2
8084 #define mmDP_AUX5_AUX_ARB_CONTROL 0x1fde
8085 #define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2
8086 #define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x1fdf
8087 #define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2
8088 #define mmDP_AUX5_AUX_SW_STATUS 0x1fe0
8089 #define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2
8090 #define mmDP_AUX5_AUX_LS_STATUS 0x1fe1
8091 #define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2
8092 #define mmDP_AUX5_AUX_SW_DATA 0x1fe2
8093 #define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2
8094 #define mmDP_AUX5_AUX_LS_DATA 0x1fe3
8095 #define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2
8096 #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x1fe4
8097 #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
8098 #define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x1fe5
8099 #define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2
8100 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x1fe6
8101 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
8102 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x1fe7
8103 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
8104 #define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x1fe8
8105 #define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2
8106 #define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x1fe9
8107 #define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2
8108 #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1feb
8109 #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
8110 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fec
8111 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
8112 #define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1fed
8113 #define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2
8116 // addressBlock: dce_dc_dio_dp_aux6_dispdec
8117 // base address: 0x2a0
8118 #define mmDP_AUX6_AUX_CONTROL 0x1ff8
8119 #define mmDP_AUX6_AUX_CONTROL_BASE_IDX 2
8120 #define mmDP_AUX6_AUX_SW_CONTROL 0x1ff9
8121 #define mmDP_AUX6_AUX_SW_CONTROL_BASE_IDX 2
8122 #define mmDP_AUX6_AUX_ARB_CONTROL 0x1ffa
8123 #define mmDP_AUX6_AUX_ARB_CONTROL_BASE_IDX 2
8124 #define mmDP_AUX6_AUX_INTERRUPT_CONTROL 0x1ffb
8125 #define mmDP_AUX6_AUX_INTERRUPT_CONTROL_BASE_IDX 2
8126 #define mmDP_AUX6_AUX_SW_STATUS 0x1ffc
8127 #define mmDP_AUX6_AUX_SW_STATUS_BASE_IDX 2
8128 #define mmDP_AUX6_AUX_LS_STATUS 0x1ffd
8129 #define mmDP_AUX6_AUX_LS_STATUS_BASE_IDX 2
8130 #define mmDP_AUX6_AUX_SW_DATA 0x1ffe
8131 #define mmDP_AUX6_AUX_SW_DATA_BASE_IDX 2
8132 #define mmDP_AUX6_AUX_LS_DATA 0x1fff
8133 #define mmDP_AUX6_AUX_LS_DATA_BASE_IDX 2
8134 #define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL 0x2000
8135 #define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
8136 #define mmDP_AUX6_AUX_DPHY_TX_CONTROL 0x2001
8137 #define mmDP_AUX6_AUX_DPHY_TX_CONTROL_BASE_IDX 2
8138 #define mmDP_AUX6_AUX_DPHY_RX_CONTROL0 0x2002
8139 #define mmDP_AUX6_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
8140 #define mmDP_AUX6_AUX_DPHY_RX_CONTROL1 0x2003
8141 #define mmDP_AUX6_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
8142 #define mmDP_AUX6_AUX_DPHY_TX_STATUS 0x2004
8143 #define mmDP_AUX6_AUX_DPHY_TX_STATUS_BASE_IDX 2
8144 #define mmDP_AUX6_AUX_DPHY_RX_STATUS 0x2005
8145 #define mmDP_AUX6_AUX_DPHY_RX_STATUS_BASE_IDX 2
8146 #define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL 0x2007
8147 #define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
8148 #define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS 0x2008
8149 #define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
8150 #define mmDP_AUX6_AUX_GTC_SYNC_STATUS 0x2009
8151 #define mmDP_AUX6_AUX_GTC_SYNC_STATUS_BASE_IDX 2
8154 // addressBlock: dce_dc_dio_dig0_dispdec
8155 // base address: 0x0
8156 #define mmDIG0_DIG_FE_CNTL 0x2068
8157 #define mmDIG0_DIG_FE_CNTL_BASE_IDX 2
8158 #define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x2069
8159 #define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
8160 #define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x206a
8161 #define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
8162 #define mmDIG0_DIG_CLOCK_PATTERN 0x206b
8163 #define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2
8164 #define mmDIG0_DIG_TEST_PATTERN 0x206c
8165 #define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2
8166 #define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x206d
8167 #define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
8168 #define mmDIG0_DIG_FIFO_STATUS 0x206e
8169 #define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2
8170 #define mmDIG0_HDMI_CONTROL 0x2071
8171 #define mmDIG0_HDMI_CONTROL_BASE_IDX 2
8172 #define mmDIG0_HDMI_STATUS 0x2072
8173 #define mmDIG0_HDMI_STATUS_BASE_IDX 2
8174 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2073
8175 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
8176 #define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2074
8177 #define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
8178 #define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2075
8179 #define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
8180 #define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2076
8181 #define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
8182 #define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2077
8183 #define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
8184 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x2078
8185 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
8186 #define mmDIG0_AFMT_INTERRUPT_STATUS 0x2079
8187 #define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2
8188 #define mmDIG0_HDMI_GC 0x207b
8189 #define mmDIG0_HDMI_GC_BASE_IDX 2
8190 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x207c
8191 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
8192 #define mmDIG0_AFMT_ISRC1_0 0x207d
8193 #define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2
8194 #define mmDIG0_AFMT_ISRC1_1 0x207e
8195 #define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2
8196 #define mmDIG0_AFMT_ISRC1_2 0x207f
8197 #define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2
8198 #define mmDIG0_AFMT_ISRC1_3 0x2080
8199 #define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2
8200 #define mmDIG0_AFMT_ISRC1_4 0x2081
8201 #define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2
8202 #define mmDIG0_AFMT_ISRC2_0 0x2082
8203 #define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2
8204 #define mmDIG0_AFMT_ISRC2_1 0x2083
8205 #define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2
8206 #define mmDIG0_AFMT_ISRC2_2 0x2084
8207 #define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2
8208 #define mmDIG0_AFMT_ISRC2_3 0x2085
8209 #define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2
8210 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x2086
8211 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
8212 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x2087
8213 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
8214 #define mmDIG0_HDMI_DB_CONTROL 0x2088
8215 #define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2
8216 #define mmDIG0_AFMT_MPEG_INFO0 0x208a
8217 #define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2
8218 #define mmDIG0_AFMT_MPEG_INFO1 0x208b
8219 #define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2
8220 #define mmDIG0_AFMT_GENERIC_HDR 0x208c
8221 #define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2
8222 #define mmDIG0_AFMT_GENERIC_0 0x208d
8223 #define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2
8224 #define mmDIG0_AFMT_GENERIC_1 0x208e
8225 #define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2
8226 #define mmDIG0_AFMT_GENERIC_2 0x208f
8227 #define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2
8228 #define mmDIG0_AFMT_GENERIC_3 0x2090
8229 #define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2
8230 #define mmDIG0_AFMT_GENERIC_4 0x2091
8231 #define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2
8232 #define mmDIG0_AFMT_GENERIC_5 0x2092
8233 #define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2
8234 #define mmDIG0_AFMT_GENERIC_6 0x2093
8235 #define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2
8236 #define mmDIG0_AFMT_GENERIC_7 0x2094
8237 #define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2
8238 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x2095
8239 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
8240 #define mmDIG0_HDMI_ACR_32_0 0x2096
8241 #define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2
8242 #define mmDIG0_HDMI_ACR_32_1 0x2097
8243 #define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2
8244 #define mmDIG0_HDMI_ACR_44_0 0x2098
8245 #define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2
8246 #define mmDIG0_HDMI_ACR_44_1 0x2099
8247 #define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2
8248 #define mmDIG0_HDMI_ACR_48_0 0x209a
8249 #define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2
8250 #define mmDIG0_HDMI_ACR_48_1 0x209b
8251 #define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2
8252 #define mmDIG0_HDMI_ACR_STATUS_0 0x209c
8253 #define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2
8254 #define mmDIG0_HDMI_ACR_STATUS_1 0x209d
8255 #define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2
8256 #define mmDIG0_AFMT_AUDIO_INFO0 0x209e
8257 #define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2
8258 #define mmDIG0_AFMT_AUDIO_INFO1 0x209f
8259 #define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2
8260 #define mmDIG0_AFMT_60958_0 0x20a0
8261 #define mmDIG0_AFMT_60958_0_BASE_IDX 2
8262 #define mmDIG0_AFMT_60958_1 0x20a1
8263 #define mmDIG0_AFMT_60958_1_BASE_IDX 2
8264 #define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x20a2
8265 #define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
8266 #define mmDIG0_AFMT_RAMP_CONTROL0 0x20a3
8267 #define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2
8268 #define mmDIG0_AFMT_RAMP_CONTROL1 0x20a4
8269 #define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2
8270 #define mmDIG0_AFMT_RAMP_CONTROL2 0x20a5
8271 #define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2
8272 #define mmDIG0_AFMT_RAMP_CONTROL3 0x20a6
8273 #define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2
8274 #define mmDIG0_AFMT_60958_2 0x20a7
8275 #define mmDIG0_AFMT_60958_2_BASE_IDX 2
8276 #define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x20a8
8277 #define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
8278 #define mmDIG0_AFMT_STATUS 0x20a9
8279 #define mmDIG0_AFMT_STATUS_BASE_IDX 2
8280 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x20aa
8281 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
8282 #define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x20ab
8283 #define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
8284 #define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x20ac
8285 #define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
8286 #define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x20ad
8287 #define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
8288 #define mmDIG0_DIG_BE_CNTL 0x20af
8289 #define mmDIG0_DIG_BE_CNTL_BASE_IDX 2
8290 #define mmDIG0_DIG_BE_EN_CNTL 0x20b0
8291 #define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
8292 #define mmDIG0_TMDS_CNTL 0x20d3
8293 #define mmDIG0_TMDS_CNTL_BASE_IDX 2
8294 #define mmDIG0_TMDS_CONTROL_CHAR 0x20d4
8295 #define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2
8296 #define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d5
8297 #define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
8298 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20d6
8299 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
8300 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20d7
8301 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
8302 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20d8
8303 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
8304 #define mmDIG0_TMDS_CTL_BITS 0x20da
8305 #define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2
8306 #define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20db
8307 #define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
8308 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20dd
8309 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
8310 #define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20de
8311 #define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
8312 #define mmDIG0_DIG_VERSION 0x20e0
8313 #define mmDIG0_DIG_VERSION_BASE_IDX 2
8314 #define mmDIG0_DIG_LANE_ENABLE 0x20e1
8315 #define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2
8316 #define mmDIG0_AFMT_CNTL 0x20e6
8317 #define mmDIG0_AFMT_CNTL_BASE_IDX 2
8318 #define mmDIG0_AFMT_VBI_PACKET_CONTROL1 0x20e7
8319 #define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
8322 // addressBlock: dce_dc_dio_dp0_dispdec
8323 // base address: 0x0
8324 #define mmDP0_DP_LINK_CNTL 0x2108
8325 #define mmDP0_DP_LINK_CNTL_BASE_IDX 2
8326 #define mmDP0_DP_PIXEL_FORMAT 0x2109
8327 #define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2
8328 #define mmDP0_DP_MSA_COLORIMETRY 0x210a
8329 #define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2
8330 #define mmDP0_DP_CONFIG 0x210b
8331 #define mmDP0_DP_CONFIG_BASE_IDX 2
8332 #define mmDP0_DP_VID_STREAM_CNTL 0x210c
8333 #define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2
8334 #define mmDP0_DP_STEER_FIFO 0x210d
8335 #define mmDP0_DP_STEER_FIFO_BASE_IDX 2
8336 #define mmDP0_DP_MSA_MISC 0x210e
8337 #define mmDP0_DP_MSA_MISC_BASE_IDX 2
8338 #define mmDP0_DP_VID_TIMING 0x2110
8339 #define mmDP0_DP_VID_TIMING_BASE_IDX 2
8340 #define mmDP0_DP_VID_N 0x2111
8341 #define mmDP0_DP_VID_N_BASE_IDX 2
8342 #define mmDP0_DP_VID_M 0x2112
8343 #define mmDP0_DP_VID_M_BASE_IDX 2
8344 #define mmDP0_DP_LINK_FRAMING_CNTL 0x2113
8345 #define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2
8346 #define mmDP0_DP_HBR2_EYE_PATTERN 0x2114
8347 #define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2
8348 #define mmDP0_DP_VID_MSA_VBID 0x2115
8349 #define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2
8350 #define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116
8351 #define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
8352 #define mmDP0_DP_DPHY_CNTL 0x2117
8353 #define mmDP0_DP_DPHY_CNTL_BASE_IDX 2
8354 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118
8355 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
8356 #define mmDP0_DP_DPHY_SYM0 0x2119
8357 #define mmDP0_DP_DPHY_SYM0_BASE_IDX 2
8358 #define mmDP0_DP_DPHY_SYM1 0x211a
8359 #define mmDP0_DP_DPHY_SYM1_BASE_IDX 2
8360 #define mmDP0_DP_DPHY_SYM2 0x211b
8361 #define mmDP0_DP_DPHY_SYM2_BASE_IDX 2
8362 #define mmDP0_DP_DPHY_8B10B_CNTL 0x211c
8363 #define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2
8364 #define mmDP0_DP_DPHY_PRBS_CNTL 0x211d
8365 #define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2
8366 #define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e
8367 #define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
8368 #define mmDP0_DP_DPHY_CRC_EN 0x211f
8369 #define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2
8370 #define mmDP0_DP_DPHY_CRC_CNTL 0x2120
8371 #define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2
8372 #define mmDP0_DP_DPHY_CRC_RESULT 0x2121
8373 #define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2
8374 #define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122
8375 #define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
8376 #define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123
8377 #define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
8378 #define mmDP0_DP_DPHY_FAST_TRAINING 0x2124
8379 #define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2
8380 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125
8381 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
8382 #define mmDP0_DP_SEC_CNTL 0x212b
8383 #define mmDP0_DP_SEC_CNTL_BASE_IDX 2
8384 #define mmDP0_DP_SEC_CNTL1 0x212c
8385 #define mmDP0_DP_SEC_CNTL1_BASE_IDX 2
8386 #define mmDP0_DP_SEC_FRAMING1 0x212d
8387 #define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2
8388 #define mmDP0_DP_SEC_FRAMING2 0x212e
8389 #define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2
8390 #define mmDP0_DP_SEC_FRAMING3 0x212f
8391 #define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2
8392 #define mmDP0_DP_SEC_FRAMING4 0x2130
8393 #define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2
8394 #define mmDP0_DP_SEC_AUD_N 0x2131
8395 #define mmDP0_DP_SEC_AUD_N_BASE_IDX 2
8396 #define mmDP0_DP_SEC_AUD_N_READBACK 0x2132
8397 #define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2
8398 #define mmDP0_DP_SEC_AUD_M 0x2133
8399 #define mmDP0_DP_SEC_AUD_M_BASE_IDX 2
8400 #define mmDP0_DP_SEC_AUD_M_READBACK 0x2134
8401 #define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2
8402 #define mmDP0_DP_SEC_TIMESTAMP 0x2135
8403 #define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2
8404 #define mmDP0_DP_SEC_PACKET_CNTL 0x2136
8405 #define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2
8406 #define mmDP0_DP_MSE_RATE_CNTL 0x2137
8407 #define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2
8408 #define mmDP0_DP_MSE_RATE_UPDATE 0x2139
8409 #define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2
8410 #define mmDP0_DP_MSE_SAT0 0x213a
8411 #define mmDP0_DP_MSE_SAT0_BASE_IDX 2
8412 #define mmDP0_DP_MSE_SAT1 0x213b
8413 #define mmDP0_DP_MSE_SAT1_BASE_IDX 2
8414 #define mmDP0_DP_MSE_SAT2 0x213c
8415 #define mmDP0_DP_MSE_SAT2_BASE_IDX 2
8416 #define mmDP0_DP_MSE_SAT_UPDATE 0x213d
8417 #define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2
8418 #define mmDP0_DP_MSE_LINK_TIMING 0x213e
8419 #define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2
8420 #define mmDP0_DP_MSE_MISC_CNTL 0x213f
8421 #define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2
8422 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144
8423 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
8424 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145
8425 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
8426 #define mmDP0_DP_MSE_SAT0_STATUS 0x2147
8427 #define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2
8428 #define mmDP0_DP_MSE_SAT1_STATUS 0x2148
8429 #define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2
8430 #define mmDP0_DP_MSE_SAT2_STATUS 0x2149
8431 #define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2
8432 #define mmDP0_DP_MSA_TIMING_PARAM1 0x214c
8433 #define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2
8434 #define mmDP0_DP_MSA_TIMING_PARAM2 0x214d
8435 #define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2
8436 #define mmDP0_DP_MSA_TIMING_PARAM3 0x214e
8437 #define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2
8438 #define mmDP0_DP_MSA_TIMING_PARAM4 0x214f
8439 #define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2
8440 #define mmDP0_DP_MSO_CNTL 0x2150
8441 #define mmDP0_DP_MSO_CNTL_BASE_IDX 2
8442 #define mmDP0_DP_MSO_CNTL1 0x2151
8443 #define mmDP0_DP_MSO_CNTL1_BASE_IDX 2
8444 #define mmDP0_DP_DSC_CNTL 0x2152
8445 #define mmDP0_DP_DSC_CNTL_BASE_IDX 2
8446 #define mmDP0_DP_SEC_CNTL2 0x2153
8447 #define mmDP0_DP_SEC_CNTL2_BASE_IDX 2
8448 #define mmDP0_DP_SEC_CNTL3 0x2154
8449 #define mmDP0_DP_SEC_CNTL3_BASE_IDX 2
8450 #define mmDP0_DP_SEC_CNTL4 0x2155
8451 #define mmDP0_DP_SEC_CNTL4_BASE_IDX 2
8452 #define mmDP0_DP_SEC_CNTL5 0x2156
8453 #define mmDP0_DP_SEC_CNTL5_BASE_IDX 2
8454 #define mmDP0_DP_SEC_CNTL6 0x2157
8455 #define mmDP0_DP_SEC_CNTL6_BASE_IDX 2
8456 #define mmDP0_DP_SEC_CNTL7 0x2158
8457 #define mmDP0_DP_SEC_CNTL7_BASE_IDX 2
8458 #define mmDP0_DP_DB_CNTL 0x2159
8459 #define mmDP0_DP_DB_CNTL_BASE_IDX 2
8460 #define mmDP0_DP_MSA_VBID_MISC 0x215a
8461 #define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2
8464 // addressBlock: dce_dc_dio_dig1_dispdec
8465 // base address: 0x400
8466 #define mmDIG1_DIG_FE_CNTL 0x2168
8467 #define mmDIG1_DIG_FE_CNTL_BASE_IDX 2
8468 #define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x2169
8469 #define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
8470 #define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x216a
8471 #define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
8472 #define mmDIG1_DIG_CLOCK_PATTERN 0x216b
8473 #define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2
8474 #define mmDIG1_DIG_TEST_PATTERN 0x216c
8475 #define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2
8476 #define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x216d
8477 #define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
8478 #define mmDIG1_DIG_FIFO_STATUS 0x216e
8479 #define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2
8480 #define mmDIG1_HDMI_CONTROL 0x2171
8481 #define mmDIG1_HDMI_CONTROL_BASE_IDX 2
8482 #define mmDIG1_HDMI_STATUS 0x2172
8483 #define mmDIG1_HDMI_STATUS_BASE_IDX 2
8484 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2173
8485 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
8486 #define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2174
8487 #define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
8488 #define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2175
8489 #define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
8490 #define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2176
8491 #define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
8492 #define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2177
8493 #define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
8494 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x2178
8495 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
8496 #define mmDIG1_AFMT_INTERRUPT_STATUS 0x2179
8497 #define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2
8498 #define mmDIG1_HDMI_GC 0x217b
8499 #define mmDIG1_HDMI_GC_BASE_IDX 2
8500 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x217c
8501 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
8502 #define mmDIG1_AFMT_ISRC1_0 0x217d
8503 #define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2
8504 #define mmDIG1_AFMT_ISRC1_1 0x217e
8505 #define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2
8506 #define mmDIG1_AFMT_ISRC1_2 0x217f
8507 #define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2
8508 #define mmDIG1_AFMT_ISRC1_3 0x2180
8509 #define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2
8510 #define mmDIG1_AFMT_ISRC1_4 0x2181
8511 #define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2
8512 #define mmDIG1_AFMT_ISRC2_0 0x2182
8513 #define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2
8514 #define mmDIG1_AFMT_ISRC2_1 0x2183
8515 #define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2
8516 #define mmDIG1_AFMT_ISRC2_2 0x2184
8517 #define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2
8518 #define mmDIG1_AFMT_ISRC2_3 0x2185
8519 #define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2
8520 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x2186
8521 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
8522 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x2187
8523 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
8524 #define mmDIG1_HDMI_DB_CONTROL 0x2188
8525 #define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2
8526 #define mmDIG1_AFMT_MPEG_INFO0 0x218a
8527 #define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2
8528 #define mmDIG1_AFMT_MPEG_INFO1 0x218b
8529 #define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2
8530 #define mmDIG1_AFMT_GENERIC_HDR 0x218c
8531 #define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2
8532 #define mmDIG1_AFMT_GENERIC_0 0x218d
8533 #define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2
8534 #define mmDIG1_AFMT_GENERIC_1 0x218e
8535 #define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2
8536 #define mmDIG1_AFMT_GENERIC_2 0x218f
8537 #define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2
8538 #define mmDIG1_AFMT_GENERIC_3 0x2190
8539 #define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2
8540 #define mmDIG1_AFMT_GENERIC_4 0x2191
8541 #define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2
8542 #define mmDIG1_AFMT_GENERIC_5 0x2192
8543 #define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2
8544 #define mmDIG1_AFMT_GENERIC_6 0x2193
8545 #define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2
8546 #define mmDIG1_AFMT_GENERIC_7 0x2194
8547 #define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2
8548 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x2195
8549 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
8550 #define mmDIG1_HDMI_ACR_32_0 0x2196
8551 #define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2
8552 #define mmDIG1_HDMI_ACR_32_1 0x2197
8553 #define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2
8554 #define mmDIG1_HDMI_ACR_44_0 0x2198
8555 #define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2
8556 #define mmDIG1_HDMI_ACR_44_1 0x2199
8557 #define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2
8558 #define mmDIG1_HDMI_ACR_48_0 0x219a
8559 #define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2
8560 #define mmDIG1_HDMI_ACR_48_1 0x219b
8561 #define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2
8562 #define mmDIG1_HDMI_ACR_STATUS_0 0x219c
8563 #define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2
8564 #define mmDIG1_HDMI_ACR_STATUS_1 0x219d
8565 #define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2
8566 #define mmDIG1_AFMT_AUDIO_INFO0 0x219e
8567 #define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2
8568 #define mmDIG1_AFMT_AUDIO_INFO1 0x219f
8569 #define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2
8570 #define mmDIG1_AFMT_60958_0 0x21a0
8571 #define mmDIG1_AFMT_60958_0_BASE_IDX 2
8572 #define mmDIG1_AFMT_60958_1 0x21a1
8573 #define mmDIG1_AFMT_60958_1_BASE_IDX 2
8574 #define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x21a2
8575 #define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
8576 #define mmDIG1_AFMT_RAMP_CONTROL0 0x21a3
8577 #define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2
8578 #define mmDIG1_AFMT_RAMP_CONTROL1 0x21a4
8579 #define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2
8580 #define mmDIG1_AFMT_RAMP_CONTROL2 0x21a5
8581 #define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2
8582 #define mmDIG1_AFMT_RAMP_CONTROL3 0x21a6
8583 #define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2
8584 #define mmDIG1_AFMT_60958_2 0x21a7
8585 #define mmDIG1_AFMT_60958_2_BASE_IDX 2
8586 #define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x21a8
8587 #define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
8588 #define mmDIG1_AFMT_STATUS 0x21a9
8589 #define mmDIG1_AFMT_STATUS_BASE_IDX 2
8590 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x21aa
8591 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
8592 #define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x21ab
8593 #define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
8594 #define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x21ac
8595 #define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
8596 #define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x21ad
8597 #define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
8598 #define mmDIG1_DIG_BE_CNTL 0x21af
8599 #define mmDIG1_DIG_BE_CNTL_BASE_IDX 2
8600 #define mmDIG1_DIG_BE_EN_CNTL 0x21b0
8601 #define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
8602 #define mmDIG1_TMDS_CNTL 0x21d3
8603 #define mmDIG1_TMDS_CNTL_BASE_IDX 2
8604 #define mmDIG1_TMDS_CONTROL_CHAR 0x21d4
8605 #define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2
8606 #define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d5
8607 #define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
8608 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21d6
8609 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
8610 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21d7
8611 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
8612 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21d8
8613 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
8614 #define mmDIG1_TMDS_CTL_BITS 0x21da
8615 #define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2
8616 #define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21db
8617 #define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
8618 #define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21dd
8619 #define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
8620 #define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21de
8621 #define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
8622 #define mmDIG1_DIG_VERSION 0x21e0
8623 #define mmDIG1_DIG_VERSION_BASE_IDX 2
8624 #define mmDIG1_DIG_LANE_ENABLE 0x21e1
8625 #define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2
8626 #define mmDIG1_AFMT_CNTL 0x21e6
8627 #define mmDIG1_AFMT_CNTL_BASE_IDX 2
8628 #define mmDIG1_AFMT_VBI_PACKET_CONTROL1 0x21e7
8629 #define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
8632 // addressBlock: dce_dc_dio_dp1_dispdec
8633 // base address: 0x400
8634 #define mmDP1_DP_LINK_CNTL 0x2208
8635 #define mmDP1_DP_LINK_CNTL_BASE_IDX 2
8636 #define mmDP1_DP_PIXEL_FORMAT 0x2209
8637 #define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2
8638 #define mmDP1_DP_MSA_COLORIMETRY 0x220a
8639 #define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2
8640 #define mmDP1_DP_CONFIG 0x220b
8641 #define mmDP1_DP_CONFIG_BASE_IDX 2
8642 #define mmDP1_DP_VID_STREAM_CNTL 0x220c
8643 #define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2
8644 #define mmDP1_DP_STEER_FIFO 0x220d
8645 #define mmDP1_DP_STEER_FIFO_BASE_IDX 2
8646 #define mmDP1_DP_MSA_MISC 0x220e
8647 #define mmDP1_DP_MSA_MISC_BASE_IDX 2
8648 #define mmDP1_DP_VID_TIMING 0x2210
8649 #define mmDP1_DP_VID_TIMING_BASE_IDX 2
8650 #define mmDP1_DP_VID_N 0x2211
8651 #define mmDP1_DP_VID_N_BASE_IDX 2
8652 #define mmDP1_DP_VID_M 0x2212
8653 #define mmDP1_DP_VID_M_BASE_IDX 2
8654 #define mmDP1_DP_LINK_FRAMING_CNTL 0x2213
8655 #define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2
8656 #define mmDP1_DP_HBR2_EYE_PATTERN 0x2214
8657 #define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2
8658 #define mmDP1_DP_VID_MSA_VBID 0x2215
8659 #define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2
8660 #define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216
8661 #define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
8662 #define mmDP1_DP_DPHY_CNTL 0x2217
8663 #define mmDP1_DP_DPHY_CNTL_BASE_IDX 2
8664 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218
8665 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
8666 #define mmDP1_DP_DPHY_SYM0 0x2219
8667 #define mmDP1_DP_DPHY_SYM0_BASE_IDX 2
8668 #define mmDP1_DP_DPHY_SYM1 0x221a
8669 #define mmDP1_DP_DPHY_SYM1_BASE_IDX 2
8670 #define mmDP1_DP_DPHY_SYM2 0x221b
8671 #define mmDP1_DP_DPHY_SYM2_BASE_IDX 2
8672 #define mmDP1_DP_DPHY_8B10B_CNTL 0x221c
8673 #define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2
8674 #define mmDP1_DP_DPHY_PRBS_CNTL 0x221d
8675 #define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2
8676 #define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e
8677 #define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
8678 #define mmDP1_DP_DPHY_CRC_EN 0x221f
8679 #define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2
8680 #define mmDP1_DP_DPHY_CRC_CNTL 0x2220
8681 #define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2
8682 #define mmDP1_DP_DPHY_CRC_RESULT 0x2221
8683 #define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2
8684 #define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222
8685 #define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
8686 #define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223
8687 #define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
8688 #define mmDP1_DP_DPHY_FAST_TRAINING 0x2224
8689 #define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2
8690 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225
8691 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
8692 #define mmDP1_DP_SEC_CNTL 0x222b
8693 #define mmDP1_DP_SEC_CNTL_BASE_IDX 2
8694 #define mmDP1_DP_SEC_CNTL1 0x222c
8695 #define mmDP1_DP_SEC_CNTL1_BASE_IDX 2
8696 #define mmDP1_DP_SEC_FRAMING1 0x222d
8697 #define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2
8698 #define mmDP1_DP_SEC_FRAMING2 0x222e
8699 #define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2
8700 #define mmDP1_DP_SEC_FRAMING3 0x222f
8701 #define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2
8702 #define mmDP1_DP_SEC_FRAMING4 0x2230
8703 #define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2
8704 #define mmDP1_DP_SEC_AUD_N 0x2231
8705 #define mmDP1_DP_SEC_AUD_N_BASE_IDX 2
8706 #define mmDP1_DP_SEC_AUD_N_READBACK 0x2232
8707 #define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2
8708 #define mmDP1_DP_SEC_AUD_M 0x2233
8709 #define mmDP1_DP_SEC_AUD_M_BASE_IDX 2
8710 #define mmDP1_DP_SEC_AUD_M_READBACK 0x2234
8711 #define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2
8712 #define mmDP1_DP_SEC_TIMESTAMP 0x2235
8713 #define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2
8714 #define mmDP1_DP_SEC_PACKET_CNTL 0x2236
8715 #define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2
8716 #define mmDP1_DP_MSE_RATE_CNTL 0x2237
8717 #define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2
8718 #define mmDP1_DP_MSE_RATE_UPDATE 0x2239
8719 #define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2
8720 #define mmDP1_DP_MSE_SAT0 0x223a
8721 #define mmDP1_DP_MSE_SAT0_BASE_IDX 2
8722 #define mmDP1_DP_MSE_SAT1 0x223b
8723 #define mmDP1_DP_MSE_SAT1_BASE_IDX 2
8724 #define mmDP1_DP_MSE_SAT2 0x223c
8725 #define mmDP1_DP_MSE_SAT2_BASE_IDX 2
8726 #define mmDP1_DP_MSE_SAT_UPDATE 0x223d
8727 #define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2
8728 #define mmDP1_DP_MSE_LINK_TIMING 0x223e
8729 #define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2
8730 #define mmDP1_DP_MSE_MISC_CNTL 0x223f
8731 #define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2
8732 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244
8733 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
8734 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245
8735 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
8736 #define mmDP1_DP_MSE_SAT0_STATUS 0x2247
8737 #define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2
8738 #define mmDP1_DP_MSE_SAT1_STATUS 0x2248
8739 #define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2
8740 #define mmDP1_DP_MSE_SAT2_STATUS 0x2249
8741 #define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2
8742 #define mmDP1_DP_MSA_TIMING_PARAM1 0x224c
8743 #define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2
8744 #define mmDP1_DP_MSA_TIMING_PARAM2 0x224d
8745 #define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2
8746 #define mmDP1_DP_MSA_TIMING_PARAM3 0x224e
8747 #define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2
8748 #define mmDP1_DP_MSA_TIMING_PARAM4 0x224f
8749 #define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2
8750 #define mmDP1_DP_MSO_CNTL 0x2250
8751 #define mmDP1_DP_MSO_CNTL_BASE_IDX 2
8752 #define mmDP1_DP_MSO_CNTL1 0x2251
8753 #define mmDP1_DP_MSO_CNTL1_BASE_IDX 2
8754 #define mmDP1_DP_DSC_CNTL 0x2252
8755 #define mmDP1_DP_DSC_CNTL_BASE_IDX 2
8756 #define mmDP1_DP_SEC_CNTL2 0x2253
8757 #define mmDP1_DP_SEC_CNTL2_BASE_IDX 2
8758 #define mmDP1_DP_SEC_CNTL3 0x2254
8759 #define mmDP1_DP_SEC_CNTL3_BASE_IDX 2
8760 #define mmDP1_DP_SEC_CNTL4 0x2255
8761 #define mmDP1_DP_SEC_CNTL4_BASE_IDX 2
8762 #define mmDP1_DP_SEC_CNTL5 0x2256
8763 #define mmDP1_DP_SEC_CNTL5_BASE_IDX 2
8764 #define mmDP1_DP_SEC_CNTL6 0x2257
8765 #define mmDP1_DP_SEC_CNTL6_BASE_IDX 2
8766 #define mmDP1_DP_SEC_CNTL7 0x2258
8767 #define mmDP1_DP_SEC_CNTL7_BASE_IDX 2
8768 #define mmDP1_DP_DB_CNTL 0x2259
8769 #define mmDP1_DP_DB_CNTL_BASE_IDX 2
8770 #define mmDP1_DP_MSA_VBID_MISC 0x225a
8771 #define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2
8774 // addressBlock: dce_dc_dio_dig2_dispdec
8775 // base address: 0x800
8776 #define mmDIG2_DIG_FE_CNTL 0x2268
8777 #define mmDIG2_DIG_FE_CNTL_BASE_IDX 2
8778 #define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x2269
8779 #define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
8780 #define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x226a
8781 #define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
8782 #define mmDIG2_DIG_CLOCK_PATTERN 0x226b
8783 #define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2
8784 #define mmDIG2_DIG_TEST_PATTERN 0x226c
8785 #define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2
8786 #define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x226d
8787 #define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
8788 #define mmDIG2_DIG_FIFO_STATUS 0x226e
8789 #define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2
8790 #define mmDIG2_HDMI_CONTROL 0x2271
8791 #define mmDIG2_HDMI_CONTROL_BASE_IDX 2
8792 #define mmDIG2_HDMI_STATUS 0x2272
8793 #define mmDIG2_HDMI_STATUS_BASE_IDX 2
8794 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2273
8795 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
8796 #define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x2274
8797 #define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
8798 #define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x2275
8799 #define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
8800 #define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x2276
8801 #define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
8802 #define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x2277
8803 #define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
8804 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x2278
8805 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
8806 #define mmDIG2_AFMT_INTERRUPT_STATUS 0x2279
8807 #define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2
8808 #define mmDIG2_HDMI_GC 0x227b
8809 #define mmDIG2_HDMI_GC_BASE_IDX 2
8810 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x227c
8811 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
8812 #define mmDIG2_AFMT_ISRC1_0 0x227d
8813 #define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2
8814 #define mmDIG2_AFMT_ISRC1_1 0x227e
8815 #define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2
8816 #define mmDIG2_AFMT_ISRC1_2 0x227f
8817 #define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2
8818 #define mmDIG2_AFMT_ISRC1_3 0x2280
8819 #define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2
8820 #define mmDIG2_AFMT_ISRC1_4 0x2281
8821 #define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2
8822 #define mmDIG2_AFMT_ISRC2_0 0x2282
8823 #define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2
8824 #define mmDIG2_AFMT_ISRC2_1 0x2283
8825 #define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2
8826 #define mmDIG2_AFMT_ISRC2_2 0x2284
8827 #define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2
8828 #define mmDIG2_AFMT_ISRC2_3 0x2285
8829 #define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2
8830 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x2286
8831 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
8832 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x2287
8833 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
8834 #define mmDIG2_HDMI_DB_CONTROL 0x2288
8835 #define mmDIG2_HDMI_DB_CONTROL_BASE_IDX 2
8836 #define mmDIG2_AFMT_MPEG_INFO0 0x228a
8837 #define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2
8838 #define mmDIG2_AFMT_MPEG_INFO1 0x228b
8839 #define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2
8840 #define mmDIG2_AFMT_GENERIC_HDR 0x228c
8841 #define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2
8842 #define mmDIG2_AFMT_GENERIC_0 0x228d
8843 #define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2
8844 #define mmDIG2_AFMT_GENERIC_1 0x228e
8845 #define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2
8846 #define mmDIG2_AFMT_GENERIC_2 0x228f
8847 #define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2
8848 #define mmDIG2_AFMT_GENERIC_3 0x2290
8849 #define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2
8850 #define mmDIG2_AFMT_GENERIC_4 0x2291
8851 #define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2
8852 #define mmDIG2_AFMT_GENERIC_5 0x2292
8853 #define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2
8854 #define mmDIG2_AFMT_GENERIC_6 0x2293
8855 #define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2
8856 #define mmDIG2_AFMT_GENERIC_7 0x2294
8857 #define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2
8858 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x2295
8859 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
8860 #define mmDIG2_HDMI_ACR_32_0 0x2296
8861 #define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2
8862 #define mmDIG2_HDMI_ACR_32_1 0x2297
8863 #define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2
8864 #define mmDIG2_HDMI_ACR_44_0 0x2298
8865 #define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2
8866 #define mmDIG2_HDMI_ACR_44_1 0x2299
8867 #define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2
8868 #define mmDIG2_HDMI_ACR_48_0 0x229a
8869 #define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2
8870 #define mmDIG2_HDMI_ACR_48_1 0x229b
8871 #define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2
8872 #define mmDIG2_HDMI_ACR_STATUS_0 0x229c
8873 #define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2
8874 #define mmDIG2_HDMI_ACR_STATUS_1 0x229d
8875 #define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2
8876 #define mmDIG2_AFMT_AUDIO_INFO0 0x229e
8877 #define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2
8878 #define mmDIG2_AFMT_AUDIO_INFO1 0x229f
8879 #define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2
8880 #define mmDIG2_AFMT_60958_0 0x22a0
8881 #define mmDIG2_AFMT_60958_0_BASE_IDX 2
8882 #define mmDIG2_AFMT_60958_1 0x22a1
8883 #define mmDIG2_AFMT_60958_1_BASE_IDX 2
8884 #define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x22a2
8885 #define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
8886 #define mmDIG2_AFMT_RAMP_CONTROL0 0x22a3
8887 #define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2
8888 #define mmDIG2_AFMT_RAMP_CONTROL1 0x22a4
8889 #define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2
8890 #define mmDIG2_AFMT_RAMP_CONTROL2 0x22a5
8891 #define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2
8892 #define mmDIG2_AFMT_RAMP_CONTROL3 0x22a6
8893 #define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2
8894 #define mmDIG2_AFMT_60958_2 0x22a7
8895 #define mmDIG2_AFMT_60958_2_BASE_IDX 2
8896 #define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x22a8
8897 #define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
8898 #define mmDIG2_AFMT_STATUS 0x22a9
8899 #define mmDIG2_AFMT_STATUS_BASE_IDX 2
8900 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x22aa
8901 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
8902 #define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x22ab
8903 #define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
8904 #define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x22ac
8905 #define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
8906 #define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x22ad
8907 #define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
8908 #define mmDIG2_DIG_BE_CNTL 0x22af
8909 #define mmDIG2_DIG_BE_CNTL_BASE_IDX 2
8910 #define mmDIG2_DIG_BE_EN_CNTL 0x22b0
8911 #define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2
8912 #define mmDIG2_TMDS_CNTL 0x22d3
8913 #define mmDIG2_TMDS_CNTL_BASE_IDX 2
8914 #define mmDIG2_TMDS_CONTROL_CHAR 0x22d4
8915 #define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2
8916 #define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x22d5
8917 #define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
8918 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22d6
8919 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
8920 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22d7
8921 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
8922 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22d8
8923 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
8924 #define mmDIG2_TMDS_CTL_BITS 0x22da
8925 #define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2
8926 #define mmDIG2_TMDS_DCBALANCER_CONTROL 0x22db
8927 #define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
8928 #define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x22dd
8929 #define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
8930 #define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x22de
8931 #define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
8932 #define mmDIG2_DIG_VERSION 0x22e0
8933 #define mmDIG2_DIG_VERSION_BASE_IDX 2
8934 #define mmDIG2_DIG_LANE_ENABLE 0x22e1
8935 #define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2
8936 #define mmDIG2_AFMT_CNTL 0x22e6
8937 #define mmDIG2_AFMT_CNTL_BASE_IDX 2
8938 #define mmDIG2_AFMT_VBI_PACKET_CONTROL1 0x22e7
8939 #define mmDIG2_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
8942 // addressBlock: dce_dc_dio_dp2_dispdec
8943 // base address: 0x800
8944 #define mmDP2_DP_LINK_CNTL 0x2308
8945 #define mmDP2_DP_LINK_CNTL_BASE_IDX 2
8946 #define mmDP2_DP_PIXEL_FORMAT 0x2309
8947 #define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2
8948 #define mmDP2_DP_MSA_COLORIMETRY 0x230a
8949 #define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2
8950 #define mmDP2_DP_CONFIG 0x230b
8951 #define mmDP2_DP_CONFIG_BASE_IDX 2
8952 #define mmDP2_DP_VID_STREAM_CNTL 0x230c
8953 #define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2
8954 #define mmDP2_DP_STEER_FIFO 0x230d
8955 #define mmDP2_DP_STEER_FIFO_BASE_IDX 2
8956 #define mmDP2_DP_MSA_MISC 0x230e
8957 #define mmDP2_DP_MSA_MISC_BASE_IDX 2
8958 #define mmDP2_DP_VID_TIMING 0x2310
8959 #define mmDP2_DP_VID_TIMING_BASE_IDX 2
8960 #define mmDP2_DP_VID_N 0x2311
8961 #define mmDP2_DP_VID_N_BASE_IDX 2
8962 #define mmDP2_DP_VID_M 0x2312
8963 #define mmDP2_DP_VID_M_BASE_IDX 2
8964 #define mmDP2_DP_LINK_FRAMING_CNTL 0x2313
8965 #define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2
8966 #define mmDP2_DP_HBR2_EYE_PATTERN 0x2314
8967 #define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2
8968 #define mmDP2_DP_VID_MSA_VBID 0x2315
8969 #define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2
8970 #define mmDP2_DP_VID_INTERRUPT_CNTL 0x2316
8971 #define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
8972 #define mmDP2_DP_DPHY_CNTL 0x2317
8973 #define mmDP2_DP_DPHY_CNTL_BASE_IDX 2
8974 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318
8975 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
8976 #define mmDP2_DP_DPHY_SYM0 0x2319
8977 #define mmDP2_DP_DPHY_SYM0_BASE_IDX 2
8978 #define mmDP2_DP_DPHY_SYM1 0x231a
8979 #define mmDP2_DP_DPHY_SYM1_BASE_IDX 2
8980 #define mmDP2_DP_DPHY_SYM2 0x231b
8981 #define mmDP2_DP_DPHY_SYM2_BASE_IDX 2
8982 #define mmDP2_DP_DPHY_8B10B_CNTL 0x231c
8983 #define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2
8984 #define mmDP2_DP_DPHY_PRBS_CNTL 0x231d
8985 #define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2
8986 #define mmDP2_DP_DPHY_SCRAM_CNTL 0x231e
8987 #define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
8988 #define mmDP2_DP_DPHY_CRC_EN 0x231f
8989 #define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2
8990 #define mmDP2_DP_DPHY_CRC_CNTL 0x2320
8991 #define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2
8992 #define mmDP2_DP_DPHY_CRC_RESULT 0x2321
8993 #define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2
8994 #define mmDP2_DP_DPHY_CRC_MST_CNTL 0x2322
8995 #define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
8996 #define mmDP2_DP_DPHY_CRC_MST_STATUS 0x2323
8997 #define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
8998 #define mmDP2_DP_DPHY_FAST_TRAINING 0x2324
8999 #define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2
9000 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325
9001 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
9002 #define mmDP2_DP_SEC_CNTL 0x232b
9003 #define mmDP2_DP_SEC_CNTL_BASE_IDX 2
9004 #define mmDP2_DP_SEC_CNTL1 0x232c
9005 #define mmDP2_DP_SEC_CNTL1_BASE_IDX 2
9006 #define mmDP2_DP_SEC_FRAMING1 0x232d
9007 #define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2
9008 #define mmDP2_DP_SEC_FRAMING2 0x232e
9009 #define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2
9010 #define mmDP2_DP_SEC_FRAMING3 0x232f
9011 #define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2
9012 #define mmDP2_DP_SEC_FRAMING4 0x2330
9013 #define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2
9014 #define mmDP2_DP_SEC_AUD_N 0x2331
9015 #define mmDP2_DP_SEC_AUD_N_BASE_IDX 2
9016 #define mmDP2_DP_SEC_AUD_N_READBACK 0x2332
9017 #define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2
9018 #define mmDP2_DP_SEC_AUD_M 0x2333
9019 #define mmDP2_DP_SEC_AUD_M_BASE_IDX 2
9020 #define mmDP2_DP_SEC_AUD_M_READBACK 0x2334
9021 #define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2
9022 #define mmDP2_DP_SEC_TIMESTAMP 0x2335
9023 #define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2
9024 #define mmDP2_DP_SEC_PACKET_CNTL 0x2336
9025 #define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2
9026 #define mmDP2_DP_MSE_RATE_CNTL 0x2337
9027 #define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2
9028 #define mmDP2_DP_MSE_RATE_UPDATE 0x2339
9029 #define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2
9030 #define mmDP2_DP_MSE_SAT0 0x233a
9031 #define mmDP2_DP_MSE_SAT0_BASE_IDX 2
9032 #define mmDP2_DP_MSE_SAT1 0x233b
9033 #define mmDP2_DP_MSE_SAT1_BASE_IDX 2
9034 #define mmDP2_DP_MSE_SAT2 0x233c
9035 #define mmDP2_DP_MSE_SAT2_BASE_IDX 2
9036 #define mmDP2_DP_MSE_SAT_UPDATE 0x233d
9037 #define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2
9038 #define mmDP2_DP_MSE_LINK_TIMING 0x233e
9039 #define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2
9040 #define mmDP2_DP_MSE_MISC_CNTL 0x233f
9041 #define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2
9042 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344
9043 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
9044 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345
9045 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
9046 #define mmDP2_DP_MSE_SAT0_STATUS 0x2347
9047 #define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2
9048 #define mmDP2_DP_MSE_SAT1_STATUS 0x2348
9049 #define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2
9050 #define mmDP2_DP_MSE_SAT2_STATUS 0x2349
9051 #define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2
9052 #define mmDP2_DP_MSA_TIMING_PARAM1 0x234c
9053 #define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2
9054 #define mmDP2_DP_MSA_TIMING_PARAM2 0x234d
9055 #define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2
9056 #define mmDP2_DP_MSA_TIMING_PARAM3 0x234e
9057 #define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2
9058 #define mmDP2_DP_MSA_TIMING_PARAM4 0x234f
9059 #define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2
9060 #define mmDP2_DP_MSO_CNTL 0x2350
9061 #define mmDP2_DP_MSO_CNTL_BASE_IDX 2
9062 #define mmDP2_DP_MSO_CNTL1 0x2351
9063 #define mmDP2_DP_MSO_CNTL1_BASE_IDX 2
9064 #define mmDP2_DP_DSC_CNTL 0x2352
9065 #define mmDP2_DP_DSC_CNTL_BASE_IDX 2
9066 #define mmDP2_DP_SEC_CNTL2 0x2353
9067 #define mmDP2_DP_SEC_CNTL2_BASE_IDX 2
9068 #define mmDP2_DP_SEC_CNTL3 0x2354
9069 #define mmDP2_DP_SEC_CNTL3_BASE_IDX 2
9070 #define mmDP2_DP_SEC_CNTL4 0x2355
9071 #define mmDP2_DP_SEC_CNTL4_BASE_IDX 2
9072 #define mmDP2_DP_SEC_CNTL5 0x2356
9073 #define mmDP2_DP_SEC_CNTL5_BASE_IDX 2
9074 #define mmDP2_DP_SEC_CNTL6 0x2357
9075 #define mmDP2_DP_SEC_CNTL6_BASE_IDX 2
9076 #define mmDP2_DP_SEC_CNTL7 0x2358
9077 #define mmDP2_DP_SEC_CNTL7_BASE_IDX 2
9078 #define mmDP2_DP_DB_CNTL 0x2359
9079 #define mmDP2_DP_DB_CNTL_BASE_IDX 2
9080 #define mmDP2_DP_MSA_VBID_MISC 0x235a
9081 #define mmDP2_DP_MSA_VBID_MISC_BASE_IDX 2
9084 // addressBlock: dce_dc_dio_dig3_dispdec
9085 // base address: 0xc00
9086 #define mmDIG3_DIG_FE_CNTL 0x2368
9087 #define mmDIG3_DIG_FE_CNTL_BASE_IDX 2
9088 #define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x2369
9089 #define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
9090 #define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x236a
9091 #define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
9092 #define mmDIG3_DIG_CLOCK_PATTERN 0x236b
9093 #define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2
9094 #define mmDIG3_DIG_TEST_PATTERN 0x236c
9095 #define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2
9096 #define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x236d
9097 #define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
9098 #define mmDIG3_DIG_FIFO_STATUS 0x236e
9099 #define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2
9100 #define mmDIG3_HDMI_CONTROL 0x2371
9101 #define mmDIG3_HDMI_CONTROL_BASE_IDX 2
9102 #define mmDIG3_HDMI_STATUS 0x2372
9103 #define mmDIG3_HDMI_STATUS_BASE_IDX 2
9104 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2373
9105 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
9106 #define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x2374
9107 #define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
9108 #define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x2375
9109 #define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
9110 #define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x2376
9111 #define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
9112 #define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x2377
9113 #define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
9114 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2378
9115 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
9116 #define mmDIG3_AFMT_INTERRUPT_STATUS 0x2379
9117 #define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2
9118 #define mmDIG3_HDMI_GC 0x237b
9119 #define mmDIG3_HDMI_GC_BASE_IDX 2
9120 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x237c
9121 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
9122 #define mmDIG3_AFMT_ISRC1_0 0x237d
9123 #define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2
9124 #define mmDIG3_AFMT_ISRC1_1 0x237e
9125 #define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2
9126 #define mmDIG3_AFMT_ISRC1_2 0x237f
9127 #define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2
9128 #define mmDIG3_AFMT_ISRC1_3 0x2380
9129 #define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2
9130 #define mmDIG3_AFMT_ISRC1_4 0x2381
9131 #define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2
9132 #define mmDIG3_AFMT_ISRC2_0 0x2382
9133 #define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2
9134 #define mmDIG3_AFMT_ISRC2_1 0x2383
9135 #define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2
9136 #define mmDIG3_AFMT_ISRC2_2 0x2384
9137 #define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2
9138 #define mmDIG3_AFMT_ISRC2_3 0x2385
9139 #define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2
9140 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2386
9141 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
9142 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2387
9143 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
9144 #define mmDIG3_HDMI_DB_CONTROL 0x2388
9145 #define mmDIG3_HDMI_DB_CONTROL_BASE_IDX 2
9146 #define mmDIG3_AFMT_MPEG_INFO0 0x238a
9147 #define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2
9148 #define mmDIG3_AFMT_MPEG_INFO1 0x238b
9149 #define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2
9150 #define mmDIG3_AFMT_GENERIC_HDR 0x238c
9151 #define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2
9152 #define mmDIG3_AFMT_GENERIC_0 0x238d
9153 #define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2
9154 #define mmDIG3_AFMT_GENERIC_1 0x238e
9155 #define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2
9156 #define mmDIG3_AFMT_GENERIC_2 0x238f
9157 #define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2
9158 #define mmDIG3_AFMT_GENERIC_3 0x2390
9159 #define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2
9160 #define mmDIG3_AFMT_GENERIC_4 0x2391
9161 #define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2
9162 #define mmDIG3_AFMT_GENERIC_5 0x2392
9163 #define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2
9164 #define mmDIG3_AFMT_GENERIC_6 0x2393
9165 #define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2
9166 #define mmDIG3_AFMT_GENERIC_7 0x2394
9167 #define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2
9168 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2395
9169 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
9170 #define mmDIG3_HDMI_ACR_32_0 0x2396
9171 #define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2
9172 #define mmDIG3_HDMI_ACR_32_1 0x2397
9173 #define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2
9174 #define mmDIG3_HDMI_ACR_44_0 0x2398
9175 #define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2
9176 #define mmDIG3_HDMI_ACR_44_1 0x2399
9177 #define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2
9178 #define mmDIG3_HDMI_ACR_48_0 0x239a
9179 #define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2
9180 #define mmDIG3_HDMI_ACR_48_1 0x239b
9181 #define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2
9182 #define mmDIG3_HDMI_ACR_STATUS_0 0x239c
9183 #define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2
9184 #define mmDIG3_HDMI_ACR_STATUS_1 0x239d
9185 #define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2
9186 #define mmDIG3_AFMT_AUDIO_INFO0 0x239e
9187 #define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2
9188 #define mmDIG3_AFMT_AUDIO_INFO1 0x239f
9189 #define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2
9190 #define mmDIG3_AFMT_60958_0 0x23a0
9191 #define mmDIG3_AFMT_60958_0_BASE_IDX 2
9192 #define mmDIG3_AFMT_60958_1 0x23a1
9193 #define mmDIG3_AFMT_60958_1_BASE_IDX 2
9194 #define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x23a2
9195 #define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
9196 #define mmDIG3_AFMT_RAMP_CONTROL0 0x23a3
9197 #define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2
9198 #define mmDIG3_AFMT_RAMP_CONTROL1 0x23a4
9199 #define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2
9200 #define mmDIG3_AFMT_RAMP_CONTROL2 0x23a5
9201 #define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2
9202 #define mmDIG3_AFMT_RAMP_CONTROL3 0x23a6
9203 #define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2
9204 #define mmDIG3_AFMT_60958_2 0x23a7
9205 #define mmDIG3_AFMT_60958_2_BASE_IDX 2
9206 #define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x23a8
9207 #define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
9208 #define mmDIG3_AFMT_STATUS 0x23a9
9209 #define mmDIG3_AFMT_STATUS_BASE_IDX 2
9210 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x23aa
9211 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
9212 #define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x23ab
9213 #define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
9214 #define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x23ac
9215 #define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
9216 #define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x23ad
9217 #define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
9218 #define mmDIG3_DIG_BE_CNTL 0x23af
9219 #define mmDIG3_DIG_BE_CNTL_BASE_IDX 2
9220 #define mmDIG3_DIG_BE_EN_CNTL 0x23b0
9221 #define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2
9222 #define mmDIG3_TMDS_CNTL 0x23d3
9223 #define mmDIG3_TMDS_CNTL_BASE_IDX 2
9224 #define mmDIG3_TMDS_CONTROL_CHAR 0x23d4
9225 #define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2
9226 #define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x23d5
9227 #define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
9228 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23d6
9229 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
9230 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23d7
9231 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
9232 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23d8
9233 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
9234 #define mmDIG3_TMDS_CTL_BITS 0x23da
9235 #define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2
9236 #define mmDIG3_TMDS_DCBALANCER_CONTROL 0x23db
9237 #define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
9238 #define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x23dd
9239 #define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
9240 #define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x23de
9241 #define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
9242 #define mmDIG3_DIG_VERSION 0x23e0
9243 #define mmDIG3_DIG_VERSION_BASE_IDX 2
9244 #define mmDIG3_DIG_LANE_ENABLE 0x23e1
9245 #define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2
9246 #define mmDIG3_AFMT_CNTL 0x23e6
9247 #define mmDIG3_AFMT_CNTL_BASE_IDX 2
9248 #define mmDIG3_AFMT_VBI_PACKET_CONTROL1 0x23e7
9249 #define mmDIG3_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
9252 // addressBlock: dce_dc_dio_dp3_dispdec
9253 // base address: 0xc00
9254 #define mmDP3_DP_LINK_CNTL 0x2408
9255 #define mmDP3_DP_LINK_CNTL_BASE_IDX 2
9256 #define mmDP3_DP_PIXEL_FORMAT 0x2409
9257 #define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2
9258 #define mmDP3_DP_MSA_COLORIMETRY 0x240a
9259 #define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2
9260 #define mmDP3_DP_CONFIG 0x240b
9261 #define mmDP3_DP_CONFIG_BASE_IDX 2
9262 #define mmDP3_DP_VID_STREAM_CNTL 0x240c
9263 #define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2
9264 #define mmDP3_DP_STEER_FIFO 0x240d
9265 #define mmDP3_DP_STEER_FIFO_BASE_IDX 2
9266 #define mmDP3_DP_MSA_MISC 0x240e
9267 #define mmDP3_DP_MSA_MISC_BASE_IDX 2
9268 #define mmDP3_DP_VID_TIMING 0x2410
9269 #define mmDP3_DP_VID_TIMING_BASE_IDX 2
9270 #define mmDP3_DP_VID_N 0x2411
9271 #define mmDP3_DP_VID_N_BASE_IDX 2
9272 #define mmDP3_DP_VID_M 0x2412
9273 #define mmDP3_DP_VID_M_BASE_IDX 2
9274 #define mmDP3_DP_LINK_FRAMING_CNTL 0x2413
9275 #define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2
9276 #define mmDP3_DP_HBR2_EYE_PATTERN 0x2414
9277 #define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2
9278 #define mmDP3_DP_VID_MSA_VBID 0x2415
9279 #define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2
9280 #define mmDP3_DP_VID_INTERRUPT_CNTL 0x2416
9281 #define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
9282 #define mmDP3_DP_DPHY_CNTL 0x2417
9283 #define mmDP3_DP_DPHY_CNTL_BASE_IDX 2
9284 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418
9285 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
9286 #define mmDP3_DP_DPHY_SYM0 0x2419
9287 #define mmDP3_DP_DPHY_SYM0_BASE_IDX 2
9288 #define mmDP3_DP_DPHY_SYM1 0x241a
9289 #define mmDP3_DP_DPHY_SYM1_BASE_IDX 2
9290 #define mmDP3_DP_DPHY_SYM2 0x241b
9291 #define mmDP3_DP_DPHY_SYM2_BASE_IDX 2
9292 #define mmDP3_DP_DPHY_8B10B_CNTL 0x241c
9293 #define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2
9294 #define mmDP3_DP_DPHY_PRBS_CNTL 0x241d
9295 #define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2
9296 #define mmDP3_DP_DPHY_SCRAM_CNTL 0x241e
9297 #define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
9298 #define mmDP3_DP_DPHY_CRC_EN 0x241f
9299 #define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2
9300 #define mmDP3_DP_DPHY_CRC_CNTL 0x2420
9301 #define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2
9302 #define mmDP3_DP_DPHY_CRC_RESULT 0x2421
9303 #define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2
9304 #define mmDP3_DP_DPHY_CRC_MST_CNTL 0x2422
9305 #define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
9306 #define mmDP3_DP_DPHY_CRC_MST_STATUS 0x2423
9307 #define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
9308 #define mmDP3_DP_DPHY_FAST_TRAINING 0x2424
9309 #define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2
9310 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425
9311 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
9312 #define mmDP3_DP_SEC_CNTL 0x242b
9313 #define mmDP3_DP_SEC_CNTL_BASE_IDX 2
9314 #define mmDP3_DP_SEC_CNTL1 0x242c
9315 #define mmDP3_DP_SEC_CNTL1_BASE_IDX 2
9316 #define mmDP3_DP_SEC_FRAMING1 0x242d
9317 #define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2
9318 #define mmDP3_DP_SEC_FRAMING2 0x242e
9319 #define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2
9320 #define mmDP3_DP_SEC_FRAMING3 0x242f
9321 #define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2
9322 #define mmDP3_DP_SEC_FRAMING4 0x2430
9323 #define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2
9324 #define mmDP3_DP_SEC_AUD_N 0x2431
9325 #define mmDP3_DP_SEC_AUD_N_BASE_IDX 2
9326 #define mmDP3_DP_SEC_AUD_N_READBACK 0x2432
9327 #define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2
9328 #define mmDP3_DP_SEC_AUD_M 0x2433
9329 #define mmDP3_DP_SEC_AUD_M_BASE_IDX 2
9330 #define mmDP3_DP_SEC_AUD_M_READBACK 0x2434
9331 #define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2
9332 #define mmDP3_DP_SEC_TIMESTAMP 0x2435
9333 #define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2
9334 #define mmDP3_DP_SEC_PACKET_CNTL 0x2436
9335 #define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2
9336 #define mmDP3_DP_MSE_RATE_CNTL 0x2437
9337 #define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2
9338 #define mmDP3_DP_MSE_RATE_UPDATE 0x2439
9339 #define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2
9340 #define mmDP3_DP_MSE_SAT0 0x243a
9341 #define mmDP3_DP_MSE_SAT0_BASE_IDX 2
9342 #define mmDP3_DP_MSE_SAT1 0x243b
9343 #define mmDP3_DP_MSE_SAT1_BASE_IDX 2
9344 #define mmDP3_DP_MSE_SAT2 0x243c
9345 #define mmDP3_DP_MSE_SAT2_BASE_IDX 2
9346 #define mmDP3_DP_MSE_SAT_UPDATE 0x243d
9347 #define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2
9348 #define mmDP3_DP_MSE_LINK_TIMING 0x243e
9349 #define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2
9350 #define mmDP3_DP_MSE_MISC_CNTL 0x243f
9351 #define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2
9352 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444
9353 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
9354 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445
9355 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
9356 #define mmDP3_DP_MSE_SAT0_STATUS 0x2447
9357 #define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2
9358 #define mmDP3_DP_MSE_SAT1_STATUS 0x2448
9359 #define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2
9360 #define mmDP3_DP_MSE_SAT2_STATUS 0x2449
9361 #define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2
9362 #define mmDP3_DP_MSA_TIMING_PARAM1 0x244c
9363 #define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2
9364 #define mmDP3_DP_MSA_TIMING_PARAM2 0x244d
9365 #define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2
9366 #define mmDP3_DP_MSA_TIMING_PARAM3 0x244e
9367 #define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2
9368 #define mmDP3_DP_MSA_TIMING_PARAM4 0x244f
9369 #define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2
9370 #define mmDP3_DP_MSO_CNTL 0x2450
9371 #define mmDP3_DP_MSO_CNTL_BASE_IDX 2
9372 #define mmDP3_DP_MSO_CNTL1 0x2451
9373 #define mmDP3_DP_MSO_CNTL1_BASE_IDX 2
9374 #define mmDP3_DP_DSC_CNTL 0x2452
9375 #define mmDP3_DP_DSC_CNTL_BASE_IDX 2
9376 #define mmDP3_DP_SEC_CNTL2 0x2453
9377 #define mmDP3_DP_SEC_CNTL2_BASE_IDX 2
9378 #define mmDP3_DP_SEC_CNTL3 0x2454
9379 #define mmDP3_DP_SEC_CNTL3_BASE_IDX 2
9380 #define mmDP3_DP_SEC_CNTL4 0x2455
9381 #define mmDP3_DP_SEC_CNTL4_BASE_IDX 2
9382 #define mmDP3_DP_SEC_CNTL5 0x2456
9383 #define mmDP3_DP_SEC_CNTL5_BASE_IDX 2
9384 #define mmDP3_DP_SEC_CNTL6 0x2457
9385 #define mmDP3_DP_SEC_CNTL6_BASE_IDX 2
9386 #define mmDP3_DP_SEC_CNTL7 0x2458
9387 #define mmDP3_DP_SEC_CNTL7_BASE_IDX 2
9388 #define mmDP3_DP_DB_CNTL 0x2459
9389 #define mmDP3_DP_DB_CNTL_BASE_IDX 2
9390 #define mmDP3_DP_MSA_VBID_MISC 0x245a
9391 #define mmDP3_DP_MSA_VBID_MISC_BASE_IDX 2
9394 // addressBlock: dce_dc_dio_dig4_dispdec
9395 // base address: 0x1000
9396 #define mmDIG4_DIG_FE_CNTL 0x2468
9397 #define mmDIG4_DIG_FE_CNTL_BASE_IDX 2
9398 #define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x2469
9399 #define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
9400 #define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x246a
9401 #define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
9402 #define mmDIG4_DIG_CLOCK_PATTERN 0x246b
9403 #define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2
9404 #define mmDIG4_DIG_TEST_PATTERN 0x246c
9405 #define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2
9406 #define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x246d
9407 #define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
9408 #define mmDIG4_DIG_FIFO_STATUS 0x246e
9409 #define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2
9410 #define mmDIG4_HDMI_CONTROL 0x2471
9411 #define mmDIG4_HDMI_CONTROL_BASE_IDX 2
9412 #define mmDIG4_HDMI_STATUS 0x2472
9413 #define mmDIG4_HDMI_STATUS_BASE_IDX 2
9414 #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2473
9415 #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
9416 #define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x2474
9417 #define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
9418 #define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x2475
9419 #define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
9420 #define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x2476
9421 #define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
9422 #define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x2477
9423 #define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
9424 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x2478
9425 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
9426 #define mmDIG4_AFMT_INTERRUPT_STATUS 0x2479
9427 #define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2
9428 #define mmDIG4_HDMI_GC 0x247b
9429 #define mmDIG4_HDMI_GC_BASE_IDX 2
9430 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x247c
9431 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
9432 #define mmDIG4_AFMT_ISRC1_0 0x247d
9433 #define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2
9434 #define mmDIG4_AFMT_ISRC1_1 0x247e
9435 #define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2
9436 #define mmDIG4_AFMT_ISRC1_2 0x247f
9437 #define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2
9438 #define mmDIG4_AFMT_ISRC1_3 0x2480
9439 #define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2
9440 #define mmDIG4_AFMT_ISRC1_4 0x2481
9441 #define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2
9442 #define mmDIG4_AFMT_ISRC2_0 0x2482
9443 #define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2
9444 #define mmDIG4_AFMT_ISRC2_1 0x2483
9445 #define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2
9446 #define mmDIG4_AFMT_ISRC2_2 0x2484
9447 #define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2
9448 #define mmDIG4_AFMT_ISRC2_3 0x2485
9449 #define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2
9450 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x2486
9451 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
9452 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x2487
9453 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
9454 #define mmDIG4_HDMI_DB_CONTROL 0x2488
9455 #define mmDIG4_HDMI_DB_CONTROL_BASE_IDX 2
9456 #define mmDIG4_AFMT_MPEG_INFO0 0x248a
9457 #define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2
9458 #define mmDIG4_AFMT_MPEG_INFO1 0x248b
9459 #define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2
9460 #define mmDIG4_AFMT_GENERIC_HDR 0x248c
9461 #define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2
9462 #define mmDIG4_AFMT_GENERIC_0 0x248d
9463 #define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2
9464 #define mmDIG4_AFMT_GENERIC_1 0x248e
9465 #define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2
9466 #define mmDIG4_AFMT_GENERIC_2 0x248f
9467 #define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2
9468 #define mmDIG4_AFMT_GENERIC_3 0x2490
9469 #define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2
9470 #define mmDIG4_AFMT_GENERIC_4 0x2491
9471 #define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2
9472 #define mmDIG4_AFMT_GENERIC_5 0x2492
9473 #define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2
9474 #define mmDIG4_AFMT_GENERIC_6 0x2493
9475 #define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2
9476 #define mmDIG4_AFMT_GENERIC_7 0x2494
9477 #define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2
9478 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x2495
9479 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
9480 #define mmDIG4_HDMI_ACR_32_0 0x2496
9481 #define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2
9482 #define mmDIG4_HDMI_ACR_32_1 0x2497
9483 #define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2
9484 #define mmDIG4_HDMI_ACR_44_0 0x2498
9485 #define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2
9486 #define mmDIG4_HDMI_ACR_44_1 0x2499
9487 #define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2
9488 #define mmDIG4_HDMI_ACR_48_0 0x249a
9489 #define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2
9490 #define mmDIG4_HDMI_ACR_48_1 0x249b
9491 #define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2
9492 #define mmDIG4_HDMI_ACR_STATUS_0 0x249c
9493 #define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2
9494 #define mmDIG4_HDMI_ACR_STATUS_1 0x249d
9495 #define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2
9496 #define mmDIG4_AFMT_AUDIO_INFO0 0x249e
9497 #define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2
9498 #define mmDIG4_AFMT_AUDIO_INFO1 0x249f
9499 #define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2
9500 #define mmDIG4_AFMT_60958_0 0x24a0
9501 #define mmDIG4_AFMT_60958_0_BASE_IDX 2
9502 #define mmDIG4_AFMT_60958_1 0x24a1
9503 #define mmDIG4_AFMT_60958_1_BASE_IDX 2
9504 #define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x24a2
9505 #define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
9506 #define mmDIG4_AFMT_RAMP_CONTROL0 0x24a3
9507 #define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2
9508 #define mmDIG4_AFMT_RAMP_CONTROL1 0x24a4
9509 #define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2
9510 #define mmDIG4_AFMT_RAMP_CONTROL2 0x24a5
9511 #define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2
9512 #define mmDIG4_AFMT_RAMP_CONTROL3 0x24a6
9513 #define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2
9514 #define mmDIG4_AFMT_60958_2 0x24a7
9515 #define mmDIG4_AFMT_60958_2_BASE_IDX 2
9516 #define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x24a8
9517 #define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
9518 #define mmDIG4_AFMT_STATUS 0x24a9
9519 #define mmDIG4_AFMT_STATUS_BASE_IDX 2
9520 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x24aa
9521 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
9522 #define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x24ab
9523 #define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
9524 #define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x24ac
9525 #define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
9526 #define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x24ad
9527 #define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
9528 #define mmDIG4_DIG_BE_CNTL 0x24af
9529 #define mmDIG4_DIG_BE_CNTL_BASE_IDX 2
9530 #define mmDIG4_DIG_BE_EN_CNTL 0x24b0
9531 #define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2
9532 #define mmDIG4_TMDS_CNTL 0x24d3
9533 #define mmDIG4_TMDS_CNTL_BASE_IDX 2
9534 #define mmDIG4_TMDS_CONTROL_CHAR 0x24d4
9535 #define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2
9536 #define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x24d5
9537 #define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
9538 #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24d6
9539 #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
9540 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24d7
9541 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
9542 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24d8
9543 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
9544 #define mmDIG4_TMDS_CTL_BITS 0x24da
9545 #define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2
9546 #define mmDIG4_TMDS_DCBALANCER_CONTROL 0x24db
9547 #define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
9548 #define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x24dd
9549 #define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
9550 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x24de
9551 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
9552 #define mmDIG4_DIG_VERSION 0x24e0
9553 #define mmDIG4_DIG_VERSION_BASE_IDX 2
9554 #define mmDIG4_DIG_LANE_ENABLE 0x24e1
9555 #define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2
9556 #define mmDIG4_AFMT_CNTL 0x24e6
9557 #define mmDIG4_AFMT_CNTL_BASE_IDX 2
9558 #define mmDIG4_AFMT_VBI_PACKET_CONTROL1 0x24e7
9559 #define mmDIG4_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
9562 // addressBlock: dce_dc_dio_dp4_dispdec
9563 // base address: 0x1000
9564 #define mmDP4_DP_LINK_CNTL 0x2508
9565 #define mmDP4_DP_LINK_CNTL_BASE_IDX 2
9566 #define mmDP4_DP_PIXEL_FORMAT 0x2509
9567 #define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2
9568 #define mmDP4_DP_MSA_COLORIMETRY 0x250a
9569 #define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2
9570 #define mmDP4_DP_CONFIG 0x250b
9571 #define mmDP4_DP_CONFIG_BASE_IDX 2
9572 #define mmDP4_DP_VID_STREAM_CNTL 0x250c
9573 #define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2
9574 #define mmDP4_DP_STEER_FIFO 0x250d
9575 #define mmDP4_DP_STEER_FIFO_BASE_IDX 2
9576 #define mmDP4_DP_MSA_MISC 0x250e
9577 #define mmDP4_DP_MSA_MISC_BASE_IDX 2
9578 #define mmDP4_DP_VID_TIMING 0x2510
9579 #define mmDP4_DP_VID_TIMING_BASE_IDX 2
9580 #define mmDP4_DP_VID_N 0x2511
9581 #define mmDP4_DP_VID_N_BASE_IDX 2
9582 #define mmDP4_DP_VID_M 0x2512
9583 #define mmDP4_DP_VID_M_BASE_IDX 2
9584 #define mmDP4_DP_LINK_FRAMING_CNTL 0x2513
9585 #define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2
9586 #define mmDP4_DP_HBR2_EYE_PATTERN 0x2514
9587 #define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2
9588 #define mmDP4_DP_VID_MSA_VBID 0x2515
9589 #define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2
9590 #define mmDP4_DP_VID_INTERRUPT_CNTL 0x2516
9591 #define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
9592 #define mmDP4_DP_DPHY_CNTL 0x2517
9593 #define mmDP4_DP_DPHY_CNTL_BASE_IDX 2
9594 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518
9595 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
9596 #define mmDP4_DP_DPHY_SYM0 0x2519
9597 #define mmDP4_DP_DPHY_SYM0_BASE_IDX 2
9598 #define mmDP4_DP_DPHY_SYM1 0x251a
9599 #define mmDP4_DP_DPHY_SYM1_BASE_IDX 2
9600 #define mmDP4_DP_DPHY_SYM2 0x251b
9601 #define mmDP4_DP_DPHY_SYM2_BASE_IDX 2
9602 #define mmDP4_DP_DPHY_8B10B_CNTL 0x251c
9603 #define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2
9604 #define mmDP4_DP_DPHY_PRBS_CNTL 0x251d
9605 #define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2
9606 #define mmDP4_DP_DPHY_SCRAM_CNTL 0x251e
9607 #define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
9608 #define mmDP4_DP_DPHY_CRC_EN 0x251f
9609 #define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2
9610 #define mmDP4_DP_DPHY_CRC_CNTL 0x2520
9611 #define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2
9612 #define mmDP4_DP_DPHY_CRC_RESULT 0x2521
9613 #define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2
9614 #define mmDP4_DP_DPHY_CRC_MST_CNTL 0x2522
9615 #define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
9616 #define mmDP4_DP_DPHY_CRC_MST_STATUS 0x2523
9617 #define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
9618 #define mmDP4_DP_DPHY_FAST_TRAINING 0x2524
9619 #define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2
9620 #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525
9621 #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
9622 #define mmDP4_DP_SEC_CNTL 0x252b
9623 #define mmDP4_DP_SEC_CNTL_BASE_IDX 2
9624 #define mmDP4_DP_SEC_CNTL1 0x252c
9625 #define mmDP4_DP_SEC_CNTL1_BASE_IDX 2
9626 #define mmDP4_DP_SEC_FRAMING1 0x252d
9627 #define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2
9628 #define mmDP4_DP_SEC_FRAMING2 0x252e
9629 #define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2
9630 #define mmDP4_DP_SEC_FRAMING3 0x252f
9631 #define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2
9632 #define mmDP4_DP_SEC_FRAMING4 0x2530
9633 #define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2
9634 #define mmDP4_DP_SEC_AUD_N 0x2531
9635 #define mmDP4_DP_SEC_AUD_N_BASE_IDX 2
9636 #define mmDP4_DP_SEC_AUD_N_READBACK 0x2532
9637 #define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2
9638 #define mmDP4_DP_SEC_AUD_M 0x2533
9639 #define mmDP4_DP_SEC_AUD_M_BASE_IDX 2
9640 #define mmDP4_DP_SEC_AUD_M_READBACK 0x2534
9641 #define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2
9642 #define mmDP4_DP_SEC_TIMESTAMP 0x2535
9643 #define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2
9644 #define mmDP4_DP_SEC_PACKET_CNTL 0x2536
9645 #define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2
9646 #define mmDP4_DP_MSE_RATE_CNTL 0x2537
9647 #define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2
9648 #define mmDP4_DP_MSE_RATE_UPDATE 0x2539
9649 #define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2
9650 #define mmDP4_DP_MSE_SAT0 0x253a
9651 #define mmDP4_DP_MSE_SAT0_BASE_IDX 2
9652 #define mmDP4_DP_MSE_SAT1 0x253b
9653 #define mmDP4_DP_MSE_SAT1_BASE_IDX 2
9654 #define mmDP4_DP_MSE_SAT2 0x253c
9655 #define mmDP4_DP_MSE_SAT2_BASE_IDX 2
9656 #define mmDP4_DP_MSE_SAT_UPDATE 0x253d
9657 #define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2
9658 #define mmDP4_DP_MSE_LINK_TIMING 0x253e
9659 #define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2
9660 #define mmDP4_DP_MSE_MISC_CNTL 0x253f
9661 #define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2
9662 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544
9663 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
9664 #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545
9665 #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
9666 #define mmDP4_DP_MSE_SAT0_STATUS 0x2547
9667 #define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2
9668 #define mmDP4_DP_MSE_SAT1_STATUS 0x2548
9669 #define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2
9670 #define mmDP4_DP_MSE_SAT2_STATUS 0x2549
9671 #define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2
9672 #define mmDP4_DP_MSA_TIMING_PARAM1 0x254c
9673 #define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2
9674 #define mmDP4_DP_MSA_TIMING_PARAM2 0x254d
9675 #define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2
9676 #define mmDP4_DP_MSA_TIMING_PARAM3 0x254e
9677 #define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2
9678 #define mmDP4_DP_MSA_TIMING_PARAM4 0x254f
9679 #define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2
9680 #define mmDP4_DP_MSO_CNTL 0x2550
9681 #define mmDP4_DP_MSO_CNTL_BASE_IDX 2
9682 #define mmDP4_DP_MSO_CNTL1 0x2551
9683 #define mmDP4_DP_MSO_CNTL1_BASE_IDX 2
9684 #define mmDP4_DP_DSC_CNTL 0x2552
9685 #define mmDP4_DP_DSC_CNTL_BASE_IDX 2
9686 #define mmDP4_DP_SEC_CNTL2 0x2553
9687 #define mmDP4_DP_SEC_CNTL2_BASE_IDX 2
9688 #define mmDP4_DP_SEC_CNTL3 0x2554
9689 #define mmDP4_DP_SEC_CNTL3_BASE_IDX 2
9690 #define mmDP4_DP_SEC_CNTL4 0x2555
9691 #define mmDP4_DP_SEC_CNTL4_BASE_IDX 2
9692 #define mmDP4_DP_SEC_CNTL5 0x2556
9693 #define mmDP4_DP_SEC_CNTL5_BASE_IDX 2
9694 #define mmDP4_DP_SEC_CNTL6 0x2557
9695 #define mmDP4_DP_SEC_CNTL6_BASE_IDX 2
9696 #define mmDP4_DP_SEC_CNTL7 0x2558
9697 #define mmDP4_DP_SEC_CNTL7_BASE_IDX 2
9698 #define mmDP4_DP_DB_CNTL 0x2559
9699 #define mmDP4_DP_DB_CNTL_BASE_IDX 2
9700 #define mmDP4_DP_MSA_VBID_MISC 0x255a
9701 #define mmDP4_DP_MSA_VBID_MISC_BASE_IDX 2
9704 // addressBlock: dce_dc_dio_dig5_dispdec
9705 // base address: 0x1400
9706 #define mmDIG5_DIG_FE_CNTL 0x2568
9707 #define mmDIG5_DIG_FE_CNTL_BASE_IDX 2
9708 #define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x2569
9709 #define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
9710 #define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x256a
9711 #define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
9712 #define mmDIG5_DIG_CLOCK_PATTERN 0x256b
9713 #define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2
9714 #define mmDIG5_DIG_TEST_PATTERN 0x256c
9715 #define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2
9716 #define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x256d
9717 #define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
9718 #define mmDIG5_DIG_FIFO_STATUS 0x256e
9719 #define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2
9720 #define mmDIG5_HDMI_CONTROL 0x2571
9721 #define mmDIG5_HDMI_CONTROL_BASE_IDX 2
9722 #define mmDIG5_HDMI_STATUS 0x2572
9723 #define mmDIG5_HDMI_STATUS_BASE_IDX 2
9724 #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x2573
9725 #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
9726 #define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x2574
9727 #define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
9728 #define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x2575
9729 #define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
9730 #define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x2576
9731 #define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
9732 #define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x2577
9733 #define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
9734 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x2578
9735 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
9736 #define mmDIG5_AFMT_INTERRUPT_STATUS 0x2579
9737 #define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX 2
9738 #define mmDIG5_HDMI_GC 0x257b
9739 #define mmDIG5_HDMI_GC_BASE_IDX 2
9740 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x257c
9741 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
9742 #define mmDIG5_AFMT_ISRC1_0 0x257d
9743 #define mmDIG5_AFMT_ISRC1_0_BASE_IDX 2
9744 #define mmDIG5_AFMT_ISRC1_1 0x257e
9745 #define mmDIG5_AFMT_ISRC1_1_BASE_IDX 2
9746 #define mmDIG5_AFMT_ISRC1_2 0x257f
9747 #define mmDIG5_AFMT_ISRC1_2_BASE_IDX 2
9748 #define mmDIG5_AFMT_ISRC1_3 0x2580
9749 #define mmDIG5_AFMT_ISRC1_3_BASE_IDX 2
9750 #define mmDIG5_AFMT_ISRC1_4 0x2581
9751 #define mmDIG5_AFMT_ISRC1_4_BASE_IDX 2
9752 #define mmDIG5_AFMT_ISRC2_0 0x2582
9753 #define mmDIG5_AFMT_ISRC2_0_BASE_IDX 2
9754 #define mmDIG5_AFMT_ISRC2_1 0x2583
9755 #define mmDIG5_AFMT_ISRC2_1_BASE_IDX 2
9756 #define mmDIG5_AFMT_ISRC2_2 0x2584
9757 #define mmDIG5_AFMT_ISRC2_2_BASE_IDX 2
9758 #define mmDIG5_AFMT_ISRC2_3 0x2585
9759 #define mmDIG5_AFMT_ISRC2_3_BASE_IDX 2
9760 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2 0x2586
9761 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
9762 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3 0x2587
9763 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
9764 #define mmDIG5_HDMI_DB_CONTROL 0x2588
9765 #define mmDIG5_HDMI_DB_CONTROL_BASE_IDX 2
9766 #define mmDIG5_AFMT_MPEG_INFO0 0x258a
9767 #define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX 2
9768 #define mmDIG5_AFMT_MPEG_INFO1 0x258b
9769 #define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX 2
9770 #define mmDIG5_AFMT_GENERIC_HDR 0x258c
9771 #define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX 2
9772 #define mmDIG5_AFMT_GENERIC_0 0x258d
9773 #define mmDIG5_AFMT_GENERIC_0_BASE_IDX 2
9774 #define mmDIG5_AFMT_GENERIC_1 0x258e
9775 #define mmDIG5_AFMT_GENERIC_1_BASE_IDX 2
9776 #define mmDIG5_AFMT_GENERIC_2 0x258f
9777 #define mmDIG5_AFMT_GENERIC_2_BASE_IDX 2
9778 #define mmDIG5_AFMT_GENERIC_3 0x2590
9779 #define mmDIG5_AFMT_GENERIC_3_BASE_IDX 2
9780 #define mmDIG5_AFMT_GENERIC_4 0x2591
9781 #define mmDIG5_AFMT_GENERIC_4_BASE_IDX 2
9782 #define mmDIG5_AFMT_GENERIC_5 0x2592
9783 #define mmDIG5_AFMT_GENERIC_5_BASE_IDX 2
9784 #define mmDIG5_AFMT_GENERIC_6 0x2593
9785 #define mmDIG5_AFMT_GENERIC_6_BASE_IDX 2
9786 #define mmDIG5_AFMT_GENERIC_7 0x2594
9787 #define mmDIG5_AFMT_GENERIC_7_BASE_IDX 2
9788 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x2595
9789 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
9790 #define mmDIG5_HDMI_ACR_32_0 0x2596
9791 #define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2
9792 #define mmDIG5_HDMI_ACR_32_1 0x2597
9793 #define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2
9794 #define mmDIG5_HDMI_ACR_44_0 0x2598
9795 #define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2
9796 #define mmDIG5_HDMI_ACR_44_1 0x2599
9797 #define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2
9798 #define mmDIG5_HDMI_ACR_48_0 0x259a
9799 #define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2
9800 #define mmDIG5_HDMI_ACR_48_1 0x259b
9801 #define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2
9802 #define mmDIG5_HDMI_ACR_STATUS_0 0x259c
9803 #define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2
9804 #define mmDIG5_HDMI_ACR_STATUS_1 0x259d
9805 #define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2
9806 #define mmDIG5_AFMT_AUDIO_INFO0 0x259e
9807 #define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX 2
9808 #define mmDIG5_AFMT_AUDIO_INFO1 0x259f
9809 #define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX 2
9810 #define mmDIG5_AFMT_60958_0 0x25a0
9811 #define mmDIG5_AFMT_60958_0_BASE_IDX 2
9812 #define mmDIG5_AFMT_60958_1 0x25a1
9813 #define mmDIG5_AFMT_60958_1_BASE_IDX 2
9814 #define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x25a2
9815 #define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
9816 #define mmDIG5_AFMT_RAMP_CONTROL0 0x25a3
9817 #define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX 2
9818 #define mmDIG5_AFMT_RAMP_CONTROL1 0x25a4
9819 #define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX 2
9820 #define mmDIG5_AFMT_RAMP_CONTROL2 0x25a5
9821 #define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX 2
9822 #define mmDIG5_AFMT_RAMP_CONTROL3 0x25a6
9823 #define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX 2
9824 #define mmDIG5_AFMT_60958_2 0x25a7
9825 #define mmDIG5_AFMT_60958_2_BASE_IDX 2
9826 #define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x25a8
9827 #define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
9828 #define mmDIG5_AFMT_STATUS 0x25a9
9829 #define mmDIG5_AFMT_STATUS_BASE_IDX 2
9830 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x25aa
9831 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
9832 #define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x25ab
9833 #define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
9834 #define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x25ac
9835 #define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
9836 #define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x25ad
9837 #define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
9838 #define mmDIG5_DIG_BE_CNTL 0x25af
9839 #define mmDIG5_DIG_BE_CNTL_BASE_IDX 2
9840 #define mmDIG5_DIG_BE_EN_CNTL 0x25b0
9841 #define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2
9842 #define mmDIG5_TMDS_CNTL 0x25d3
9843 #define mmDIG5_TMDS_CNTL_BASE_IDX 2
9844 #define mmDIG5_TMDS_CONTROL_CHAR 0x25d4
9845 #define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2
9846 #define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x25d5
9847 #define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
9848 #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x25d6
9849 #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
9850 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x25d7
9851 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
9852 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x25d8
9853 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
9854 #define mmDIG5_TMDS_CTL_BITS 0x25da
9855 #define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2
9856 #define mmDIG5_TMDS_DCBALANCER_CONTROL 0x25db
9857 #define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
9858 #define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x25dd
9859 #define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
9860 #define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x25de
9861 #define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
9862 #define mmDIG5_DIG_VERSION 0x25e0
9863 #define mmDIG5_DIG_VERSION_BASE_IDX 2
9864 #define mmDIG5_DIG_LANE_ENABLE 0x25e1
9865 #define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2
9866 #define mmDIG5_AFMT_CNTL 0x25e6
9867 #define mmDIG5_AFMT_CNTL_BASE_IDX 2
9868 #define mmDIG5_AFMT_VBI_PACKET_CONTROL1 0x25e7
9869 #define mmDIG5_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
9872 // addressBlock: dce_dc_dio_dp5_dispdec
9873 // base address: 0x1400
9874 #define mmDP5_DP_LINK_CNTL 0x2608
9875 #define mmDP5_DP_LINK_CNTL_BASE_IDX 2
9876 #define mmDP5_DP_PIXEL_FORMAT 0x2609
9877 #define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2
9878 #define mmDP5_DP_MSA_COLORIMETRY 0x260a
9879 #define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2
9880 #define mmDP5_DP_CONFIG 0x260b
9881 #define mmDP5_DP_CONFIG_BASE_IDX 2
9882 #define mmDP5_DP_VID_STREAM_CNTL 0x260c
9883 #define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2
9884 #define mmDP5_DP_STEER_FIFO 0x260d
9885 #define mmDP5_DP_STEER_FIFO_BASE_IDX 2
9886 #define mmDP5_DP_MSA_MISC 0x260e
9887 #define mmDP5_DP_MSA_MISC_BASE_IDX 2
9888 #define mmDP5_DP_VID_TIMING 0x2610
9889 #define mmDP5_DP_VID_TIMING_BASE_IDX 2
9890 #define mmDP5_DP_VID_N 0x2611
9891 #define mmDP5_DP_VID_N_BASE_IDX 2
9892 #define mmDP5_DP_VID_M 0x2612
9893 #define mmDP5_DP_VID_M_BASE_IDX 2
9894 #define mmDP5_DP_LINK_FRAMING_CNTL 0x2613
9895 #define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2
9896 #define mmDP5_DP_HBR2_EYE_PATTERN 0x2614
9897 #define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2
9898 #define mmDP5_DP_VID_MSA_VBID 0x2615
9899 #define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2
9900 #define mmDP5_DP_VID_INTERRUPT_CNTL 0x2616
9901 #define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
9902 #define mmDP5_DP_DPHY_CNTL 0x2617
9903 #define mmDP5_DP_DPHY_CNTL_BASE_IDX 2
9904 #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x2618
9905 #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
9906 #define mmDP5_DP_DPHY_SYM0 0x2619
9907 #define mmDP5_DP_DPHY_SYM0_BASE_IDX 2
9908 #define mmDP5_DP_DPHY_SYM1 0x261a
9909 #define mmDP5_DP_DPHY_SYM1_BASE_IDX 2
9910 #define mmDP5_DP_DPHY_SYM2 0x261b
9911 #define mmDP5_DP_DPHY_SYM2_BASE_IDX 2
9912 #define mmDP5_DP_DPHY_8B10B_CNTL 0x261c
9913 #define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2
9914 #define mmDP5_DP_DPHY_PRBS_CNTL 0x261d
9915 #define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2
9916 #define mmDP5_DP_DPHY_SCRAM_CNTL 0x261e
9917 #define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
9918 #define mmDP5_DP_DPHY_CRC_EN 0x261f
9919 #define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2
9920 #define mmDP5_DP_DPHY_CRC_CNTL 0x2620
9921 #define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2
9922 #define mmDP5_DP_DPHY_CRC_RESULT 0x2621
9923 #define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2
9924 #define mmDP5_DP_DPHY_CRC_MST_CNTL 0x2622
9925 #define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
9926 #define mmDP5_DP_DPHY_CRC_MST_STATUS 0x2623
9927 #define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
9928 #define mmDP5_DP_DPHY_FAST_TRAINING 0x2624
9929 #define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2
9930 #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x2625
9931 #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
9932 #define mmDP5_DP_SEC_CNTL 0x262b
9933 #define mmDP5_DP_SEC_CNTL_BASE_IDX 2
9934 #define mmDP5_DP_SEC_CNTL1 0x262c
9935 #define mmDP5_DP_SEC_CNTL1_BASE_IDX 2
9936 #define mmDP5_DP_SEC_FRAMING1 0x262d
9937 #define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2
9938 #define mmDP5_DP_SEC_FRAMING2 0x262e
9939 #define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2
9940 #define mmDP5_DP_SEC_FRAMING3 0x262f
9941 #define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2
9942 #define mmDP5_DP_SEC_FRAMING4 0x2630
9943 #define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2
9944 #define mmDP5_DP_SEC_AUD_N 0x2631
9945 #define mmDP5_DP_SEC_AUD_N_BASE_IDX 2
9946 #define mmDP5_DP_SEC_AUD_N_READBACK 0x2632
9947 #define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2
9948 #define mmDP5_DP_SEC_AUD_M 0x2633
9949 #define mmDP5_DP_SEC_AUD_M_BASE_IDX 2
9950 #define mmDP5_DP_SEC_AUD_M_READBACK 0x2634
9951 #define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2
9952 #define mmDP5_DP_SEC_TIMESTAMP 0x2635
9953 #define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2
9954 #define mmDP5_DP_SEC_PACKET_CNTL 0x2636
9955 #define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2
9956 #define mmDP5_DP_MSE_RATE_CNTL 0x2637
9957 #define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2
9958 #define mmDP5_DP_MSE_RATE_UPDATE 0x2639
9959 #define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2
9960 #define mmDP5_DP_MSE_SAT0 0x263a
9961 #define mmDP5_DP_MSE_SAT0_BASE_IDX 2
9962 #define mmDP5_DP_MSE_SAT1 0x263b
9963 #define mmDP5_DP_MSE_SAT1_BASE_IDX 2
9964 #define mmDP5_DP_MSE_SAT2 0x263c
9965 #define mmDP5_DP_MSE_SAT2_BASE_IDX 2
9966 #define mmDP5_DP_MSE_SAT_UPDATE 0x263d
9967 #define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2
9968 #define mmDP5_DP_MSE_LINK_TIMING 0x263e
9969 #define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2
9970 #define mmDP5_DP_MSE_MISC_CNTL 0x263f
9971 #define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2
9972 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x2644
9973 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
9974 #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x2645
9975 #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
9976 #define mmDP5_DP_MSE_SAT0_STATUS 0x2647
9977 #define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2
9978 #define mmDP5_DP_MSE_SAT1_STATUS 0x2648
9979 #define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2
9980 #define mmDP5_DP_MSE_SAT2_STATUS 0x2649
9981 #define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2
9982 #define mmDP5_DP_MSA_TIMING_PARAM1 0x264c
9983 #define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX 2
9984 #define mmDP5_DP_MSA_TIMING_PARAM2 0x264d
9985 #define mmDP5_DP_MSA_TIMING_PARAM2_BASE_IDX 2
9986 #define mmDP5_DP_MSA_TIMING_PARAM3 0x264e
9987 #define mmDP5_DP_MSA_TIMING_PARAM3_BASE_IDX 2
9988 #define mmDP5_DP_MSA_TIMING_PARAM4 0x264f
9989 #define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX 2
9990 #define mmDP5_DP_MSO_CNTL 0x2650
9991 #define mmDP5_DP_MSO_CNTL_BASE_IDX 2
9992 #define mmDP5_DP_MSO_CNTL1 0x2651
9993 #define mmDP5_DP_MSO_CNTL1_BASE_IDX 2
9994 #define mmDP5_DP_DSC_CNTL 0x2652
9995 #define mmDP5_DP_DSC_CNTL_BASE_IDX 2
9996 #define mmDP5_DP_SEC_CNTL2 0x2653
9997 #define mmDP5_DP_SEC_CNTL2_BASE_IDX 2
9998 #define mmDP5_DP_SEC_CNTL3 0x2654
9999 #define mmDP5_DP_SEC_CNTL3_BASE_IDX 2
10000 #define mmDP5_DP_SEC_CNTL4 0x2655
10001 #define mmDP5_DP_SEC_CNTL4_BASE_IDX 2
10002 #define mmDP5_DP_SEC_CNTL5 0x2656
10003 #define mmDP5_DP_SEC_CNTL5_BASE_IDX 2
10004 #define mmDP5_DP_SEC_CNTL6 0x2657
10005 #define mmDP5_DP_SEC_CNTL6_BASE_IDX 2
10006 #define mmDP5_DP_SEC_CNTL7 0x2658
10007 #define mmDP5_DP_SEC_CNTL7_BASE_IDX 2
10008 #define mmDP5_DP_DB_CNTL 0x2659
10009 #define mmDP5_DP_DB_CNTL_BASE_IDX 2
10010 #define mmDP5_DP_MSA_VBID_MISC 0x265a
10011 #define mmDP5_DP_MSA_VBID_MISC_BASE_IDX 2
10014 // addressBlock: dce_dc_dio_dig6_dispdec
10015 // base address: 0x1800
10016 #define mmDIG6_DIG_FE_CNTL 0x2668
10017 #define mmDIG6_DIG_FE_CNTL_BASE_IDX 2
10018 #define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x2669
10019 #define mmDIG6_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
10020 #define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x266a
10021 #define mmDIG6_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
10022 #define mmDIG6_DIG_CLOCK_PATTERN 0x266b
10023 #define mmDIG6_DIG_CLOCK_PATTERN_BASE_IDX 2
10024 #define mmDIG6_DIG_TEST_PATTERN 0x266c
10025 #define mmDIG6_DIG_TEST_PATTERN_BASE_IDX 2
10026 #define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x266d
10027 #define mmDIG6_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
10028 #define mmDIG6_DIG_FIFO_STATUS 0x266e
10029 #define mmDIG6_DIG_FIFO_STATUS_BASE_IDX 2
10030 #define mmDIG6_HDMI_CONTROL 0x2671
10031 #define mmDIG6_HDMI_CONTROL_BASE_IDX 2
10032 #define mmDIG6_HDMI_STATUS 0x2672
10033 #define mmDIG6_HDMI_STATUS_BASE_IDX 2
10034 #define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x2673
10035 #define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
10036 #define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x2674
10037 #define mmDIG6_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
10038 #define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x2675
10039 #define mmDIG6_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
10040 #define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x2676
10041 #define mmDIG6_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
10042 #define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x2677
10043 #define mmDIG6_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
10044 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x2678
10045 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
10046 #define mmDIG6_AFMT_INTERRUPT_STATUS 0x2679
10047 #define mmDIG6_AFMT_INTERRUPT_STATUS_BASE_IDX 2
10048 #define mmDIG6_HDMI_GC 0x267b
10049 #define mmDIG6_HDMI_GC_BASE_IDX 2
10050 #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x267c
10051 #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
10052 #define mmDIG6_AFMT_ISRC1_0 0x267d
10053 #define mmDIG6_AFMT_ISRC1_0_BASE_IDX 2
10054 #define mmDIG6_AFMT_ISRC1_1 0x267e
10055 #define mmDIG6_AFMT_ISRC1_1_BASE_IDX 2
10056 #define mmDIG6_AFMT_ISRC1_2 0x267f
10057 #define mmDIG6_AFMT_ISRC1_2_BASE_IDX 2
10058 #define mmDIG6_AFMT_ISRC1_3 0x2680
10059 #define mmDIG6_AFMT_ISRC1_3_BASE_IDX 2
10060 #define mmDIG6_AFMT_ISRC1_4 0x2681
10061 #define mmDIG6_AFMT_ISRC1_4_BASE_IDX 2
10062 #define mmDIG6_AFMT_ISRC2_0 0x2682
10063 #define mmDIG6_AFMT_ISRC2_0_BASE_IDX 2
10064 #define mmDIG6_AFMT_ISRC2_1 0x2683
10065 #define mmDIG6_AFMT_ISRC2_1_BASE_IDX 2
10066 #define mmDIG6_AFMT_ISRC2_2 0x2684
10067 #define mmDIG6_AFMT_ISRC2_2_BASE_IDX 2
10068 #define mmDIG6_AFMT_ISRC2_3 0x2685
10069 #define mmDIG6_AFMT_ISRC2_3_BASE_IDX 2
10070 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2 0x2686
10071 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
10072 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3 0x2687
10073 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
10074 #define mmDIG6_HDMI_DB_CONTROL 0x2688
10075 #define mmDIG6_HDMI_DB_CONTROL_BASE_IDX 2
10076 #define mmDIG6_AFMT_MPEG_INFO0 0x268a
10077 #define mmDIG6_AFMT_MPEG_INFO0_BASE_IDX 2
10078 #define mmDIG6_AFMT_MPEG_INFO1 0x268b
10079 #define mmDIG6_AFMT_MPEG_INFO1_BASE_IDX 2
10080 #define mmDIG6_AFMT_GENERIC_HDR 0x268c
10081 #define mmDIG6_AFMT_GENERIC_HDR_BASE_IDX 2
10082 #define mmDIG6_AFMT_GENERIC_0 0x268d
10083 #define mmDIG6_AFMT_GENERIC_0_BASE_IDX 2
10084 #define mmDIG6_AFMT_GENERIC_1 0x268e
10085 #define mmDIG6_AFMT_GENERIC_1_BASE_IDX 2
10086 #define mmDIG6_AFMT_GENERIC_2 0x268f
10087 #define mmDIG6_AFMT_GENERIC_2_BASE_IDX 2
10088 #define mmDIG6_AFMT_GENERIC_3 0x2690
10089 #define mmDIG6_AFMT_GENERIC_3_BASE_IDX 2
10090 #define mmDIG6_AFMT_GENERIC_4 0x2691
10091 #define mmDIG6_AFMT_GENERIC_4_BASE_IDX 2
10092 #define mmDIG6_AFMT_GENERIC_5 0x2692
10093 #define mmDIG6_AFMT_GENERIC_5_BASE_IDX 2
10094 #define mmDIG6_AFMT_GENERIC_6 0x2693
10095 #define mmDIG6_AFMT_GENERIC_6_BASE_IDX 2
10096 #define mmDIG6_AFMT_GENERIC_7 0x2694
10097 #define mmDIG6_AFMT_GENERIC_7_BASE_IDX 2
10098 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x2695
10099 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
10100 #define mmDIG6_HDMI_ACR_32_0 0x2696
10101 #define mmDIG6_HDMI_ACR_32_0_BASE_IDX 2
10102 #define mmDIG6_HDMI_ACR_32_1 0x2697
10103 #define mmDIG6_HDMI_ACR_32_1_BASE_IDX 2
10104 #define mmDIG6_HDMI_ACR_44_0 0x2698
10105 #define mmDIG6_HDMI_ACR_44_0_BASE_IDX 2
10106 #define mmDIG6_HDMI_ACR_44_1 0x2699
10107 #define mmDIG6_HDMI_ACR_44_1_BASE_IDX 2
10108 #define mmDIG6_HDMI_ACR_48_0 0x269a
10109 #define mmDIG6_HDMI_ACR_48_0_BASE_IDX 2
10110 #define mmDIG6_HDMI_ACR_48_1 0x269b
10111 #define mmDIG6_HDMI_ACR_48_1_BASE_IDX 2
10112 #define mmDIG6_HDMI_ACR_STATUS_0 0x269c
10113 #define mmDIG6_HDMI_ACR_STATUS_0_BASE_IDX 2
10114 #define mmDIG6_HDMI_ACR_STATUS_1 0x269d
10115 #define mmDIG6_HDMI_ACR_STATUS_1_BASE_IDX 2
10116 #define mmDIG6_AFMT_AUDIO_INFO0 0x269e
10117 #define mmDIG6_AFMT_AUDIO_INFO0_BASE_IDX 2
10118 #define mmDIG6_AFMT_AUDIO_INFO1 0x269f
10119 #define mmDIG6_AFMT_AUDIO_INFO1_BASE_IDX 2
10120 #define mmDIG6_AFMT_60958_0 0x26a0
10121 #define mmDIG6_AFMT_60958_0_BASE_IDX 2
10122 #define mmDIG6_AFMT_60958_1 0x26a1
10123 #define mmDIG6_AFMT_60958_1_BASE_IDX 2
10124 #define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x26a2
10125 #define mmDIG6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
10126 #define mmDIG6_AFMT_RAMP_CONTROL0 0x26a3
10127 #define mmDIG6_AFMT_RAMP_CONTROL0_BASE_IDX 2
10128 #define mmDIG6_AFMT_RAMP_CONTROL1 0x26a4
10129 #define mmDIG6_AFMT_RAMP_CONTROL1_BASE_IDX 2
10130 #define mmDIG6_AFMT_RAMP_CONTROL2 0x26a5
10131 #define mmDIG6_AFMT_RAMP_CONTROL2_BASE_IDX 2
10132 #define mmDIG6_AFMT_RAMP_CONTROL3 0x26a6
10133 #define mmDIG6_AFMT_RAMP_CONTROL3_BASE_IDX 2
10134 #define mmDIG6_AFMT_60958_2 0x26a7
10135 #define mmDIG6_AFMT_60958_2_BASE_IDX 2
10136 #define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x26a8
10137 #define mmDIG6_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
10138 #define mmDIG6_AFMT_STATUS 0x26a9
10139 #define mmDIG6_AFMT_STATUS_BASE_IDX 2
10140 #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x26aa
10141 #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
10142 #define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x26ab
10143 #define mmDIG6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
10144 #define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x26ac
10145 #define mmDIG6_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
10146 #define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x26ad
10147 #define mmDIG6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
10148 #define mmDIG6_DIG_BE_CNTL 0x26af
10149 #define mmDIG6_DIG_BE_CNTL_BASE_IDX 2
10150 #define mmDIG6_DIG_BE_EN_CNTL 0x26b0
10151 #define mmDIG6_DIG_BE_EN_CNTL_BASE_IDX 2
10152 #define mmDIG6_TMDS_CNTL 0x26d3
10153 #define mmDIG6_TMDS_CNTL_BASE_IDX 2
10154 #define mmDIG6_TMDS_CONTROL_CHAR 0x26d4
10155 #define mmDIG6_TMDS_CONTROL_CHAR_BASE_IDX 2
10156 #define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x26d5
10157 #define mmDIG6_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
10158 #define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x26d6
10159 #define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
10160 #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x26d7
10161 #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
10162 #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x26d8
10163 #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
10164 #define mmDIG6_TMDS_CTL_BITS 0x26da
10165 #define mmDIG6_TMDS_CTL_BITS_BASE_IDX 2
10166 #define mmDIG6_TMDS_DCBALANCER_CONTROL 0x26db
10167 #define mmDIG6_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
10168 #define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x26dd
10169 #define mmDIG6_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
10170 #define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x26de
10171 #define mmDIG6_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
10172 #define mmDIG6_DIG_VERSION 0x26e0
10173 #define mmDIG6_DIG_VERSION_BASE_IDX 2
10174 #define mmDIG6_DIG_LANE_ENABLE 0x26e1
10175 #define mmDIG6_DIG_LANE_ENABLE_BASE_IDX 2
10176 #define mmDIG6_AFMT_CNTL 0x26e6
10177 #define mmDIG6_AFMT_CNTL_BASE_IDX 2
10178 #define mmDIG6_AFMT_VBI_PACKET_CONTROL1 0x26e7
10179 #define mmDIG6_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
10182 // addressBlock: dce_dc_dio_dp6_dispdec
10183 // base address: 0x1800
10184 #define mmDP6_DP_LINK_CNTL 0x2708
10185 #define mmDP6_DP_LINK_CNTL_BASE_IDX 2
10186 #define mmDP6_DP_PIXEL_FORMAT 0x2709
10187 #define mmDP6_DP_PIXEL_FORMAT_BASE_IDX 2
10188 #define mmDP6_DP_MSA_COLORIMETRY 0x270a
10189 #define mmDP6_DP_MSA_COLORIMETRY_BASE_IDX 2
10190 #define mmDP6_DP_CONFIG 0x270b
10191 #define mmDP6_DP_CONFIG_BASE_IDX 2
10192 #define mmDP6_DP_VID_STREAM_CNTL 0x270c
10193 #define mmDP6_DP_VID_STREAM_CNTL_BASE_IDX 2
10194 #define mmDP6_DP_STEER_FIFO 0x270d
10195 #define mmDP6_DP_STEER_FIFO_BASE_IDX 2
10196 #define mmDP6_DP_MSA_MISC 0x270e
10197 #define mmDP6_DP_MSA_MISC_BASE_IDX 2
10198 #define mmDP6_DP_VID_TIMING 0x2710
10199 #define mmDP6_DP_VID_TIMING_BASE_IDX 2
10200 #define mmDP6_DP_VID_N 0x2711
10201 #define mmDP6_DP_VID_N_BASE_IDX 2
10202 #define mmDP6_DP_VID_M 0x2712
10203 #define mmDP6_DP_VID_M_BASE_IDX 2
10204 #define mmDP6_DP_LINK_FRAMING_CNTL 0x2713
10205 #define mmDP6_DP_LINK_FRAMING_CNTL_BASE_IDX 2
10206 #define mmDP6_DP_HBR2_EYE_PATTERN 0x2714
10207 #define mmDP6_DP_HBR2_EYE_PATTERN_BASE_IDX 2
10208 #define mmDP6_DP_VID_MSA_VBID 0x2715
10209 #define mmDP6_DP_VID_MSA_VBID_BASE_IDX 2
10210 #define mmDP6_DP_VID_INTERRUPT_CNTL 0x2716
10211 #define mmDP6_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
10212 #define mmDP6_DP_DPHY_CNTL 0x2717
10213 #define mmDP6_DP_DPHY_CNTL_BASE_IDX 2
10214 #define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x2718
10215 #define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
10216 #define mmDP6_DP_DPHY_SYM0 0x2719
10217 #define mmDP6_DP_DPHY_SYM0_BASE_IDX 2
10218 #define mmDP6_DP_DPHY_SYM1 0x271a
10219 #define mmDP6_DP_DPHY_SYM1_BASE_IDX 2
10220 #define mmDP6_DP_DPHY_SYM2 0x271b
10221 #define mmDP6_DP_DPHY_SYM2_BASE_IDX 2
10222 #define mmDP6_DP_DPHY_8B10B_CNTL 0x271c
10223 #define mmDP6_DP_DPHY_8B10B_CNTL_BASE_IDX 2
10224 #define mmDP6_DP_DPHY_PRBS_CNTL 0x271d
10225 #define mmDP6_DP_DPHY_PRBS_CNTL_BASE_IDX 2
10226 #define mmDP6_DP_DPHY_SCRAM_CNTL 0x271e
10227 #define mmDP6_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
10228 #define mmDP6_DP_DPHY_CRC_EN 0x271f
10229 #define mmDP6_DP_DPHY_CRC_EN_BASE_IDX 2
10230 #define mmDP6_DP_DPHY_CRC_CNTL 0x2720
10231 #define mmDP6_DP_DPHY_CRC_CNTL_BASE_IDX 2
10232 #define mmDP6_DP_DPHY_CRC_RESULT 0x2721
10233 #define mmDP6_DP_DPHY_CRC_RESULT_BASE_IDX 2
10234 #define mmDP6_DP_DPHY_CRC_MST_CNTL 0x2722
10235 #define mmDP6_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
10236 #define mmDP6_DP_DPHY_CRC_MST_STATUS 0x2723
10237 #define mmDP6_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
10238 #define mmDP6_DP_DPHY_FAST_TRAINING 0x2724
10239 #define mmDP6_DP_DPHY_FAST_TRAINING_BASE_IDX 2
10240 #define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x2725
10241 #define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
10242 #define mmDP6_DP_SEC_CNTL 0x272b
10243 #define mmDP6_DP_SEC_CNTL_BASE_IDX 2
10244 #define mmDP6_DP_SEC_CNTL1 0x272c
10245 #define mmDP6_DP_SEC_CNTL1_BASE_IDX 2
10246 #define mmDP6_DP_SEC_FRAMING1 0x272d
10247 #define mmDP6_DP_SEC_FRAMING1_BASE_IDX 2
10248 #define mmDP6_DP_SEC_FRAMING2 0x272e
10249 #define mmDP6_DP_SEC_FRAMING2_BASE_IDX 2
10250 #define mmDP6_DP_SEC_FRAMING3 0x272f
10251 #define mmDP6_DP_SEC_FRAMING3_BASE_IDX 2
10252 #define mmDP6_DP_SEC_FRAMING4 0x2730
10253 #define mmDP6_DP_SEC_FRAMING4_BASE_IDX 2
10254 #define mmDP6_DP_SEC_AUD_N 0x2731
10255 #define mmDP6_DP_SEC_AUD_N_BASE_IDX 2
10256 #define mmDP6_DP_SEC_AUD_N_READBACK 0x2732
10257 #define mmDP6_DP_SEC_AUD_N_READBACK_BASE_IDX 2
10258 #define mmDP6_DP_SEC_AUD_M 0x2733
10259 #define mmDP6_DP_SEC_AUD_M_BASE_IDX 2
10260 #define mmDP6_DP_SEC_AUD_M_READBACK 0x2734
10261 #define mmDP6_DP_SEC_AUD_M_READBACK_BASE_IDX 2
10262 #define mmDP6_DP_SEC_TIMESTAMP 0x2735
10263 #define mmDP6_DP_SEC_TIMESTAMP_BASE_IDX 2
10264 #define mmDP6_DP_SEC_PACKET_CNTL 0x2736
10265 #define mmDP6_DP_SEC_PACKET_CNTL_BASE_IDX 2
10266 #define mmDP6_DP_MSE_RATE_CNTL 0x2737
10267 #define mmDP6_DP_MSE_RATE_CNTL_BASE_IDX 2
10268 #define mmDP6_DP_MSE_RATE_UPDATE 0x2739
10269 #define mmDP6_DP_MSE_RATE_UPDATE_BASE_IDX 2
10270 #define mmDP6_DP_MSE_SAT0 0x273a
10271 #define mmDP6_DP_MSE_SAT0_BASE_IDX 2
10272 #define mmDP6_DP_MSE_SAT1 0x273b
10273 #define mmDP6_DP_MSE_SAT1_BASE_IDX 2
10274 #define mmDP6_DP_MSE_SAT2 0x273c
10275 #define mmDP6_DP_MSE_SAT2_BASE_IDX 2
10276 #define mmDP6_DP_MSE_SAT_UPDATE 0x273d
10277 #define mmDP6_DP_MSE_SAT_UPDATE_BASE_IDX 2
10278 #define mmDP6_DP_MSE_LINK_TIMING 0x273e
10279 #define mmDP6_DP_MSE_LINK_TIMING_BASE_IDX 2
10280 #define mmDP6_DP_MSE_MISC_CNTL 0x273f
10281 #define mmDP6_DP_MSE_MISC_CNTL_BASE_IDX 2
10282 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x2744
10283 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
10284 #define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x2745
10285 #define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
10286 #define mmDP6_DP_MSE_SAT0_STATUS 0x2747
10287 #define mmDP6_DP_MSE_SAT0_STATUS_BASE_IDX 2
10288 #define mmDP6_DP_MSE_SAT1_STATUS 0x2748
10289 #define mmDP6_DP_MSE_SAT1_STATUS_BASE_IDX 2
10290 #define mmDP6_DP_MSE_SAT2_STATUS 0x2749
10291 #define mmDP6_DP_MSE_SAT2_STATUS_BASE_IDX 2
10292 #define mmDP6_DP_MSA_TIMING_PARAM1 0x274c
10293 #define mmDP6_DP_MSA_TIMING_PARAM1_BASE_IDX 2
10294 #define mmDP6_DP_MSA_TIMING_PARAM2 0x274d
10295 #define mmDP6_DP_MSA_TIMING_PARAM2_BASE_IDX 2
10296 #define mmDP6_DP_MSA_TIMING_PARAM3 0x274e
10297 #define mmDP6_DP_MSA_TIMING_PARAM3_BASE_IDX 2
10298 #define mmDP6_DP_MSA_TIMING_PARAM4 0x274f
10299 #define mmDP6_DP_MSA_TIMING_PARAM4_BASE_IDX 2
10300 #define mmDP6_DP_MSO_CNTL 0x2750
10301 #define mmDP6_DP_MSO_CNTL_BASE_IDX 2
10302 #define mmDP6_DP_MSO_CNTL1 0x2751
10303 #define mmDP6_DP_MSO_CNTL1_BASE_IDX 2
10304 #define mmDP6_DP_DSC_CNTL 0x2752
10305 #define mmDP6_DP_DSC_CNTL_BASE_IDX 2
10306 #define mmDP6_DP_SEC_CNTL2 0x2753
10307 #define mmDP6_DP_SEC_CNTL2_BASE_IDX 2
10308 #define mmDP6_DP_SEC_CNTL3 0x2754
10309 #define mmDP6_DP_SEC_CNTL3_BASE_IDX 2
10310 #define mmDP6_DP_SEC_CNTL4 0x2755
10311 #define mmDP6_DP_SEC_CNTL4_BASE_IDX 2
10312 #define mmDP6_DP_SEC_CNTL5 0x2756
10313 #define mmDP6_DP_SEC_CNTL5_BASE_IDX 2
10314 #define mmDP6_DP_SEC_CNTL6 0x2757
10315 #define mmDP6_DP_SEC_CNTL6_BASE_IDX 2
10316 #define mmDP6_DP_SEC_CNTL7 0x2758
10317 #define mmDP6_DP_SEC_CNTL7_BASE_IDX 2
10318 #define mmDP6_DP_DB_CNTL 0x2759
10319 #define mmDP6_DP_DB_CNTL_BASE_IDX 2
10320 #define mmDP6_DP_MSA_VBID_MISC 0x275a
10321 #define mmDP6_DP_MSA_VBID_MISC_BASE_IDX 2
10324 // addressBlock: dce_dc_dcio_dcio_dispdec
10325 // base address: 0x0
10326 #define mmDC_GENERICA 0x2868
10327 #define mmDC_GENERICA_BASE_IDX 2
10328 #define mmDC_GENERICB 0x2869
10329 #define mmDC_GENERICB_BASE_IDX 2
10330 #define mmDC_REF_CLK_CNTL 0x286b
10331 #define mmDC_REF_CLK_CNTL_BASE_IDX 2
10332 #define mmDC_GPIO_DEBUG 0x286c
10333 #define mmDC_GPIO_DEBUG_BASE_IDX 2
10334 #define mmUNIPHYA_LINK_CNTL 0x286d
10335 #define mmUNIPHYA_LINK_CNTL_BASE_IDX 2
10336 #define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e
10337 #define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
10338 #define mmUNIPHYB_LINK_CNTL 0x286f
10339 #define mmUNIPHYB_LINK_CNTL_BASE_IDX 2
10340 #define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870
10341 #define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
10342 #define mmUNIPHYC_LINK_CNTL 0x2871
10343 #define mmUNIPHYC_LINK_CNTL_BASE_IDX 2
10344 #define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2872
10345 #define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
10346 #define mmUNIPHYD_LINK_CNTL 0x2873
10347 #define mmUNIPHYD_LINK_CNTL_BASE_IDX 2
10348 #define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x2874
10349 #define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
10350 #define mmUNIPHYE_LINK_CNTL 0x2875
10351 #define mmUNIPHYE_LINK_CNTL_BASE_IDX 2
10352 #define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x2876
10353 #define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
10354 #define mmUNIPHYF_LINK_CNTL 0x2877
10355 #define mmUNIPHYF_LINK_CNTL_BASE_IDX 2
10356 #define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x2878
10357 #define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2
10358 #define mmUNIPHYG_LINK_CNTL 0x2879
10359 #define mmUNIPHYG_LINK_CNTL_BASE_IDX 2
10360 #define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x287a
10361 #define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2
10362 #define mmDCIO_WRCMD_DELAY 0x287e
10363 #define mmDCIO_WRCMD_DELAY_BASE_IDX 2
10364 #define mmDC_DVODATA_CONFIG 0x2882
10365 #define mmDC_DVODATA_CONFIG_BASE_IDX 2
10366 #define mmLVTMA_PWRSEQ_CNTL 0x2883
10367 #define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2
10368 #define mmLVTMA_PWRSEQ_STATE 0x2884
10369 #define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2
10370 #define mmLVTMA_PWRSEQ_REF_DIV 0x2885
10371 #define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2
10372 #define mmLVTMA_PWRSEQ_DELAY1 0x2886
10373 #define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2
10374 #define mmLVTMA_PWRSEQ_DELAY2 0x2887
10375 #define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2
10376 #define mmBL_PWM_CNTL 0x2888
10377 #define mmBL_PWM_CNTL_BASE_IDX 2
10378 #define mmBL_PWM_CNTL2 0x2889
10379 #define mmBL_PWM_CNTL2_BASE_IDX 2
10380 #define mmBL_PWM_PERIOD_CNTL 0x288a
10381 #define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2
10382 #define mmBL_PWM_GRP1_REG_LOCK 0x288b
10383 #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2
10384 #define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c
10385 #define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
10386 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d
10387 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
10388 #define mmDCIO_CLOCK_CNTL 0x2895
10389 #define mmDCIO_CLOCK_CNTL_BASE_IDX 2
10390 #define mmDIO_OTG_EXT_VSYNC_CNTL 0x2898
10391 #define mmDIO_OTG_EXT_VSYNC_CNTL_BASE_IDX 2
10392 #define mmDCIO_SOFT_RESET 0x289e
10393 #define mmDCIO_SOFT_RESET_BASE_IDX 2
10394 #define mmDCIO_DPHY_SEL 0x289f
10395 #define mmDCIO_DPHY_SEL_BASE_IDX 2
10396 #define mmUNIPHY_IMPCAL_LINKA 0x28a0
10397 #define mmUNIPHY_IMPCAL_LINKA_BASE_IDX 2
10398 #define mmUNIPHY_IMPCAL_LINKB 0x28a1
10399 #define mmUNIPHY_IMPCAL_LINKB_BASE_IDX 2
10400 #define mmUNIPHY_IMPCAL_PERIOD 0x28a2
10401 #define mmUNIPHY_IMPCAL_PERIOD_BASE_IDX 2
10402 #define mmAUXP_IMPCAL 0x28a3
10403 #define mmAUXP_IMPCAL_BASE_IDX 2
10404 #define mmAUXN_IMPCAL 0x28a4
10405 #define mmAUXN_IMPCAL_BASE_IDX 2
10406 #define mmDCIO_IMPCAL_CNTL 0x28a5
10407 #define mmDCIO_IMPCAL_CNTL_BASE_IDX 2
10408 #define mmUNIPHY_IMPCAL_PSW_AB 0x28a6
10409 #define mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX 2
10410 #define mmUNIPHY_IMPCAL_LINKC 0x28a7
10411 #define mmUNIPHY_IMPCAL_LINKC_BASE_IDX 2
10412 #define mmUNIPHY_IMPCAL_LINKD 0x28a8
10413 #define mmUNIPHY_IMPCAL_LINKD_BASE_IDX 2
10414 #define mmDCIO_IMPCAL_CNTL_CD 0x28a9
10415 #define mmDCIO_IMPCAL_CNTL_CD_BASE_IDX 2
10416 #define mmUNIPHY_IMPCAL_PSW_CD 0x28aa
10417 #define mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX 2
10418 #define mmUNIPHY_IMPCAL_LINKE 0x28ab
10419 #define mmUNIPHY_IMPCAL_LINKE_BASE_IDX 2
10420 #define mmUNIPHY_IMPCAL_LINKF 0x28ac
10421 #define mmUNIPHY_IMPCAL_LINKF_BASE_IDX 2
10422 #define mmDCIO_IMPCAL_CNTL_EF 0x28ad
10423 #define mmDCIO_IMPCAL_CNTL_EF_BASE_IDX 2
10424 #define mmUNIPHY_IMPCAL_PSW_EF 0x28ae
10425 #define mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX 2
10426 #define mmDCIO_DPCS_TX_INTERRUPT 0x28b3
10427 #define mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX 2
10428 #define mmDCIO_DPCS_RX_INTERRUPT 0x28b4
10429 #define mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX 2
10430 #define mmDCIO_SEMAPHORE0 0x28b5
10431 #define mmDCIO_SEMAPHORE0_BASE_IDX 2
10432 #define mmDCIO_SEMAPHORE1 0x28b6
10433 #define mmDCIO_SEMAPHORE1_BASE_IDX 2
10434 #define mmDCIO_SEMAPHORE2 0x28b7
10435 #define mmDCIO_SEMAPHORE2_BASE_IDX 2
10436 #define mmDCIO_SEMAPHORE3 0x28b8
10437 #define mmDCIO_SEMAPHORE3_BASE_IDX 2
10438 #define mmDCIO_SEMAPHORE4 0x28b9
10439 #define mmDCIO_SEMAPHORE4_BASE_IDX 2
10440 #define mmDCIO_SEMAPHORE5 0x28ba
10441 #define mmDCIO_SEMAPHORE5_BASE_IDX 2
10442 #define mmDCIO_SEMAPHORE6 0x28bb
10443 #define mmDCIO_SEMAPHORE6_BASE_IDX 2
10444 #define mmDCIO_SEMAPHORE7 0x28bc
10445 #define mmDCIO_SEMAPHORE7_BASE_IDX 2
10446 #define mmDCIO_USBC_FLIP_EN_SEL 0x28bd
10447 #define mmDCIO_USBC_FLIP_EN_SEL_BASE_IDX 2
10450 // addressBlock: dce_dc_dcio_dcio_chip_dispdec
10451 // base address: 0x0
10452 #define mmDC_GPIO_GENERIC_MASK 0x28c8
10453 #define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2
10454 #define mmDC_GPIO_GENERIC_A 0x28c9
10455 #define mmDC_GPIO_GENERIC_A_BASE_IDX 2
10456 #define mmDC_GPIO_GENERIC_EN 0x28ca
10457 #define mmDC_GPIO_GENERIC_EN_BASE_IDX 2
10458 #define mmDC_GPIO_GENERIC_Y 0x28cb
10459 #define mmDC_GPIO_GENERIC_Y_BASE_IDX 2
10460 #define mmDC_GPIO_DVODATA_MASK 0x28cc
10461 #define mmDC_GPIO_DVODATA_MASK_BASE_IDX 2
10462 #define mmDC_GPIO_DVODATA_A 0x28cd
10463 #define mmDC_GPIO_DVODATA_A_BASE_IDX 2
10464 #define mmDC_GPIO_DVODATA_EN 0x28ce
10465 #define mmDC_GPIO_DVODATA_EN_BASE_IDX 2
10466 #define mmDC_GPIO_DVODATA_Y 0x28cf
10467 #define mmDC_GPIO_DVODATA_Y_BASE_IDX 2
10468 #define mmDC_GPIO_DDC1_MASK 0x28d0
10469 #define mmDC_GPIO_DDC1_MASK_BASE_IDX 2
10470 #define mmDC_GPIO_DDC1_A 0x28d1
10471 #define mmDC_GPIO_DDC1_A_BASE_IDX 2
10472 #define mmDC_GPIO_DDC1_EN 0x28d2
10473 #define mmDC_GPIO_DDC1_EN_BASE_IDX 2
10474 #define mmDC_GPIO_DDC1_Y 0x28d3
10475 #define mmDC_GPIO_DDC1_Y_BASE_IDX 2
10476 #define mmDC_GPIO_DDC2_MASK 0x28d4
10477 #define mmDC_GPIO_DDC2_MASK_BASE_IDX 2
10478 #define mmDC_GPIO_DDC2_A 0x28d5
10479 #define mmDC_GPIO_DDC2_A_BASE_IDX 2
10480 #define mmDC_GPIO_DDC2_EN 0x28d6
10481 #define mmDC_GPIO_DDC2_EN_BASE_IDX 2
10482 #define mmDC_GPIO_DDC2_Y 0x28d7
10483 #define mmDC_GPIO_DDC2_Y_BASE_IDX 2
10484 #define mmDC_GPIO_DDC3_MASK 0x28d8
10485 #define mmDC_GPIO_DDC3_MASK_BASE_IDX 2
10486 #define mmDC_GPIO_DDC3_A 0x28d9
10487 #define mmDC_GPIO_DDC3_A_BASE_IDX 2
10488 #define mmDC_GPIO_DDC3_EN 0x28da
10489 #define mmDC_GPIO_DDC3_EN_BASE_IDX 2
10490 #define mmDC_GPIO_DDC3_Y 0x28db
10491 #define mmDC_GPIO_DDC3_Y_BASE_IDX 2
10492 #define mmDC_GPIO_DDC4_MASK 0x28dc
10493 #define mmDC_GPIO_DDC4_MASK_BASE_IDX 2
10494 #define mmDC_GPIO_DDC4_A 0x28dd
10495 #define mmDC_GPIO_DDC4_A_BASE_IDX 2
10496 #define mmDC_GPIO_DDC4_EN 0x28de
10497 #define mmDC_GPIO_DDC4_EN_BASE_IDX 2
10498 #define mmDC_GPIO_DDC4_Y 0x28df
10499 #define mmDC_GPIO_DDC4_Y_BASE_IDX 2
10500 #define mmDC_GPIO_DDC5_MASK 0x28e0
10501 #define mmDC_GPIO_DDC5_MASK_BASE_IDX 2
10502 #define mmDC_GPIO_DDC5_A 0x28e1
10503 #define mmDC_GPIO_DDC5_A_BASE_IDX 2
10504 #define mmDC_GPIO_DDC5_EN 0x28e2
10505 #define mmDC_GPIO_DDC5_EN_BASE_IDX 2
10506 #define mmDC_GPIO_DDC5_Y 0x28e3
10507 #define mmDC_GPIO_DDC5_Y_BASE_IDX 2
10508 #define mmDC_GPIO_DDC6_MASK 0x28e4
10509 #define mmDC_GPIO_DDC6_MASK_BASE_IDX 2
10510 #define mmDC_GPIO_DDC6_A 0x28e5
10511 #define mmDC_GPIO_DDC6_A_BASE_IDX 2
10512 #define mmDC_GPIO_DDC6_EN 0x28e6
10513 #define mmDC_GPIO_DDC6_EN_BASE_IDX 2
10514 #define mmDC_GPIO_DDC6_Y 0x28e7
10515 #define mmDC_GPIO_DDC6_Y_BASE_IDX 2
10516 #define mmDC_GPIO_DDCVGA_MASK 0x28e8
10517 #define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2
10518 #define mmDC_GPIO_DDCVGA_A 0x28e9
10519 #define mmDC_GPIO_DDCVGA_A_BASE_IDX 2
10520 #define mmDC_GPIO_DDCVGA_EN 0x28ea
10521 #define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2
10522 #define mmDC_GPIO_DDCVGA_Y 0x28eb
10523 #define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2
10524 #define mmDC_GPIO_SYNCA_MASK 0x28ec
10525 #define mmDC_GPIO_SYNCA_MASK_BASE_IDX 2
10526 #define mmDC_GPIO_SYNCA_A 0x28ed
10527 #define mmDC_GPIO_SYNCA_A_BASE_IDX 2
10528 #define mmDC_GPIO_SYNCA_EN 0x28ee
10529 #define mmDC_GPIO_SYNCA_EN_BASE_IDX 2
10530 #define mmDC_GPIO_SYNCA_Y 0x28ef
10531 #define mmDC_GPIO_SYNCA_Y_BASE_IDX 2
10532 #define mmDC_GPIO_GENLK_MASK 0x28f0
10533 #define mmDC_GPIO_GENLK_MASK_BASE_IDX 2
10534 #define mmDC_GPIO_GENLK_A 0x28f1
10535 #define mmDC_GPIO_GENLK_A_BASE_IDX 2
10536 #define mmDC_GPIO_GENLK_EN 0x28f2
10537 #define mmDC_GPIO_GENLK_EN_BASE_IDX 2
10538 #define mmDC_GPIO_GENLK_Y 0x28f3
10539 #define mmDC_GPIO_GENLK_Y_BASE_IDX 2
10540 #define mmDC_GPIO_HPD_MASK 0x28f4
10541 #define mmDC_GPIO_HPD_MASK_BASE_IDX 2
10542 #define mmDC_GPIO_HPD_A 0x28f5
10543 #define mmDC_GPIO_HPD_A_BASE_IDX 2
10544 #define mmDC_GPIO_HPD_EN 0x28f6
10545 #define mmDC_GPIO_HPD_EN_BASE_IDX 2
10546 #define mmDC_GPIO_HPD_Y 0x28f7
10547 #define mmDC_GPIO_HPD_Y_BASE_IDX 2
10548 #define mmDC_GPIO_PWRSEQ_MASK 0x28f8
10549 #define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2
10550 #define mmDC_GPIO_PWRSEQ_A 0x28f9
10551 #define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2
10552 #define mmDC_GPIO_PWRSEQ_EN 0x28fa
10553 #define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2
10554 #define mmDC_GPIO_PWRSEQ_Y 0x28fb
10555 #define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2
10556 #define mmDC_GPIO_PAD_STRENGTH_1 0x28fc
10557 #define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
10558 #define mmDC_GPIO_PAD_STRENGTH_2 0x28fd
10559 #define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2
10560 #define mmPHY_AUX_CNTL 0x28ff
10561 #define mmPHY_AUX_CNTL_BASE_IDX 2
10562 #define mmDC_GPIO_I2CPAD_MASK 0x2900
10563 #define mmDC_GPIO_I2CPAD_MASK_BASE_IDX 2
10564 #define mmDC_GPIO_I2CPAD_A 0x2901
10565 #define mmDC_GPIO_I2CPAD_A_BASE_IDX 2
10566 #define mmDC_GPIO_I2CPAD_EN 0x2902
10567 #define mmDC_GPIO_I2CPAD_EN_BASE_IDX 2
10568 #define mmDC_GPIO_I2CPAD_Y 0x2903
10569 #define mmDC_GPIO_I2CPAD_Y_BASE_IDX 2
10570 #define mmDC_GPIO_I2CPAD_STRENGTH 0x2904
10571 #define mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX 2
10572 #define mmDVO_STRENGTH_CONTROL 0x2905
10573 #define mmDVO_STRENGTH_CONTROL_BASE_IDX 2
10574 #define mmDVO_VREF_CONTROL 0x2906
10575 #define mmDVO_VREF_CONTROL_BASE_IDX 2
10576 #define mmDVO_SKEW_ADJUST 0x2907
10577 #define mmDVO_SKEW_ADJUST_BASE_IDX 2
10578 #define mmDC_GPIO_I2S_SPDIF_MASK 0x2910
10579 #define mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX 2
10580 #define mmDC_GPIO_I2S_SPDIF_A 0x2911
10581 #define mmDC_GPIO_I2S_SPDIF_A_BASE_IDX 2
10582 #define mmDC_GPIO_I2S_SPDIF_EN 0x2912
10583 #define mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX 2
10584 #define mmDC_GPIO_I2S_SPDIF_Y 0x2913
10585 #define mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX 2
10586 #define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x2914
10587 #define mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX 2
10588 #define mmDC_GPIO_TX12_EN 0x2915
10589 #define mmDC_GPIO_TX12_EN_BASE_IDX 2
10590 #define mmDC_GPIO_AUX_CTRL_0 0x2916
10591 #define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2
10592 #define mmDC_GPIO_AUX_CTRL_1 0x2917
10593 #define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2
10594 #define mmDC_GPIO_AUX_CTRL_2 0x2918
10595 #define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2
10596 #define mmDC_GPIO_RXEN 0x2919
10597 #define mmDC_GPIO_RXEN_BASE_IDX 2
10598 #define mmDC_GPIO_PULLUPEN 0x291a
10599 #define mmDC_GPIO_PULLUPEN_BASE_IDX 2
10602 // addressBlock: dce_dc_dcio_dcio_dac_dispdec
10603 // base address: 0x0
10604 #define mmDAC_MACRO_CNTL_RESERVED0 0x2920
10605 #define mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX 2
10606 #define mmDAC_MACRO_CNTL_RESERVED1 0x2921
10607 #define mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX 2
10608 #define mmDAC_MACRO_CNTL_RESERVED2 0x2922
10609 #define mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX 2
10610 #define mmDAC_MACRO_CNTL_RESERVED3 0x2923
10611 #define mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX 2
10614 // addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec
10615 // base address: 0x0
10616 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x2928
10617 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
10618 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x2929
10619 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
10620 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x292a
10621 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
10622 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x292b
10623 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
10624 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x292c
10625 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
10626 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x292d
10627 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
10628 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x292e
10629 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
10630 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x292f
10631 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
10632 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2930
10633 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
10634 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2931
10635 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
10636 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2932
10637 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
10638 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2933
10639 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
10640 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x2934
10641 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
10642 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x2935
10643 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
10644 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x2936
10645 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
10646 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x2937
10647 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
10648 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x2938
10649 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
10650 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x2939
10651 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
10652 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x293a
10653 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
10654 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x293b
10655 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
10656 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x293c
10657 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
10658 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x293d
10659 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
10660 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x293e
10661 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
10662 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x293f
10663 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
10664 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2940
10665 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
10666 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2941
10667 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
10668 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2942
10669 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
10670 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2943
10671 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
10672 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x2944
10673 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
10674 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x2945
10675 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
10676 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x2946
10677 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
10678 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x2947
10679 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
10680 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x2948
10681 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
10682 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x2949
10683 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
10684 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x294a
10685 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
10686 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x294b
10687 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
10688 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x294c
10689 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
10690 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x294d
10691 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
10692 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x294e
10693 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
10694 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x294f
10695 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
10696 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2950
10697 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
10698 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2951
10699 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
10700 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2952
10701 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
10702 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2953
10703 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
10704 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x2954
10705 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
10706 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x2955
10707 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
10708 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x2956
10709 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
10710 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x2957
10711 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
10712 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x2958
10713 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
10714 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x2959
10715 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
10716 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x295a
10717 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
10718 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x295b
10719 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
10720 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x295c
10721 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
10722 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x295d
10723 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
10724 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x295e
10725 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
10726 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x295f
10727 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
10728 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2960
10729 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
10730 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2961
10731 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
10732 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0x2962
10733 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
10734 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0x2963
10735 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
10736 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0x2964
10737 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
10738 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0x2965
10739 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
10740 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0x2966
10741 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
10742 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0x2967
10743 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
10744 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0x2968
10745 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
10746 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0x2969
10747 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
10748 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0x296a
10749 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
10750 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0x296b
10751 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
10752 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0x296c
10753 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
10754 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0x296d
10755 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
10756 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0x296e
10757 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
10758 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0x296f
10759 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
10760 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0x2970
10761 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
10762 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0x2971
10763 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
10764 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0x2972
10765 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
10766 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0x2973
10767 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
10768 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0x2974
10769 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
10770 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0x2975
10771 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
10772 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0x2976
10773 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
10774 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0x2977
10775 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
10776 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0x2978
10777 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
10778 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0x2979
10779 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
10780 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0x297a
10781 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
10782 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0x297b
10783 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
10784 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0x297c
10785 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
10786 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0x297d
10787 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
10788 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0x297e
10789 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
10790 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0x297f
10791 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
10792 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0x2980
10793 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
10794 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0x2981
10795 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
10796 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0x2982
10797 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
10798 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0x2983
10799 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
10800 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0x2984
10801 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
10802 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0x2985
10803 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
10804 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0x2986
10805 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
10806 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0x2987
10807 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
10808 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0x2988
10809 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
10810 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0x2989
10811 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
10812 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0x298a
10813 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
10814 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0x298b
10815 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
10816 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0x298c
10817 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
10818 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0x298d
10819 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
10820 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0x298e
10821 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
10822 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0x298f
10823 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
10824 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0x2990
10825 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
10826 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0x2991
10827 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
10828 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0x2992
10829 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
10830 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0x2993
10831 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
10832 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0x2994
10833 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
10834 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0x2995
10835 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
10836 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0x2996
10837 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
10838 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0x2997
10839 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
10840 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0x2998
10841 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
10842 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0x2999
10843 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
10844 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0x299a
10845 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
10846 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0x299b
10847 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
10848 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0x299c
10849 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
10850 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0x299d
10851 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
10852 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0x299e
10853 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
10854 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0x299f
10855 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
10856 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0x29a0
10857 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
10858 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0x29a1
10859 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
10860 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0x29a2
10861 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
10862 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0x29a3
10863 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
10864 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0x29a4
10865 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
10866 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0x29a5
10867 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
10868 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0x29a6
10869 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
10870 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0x29a7
10871 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
10872 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0x29a8
10873 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
10874 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0x29a9
10875 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
10876 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0x29aa
10877 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
10878 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0x29ab
10879 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
10880 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0x29ac
10881 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
10882 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0x29ad
10883 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
10884 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0x29ae
10885 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
10886 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0x29af
10887 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
10888 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0x29b0
10889 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
10890 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0x29b1
10891 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
10892 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0x29b2
10893 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
10894 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0x29b3
10895 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
10896 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0x29b4
10897 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
10898 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0x29b5
10899 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
10900 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0x29b6
10901 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
10902 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0x29b7
10903 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
10904 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0x29b8
10905 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
10906 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0x29b9
10907 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
10908 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0x29ba
10909 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
10910 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0x29bb
10911 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
10912 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0x29bc
10913 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
10914 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0x29bd
10915 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
10916 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0x29be
10917 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
10918 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0x29bf
10919 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
10920 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0x29c0
10921 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
10922 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0x29c1
10923 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
10924 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0x29c2
10925 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
10926 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0x29c3
10927 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
10928 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0x29c4
10929 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
10930 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0x29c5
10931 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
10932 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0x29c6
10933 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
10934 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0x29c7
10935 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
10938 // addressBlock: dce_dc_combophy_dc_combophycmregs0_dispdec
10939 // base address: 0x0
10940 #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 0x2928
10941 #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_BASE_IDX 2
10942 #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 0x2929
10943 #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_BASE_IDX 2
10944 #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 0x292a
10945 #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_BASE_IDX 2
10946 #define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0x292b
10947 #define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
10948 #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0x292c
10949 #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_BASE_IDX 2
10950 #define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0x292d
10951 #define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_BASE_IDX 2
10952 #define mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0x292e
10953 #define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_BASE_IDX 2
10954 #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0x292f
10955 #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_BASE_IDX 2
10956 #define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0x2930
10957 #define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_BASE_IDX 2
10958 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0x2931
10959 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_BASE_IDX 2
10960 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0x2932
10961 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_BASE_IDX 2
10962 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0x2933
10963 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_BASE_IDX 2
10964 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0x2934
10965 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_BASE_IDX 2
10966 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0x2935
10967 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_BASE_IDX 2
10968 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0x2936
10969 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_BASE_IDX 2
10970 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0x2937
10971 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_BASE_IDX 2
10974 // addressBlock: dce_dc_combophy_dc_combophytxregs0_dispdec
10975 // base address: 0x0
10976 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0x2948
10977 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
10978 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0x2949
10979 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_BASE_IDX 2
10980 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x294a
10981 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
10982 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0x294b
10983 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_BASE_IDX 2
10984 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0x294c
10985 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_BASE_IDX 2
10986 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0x294d
10987 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_BASE_IDX 2
10988 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0x294e
10989 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_BASE_IDX 2
10990 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0x294f
10991 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_BASE_IDX 2
10992 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0x2950
10993 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_BASE_IDX 2
10994 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0x2951
10995 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_BASE_IDX 2
10996 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0x2952
10997 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_BASE_IDX 2
10998 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0x2953
10999 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_BASE_IDX 2
11000 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0x2954
11001 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_BASE_IDX 2
11002 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0x2955
11003 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_BASE_IDX 2
11004 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0x2956
11005 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_BASE_IDX 2
11006 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0x2957
11007 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_BASE_IDX 2
11008 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0x2958
11009 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
11010 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0x2959
11011 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_BASE_IDX 2
11012 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x295a
11013 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
11014 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0x295b
11015 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_BASE_IDX 2
11016 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0x295c
11017 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_BASE_IDX 2
11018 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0x295d
11019 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_BASE_IDX 2
11020 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0x295e
11021 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_BASE_IDX 2
11022 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0x295f
11023 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_BASE_IDX 2
11024 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0x2960
11025 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_BASE_IDX 2
11026 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0x2961
11027 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_BASE_IDX 2
11028 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0x2962
11029 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_BASE_IDX 2
11030 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0x2963
11031 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_BASE_IDX 2
11032 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0x2964
11033 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_BASE_IDX 2
11034 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0x2965
11035 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_BASE_IDX 2
11036 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0x2966
11037 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_BASE_IDX 2
11038 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0x2967
11039 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_BASE_IDX 2
11040 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0x2968
11041 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
11042 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0x2969
11043 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_BASE_IDX 2
11044 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x296a
11045 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
11046 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0x296b
11047 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_BASE_IDX 2
11048 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0x296c
11049 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_BASE_IDX 2
11050 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0x296d
11051 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_BASE_IDX 2
11052 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0x296e
11053 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_BASE_IDX 2
11054 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0x296f
11055 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_BASE_IDX 2
11056 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0x2970
11057 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_BASE_IDX 2
11058 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0x2971
11059 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_BASE_IDX 2
11060 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0x2972
11061 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_BASE_IDX 2
11062 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0x2973
11063 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_BASE_IDX 2
11064 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0x2974
11065 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_BASE_IDX 2
11066 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0x2975
11067 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_BASE_IDX 2
11068 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0x2976
11069 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_BASE_IDX 2
11070 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0x2977
11071 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_BASE_IDX 2
11072 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0x2978
11073 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
11074 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0x2979
11075 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_BASE_IDX 2
11076 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x297a
11077 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
11078 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0x297b
11079 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_BASE_IDX 2
11080 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0x297c
11081 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_BASE_IDX 2
11082 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0x297d
11083 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_BASE_IDX 2
11084 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0x297e
11085 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_BASE_IDX 2
11086 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0x297f
11087 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_BASE_IDX 2
11088 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0x2980
11089 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_BASE_IDX 2
11090 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0x2981
11091 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_BASE_IDX 2
11092 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0x2982
11093 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_BASE_IDX 2
11094 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0x2983
11095 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_BASE_IDX 2
11096 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0x2984
11097 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_BASE_IDX 2
11098 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0x2985
11099 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_BASE_IDX 2
11100 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0x2986
11101 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_BASE_IDX 2
11102 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0x2987
11103 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_BASE_IDX 2
11106 // addressBlock: dce_dc_combophy_dc_combophypllregs0_dispdec
11107 // base address: 0x0
11108 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0x2988
11109 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_BASE_IDX 2
11110 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0x2989
11111 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_BASE_IDX 2
11112 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0x298a
11113 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_BASE_IDX 2
11114 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0x298b
11115 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_BASE_IDX 2
11116 #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0x298c
11117 #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_BASE_IDX 2
11118 #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0x298d
11119 #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_BASE_IDX 2
11120 #define mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0x298e
11121 #define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_BASE_IDX 2
11122 #define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0x298f
11123 #define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_BASE_IDX 2
11124 #define mmDC_COMBOPHYPLLREGS0_VREG_CFG 0x2991
11125 #define mmDC_COMBOPHYPLLREGS0_VREG_CFG_BASE_IDX 2
11126 #define mmDC_COMBOPHYPLLREGS0_OBSERVE0 0x2992
11127 #define mmDC_COMBOPHYPLLREGS0_OBSERVE0_BASE_IDX 2
11128 #define mmDC_COMBOPHYPLLREGS0_OBSERVE1 0x2993
11129 #define mmDC_COMBOPHYPLLREGS0_OBSERVE1_BASE_IDX 2
11130 #define mmDC_COMBOPHYPLLREGS0_DFT_OUT 0x2994
11131 #define mmDC_COMBOPHYPLLREGS0_DFT_OUT_BASE_IDX 2
11132 #define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1 0x29c6
11133 #define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1_BASE_IDX 2
11134 #define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL 0x29c7
11135 #define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL_BASE_IDX 2
11138 // addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
11139 // base address: 0x360
11140 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00
11141 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
11142 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01
11143 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
11144 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02
11145 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
11146 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03
11147 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
11148 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04
11149 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
11150 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05
11151 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
11152 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06
11153 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
11154 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07
11155 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
11156 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08
11157 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
11158 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09
11159 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
11160 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a
11161 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
11162 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b
11163 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
11164 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c
11165 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
11166 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d
11167 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
11168 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e
11169 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
11170 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f
11171 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
11172 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10
11173 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
11174 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11
11175 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
11176 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12
11177 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
11178 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13
11179 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
11180 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14
11181 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
11182 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15
11183 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
11184 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16
11185 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
11186 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17
11187 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
11188 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18
11189 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
11190 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19
11191 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
11192 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a
11193 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
11194 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b
11195 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
11196 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c
11197 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
11198 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d
11199 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
11200 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e
11201 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
11202 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f
11203 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
11204 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20
11205 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
11206 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21
11207 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
11208 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22
11209 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
11210 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23
11211 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
11212 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24
11213 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
11214 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25
11215 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
11216 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26
11217 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
11218 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27
11219 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
11220 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28
11221 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
11222 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29
11223 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
11224 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a
11225 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
11226 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b
11227 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
11228 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c
11229 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
11230 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d
11231 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
11232 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e
11233 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
11234 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f
11235 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
11236 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30
11237 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
11238 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31
11239 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
11240 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32
11241 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
11242 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33
11243 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
11244 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34
11245 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
11246 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35
11247 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
11248 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36
11249 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
11250 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37
11251 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
11252 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38
11253 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
11254 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39
11255 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
11256 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0x2a3a
11257 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
11258 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0x2a3b
11259 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
11260 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0x2a3c
11261 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
11262 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0x2a3d
11263 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
11264 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0x2a3e
11265 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
11266 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0x2a3f
11267 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
11268 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0x2a40
11269 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
11270 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0x2a41
11271 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
11272 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0x2a42
11273 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
11274 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0x2a43
11275 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
11276 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0x2a44
11277 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
11278 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0x2a45
11279 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
11280 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0x2a46
11281 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
11282 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0x2a47
11283 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
11284 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0x2a48
11285 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
11286 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0x2a49
11287 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
11288 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0x2a4a
11289 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
11290 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0x2a4b
11291 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
11292 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0x2a4c
11293 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
11294 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0x2a4d
11295 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
11296 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0x2a4e
11297 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
11298 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0x2a4f
11299 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
11300 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0x2a50
11301 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
11302 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0x2a51
11303 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
11304 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0x2a52
11305 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
11306 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0x2a53
11307 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
11308 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0x2a54
11309 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
11310 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0x2a55
11311 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
11312 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0x2a56
11313 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
11314 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0x2a57
11315 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
11316 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0x2a58
11317 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
11318 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0x2a59
11319 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
11320 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0x2a5a
11321 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
11322 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0x2a5b
11323 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
11324 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0x2a5c
11325 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
11326 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0x2a5d
11327 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
11328 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0x2a5e
11329 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
11330 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0x2a5f
11331 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
11332 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0x2a60
11333 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
11334 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0x2a61
11335 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
11336 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0x2a62
11337 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
11338 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0x2a63
11339 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
11340 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0x2a64
11341 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
11342 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0x2a65
11343 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
11344 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0x2a66
11345 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
11346 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0x2a67
11347 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
11348 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0x2a68
11349 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
11350 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0x2a69
11351 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
11352 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0x2a6a
11353 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
11354 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0x2a6b
11355 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
11356 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0x2a6c
11357 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
11358 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0x2a6d
11359 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
11360 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0x2a6e
11361 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
11362 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0x2a6f
11363 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
11364 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0x2a70
11365 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
11366 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0x2a71
11367 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
11368 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0x2a72
11369 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
11370 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0x2a73
11371 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
11372 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0x2a74
11373 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
11374 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0x2a75
11375 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
11376 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0x2a76
11377 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
11378 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0x2a77
11379 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
11380 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0x2a78
11381 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
11382 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0x2a79
11383 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
11384 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0x2a7a
11385 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
11386 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0x2a7b
11387 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
11388 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0x2a7c
11389 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
11390 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0x2a7d
11391 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
11392 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0x2a7e
11393 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
11394 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0x2a7f
11395 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
11396 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0x2a80
11397 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
11398 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0x2a81
11399 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
11400 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0x2a82
11401 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
11402 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0x2a83
11403 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
11404 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0x2a84
11405 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
11406 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0x2a85
11407 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
11408 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0x2a86
11409 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
11410 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0x2a87
11411 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
11412 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0x2a88
11413 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
11414 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0x2a89
11415 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
11416 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0x2a8a
11417 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
11418 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0x2a8b
11419 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
11420 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0x2a8c
11421 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
11422 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0x2a8d
11423 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
11424 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0x2a8e
11425 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
11426 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0x2a8f
11427 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
11428 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0x2a90
11429 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
11430 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0x2a91
11431 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
11432 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0x2a92
11433 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
11434 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0x2a93
11435 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
11436 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0x2a94
11437 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
11438 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0x2a95
11439 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
11440 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0x2a96
11441 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
11442 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0x2a97
11443 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
11444 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0x2a98
11445 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
11446 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0x2a99
11447 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
11448 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0x2a9a
11449 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
11450 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0x2a9b
11451 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
11452 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0x2a9c
11453 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
11454 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0x2a9d
11455 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
11456 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0x2a9e
11457 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
11458 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0x2a9f
11459 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
11462 // addressBlock: dce_dc_combophy_dc_combophycmregs1_dispdec
11463 // base address: 0x360
11464 #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 0x2a00
11465 #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_BASE_IDX 2
11466 #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 0x2a01
11467 #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_BASE_IDX 2
11468 #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 0x2a02
11469 #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_BASE_IDX 2
11470 #define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0x2a03
11471 #define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
11472 #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0x2a04
11473 #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_BASE_IDX 2
11474 #define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0x2a05
11475 #define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_BASE_IDX 2
11476 #define mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0x2a06
11477 #define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_BASE_IDX 2
11478 #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0x2a07
11479 #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_BASE_IDX 2
11480 #define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0x2a08
11481 #define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_BASE_IDX 2
11482 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0x2a09
11483 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_BASE_IDX 2
11484 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0x2a0a
11485 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_BASE_IDX 2
11486 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0x2a0b
11487 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_BASE_IDX 2
11488 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0x2a0c
11489 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_BASE_IDX 2
11490 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0x2a0d
11491 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_BASE_IDX 2
11492 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0x2a0e
11493 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_BASE_IDX 2
11494 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0x2a0f
11495 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_BASE_IDX 2
11498 // addressBlock: dce_dc_combophy_dc_combophytxregs1_dispdec
11499 // base address: 0x360
11500 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0x2a20
11501 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
11502 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0x2a21
11503 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_BASE_IDX 2
11504 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2a22
11505 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
11506 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0x2a23
11507 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_BASE_IDX 2
11508 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0x2a24
11509 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_BASE_IDX 2
11510 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0x2a25
11511 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_BASE_IDX 2
11512 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0x2a26
11513 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_BASE_IDX 2
11514 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0x2a27
11515 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_BASE_IDX 2
11516 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0x2a28
11517 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_BASE_IDX 2
11518 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0x2a29
11519 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_BASE_IDX 2
11520 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0x2a2a
11521 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_BASE_IDX 2
11522 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0x2a2b
11523 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_BASE_IDX 2
11524 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0x2a2c
11525 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_BASE_IDX 2
11526 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0x2a2d
11527 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_BASE_IDX 2
11528 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0x2a2e
11529 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_BASE_IDX 2
11530 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0x2a2f
11531 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_BASE_IDX 2
11532 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0x2a30
11533 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
11534 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0x2a31
11535 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_BASE_IDX 2
11536 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2a32
11537 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
11538 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0x2a33
11539 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_BASE_IDX 2
11540 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0x2a34
11541 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_BASE_IDX 2
11542 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0x2a35
11543 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_BASE_IDX 2
11544 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0x2a36
11545 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_BASE_IDX 2
11546 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0x2a37
11547 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_BASE_IDX 2
11548 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0x2a38
11549 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_BASE_IDX 2
11550 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0x2a39
11551 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_BASE_IDX 2
11552 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0x2a3a
11553 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_BASE_IDX 2
11554 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0x2a3b
11555 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_BASE_IDX 2
11556 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0x2a3c
11557 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_BASE_IDX 2
11558 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0x2a3d
11559 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_BASE_IDX 2
11560 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0x2a3e
11561 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_BASE_IDX 2
11562 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0x2a3f
11563 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_BASE_IDX 2
11564 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0x2a40
11565 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
11566 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0x2a41
11567 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_BASE_IDX 2
11568 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2a42
11569 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
11570 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0x2a43
11571 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_BASE_IDX 2
11572 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0x2a44
11573 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_BASE_IDX 2
11574 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0x2a45
11575 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_BASE_IDX 2
11576 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0x2a46
11577 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_BASE_IDX 2
11578 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0x2a47
11579 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_BASE_IDX 2
11580 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0x2a48
11581 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_BASE_IDX 2
11582 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0x2a49
11583 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_BASE_IDX 2
11584 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0x2a4a
11585 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_BASE_IDX 2
11586 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0x2a4b
11587 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_BASE_IDX 2
11588 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0x2a4c
11589 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_BASE_IDX 2
11590 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0x2a4d
11591 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_BASE_IDX 2
11592 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0x2a4e
11593 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_BASE_IDX 2
11594 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0x2a4f
11595 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_BASE_IDX 2
11596 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0x2a50
11597 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
11598 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0x2a51
11599 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_BASE_IDX 2
11600 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2a52
11601 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
11602 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0x2a53
11603 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_BASE_IDX 2
11604 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0x2a54
11605 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_BASE_IDX 2
11606 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0x2a55
11607 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_BASE_IDX 2
11608 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0x2a56
11609 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_BASE_IDX 2
11610 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0x2a57
11611 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_BASE_IDX 2
11612 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0x2a58
11613 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_BASE_IDX 2
11614 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0x2a59
11615 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_BASE_IDX 2
11616 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0x2a5a
11617 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_BASE_IDX 2
11618 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0x2a5b
11619 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_BASE_IDX 2
11620 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0x2a5c
11621 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_BASE_IDX 2
11622 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0x2a5d
11623 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_BASE_IDX 2
11624 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0x2a5e
11625 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_BASE_IDX 2
11626 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0x2a5f
11627 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_BASE_IDX 2
11630 // addressBlock: dce_dc_combophy_dc_combophypllregs1_dispdec
11631 // base address: 0x360
11632 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0x2a60
11633 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_BASE_IDX 2
11634 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0x2a61
11635 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_BASE_IDX 2
11636 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0x2a62
11637 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_BASE_IDX 2
11638 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0x2a63
11639 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_BASE_IDX 2
11640 #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0x2a64
11641 #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_BASE_IDX 2
11642 #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0x2a65
11643 #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_BASE_IDX 2
11644 #define mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0x2a66
11645 #define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_BASE_IDX 2
11646 #define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0x2a67
11647 #define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_BASE_IDX 2
11648 #define mmDC_COMBOPHYPLLREGS1_VREG_CFG 0x2a69
11649 #define mmDC_COMBOPHYPLLREGS1_VREG_CFG_BASE_IDX 2
11650 #define mmDC_COMBOPHYPLLREGS1_OBSERVE0 0x2a6a
11651 #define mmDC_COMBOPHYPLLREGS1_OBSERVE0_BASE_IDX 2
11652 #define mmDC_COMBOPHYPLLREGS1_OBSERVE1 0x2a6b
11653 #define mmDC_COMBOPHYPLLREGS1_OBSERVE1_BASE_IDX 2
11654 #define mmDC_COMBOPHYPLLREGS1_DFT_OUT 0x2a6c
11655 #define mmDC_COMBOPHYPLLREGS1_DFT_OUT_BASE_IDX 2
11656 #define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1 0x2a9e
11657 #define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1_BASE_IDX 2
11658 #define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL 0x2a9f
11659 #define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL_BASE_IDX 2
11662 // addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
11663 // base address: 0x6c0
11664 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8
11665 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
11666 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9
11667 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
11668 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada
11669 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
11670 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb
11671 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
11672 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc
11673 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
11674 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add
11675 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
11676 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade
11677 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
11678 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf
11679 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
11680 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0
11681 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
11682 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1
11683 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
11684 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2
11685 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
11686 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3
11687 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
11688 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4
11689 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
11690 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5
11691 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
11692 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6
11693 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
11694 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7
11695 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
11696 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8
11697 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
11698 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9
11699 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
11700 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea
11701 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
11702 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb
11703 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
11704 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec
11705 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
11706 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed
11707 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
11708 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee
11709 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
11710 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef
11711 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
11712 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0
11713 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
11714 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1
11715 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
11716 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2
11717 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
11718 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3
11719 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
11720 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4
11721 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
11722 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5
11723 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
11724 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6
11725 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
11726 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7
11727 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
11728 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8
11729 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
11730 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9
11731 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
11732 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa
11733 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
11734 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb
11735 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
11736 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc
11737 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
11738 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd
11739 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
11740 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe
11741 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
11742 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff
11743 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
11744 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00
11745 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
11746 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01
11747 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
11748 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02
11749 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
11750 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03
11751 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
11752 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04
11753 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
11754 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05
11755 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
11756 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06
11757 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
11758 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07
11759 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
11760 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08
11761 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
11762 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09
11763 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
11764 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a
11765 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
11766 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b
11767 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
11768 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c
11769 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
11770 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d
11771 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
11772 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e
11773 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
11774 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f
11775 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
11776 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10
11777 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
11778 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11
11779 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
11780 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0x2b12
11781 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
11782 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0x2b13
11783 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
11784 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0x2b14
11785 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
11786 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0x2b15
11787 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
11788 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0x2b16
11789 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
11790 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0x2b17
11791 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
11792 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0x2b18
11793 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
11794 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0x2b19
11795 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
11796 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0x2b1a
11797 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
11798 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0x2b1b
11799 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
11800 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0x2b1c
11801 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
11802 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0x2b1d
11803 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
11804 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0x2b1e
11805 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
11806 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0x2b1f
11807 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
11808 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0x2b20
11809 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
11810 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0x2b21
11811 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
11812 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0x2b22
11813 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
11814 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0x2b23
11815 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
11816 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0x2b24
11817 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
11818 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0x2b25
11819 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
11820 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0x2b26
11821 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
11822 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0x2b27
11823 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
11824 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0x2b28
11825 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
11826 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0x2b29
11827 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
11828 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0x2b2a
11829 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
11830 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0x2b2b
11831 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
11832 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0x2b2c
11833 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
11834 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0x2b2d
11835 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
11836 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0x2b2e
11837 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
11838 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0x2b2f
11839 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
11840 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0x2b30
11841 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
11842 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0x2b31
11843 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
11844 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0x2b32
11845 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
11846 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0x2b33
11847 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
11848 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0x2b34
11849 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
11850 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0x2b35
11851 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
11852 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0x2b36
11853 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
11854 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0x2b37
11855 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
11856 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0x2b38
11857 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
11858 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0x2b39
11859 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
11860 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0x2b3a
11861 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
11862 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0x2b3b
11863 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
11864 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0x2b3c
11865 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
11866 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0x2b3d
11867 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
11868 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0x2b3e
11869 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
11870 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0x2b3f
11871 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
11872 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0x2b40
11873 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
11874 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0x2b41
11875 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
11876 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0x2b42
11877 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
11878 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0x2b43
11879 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
11880 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0x2b44
11881 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
11882 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0x2b45
11883 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
11884 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0x2b46
11885 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
11886 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0x2b47
11887 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
11888 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0x2b48
11889 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
11890 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0x2b49
11891 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
11892 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0x2b4a
11893 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
11894 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0x2b4b
11895 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
11896 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0x2b4c
11897 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
11898 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0x2b4d
11899 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
11900 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0x2b4e
11901 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
11902 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0x2b4f
11903 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
11904 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0x2b50
11905 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
11906 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0x2b51
11907 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
11908 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0x2b52
11909 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
11910 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0x2b53
11911 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
11912 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0x2b54
11913 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
11914 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0x2b55
11915 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
11916 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0x2b56
11917 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
11918 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0x2b57
11919 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
11920 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0x2b58
11921 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
11922 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0x2b59
11923 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
11924 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0x2b5a
11925 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
11926 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0x2b5b
11927 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
11928 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0x2b5c
11929 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
11930 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0x2b5d
11931 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
11932 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0x2b5e
11933 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
11934 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0x2b5f
11935 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
11936 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0x2b60
11937 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
11938 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0x2b61
11939 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
11940 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0x2b62
11941 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
11942 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0x2b63
11943 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
11944 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0x2b64
11945 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
11946 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0x2b65
11947 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
11948 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0x2b66
11949 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
11950 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0x2b67
11951 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
11952 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0x2b68
11953 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
11954 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0x2b69
11955 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
11956 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0x2b6a
11957 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
11958 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0x2b6b
11959 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
11960 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0x2b6c
11961 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
11962 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0x2b6d
11963 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
11964 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0x2b6e
11965 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
11966 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0x2b6f
11967 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
11968 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0x2b70
11969 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
11970 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0x2b71
11971 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
11972 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0x2b72
11973 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
11974 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0x2b73
11975 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
11976 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0x2b74
11977 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
11978 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0x2b75
11979 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
11980 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0x2b76
11981 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
11982 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0x2b77
11983 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
11986 // addressBlock: dce_dc_combophy_dc_combophycmregs2_dispdec
11987 // base address: 0x6c0
11988 #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 0x2ad8
11989 #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_BASE_IDX 2
11990 #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 0x2ad9
11991 #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_BASE_IDX 2
11992 #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 0x2ada
11993 #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_BASE_IDX 2
11994 #define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0x2adb
11995 #define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
11996 #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0x2adc
11997 #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_BASE_IDX 2
11998 #define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0x2add
11999 #define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_BASE_IDX 2
12000 #define mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0x2ade
12001 #define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_BASE_IDX 2
12002 #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0x2adf
12003 #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_BASE_IDX 2
12004 #define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0x2ae0
12005 #define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_BASE_IDX 2
12006 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0x2ae1
12007 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_BASE_IDX 2
12008 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0x2ae2
12009 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_BASE_IDX 2
12010 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0x2ae3
12011 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_BASE_IDX 2
12012 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0x2ae4
12013 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_BASE_IDX 2
12014 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0x2ae5
12015 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_BASE_IDX 2
12016 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0x2ae6
12017 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_BASE_IDX 2
12018 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0x2ae7
12019 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_BASE_IDX 2
12022 // addressBlock: dce_dc_combophy_dc_combophytxregs2_dispdec
12023 // base address: 0x6c0
12024 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0x2af8
12025 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
12026 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0x2af9
12027 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_BASE_IDX 2
12028 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2afa
12029 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
12030 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0x2afb
12031 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_BASE_IDX 2
12032 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0x2afc
12033 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_BASE_IDX 2
12034 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0x2afd
12035 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_BASE_IDX 2
12036 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0x2afe
12037 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_BASE_IDX 2
12038 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0x2aff
12039 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_BASE_IDX 2
12040 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0x2b00
12041 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_BASE_IDX 2
12042 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0x2b01
12043 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_BASE_IDX 2
12044 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0x2b02
12045 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_BASE_IDX 2
12046 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0x2b03
12047 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_BASE_IDX 2
12048 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0x2b04
12049 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_BASE_IDX 2
12050 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0x2b05
12051 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_BASE_IDX 2
12052 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0x2b06
12053 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_BASE_IDX 2
12054 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0x2b07
12055 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_BASE_IDX 2
12056 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0x2b08
12057 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
12058 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0x2b09
12059 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_BASE_IDX 2
12060 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2b0a
12061 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
12062 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0x2b0b
12063 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_BASE_IDX 2
12064 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0x2b0c
12065 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_BASE_IDX 2
12066 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0x2b0d
12067 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_BASE_IDX 2
12068 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0x2b0e
12069 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_BASE_IDX 2
12070 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0x2b0f
12071 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_BASE_IDX 2
12072 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0x2b10
12073 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_BASE_IDX 2
12074 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0x2b11
12075 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_BASE_IDX 2
12076 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0x2b12
12077 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_BASE_IDX 2
12078 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0x2b13
12079 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_BASE_IDX 2
12080 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0x2b14
12081 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_BASE_IDX 2
12082 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0x2b15
12083 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_BASE_IDX 2
12084 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0x2b16
12085 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_BASE_IDX 2
12086 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0x2b17
12087 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_BASE_IDX 2
12088 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0x2b18
12089 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
12090 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0x2b19
12091 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_BASE_IDX 2
12092 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2b1a
12093 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
12094 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0x2b1b
12095 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_BASE_IDX 2
12096 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0x2b1c
12097 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_BASE_IDX 2
12098 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0x2b1d
12099 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_BASE_IDX 2
12100 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0x2b1e
12101 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_BASE_IDX 2
12102 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0x2b1f
12103 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_BASE_IDX 2
12104 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0x2b20
12105 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_BASE_IDX 2
12106 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0x2b21
12107 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_BASE_IDX 2
12108 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0x2b22
12109 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_BASE_IDX 2
12110 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0x2b23
12111 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_BASE_IDX 2
12112 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0x2b24
12113 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_BASE_IDX 2
12114 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0x2b25
12115 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_BASE_IDX 2
12116 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0x2b26
12117 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_BASE_IDX 2
12118 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0x2b27
12119 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_BASE_IDX 2
12120 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0x2b28
12121 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
12122 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0x2b29
12123 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_BASE_IDX 2
12124 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2b2a
12125 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
12126 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0x2b2b
12127 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_BASE_IDX 2
12128 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0x2b2c
12129 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_BASE_IDX 2
12130 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0x2b2d
12131 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_BASE_IDX 2
12132 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0x2b2e
12133 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_BASE_IDX 2
12134 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0x2b2f
12135 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_BASE_IDX 2
12136 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0x2b30
12137 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_BASE_IDX 2
12138 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0x2b31
12139 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_BASE_IDX 2
12140 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0x2b32
12141 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_BASE_IDX 2
12142 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0x2b33
12143 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_BASE_IDX 2
12144 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0x2b34
12145 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_BASE_IDX 2
12146 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0x2b35
12147 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_BASE_IDX 2
12148 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0x2b36
12149 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_BASE_IDX 2
12150 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0x2b37
12151 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_BASE_IDX 2
12154 // addressBlock: dce_dc_combophy_dc_combophypllregs2_dispdec
12155 // base address: 0x6c0
12156 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0x2b38
12157 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_BASE_IDX 2
12158 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0x2b39
12159 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_BASE_IDX 2
12160 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0x2b3a
12161 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_BASE_IDX 2
12162 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0x2b3b
12163 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_BASE_IDX 2
12164 #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0x2b3c
12165 #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_BASE_IDX 2
12166 #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0x2b3d
12167 #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_BASE_IDX 2
12168 #define mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0x2b3e
12169 #define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_BASE_IDX 2
12170 #define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0x2b3f
12171 #define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_BASE_IDX 2
12172 #define mmDC_COMBOPHYPLLREGS2_VREG_CFG 0x2b41
12173 #define mmDC_COMBOPHYPLLREGS2_VREG_CFG_BASE_IDX 2
12174 #define mmDC_COMBOPHYPLLREGS2_OBSERVE0 0x2b42
12175 #define mmDC_COMBOPHYPLLREGS2_OBSERVE0_BASE_IDX 2
12176 #define mmDC_COMBOPHYPLLREGS2_OBSERVE1 0x2b43
12177 #define mmDC_COMBOPHYPLLREGS2_OBSERVE1_BASE_IDX 2
12178 #define mmDC_COMBOPHYPLLREGS2_DFT_OUT 0x2b44
12179 #define mmDC_COMBOPHYPLLREGS2_DFT_OUT_BASE_IDX 2
12180 #define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1 0x2b76
12181 #define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1_BASE_IDX 2
12182 #define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL 0x2b77
12183 #define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL_BASE_IDX 2
12186 // addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
12187 // base address: 0xa20
12188 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0
12189 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
12190 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1
12191 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
12192 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2
12193 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
12194 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3
12195 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
12196 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4
12197 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
12198 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5
12199 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
12200 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6
12201 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
12202 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7
12203 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
12204 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8
12205 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
12206 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9
12207 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
12208 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba
12209 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
12210 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb
12211 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
12212 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc
12213 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
12214 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd
12215 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
12216 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe
12217 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
12218 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf
12219 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
12220 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0
12221 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
12222 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1
12223 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
12224 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2
12225 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
12226 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3
12227 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
12228 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4
12229 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
12230 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5
12231 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
12232 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6
12233 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
12234 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7
12235 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
12236 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8
12237 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
12238 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9
12239 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
12240 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca
12241 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
12242 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb
12243 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
12244 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc
12245 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
12246 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd
12247 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
12248 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce
12249 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
12250 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf
12251 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
12252 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0
12253 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
12254 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1
12255 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
12256 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2
12257 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
12258 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3
12259 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
12260 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4
12261 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
12262 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5
12263 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
12264 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6
12265 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
12266 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7
12267 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
12268 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8
12269 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
12270 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9
12271 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
12272 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda
12273 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
12274 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb
12275 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
12276 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc
12277 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
12278 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd
12279 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
12280 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde
12281 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
12282 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf
12283 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
12284 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0
12285 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
12286 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1
12287 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
12288 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2
12289 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
12290 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3
12291 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
12292 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4
12293 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
12294 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5
12295 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
12296 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6
12297 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
12298 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7
12299 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
12300 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8
12301 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
12302 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9
12303 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
12304 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0x2bea
12305 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
12306 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0x2beb
12307 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
12308 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0x2bec
12309 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
12310 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0x2bed
12311 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
12312 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0x2bee
12313 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
12314 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0x2bef
12315 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
12316 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0x2bf0
12317 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
12318 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0x2bf1
12319 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
12320 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0x2bf2
12321 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
12322 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0x2bf3
12323 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
12324 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0x2bf4
12325 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
12326 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0x2bf5
12327 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
12328 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0x2bf6
12329 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
12330 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0x2bf7
12331 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
12332 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0x2bf8
12333 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
12334 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0x2bf9
12335 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
12336 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0x2bfa
12337 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
12338 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0x2bfb
12339 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
12340 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0x2bfc
12341 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
12342 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0x2bfd
12343 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
12344 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0x2bfe
12345 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
12346 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0x2bff
12347 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
12348 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0x2c00
12349 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
12350 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0x2c01
12351 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
12352 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0x2c02
12353 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
12354 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0x2c03
12355 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
12356 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0x2c04
12357 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
12358 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0x2c05
12359 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
12360 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0x2c06
12361 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
12362 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0x2c07
12363 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
12364 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0x2c08
12365 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
12366 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0x2c09
12367 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
12368 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0x2c0a
12369 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
12370 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0x2c0b
12371 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
12372 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0x2c0c
12373 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
12374 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0x2c0d
12375 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
12376 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0x2c0e
12377 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
12378 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0x2c0f
12379 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
12380 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0x2c10
12381 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
12382 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0x2c11
12383 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
12384 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0x2c12
12385 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
12386 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0x2c13
12387 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
12388 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0x2c14
12389 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
12390 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0x2c15
12391 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
12392 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0x2c16
12393 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
12394 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0x2c17
12395 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
12396 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0x2c18
12397 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
12398 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0x2c19
12399 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
12400 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0x2c1a
12401 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
12402 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0x2c1b
12403 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
12404 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0x2c1c
12405 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
12406 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0x2c1d
12407 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
12408 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0x2c1e
12409 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
12410 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0x2c1f
12411 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
12412 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0x2c20
12413 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
12414 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0x2c21
12415 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
12416 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0x2c22
12417 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
12418 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0x2c23
12419 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
12420 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0x2c24
12421 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
12422 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0x2c25
12423 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
12424 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0x2c26
12425 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
12426 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0x2c27
12427 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
12428 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0x2c28
12429 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
12430 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0x2c29
12431 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
12432 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0x2c2a
12433 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
12434 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0x2c2b
12435 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
12436 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0x2c2c
12437 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
12438 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0x2c2d
12439 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
12440 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0x2c2e
12441 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
12442 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0x2c2f
12443 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
12444 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0x2c30
12445 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
12446 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0x2c31
12447 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
12448 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0x2c32
12449 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
12450 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0x2c33
12451 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
12452 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0x2c34
12453 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
12454 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0x2c35
12455 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
12456 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0x2c36
12457 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
12458 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0x2c37
12459 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
12460 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0x2c38
12461 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
12462 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0x2c39
12463 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
12464 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0x2c3a
12465 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
12466 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0x2c3b
12467 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
12468 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0x2c3c
12469 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
12470 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0x2c3d
12471 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
12472 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0x2c3e
12473 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
12474 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0x2c3f
12475 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
12476 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0x2c40
12477 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
12478 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0x2c41
12479 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
12480 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0x2c42
12481 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
12482 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0x2c43
12483 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
12484 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0x2c44
12485 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
12486 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0x2c45
12487 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
12488 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0x2c46
12489 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
12490 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0x2c47
12491 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
12492 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0x2c48
12493 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
12494 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0x2c49
12495 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
12496 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0x2c4a
12497 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
12498 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0x2c4b
12499 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
12500 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0x2c4c
12501 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
12502 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0x2c4d
12503 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
12504 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0x2c4e
12505 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
12506 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0x2c4f
12507 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
12510 // addressBlock: dce_dc_combophy_dc_combophycmregs3_dispdec
12511 // base address: 0xa20
12512 #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 0x2bb0
12513 #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_BASE_IDX 2
12514 #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 0x2bb1
12515 #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_BASE_IDX 2
12516 #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 0x2bb2
12517 #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_BASE_IDX 2
12518 #define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0x2bb3
12519 #define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
12520 #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0x2bb4
12521 #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_BASE_IDX 2
12522 #define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0x2bb5
12523 #define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_BASE_IDX 2
12524 #define mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0x2bb6
12525 #define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_BASE_IDX 2
12526 #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0x2bb7
12527 #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_BASE_IDX 2
12528 #define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0x2bb8
12529 #define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_BASE_IDX 2
12530 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0x2bb9
12531 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_BASE_IDX 2
12532 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0x2bba
12533 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_BASE_IDX 2
12534 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0x2bbb
12535 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_BASE_IDX 2
12536 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0x2bbc
12537 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_BASE_IDX 2
12538 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0x2bbd
12539 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_BASE_IDX 2
12540 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0x2bbe
12541 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_BASE_IDX 2
12542 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0x2bbf
12543 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_BASE_IDX 2
12546 // addressBlock: dce_dc_combophy_dc_combophytxregs3_dispdec
12547 // base address: 0xa20
12548 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0x2bd0
12549 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
12550 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0x2bd1
12551 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_BASE_IDX 2
12552 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2bd2
12553 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
12554 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0x2bd3
12555 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_BASE_IDX 2
12556 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0x2bd4
12557 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_BASE_IDX 2
12558 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0x2bd5
12559 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_BASE_IDX 2
12560 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0x2bd6
12561 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_BASE_IDX 2
12562 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0x2bd7
12563 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_BASE_IDX 2
12564 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0x2bd8
12565 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_BASE_IDX 2
12566 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0x2bd9
12567 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_BASE_IDX 2
12568 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0x2bda
12569 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_BASE_IDX 2
12570 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0x2bdb
12571 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_BASE_IDX 2
12572 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0x2bdc
12573 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_BASE_IDX 2
12574 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0x2bdd
12575 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_BASE_IDX 2
12576 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0x2bde
12577 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_BASE_IDX 2
12578 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0x2bdf
12579 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_BASE_IDX 2
12580 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0x2be0
12581 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
12582 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0x2be1
12583 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_BASE_IDX 2
12584 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2be2
12585 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
12586 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0x2be3
12587 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_BASE_IDX 2
12588 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0x2be4
12589 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_BASE_IDX 2
12590 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0x2be5
12591 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_BASE_IDX 2
12592 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0x2be6
12593 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_BASE_IDX 2
12594 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0x2be7
12595 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_BASE_IDX 2
12596 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0x2be8
12597 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_BASE_IDX 2
12598 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0x2be9
12599 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_BASE_IDX 2
12600 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0x2bea
12601 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_BASE_IDX 2
12602 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0x2beb
12603 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_BASE_IDX 2
12604 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0x2bec
12605 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_BASE_IDX 2
12606 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0x2bed
12607 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_BASE_IDX 2
12608 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0x2bee
12609 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_BASE_IDX 2
12610 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0x2bef
12611 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_BASE_IDX 2
12612 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0x2bf0
12613 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
12614 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0x2bf1
12615 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_BASE_IDX 2
12616 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2bf2
12617 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
12618 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0x2bf3
12619 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_BASE_IDX 2
12620 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0x2bf4
12621 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_BASE_IDX 2
12622 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0x2bf5
12623 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_BASE_IDX 2
12624 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0x2bf6
12625 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_BASE_IDX 2
12626 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0x2bf7
12627 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_BASE_IDX 2
12628 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0x2bf8
12629 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_BASE_IDX 2
12630 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0x2bf9
12631 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_BASE_IDX 2
12632 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0x2bfa
12633 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_BASE_IDX 2
12634 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0x2bfb
12635 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_BASE_IDX 2
12636 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0x2bfc
12637 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_BASE_IDX 2
12638 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0x2bfd
12639 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_BASE_IDX 2
12640 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0x2bfe
12641 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_BASE_IDX 2
12642 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0x2bff
12643 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_BASE_IDX 2
12644 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0x2c00
12645 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
12646 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0x2c01
12647 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_BASE_IDX 2
12648 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2c02
12649 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
12650 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0x2c03
12651 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_BASE_IDX 2
12652 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0x2c04
12653 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_BASE_IDX 2
12654 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0x2c05
12655 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_BASE_IDX 2
12656 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0x2c06
12657 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_BASE_IDX 2
12658 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0x2c07
12659 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_BASE_IDX 2
12660 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0x2c08
12661 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_BASE_IDX 2
12662 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0x2c09
12663 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_BASE_IDX 2
12664 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0x2c0a
12665 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_BASE_IDX 2
12666 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0x2c0b
12667 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_BASE_IDX 2
12668 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0x2c0c
12669 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_BASE_IDX 2
12670 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0x2c0d
12671 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_BASE_IDX 2
12672 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0x2c0e
12673 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_BASE_IDX 2
12674 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0x2c0f
12675 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_BASE_IDX 2
12678 // addressBlock: dce_dc_combophy_dc_combophypllregs3_dispdec
12679 // base address: 0xa20
12680 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0x2c10
12681 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_BASE_IDX 2
12682 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0x2c11
12683 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_BASE_IDX 2
12684 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0x2c12
12685 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_BASE_IDX 2
12686 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0x2c13
12687 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_BASE_IDX 2
12688 #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0x2c14
12689 #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_BASE_IDX 2
12690 #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0x2c15
12691 #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_BASE_IDX 2
12692 #define mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0x2c16
12693 #define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_BASE_IDX 2
12694 #define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0x2c17
12695 #define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_BASE_IDX 2
12696 #define mmDC_COMBOPHYPLLREGS3_VREG_CFG 0x2c19
12697 #define mmDC_COMBOPHYPLLREGS3_VREG_CFG_BASE_IDX 2
12698 #define mmDC_COMBOPHYPLLREGS3_OBSERVE0 0x2c1a
12699 #define mmDC_COMBOPHYPLLREGS3_OBSERVE0_BASE_IDX 2
12700 #define mmDC_COMBOPHYPLLREGS3_OBSERVE1 0x2c1b
12701 #define mmDC_COMBOPHYPLLREGS3_OBSERVE1_BASE_IDX 2
12702 #define mmDC_COMBOPHYPLLREGS3_DFT_OUT 0x2c1c
12703 #define mmDC_COMBOPHYPLLREGS3_DFT_OUT_BASE_IDX 2
12704 #define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1 0x2c4e
12705 #define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1_BASE_IDX 2
12706 #define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL 0x2c4f
12707 #define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL_BASE_IDX 2
12710 // addressBlock: dce_dc_dcio_dcio_zcal_dispdec
12711 // base address: 0x0
12712 #define mmZCAL_MACRO_CNTL_RESERVED0 0x2fe8
12713 #define mmZCAL_MACRO_CNTL_RESERVED0_BASE_IDX 2
12714 #define mmZCAL_MACRO_CNTL_RESERVED1 0x2fe9
12715 #define mmZCAL_MACRO_CNTL_RESERVED1_BASE_IDX 2
12716 #define mmZCAL_MACRO_CNTL_RESERVED2 0x2fea
12717 #define mmZCAL_MACRO_CNTL_RESERVED2_BASE_IDX 2
12718 #define mmZCAL_MACRO_CNTL_RESERVED3 0x2feb
12719 #define mmZCAL_MACRO_CNTL_RESERVED3_BASE_IDX 2
12720 #define mmZCAL_MACRO_CNTL_RESERVED4 0x2fec
12721 #define mmZCAL_MACRO_CNTL_RESERVED4_BASE_IDX 2
12724 // addressBlock: dce_dc_zcal_dc_zcalregs_dispdec
12725 // base address: 0x0
12726 #define mmCOMP_EN_CTL 0x2fe8
12727 #define mmCOMP_EN_CTL_BASE_IDX 2
12728 #define mmCOMP_EN_DFX 0x2fe9
12729 #define mmCOMP_EN_DFX_BASE_IDX 2
12730 #define mmZCAL_FUSES 0x2fea
12731 #define mmZCAL_FUSES_BASE_IDX 2
12734 // addressBlock: vga_vgaseqind
12735 // base address: 0x0
12736 #define ixSEQ00 0x0000
12737 #define ixSEQ01 0x0001
12738 #define ixSEQ02 0x0002
12739 #define ixSEQ03 0x0003
12740 #define ixSEQ04 0x0004
12743 // addressBlock: vga_vgacrtind
12744 // base address: 0x0
12745 #define ixCRT00 0x0000
12746 #define ixCRT01 0x0001
12747 #define ixCRT02 0x0002
12748 #define ixCRT03 0x0003
12749 #define ixCRT04 0x0004
12750 #define ixCRT05 0x0005
12751 #define ixCRT06 0x0006
12752 #define ixCRT07 0x0007
12753 #define ixCRT08 0x0008
12754 #define ixCRT09 0x0009
12755 #define ixCRT0A 0x000a
12756 #define ixCRT0B 0x000b
12757 #define ixCRT0C 0x000c
12758 #define ixCRT0D 0x000d
12759 #define ixCRT0E 0x000e
12760 #define ixCRT0F 0x000f
12761 #define ixCRT10 0x0010
12762 #define ixCRT11 0x0011
12763 #define ixCRT12 0x0012
12764 #define ixCRT13 0x0013
12765 #define ixCRT14 0x0014
12766 #define ixCRT15 0x0015
12767 #define ixCRT16 0x0016
12768 #define ixCRT17 0x0017
12769 #define ixCRT18 0x0018
12770 #define ixCRT1E 0x001e
12771 #define ixCRT1F 0x001f
12772 #define ixCRT22 0x0022
12775 // addressBlock: vga_vgagrphind
12776 // base address: 0x0
12777 #define ixGRA00 0x0000
12778 #define ixGRA01 0x0001
12779 #define ixGRA02 0x0002
12780 #define ixGRA03 0x0003
12781 #define ixGRA04 0x0004
12782 #define ixGRA05 0x0005
12783 #define ixGRA06 0x0006
12784 #define ixGRA07 0x0007
12785 #define ixGRA08 0x0008
12788 // addressBlock: vga_vgaattrind
12789 // base address: 0x0
12790 #define ixATTR00 0x0000
12791 #define ixATTR01 0x0001
12792 #define ixATTR02 0x0002
12793 #define ixATTR03 0x0003
12794 #define ixATTR04 0x0004
12795 #define ixATTR05 0x0005
12796 #define ixATTR06 0x0006
12797 #define ixATTR07 0x0007
12798 #define ixATTR08 0x0008
12799 #define ixATTR09 0x0009
12800 #define ixATTR0A 0x000a
12801 #define ixATTR0B 0x000b
12802 #define ixATTR0C 0x000c
12803 #define ixATTR0D 0x000d
12804 #define ixATTR0E 0x000e
12805 #define ixATTR0F 0x000f
12806 #define ixATTR10 0x0010
12807 #define ixATTR11 0x0011
12808 #define ixATTR12 0x0012
12809 #define ixATTR13 0x0013
12810 #define ixATTR14 0x0014
12813 // base address: 0x0
12816 // base address: 0x0
12819 // base address: 0x0
12822 // base address: 0x0
12825 // base address: 0x0
12828 // base address: 0x0
12831 // base address: 0x0
12834 // base address: 0x0
12837 // base address: 0x0
12840 // base address: 0x0
12843 // base address: 0x0
12846 // base address: 0x0
12849 // base address: 0x0
12852 // base address: 0x0
12855 // base address: 0x0
12858 // base address: 0x0
12861 // base address: 0x0
12864 // base address: 0x0
12867 // base address: 0x0
12870 // base address: 0x0
12873 // base address: 0x0
12876 // base address: 0x0
12879 // base address: 0x0
12882 // base address: 0x0
12885 // base address: 0x0
12888 // base address: 0x0
12891 // base address: 0x0
12894 // base address: 0x0
12897 // base address: 0x0
12900 // base address: 0x0
12903 // base address: 0x0
12906 // base address: 0x0
12909 // base address: 0x0
12912 // base address: 0x0
12915 // base address: 0x0
12918 // addressBlock: azendpoint_f2codecind
12919 // base address: 0x0
12920 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
12921 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
12922 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
12923 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
12924 #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
12925 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
12926 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
12927 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
12928 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
12929 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
12930 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
12931 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
12932 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
12933 #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
12934 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
12935 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
12936 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
12937 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
12938 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
12939 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
12940 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
12941 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
12942 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
12943 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
12944 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
12945 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
12946 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
12947 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
12948 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
12949 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
12950 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
12951 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
12952 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
12953 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
12954 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
12955 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
12956 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
12957 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
12958 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
12959 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
12960 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
12961 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
12962 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
12963 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
12964 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
12965 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
12966 #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
12967 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
12968 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
12969 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
12970 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
12971 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
12972 #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
12973 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
12974 #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
12975 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
12976 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
12977 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
12980 // addressBlock: azendpoint_descriptorind
12981 // base address: 0x0
12982 #define ixAUDIO_DESCRIPTOR0 0x0001
12983 #define ixAUDIO_DESCRIPTOR1 0x0002
12984 #define ixAUDIO_DESCRIPTOR2 0x0003
12985 #define ixAUDIO_DESCRIPTOR3 0x0004
12986 #define ixAUDIO_DESCRIPTOR4 0x0005
12987 #define ixAUDIO_DESCRIPTOR5 0x0006
12988 #define ixAUDIO_DESCRIPTOR6 0x0007
12989 #define ixAUDIO_DESCRIPTOR7 0x0008
12990 #define ixAUDIO_DESCRIPTOR8 0x0009
12991 #define ixAUDIO_DESCRIPTOR9 0x000a
12992 #define ixAUDIO_DESCRIPTOR10 0x000b
12993 #define ixAUDIO_DESCRIPTOR11 0x000c
12994 #define ixAUDIO_DESCRIPTOR12 0x000d
12995 #define ixAUDIO_DESCRIPTOR13 0x000e
12998 // addressBlock: azendpoint_sinkinfoind
12999 // base address: 0x0
13000 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
13001 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
13002 #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
13003 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
13004 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
13005 #define ixSINK_DESCRIPTION0 0x0005
13006 #define ixSINK_DESCRIPTION1 0x0006
13007 #define ixSINK_DESCRIPTION2 0x0007
13008 #define ixSINK_DESCRIPTION3 0x0008
13009 #define ixSINK_DESCRIPTION4 0x0009
13010 #define ixSINK_DESCRIPTION5 0x000a
13011 #define ixSINK_DESCRIPTION6 0x000b
13012 #define ixSINK_DESCRIPTION7 0x000c
13013 #define ixSINK_DESCRIPTION8 0x000d
13014 #define ixSINK_DESCRIPTION9 0x000e
13015 #define ixSINK_DESCRIPTION10 0x000f
13016 #define ixSINK_DESCRIPTION11 0x0010
13017 #define ixSINK_DESCRIPTION12 0x0011
13018 #define ixSINK_DESCRIPTION13 0x0012
13019 #define ixSINK_DESCRIPTION14 0x0013
13020 #define ixSINK_DESCRIPTION15 0x0014
13021 #define ixSINK_DESCRIPTION16 0x0015
13022 #define ixSINK_DESCRIPTION17 0x0016
13025 // addressBlock: azf0controller_azinputcrc0resultind
13026 // base address: 0x0
13027 #define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000
13028 #define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001
13029 #define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002
13030 #define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003
13031 #define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004
13032 #define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005
13033 #define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006
13034 #define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007
13037 // addressBlock: azf0controller_azinputcrc1resultind
13038 // base address: 0x0
13039 #define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000
13040 #define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001
13041 #define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002
13042 #define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003
13043 #define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004
13044 #define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005
13045 #define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006
13046 #define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007
13049 // addressBlock: azf0controller_azcrc0resultind
13050 // base address: 0x0
13051 #define ixAZALIA_CRC0_CHANNEL0 0x0000
13052 #define ixAZALIA_CRC0_CHANNEL1 0x0001
13053 #define ixAZALIA_CRC0_CHANNEL2 0x0002
13054 #define ixAZALIA_CRC0_CHANNEL3 0x0003
13055 #define ixAZALIA_CRC0_CHANNEL4 0x0004
13056 #define ixAZALIA_CRC0_CHANNEL5 0x0005
13057 #define ixAZALIA_CRC0_CHANNEL6 0x0006
13058 #define ixAZALIA_CRC0_CHANNEL7 0x0007
13061 // addressBlock: azf0controller_azcrc1resultind
13062 // base address: 0x0
13063 #define ixAZALIA_CRC1_CHANNEL0 0x0000
13064 #define ixAZALIA_CRC1_CHANNEL1 0x0001
13065 #define ixAZALIA_CRC1_CHANNEL2 0x0002
13066 #define ixAZALIA_CRC1_CHANNEL3 0x0003
13067 #define ixAZALIA_CRC1_CHANNEL4 0x0004
13068 #define ixAZALIA_CRC1_CHANNEL5 0x0005
13069 #define ixAZALIA_CRC1_CHANNEL6 0x0006
13070 #define ixAZALIA_CRC1_CHANNEL7 0x0007
13073 // addressBlock: azinputendpoint_f2codecind
13074 // base address: 0x0
13075 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
13076 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
13077 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
13078 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
13079 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
13080 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
13081 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
13082 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
13083 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
13084 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
13085 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
13086 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
13087 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
13088 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
13089 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
13090 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
13091 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
13092 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
13093 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
13094 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
13095 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
13096 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
13097 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
13098 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
13099 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
13100 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
13101 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
13102 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
13103 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
13104 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
13105 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
13106 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
13109 // addressBlock: azroot_f2codecind
13110 // base address: 0x0
13111 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00
13112 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02
13113 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04
13114 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
13115 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
13116 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
13117 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
13118 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
13119 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
13120 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
13121 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
13122 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
13123 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
13124 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
13125 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
13128 // addressBlock: azf0stream0_streamind
13129 // base address: 0x0
13130 #define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000
13131 #define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13132 #define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13133 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13134 #define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13137 // addressBlock: azf0stream1_streamind
13138 // base address: 0x0
13139 #define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000
13140 #define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13141 #define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13142 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13143 #define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13146 // addressBlock: azf0stream2_streamind
13147 // base address: 0x0
13148 #define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000
13149 #define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13150 #define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13151 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13152 #define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13155 // addressBlock: azf0stream3_streamind
13156 // base address: 0x0
13157 #define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000
13158 #define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13159 #define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13160 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13161 #define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13164 // addressBlock: azf0stream4_streamind
13165 // base address: 0x0
13166 #define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000
13167 #define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13168 #define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13169 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13170 #define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13173 // addressBlock: azf0stream5_streamind
13174 // base address: 0x0
13175 #define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000
13176 #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13177 #define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13178 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13179 #define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13182 // addressBlock: azf0stream6_streamind
13183 // base address: 0x0
13184 #define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000
13185 #define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13186 #define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13187 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13188 #define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13191 // addressBlock: azf0stream7_streamind
13192 // base address: 0x0
13193 #define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000
13194 #define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13195 #define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13196 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13197 #define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13200 // addressBlock: azf0stream8_streamind
13201 // base address: 0x0
13202 #define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000
13203 #define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13204 #define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13205 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13206 #define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13209 // addressBlock: azf0stream9_streamind
13210 // base address: 0x0
13211 #define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000
13212 #define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13213 #define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13214 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13215 #define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13218 // addressBlock: azf0stream10_streamind
13219 // base address: 0x0
13220 #define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000
13221 #define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13222 #define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13223 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13224 #define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13227 // addressBlock: azf0stream11_streamind
13228 // base address: 0x0
13229 #define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000
13230 #define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13231 #define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13232 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13233 #define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13236 // addressBlock: azf0stream12_streamind
13237 // base address: 0x0
13238 #define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000
13239 #define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13240 #define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13241 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13242 #define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13245 // addressBlock: azf0stream13_streamind
13246 // base address: 0x0
13247 #define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000
13248 #define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13249 #define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13250 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13251 #define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13254 // addressBlock: azf0stream14_streamind
13255 // base address: 0x0
13256 #define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000
13257 #define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13258 #define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13259 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13260 #define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13263 // addressBlock: azf0stream15_streamind
13264 // base address: 0x0
13265 #define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000
13266 #define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
13267 #define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
13268 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
13269 #define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
13272 // addressBlock: azf0endpoint0_endpointind
13273 // base address: 0x0
13274 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
13275 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
13276 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
13277 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
13278 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
13279 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
13280 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
13281 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
13282 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
13283 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
13284 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
13285 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
13286 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
13287 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
13288 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
13289 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
13290 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
13291 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
13292 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
13293 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
13294 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
13295 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
13296 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
13297 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
13298 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
13299 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
13300 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
13301 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
13302 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
13303 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
13304 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
13305 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
13306 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
13307 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
13308 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
13309 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
13310 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
13311 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
13312 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
13313 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
13314 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
13315 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
13316 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
13317 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
13318 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
13319 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
13320 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
13321 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
13322 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
13323 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
13324 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
13325 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
13326 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
13327 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
13328 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
13329 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
13330 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
13331 #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
13332 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
13333 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
13334 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
13335 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
13336 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
13337 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
13338 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
13339 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
13340 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
13341 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
13342 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
13343 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
13344 #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
13347 // addressBlock: azf0endpoint1_endpointind
13348 // base address: 0x0
13349 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
13350 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
13351 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
13352 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
13353 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
13354 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
13355 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
13356 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
13357 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
13358 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
13359 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
13360 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
13361 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
13362 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
13363 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
13364 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
13365 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
13366 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
13367 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
13368 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
13369 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
13370 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
13371 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
13372 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
13373 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
13374 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
13375 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
13376 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
13377 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
13378 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
13379 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
13380 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
13381 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
13382 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
13383 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
13384 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
13385 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
13386 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
13387 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
13388 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
13389 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
13390 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
13391 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
13392 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
13393 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
13394 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
13395 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
13396 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
13397 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
13398 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
13399 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
13400 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
13401 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
13402 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
13403 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
13404 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
13405 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
13406 #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
13407 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
13408 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
13409 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
13410 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
13411 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
13412 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
13413 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
13414 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
13415 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
13416 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
13417 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
13418 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
13419 #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
13422 // addressBlock: azf0endpoint2_endpointind
13423 // base address: 0x0
13424 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
13425 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
13426 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
13427 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
13428 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
13429 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
13430 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
13431 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
13432 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
13433 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
13434 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
13435 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
13436 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
13437 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
13438 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
13439 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
13440 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
13441 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
13442 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
13443 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
13444 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
13445 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
13446 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
13447 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
13448 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
13449 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
13450 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
13451 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
13452 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
13453 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
13454 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
13455 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
13456 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
13457 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
13458 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
13459 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
13460 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
13461 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
13462 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
13463 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
13464 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
13465 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
13466 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
13467 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
13468 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
13469 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
13470 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
13471 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
13472 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
13473 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
13474 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
13475 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
13476 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
13477 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
13478 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
13479 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
13480 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
13481 #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
13482 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
13483 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
13484 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
13485 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
13486 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
13487 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
13488 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
13489 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
13490 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
13491 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
13492 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
13493 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
13494 #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
13497 // addressBlock: azf0endpoint3_endpointind
13498 // base address: 0x0
13499 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
13500 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
13501 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
13502 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
13503 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
13504 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
13505 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
13506 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
13507 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
13508 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
13509 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
13510 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
13511 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
13512 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
13513 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
13514 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
13515 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
13516 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
13517 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
13518 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
13519 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
13520 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
13521 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
13522 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
13523 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
13524 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
13525 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
13526 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
13527 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
13528 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
13529 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
13530 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
13531 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
13532 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
13533 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
13534 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
13535 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
13536 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
13537 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
13538 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
13539 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
13540 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
13541 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
13542 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
13543 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
13544 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
13545 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
13546 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
13547 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
13548 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
13549 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
13550 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
13551 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
13552 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
13553 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
13554 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
13555 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
13556 #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
13557 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
13558 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
13559 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
13560 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
13561 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
13562 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
13563 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
13564 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
13565 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
13566 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
13567 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
13568 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
13569 #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
13572 // addressBlock: azf0endpoint4_endpointind
13573 // base address: 0x0
13574 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
13575 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
13576 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
13577 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
13578 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
13579 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
13580 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
13581 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
13582 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
13583 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
13584 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
13585 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
13586 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
13587 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
13588 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
13589 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
13590 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
13591 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
13592 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
13593 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
13594 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
13595 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
13596 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
13597 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
13598 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
13599 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
13600 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
13601 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
13602 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
13603 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
13604 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
13605 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
13606 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
13607 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
13608 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
13609 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
13610 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
13611 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
13612 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
13613 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
13614 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
13615 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
13616 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
13617 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
13618 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
13619 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
13620 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
13621 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
13622 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
13623 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
13624 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
13625 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
13626 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
13627 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
13628 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
13629 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
13630 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
13631 #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
13632 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
13633 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
13634 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
13635 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
13636 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
13637 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
13638 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
13639 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
13640 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
13641 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
13642 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
13643 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
13644 #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
13647 // addressBlock: azf0endpoint5_endpointind
13648 // base address: 0x0
13649 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
13650 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
13651 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
13652 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
13653 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
13654 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
13655 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
13656 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
13657 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
13658 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
13659 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
13660 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
13661 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
13662 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
13663 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
13664 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
13665 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
13666 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
13667 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
13668 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
13669 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
13670 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
13671 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
13672 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
13673 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
13674 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
13675 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
13676 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
13677 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
13678 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
13679 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
13680 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
13681 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
13682 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
13683 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
13684 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
13685 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
13686 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
13687 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
13688 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
13689 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
13690 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
13691 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
13692 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
13693 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
13694 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
13695 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
13696 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
13697 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
13698 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
13699 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
13700 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
13701 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
13702 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
13703 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
13704 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
13705 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
13706 #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
13707 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
13708 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
13709 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
13710 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
13711 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
13712 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
13713 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
13714 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
13715 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
13716 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
13717 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
13718 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
13719 #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
13722 // addressBlock: azf0endpoint6_endpointind
13723 // base address: 0x0
13724 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
13725 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
13726 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
13727 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
13728 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
13729 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
13730 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
13731 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
13732 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
13733 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
13734 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
13735 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
13736 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
13737 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
13738 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
13739 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
13740 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
13741 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
13742 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
13743 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
13744 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
13745 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
13746 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
13747 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
13748 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
13749 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
13750 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
13751 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
13752 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
13753 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
13754 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
13755 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
13756 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
13757 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
13758 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
13759 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
13760 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
13761 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
13762 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
13763 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
13764 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
13765 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
13766 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
13767 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
13768 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
13769 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
13770 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
13771 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
13772 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
13773 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
13774 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
13775 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
13776 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
13777 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
13778 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
13779 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
13780 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
13781 #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
13782 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
13783 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
13784 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
13785 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
13786 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
13787 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
13788 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
13789 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
13790 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
13791 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
13792 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
13793 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
13794 #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
13797 // addressBlock: azf0endpoint7_endpointind
13798 // base address: 0x0
13799 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
13800 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
13801 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
13802 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
13803 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
13804 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
13805 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
13806 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
13807 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
13808 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
13809 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
13810 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
13811 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
13812 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
13813 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
13814 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
13815 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
13816 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
13817 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
13818 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
13819 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
13820 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
13821 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
13822 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
13823 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
13824 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
13825 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
13826 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
13827 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
13828 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
13829 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
13830 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
13831 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
13832 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
13833 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
13834 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
13835 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
13836 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
13837 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
13838 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
13839 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
13840 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
13841 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
13842 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
13843 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
13844 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
13845 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
13846 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
13847 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
13848 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
13849 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
13850 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
13851 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
13852 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
13853 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
13854 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
13855 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
13856 #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
13857 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
13858 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
13859 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
13860 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
13861 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
13862 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
13863 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
13864 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
13865 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
13866 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
13867 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
13868 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
13869 #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
13872 // addressBlock: azf0inputendpoint0_inputendpointind
13873 // base address: 0x0
13874 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
13875 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
13876 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
13877 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
13878 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
13879 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
13880 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
13881 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
13882 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
13883 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
13884 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
13885 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
13886 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
13887 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
13888 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
13889 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
13890 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
13891 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
13892 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
13893 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
13894 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
13895 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
13896 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
13899 // addressBlock: azf0inputendpoint1_inputendpointind
13900 // base address: 0x0
13901 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
13902 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
13903 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
13904 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
13905 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
13906 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
13907 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
13908 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
13909 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
13910 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
13911 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
13912 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
13913 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
13914 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
13915 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
13916 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
13917 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
13918 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
13919 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
13920 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
13921 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
13922 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
13923 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
13926 // addressBlock: azf0inputendpoint2_inputendpointind
13927 // base address: 0x0
13928 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
13929 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
13930 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
13931 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
13932 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
13933 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
13934 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
13935 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
13936 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
13937 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
13938 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
13939 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
13940 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
13941 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
13942 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
13943 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
13944 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
13945 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
13946 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
13947 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
13948 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
13949 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
13950 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
13953 // addressBlock: azf0inputendpoint3_inputendpointind
13954 // base address: 0x0
13955 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
13956 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
13957 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
13958 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
13959 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
13960 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
13961 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
13962 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
13963 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
13964 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
13965 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
13966 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
13967 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
13968 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
13969 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
13970 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
13971 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
13972 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
13973 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
13974 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
13975 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
13976 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
13977 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
13980 // addressBlock: azf0inputendpoint4_inputendpointind
13981 // base address: 0x0
13982 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
13983 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
13984 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
13985 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
13986 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
13987 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
13988 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
13989 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
13990 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
13991 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
13992 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
13993 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
13994 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
13995 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
13996 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
13997 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
13998 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
13999 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
14000 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
14001 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
14002 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
14003 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
14004 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
14007 // addressBlock: azf0inputendpoint5_inputendpointind
14008 // base address: 0x0
14009 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
14010 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
14011 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
14012 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
14013 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
14014 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
14015 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
14016 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
14017 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
14018 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
14019 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
14020 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
14021 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
14022 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
14023 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
14024 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
14025 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
14026 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
14027 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
14028 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
14029 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
14030 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
14031 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
14034 // addressBlock: azf0inputendpoint6_inputendpointind
14035 // base address: 0x0
14036 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
14037 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
14038 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
14039 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
14040 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
14041 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
14042 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
14043 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
14044 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
14045 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
14046 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
14047 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
14048 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
14049 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
14050 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
14051 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
14052 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
14053 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
14054 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
14055 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
14056 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
14057 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
14058 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
14061 // addressBlock: azf0inputendpoint7_inputendpointind
14062 // base address: 0x0
14063 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
14064 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
14065 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
14066 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
14067 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
14068 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
14069 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
14070 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
14071 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
14072 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
14073 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
14074 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
14075 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
14076 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
14077 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
14078 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
14079 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
14080 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
14081 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
14082 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
14083 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
14084 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
14085 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068