2 * BIF_5_0 Register documentation
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
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7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #define mmMM_INDEX 0x0
28 #define mmMM_INDEX_HI 0x6
30 #define mmBIF_MM_INDACCESS_CNTL 0x1500
31 #define mmBIF_DOORBELL_APER_EN 0x1501
32 #define mmBUS_CNTL 0x1508
33 #define mmCONFIG_CNTL 0x1509
34 #define mmCONFIG_MEMSIZE 0x150a
35 #define mmCONFIG_RESERVED 0x1502
36 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
37 #define mmCONFIG_F0_BASE 0x150b
38 #define mmCONFIG_APER_SIZE 0x150c
39 #define mmCONFIG_REG_APER_SIZE 0x150d
40 #define mmBIF_SCRATCH0 0x150e
41 #define mmBIF_SCRATCH1 0x150f
42 #define mmBIF_RLC_INTR_CNTL 0x1510
43 #define mmBIF_BME_STATUS 0x1511
44 #define mmBIF_ATOMIC_ERR_LOG 0x1512
45 #define mmBX_RESET_EN 0x1514
46 #define mmMM_CFGREGS_CNTL 0x1513
47 #define mmHW_DEBUG 0x1515
48 #define mmMASTER_CREDIT_CNTL 0x1516
49 #define mmSLAVE_REQ_CREDIT_CNTL 0x1517
50 #define mmBX_RESET_CNTL 0x1518
51 #define mmINTERRUPT_CNTL 0x151a
52 #define mmINTERRUPT_CNTL2 0x151b
53 #define mmBIF_DEBUG_CNTL 0x151c
54 #define mmBIF_DEBUG_MUX 0x151d
55 #define mmBIF_DEBUG_OUT 0x151e
56 #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528
57 #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520
58 #define mmCLKREQB_PAD_CNTL 0x1521
59 #define mmCLKREQB_PERF_COUNTER 0x1522
60 #define mmBIF_XDMA_LO 0x14c0
61 #define mmBIF_XDMA_HI 0x14c1
62 #define mmBIF_FEATURES_CONTROL_MISC 0x14c2
63 #define mmBIF_DOORBELL_CNTL 0x14c3
64 #define mmBIF_SLVARB_MODE 0x14c4
65 #define mmBIF_CLK_CTRL 0x14c5
66 #define mmBIF_FB_EN 0x1524
67 #define mmBIF_BUSNUM_CNTL1 0x1525
68 #define mmBIF_BUSNUM_LIST0 0x1526
69 #define mmBIF_BUSNUM_LIST1 0x1527
70 #define mmBIF_BUSNUM_CNTL2 0x152b
71 #define mmBIF_BUSY_DELAY_CNTR 0x1529
72 #define mmBIF_PERFMON_CNTL 0x152c
73 #define mmBIF_PERFCOUNTER0_RESULT 0x152d
74 #define mmBIF_PERFCOUNTER1_RESULT 0x152e
75 #define mmSLAVE_HANG_PROTECTION_CNTL 0x1536
76 #define mmGPU_HDP_FLUSH_REQ 0x1537
77 #define mmGPU_HDP_FLUSH_DONE 0x1538
78 #define mmSLAVE_HANG_ERROR 0x153b
79 #define mmCAPTURE_HOST_BUSNUM 0x153c
80 #define mmHOST_BUSNUM 0x153d
81 #define mmPEER_REG_RANGE0 0x153e
82 #define mmPEER_REG_RANGE1 0x153f
83 #define mmPEER0_FB_OFFSET_HI 0x14f3
84 #define mmPEER0_FB_OFFSET_LO 0x14f2
85 #define mmPEER1_FB_OFFSET_HI 0x14f1
86 #define mmPEER1_FB_OFFSET_LO 0x14f0
87 #define mmPEER2_FB_OFFSET_HI 0x14ef
88 #define mmPEER2_FB_OFFSET_LO 0x14ee
89 #define mmPEER3_FB_OFFSET_HI 0x14ed
90 #define mmPEER3_FB_OFFSET_LO 0x14ec
91 #define mmDBG_SMB_BYPASS_SRBM_ACCESS 0x14eb
92 #define mmBIF_MST_TRANS_PENDING 0x14ea
93 #define mmBIF_SLV_TRANS_PENDING 0x14e9
94 #define mmBIF_DEVFUNCNUM_LIST0 0x14e8
95 #define mmBIF_DEVFUNCNUM_LIST1 0x14e7
96 #define mmBACO_CNTL 0x14e5
97 #define mmBF_ANA_ISO_CNTL 0x14c7
98 #define mmMEM_TYPE_CNTL 0x14e4
99 #define mmBIF_BACO_DEBUG 0x14df
100 #define mmBIF_BACO_DEBUG_LATCH 0x14dc
101 #define mmBACO_CNTL_MISC 0x14db
102 #define mmSMU_BIF_VDDGFX_PWR_STATUS 0x14f8
103 #define mmBIF_VDDGFX_GFX0_LOWER 0x1428
104 #define mmBIF_VDDGFX_GFX0_UPPER 0x1429
105 #define mmBIF_VDDGFX_GFX1_LOWER 0x142a
106 #define mmBIF_VDDGFX_GFX1_UPPER 0x142b
107 #define mmBIF_VDDGFX_GFX2_LOWER 0x142c
108 #define mmBIF_VDDGFX_GFX2_UPPER 0x142d
109 #define mmBIF_VDDGFX_GFX3_LOWER 0x142e
110 #define mmBIF_VDDGFX_GFX3_UPPER 0x142f
111 #define mmBIF_VDDGFX_GFX4_LOWER 0x1430
112 #define mmBIF_VDDGFX_GFX4_UPPER 0x1431
113 #define mmBIF_VDDGFX_GFX5_LOWER 0x1432
114 #define mmBIF_VDDGFX_GFX5_UPPER 0x1433
115 #define mmBIF_VDDGFX_RSV1_LOWER 0x1434
116 #define mmBIF_VDDGFX_RSV1_UPPER 0x1435
117 #define mmBIF_VDDGFX_RSV2_LOWER 0x1436
118 #define mmBIF_VDDGFX_RSV2_UPPER 0x1437
119 #define mmBIF_VDDGFX_RSV3_LOWER 0x1438
120 #define mmBIF_VDDGFX_RSV3_UPPER 0x1439
121 #define mmBIF_VDDGFX_RSV4_LOWER 0x143a
122 #define mmBIF_VDDGFX_RSV4_UPPER 0x143b
123 #define mmBIF_VDDGFX_FB_CMP 0x143c
124 #define mmBIF_SMU_INDEX 0x143d
125 #define mmBIF_SMU_DATA 0x143e
126 #define mmBIF_DOORBELL_GBLAPER1_LOWER 0x14fc
127 #define mmBIF_DOORBELL_GBLAPER1_UPPER 0x14fd
128 #define mmBIF_DOORBELL_GBLAPER2_LOWER 0x14fe
129 #define mmBIF_DOORBELL_GBLAPER2_UPPER 0x14ff
130 #define mmIMPCTL_RESET 0x14f5
131 #define mmGARLIC_FLUSH_CNTL 0x1401
132 #define mmGARLIC_FLUSH_ADDR_START_0 0x1402
133 #define mmGARLIC_FLUSH_ADDR_START_1 0x1404
134 #define mmGARLIC_FLUSH_ADDR_START_2 0x1406
135 #define mmGARLIC_FLUSH_ADDR_START_3 0x1408
136 #define mmGARLIC_FLUSH_ADDR_START_4 0x140a
137 #define mmGARLIC_FLUSH_ADDR_START_5 0x140c
138 #define mmGARLIC_FLUSH_ADDR_START_6 0x140e
139 #define mmGARLIC_FLUSH_ADDR_START_7 0x1410
140 #define mmGARLIC_FLUSH_ADDR_END_0 0x1403
141 #define mmGARLIC_FLUSH_ADDR_END_1 0x1405
142 #define mmGARLIC_FLUSH_ADDR_END_2 0x1407
143 #define mmGARLIC_FLUSH_ADDR_END_3 0x1409
144 #define mmGARLIC_FLUSH_ADDR_END_4 0x140b
145 #define mmGARLIC_FLUSH_ADDR_END_5 0x140d
146 #define mmGARLIC_FLUSH_ADDR_END_6 0x140f
147 #define mmGARLIC_FLUSH_ADDR_END_7 0x1411
148 #define mmGARLIC_FLUSH_REQ 0x1412
149 #define mmGPU_GARLIC_FLUSH_REQ 0x1413
150 #define mmGPU_GARLIC_FLUSH_DONE 0x1414
151 #define mmREMAP_HDP_MEM_FLUSH_CNTL 0x1426
152 #define mmREMAP_HDP_REG_FLUSH_CNTL 0x1427
153 #define mmBIOS_SCRATCH_0 0x5c9
154 #define mmBIOS_SCRATCH_1 0x5ca
155 #define mmBIOS_SCRATCH_2 0x5cb
156 #define mmBIOS_SCRATCH_3 0x5cc
157 #define mmBIOS_SCRATCH_4 0x5cd
158 #define mmBIOS_SCRATCH_5 0x5ce
159 #define mmBIOS_SCRATCH_6 0x5cf
160 #define mmBIOS_SCRATCH_7 0x5d0
161 #define mmBIOS_SCRATCH_8 0x5d1
162 #define mmBIOS_SCRATCH_9 0x5d2
163 #define mmBIOS_SCRATCH_10 0x5d3
164 #define mmBIOS_SCRATCH_11 0x5d4
165 #define mmBIOS_SCRATCH_12 0x5d5
166 #define mmBIOS_SCRATCH_13 0x5d6
167 #define mmBIOS_SCRATCH_14 0x5d7
168 #define mmBIOS_SCRATCH_15 0x5d8
169 #define mmBIF_RB_CNTL 0x1530
170 #define mmBIF_RB_BASE 0x1531
171 #define mmBIF_RB_RPTR 0x1532
172 #define mmBIF_RB_WPTR 0x1533
173 #define mmBIF_RB_WPTR_ADDR_HI 0x1534
174 #define mmBIF_RB_WPTR_ADDR_LO 0x1535
175 #define mmMAILBOX_INDEX 0x14c6
176 #define mmMAILBOX_MSGBUF_TRN_DW0 0x14c8
177 #define mmMAILBOX_MSGBUF_TRN_DW1 0x14c9
178 #define mmMAILBOX_MSGBUF_TRN_DW2 0x14ca
179 #define mmMAILBOX_MSGBUF_TRN_DW3 0x14cb
180 #define mmMAILBOX_MSGBUF_RCV_DW0 0x14cc
181 #define mmMAILBOX_MSGBUF_RCV_DW1 0x14cd
182 #define mmMAILBOX_MSGBUF_RCV_DW2 0x14ce
183 #define mmMAILBOX_MSGBUF_RCV_DW3 0x14cf
184 #define mmMAILBOX_CONTROL 0x14d0
185 #define mmMAILBOX_INT_CNTL 0x14d1
186 #define mmBIF_VIRT_RESET_REQ 0x14d2
187 #define mmVM_INIT_STATUS 0x14d3
188 #define mmBIF_GPUIOV_RESET_NOTIFICATION 0x14d5
189 #define mmBIF_GPUIOV_VM_INIT_STATUS 0x14d6
190 #define mmBIF_GPUIOV_FB_TOTAL_FB_INFO 0x14d8
191 #define mmBIF_GPUIOV_GPU_IDLE_LATENCY 0x141c
192 #define mmBIF_GPUIOV_MMIO_MAP_RANGE0 0x141d
193 #define mmBIF_GPUIOV_MMIO_MAP_RANGE1 0x141e
194 #define mmBIF_GPUIOV_MMIO_MAP_RANGE2 0x141f
195 #define mmBIF_GPUIOV_MMIO_MAP_RANGE3 0x1420
196 #define mmBIF_GPUIOV_MMIO_MAP_RANGE4 0x1421
197 #define mmBIF_GPUIOV_MMIO_MAP_RANGE5 0x1422
198 #define mmBIF_GPU_IDLE_LATENCY 0x1415
199 #define mmBIF_MMIO_MAP_RANGE0 0x1416
200 #define mmBIF_MMIO_MAP_RANGE1 0x1417
201 #define mmBIF_MMIO_MAP_RANGE2 0x1418
202 #define mmBIF_MMIO_MAP_RANGE3 0x1419
203 #define mmBIF_MMIO_MAP_RANGE4 0x141a
204 #define mmBIF_MMIO_MAP_RANGE5 0x141b
205 #define mmVENDOR_ID 0x0
206 #define mmDEVICE_ID 0x0
207 #define mmCOMMAND 0x1
209 #define mmREVISION_ID 0x2
210 #define mmPROG_INTERFACE 0x2
211 #define mmSUB_CLASS 0x2
212 #define mmBASE_CLASS 0x2
213 #define mmCACHE_LINE 0x3
214 #define mmLATENCY 0x3
217 #define mmBASE_ADDR_1 0x4
218 #define mmBASE_ADDR_2 0x5
219 #define mmBASE_ADDR_3 0x6
220 #define mmBASE_ADDR_4 0x7
221 #define mmBASE_ADDR_5 0x8
222 #define mmBASE_ADDR_6 0x9
223 #define mmROM_BASE_ADDR 0xc
224 #define mmCAP_PTR 0xd
225 #define mmINTERRUPT_LINE 0xf
226 #define mmINTERRUPT_PIN 0xf
227 #define mmADAPTER_ID 0xb
228 #define mmMIN_GRANT 0xf
229 #define mmMAX_LATENCY 0xf
230 #define mmVENDOR_CAP_LIST 0x12
231 #define mmADAPTER_ID_W 0x13
232 #define mmPMI_CAP_LIST 0x14
233 #define mmPMI_CAP 0x14
234 #define mmPMI_STATUS_CNTL 0x15
235 #define mmPCIE_CAP_LIST 0x16
236 #define mmPCIE_CAP 0x16
237 #define mmDEVICE_CAP 0x17
238 #define mmDEVICE_CNTL 0x18
239 #define mmDEVICE_STATUS 0x18
240 #define mmLINK_CAP 0x19
241 #define mmLINK_CNTL 0x1a
242 #define mmLINK_STATUS 0x1a
243 #define mmDEVICE_CAP2 0x1f
244 #define mmDEVICE_CNTL2 0x20
245 #define mmDEVICE_STATUS2 0x20
246 #define mmLINK_CAP2 0x21
247 #define mmLINK_CNTL2 0x22
248 #define mmLINK_STATUS2 0x22
249 #define mmMSI_CAP_LIST 0x28
250 #define mmMSI_MSG_CNTL 0x28
251 #define mmMSI_MSG_ADDR_LO 0x29
252 #define mmMSI_MSG_ADDR_HI 0x2a
253 #define mmMSI_MSG_DATA_64 0x2b
254 #define mmMSI_MSG_DATA 0x2a
255 #define mmMSI_MASK 0x2b
256 #define mmMSI_PENDING 0x2c
257 #define mmMSI_MASK_64 0x2c
258 #define mmMSI_PENDING_64 0x2d
259 #define mmMSIX_CAP_LIST 0x30
260 #define mmMSIX_MSG_CNTL 0x30
261 #define mmMSIX_TABLE 0x31
262 #define mmMSIX_PBA 0x32
263 #define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40
264 #define mmPCIE_VENDOR_SPECIFIC_HDR 0x41
265 #define mmPCIE_VENDOR_SPECIFIC1 0x42
266 #define mmPCIE_VENDOR_SPECIFIC2 0x43
267 #define mmPCIE_VC_ENH_CAP_LIST 0x44
268 #define mmPCIE_PORT_VC_CAP_REG1 0x45
269 #define mmPCIE_PORT_VC_CAP_REG2 0x46
270 #define mmPCIE_PORT_VC_CNTL 0x47
271 #define mmPCIE_PORT_VC_STATUS 0x47
272 #define mmPCIE_VC0_RESOURCE_CAP 0x48
273 #define mmPCIE_VC0_RESOURCE_CNTL 0x49
274 #define mmPCIE_VC0_RESOURCE_STATUS 0x4a
275 #define mmPCIE_VC1_RESOURCE_CAP 0x4b
276 #define mmPCIE_VC1_RESOURCE_CNTL 0x4c
277 #define mmPCIE_VC1_RESOURCE_STATUS 0x4d
278 #define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50
279 #define mmPCIE_DEV_SERIAL_NUM_DW1 0x51
280 #define mmPCIE_DEV_SERIAL_NUM_DW2 0x52
281 #define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54
282 #define mmPCIE_UNCORR_ERR_STATUS 0x55
283 #define mmPCIE_UNCORR_ERR_MASK 0x56
284 #define mmPCIE_UNCORR_ERR_SEVERITY 0x57
285 #define mmPCIE_CORR_ERR_STATUS 0x58
286 #define mmPCIE_CORR_ERR_MASK 0x59
287 #define mmPCIE_ADV_ERR_CAP_CNTL 0x5a
288 #define mmPCIE_HDR_LOG0 0x5b
289 #define mmPCIE_HDR_LOG1 0x5c
290 #define mmPCIE_HDR_LOG2 0x5d
291 #define mmPCIE_HDR_LOG3 0x5e
292 #define mmPCIE_TLP_PREFIX_LOG0 0x62
293 #define mmPCIE_TLP_PREFIX_LOG1 0x63
294 #define mmPCIE_TLP_PREFIX_LOG2 0x64
295 #define mmPCIE_TLP_PREFIX_LOG3 0x65
296 #define mmPCIE_BAR_ENH_CAP_LIST 0x80
297 #define mmPCIE_BAR1_CAP 0x81
298 #define mmPCIE_BAR1_CNTL 0x82
299 #define mmPCIE_BAR2_CAP 0x83
300 #define mmPCIE_BAR2_CNTL 0x84
301 #define mmPCIE_BAR3_CAP 0x85
302 #define mmPCIE_BAR3_CNTL 0x86
303 #define mmPCIE_BAR4_CAP 0x87
304 #define mmPCIE_BAR4_CNTL 0x88
305 #define mmPCIE_BAR5_CAP 0x89
306 #define mmPCIE_BAR5_CNTL 0x8a
307 #define mmPCIE_BAR6_CAP 0x8b
308 #define mmPCIE_BAR6_CNTL 0x8c
309 #define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90
310 #define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91
311 #define mmPCIE_PWR_BUDGET_DATA 0x92
312 #define mmPCIE_PWR_BUDGET_CAP 0x93
313 #define mmPCIE_DPA_ENH_CAP_LIST 0x94
314 #define mmPCIE_DPA_CAP 0x95
315 #define mmPCIE_DPA_LATENCY_INDICATOR 0x96
316 #define mmPCIE_DPA_STATUS 0x97
317 #define mmPCIE_DPA_CNTL 0x97
318 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98
319 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98
320 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98
321 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98
322 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99
323 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99
324 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99
325 #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99
326 #define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c
327 #define mmPCIE_LINK_CNTL3 0x9d
328 #define mmPCIE_LANE_ERROR_STATUS 0x9e
329 #define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f
330 #define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f
331 #define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0
332 #define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0
333 #define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1
334 #define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1
335 #define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2
336 #define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2
337 #define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3
338 #define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3
339 #define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4
340 #define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4
341 #define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5
342 #define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5
343 #define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6
344 #define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6
345 #define mmPCIE_ACS_ENH_CAP_LIST 0xa8
346 #define mmPCIE_ACS_CAP 0xa9
347 #define mmPCIE_ACS_CNTL 0xa9
348 #define mmPCIE_ATS_ENH_CAP_LIST 0xac
349 #define mmPCIE_ATS_CAP 0xad
350 #define mmPCIE_ATS_CNTL 0xad
351 #define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0
352 #define mmPCIE_PAGE_REQ_CNTL 0xb1
353 #define mmPCIE_PAGE_REQ_STATUS 0xb1
354 #define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2
355 #define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3
356 #define mmPCIE_PASID_ENH_CAP_LIST 0xb4
357 #define mmPCIE_PASID_CAP 0xb5
358 #define mmPCIE_PASID_CNTL 0xb5
359 #define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8
360 #define mmPCIE_TPH_REQR_CAP 0xb9
361 #define mmPCIE_TPH_REQR_CNTL 0xba
362 #define mmPCIE_MC_ENH_CAP_LIST 0xbc
363 #define mmPCIE_MC_CAP 0xbd
364 #define mmPCIE_MC_CNTL 0xbd
365 #define mmPCIE_MC_ADDR0 0xbe
366 #define mmPCIE_MC_ADDR1 0xbf
367 #define mmPCIE_MC_RCV0 0xc0
368 #define mmPCIE_MC_RCV1 0xc1
369 #define mmPCIE_MC_BLOCK_ALL0 0xc2
370 #define mmPCIE_MC_BLOCK_ALL1 0xc3
371 #define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4
372 #define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5
373 #define mmPCIE_LTR_ENH_CAP_LIST 0xc8
374 #define mmPCIE_LTR_CAP 0xc9
375 #define mmPCIE_ARI_ENH_CAP_LIST 0xca
376 #define mmPCIE_ARI_CAP 0xcb
377 #define mmPCIE_ARI_CNTL 0xcb
378 #define mmPCIE_SRIOV_ENH_CAP_LIST 0xcc
379 #define mmPCIE_SRIOV_CAP 0xcd
380 #define mmPCIE_SRIOV_CONTROL 0xce
381 #define mmPCIE_SRIOV_STATUS 0xce
382 #define mmPCIE_SRIOV_INITIAL_VFS 0xcf
383 #define mmPCIE_SRIOV_TOTAL_VFS 0xcf
384 #define mmPCIE_SRIOV_NUM_VFS 0xd0
385 #define mmPCIE_SRIOV_FUNC_DEP_LINK 0xd0
386 #define mmPCIE_SRIOV_FIRST_VF_OFFSET 0xd1
387 #define mmPCIE_SRIOV_VF_STRIDE 0xd1
388 #define mmPCIE_SRIOV_VF_DEVICE_ID 0xd2
389 #define mmPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xd3
390 #define mmPCIE_SRIOV_SYSTEM_PAGE_SIZE 0xd4
391 #define mmPCIE_SRIOV_VF_BASE_ADDR_0 0xd5
392 #define mmPCIE_SRIOV_VF_BASE_ADDR_1 0xd6
393 #define mmPCIE_SRIOV_VF_BASE_ADDR_2 0xd7
394 #define mmPCIE_SRIOV_VF_BASE_ADDR_3 0xd8
395 #define mmPCIE_SRIOV_VF_BASE_ADDR_4 0xd9
396 #define mmPCIE_SRIOV_VF_BASE_ADDR_5 0xda
397 #define mmPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0xdb
398 #define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x100
399 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x101
400 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x102
401 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC 0x103
402 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS 0x104
403 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x105
404 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION 0x106
405 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS 0x107
406 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x108
407 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x109
408 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS 0x10a
409 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x10b
410 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x10c
411 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x10d
412 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x10e
413 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x10f
414 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x110
415 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x111
416 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x112
417 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x113
418 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x114
419 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x115
420 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x116
421 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x117
422 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x118
423 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x119
424 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x11a
425 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x11b
426 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT 0x11c
427 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0 0x11d
428 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1 0x11e
429 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2 0x11f
430 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3 0x120
431 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4 0x121
432 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5 0x122
433 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0 0x124
434 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1 0x125
435 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2 0x126
436 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3 0x127
437 #define mmPCIE_INDEX 0xe
438 #define mmPCIE_DATA 0xf
439 #define mmPCIE_INDEX_2 0xc
440 #define mmPCIE_DATA_2 0xd
441 #define ixPCIE_HOLD_TRAINING_A 0x1500820
442 #define ixLNCNT_CONTROL 0x1508030
443 #define ixCFG_LNC_WINDOW 0x1508031
444 #define ixLNCNT_QUAN_THRD 0x1508032
445 #define ixLNCNT_WEIGHT 0x1508033
446 #define ixLNC_TOTAL_WACC 0x1508034
447 #define ixLNC_BW_WACC 0x1508035
448 #define ixLNC_CMN_WACC 0x1508036
449 #define mmPCIE_EFUSE 0xfc0
450 #define mmPCIE_EFUSE2 0xfc1
451 #define mmPCIE_EFUSE3 0xfc2
452 #define mmPCIE_EFUSE4 0xfc3
453 #define mmPCIE_EFUSE5 0xfc4
454 #define mmPCIE_EFUSE6 0xfc5
455 #define mmPCIE_EFUSE7 0xfc6
456 #define ixPCIE_WRAP_SCRATCH1 0x1308001
457 #define ixPCIE_WRAP_SCRATCH2 0x1308002
458 #define ixPCIE_WRAP_REG_TARG_MISC 0x1308005
459 #define ixPCIE_WRAP_DTM_MISC 0x1308006
460 #define ixPCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1308007
461 #define ixPCIE_WRAP_MISC 0x1308008
462 #define ixPCIE_WRAP_PIF_MISC 0x1308009
463 #define ixPCIE_RXDET_OVERRIDE 0x130800a
464 #define ixREG_ADAPT_pciecore0_CONTROL 0x1308090
465 #define ixREG_ADAPT_pwregt_CONTROL 0x1308096
466 #define ixREG_ADAPT_pwregr_CONTROL 0x1308097
467 #define ixREG_ADAPT_pif0_CONTROL 0x1308098
468 #define ixPCIE_RESERVED 0x1400000
469 #define ixPCIE_SCRATCH 0x1400001
470 #define ixPCIE_HW_DEBUG 0x1400002
471 #define ixPCIE_RX_NUM_NAK 0x140000e
472 #define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f
473 #define ixPCIE_CNTL 0x1400010
474 #define ixPCIE_CONFIG_CNTL 0x1400011
475 #define ixPCIE_DEBUG_CNTL 0x1400012
476 #define ixPCIE_INT_CNTL 0x140001a
477 #define ixPCIE_INT_STATUS 0x140001b
478 #define ixPCIE_CNTL2 0x140001c
479 #define ixPCIE_RX_CNTL2 0x140001d
480 #define ixPCIE_TX_F0_ATTR_CNTL 0x140001e
481 #define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f
482 #define ixPCIE_CI_CNTL 0x1400020
483 #define ixPCIE_BUS_CNTL 0x1400021
484 #define ixPCIE_LC_STATE6 0x1400022
485 #define ixPCIE_LC_STATE7 0x1400023
486 #define ixPCIE_LC_STATE8 0x1400024
487 #define ixPCIE_LC_STATE9 0x1400025
488 #define ixPCIE_LC_STATE10 0x1400026
489 #define ixPCIE_LC_STATE11 0x1400027
490 #define ixPCIE_LC_STATUS1 0x1400028
491 #define ixPCIE_LC_STATUS2 0x1400029
492 #define ixPCIE_WPR_CNTL 0x1400030
493 #define ixPCIE_RX_LAST_TLP0 0x1400031
494 #define ixPCIE_RX_LAST_TLP1 0x1400032
495 #define ixPCIE_RX_LAST_TLP2 0x1400033
496 #define ixPCIE_RX_LAST_TLP3 0x1400034
497 #define ixPCIE_TX_LAST_TLP0 0x1400035
498 #define ixPCIE_TX_LAST_TLP1 0x1400036
499 #define ixPCIE_TX_LAST_TLP2 0x1400037
500 #define ixPCIE_TX_LAST_TLP3 0x1400038
501 #define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a
502 #define ixPCIE_I2C_REG_DATA 0x140003b
503 #define ixPCIE_CFG_CNTL 0x140003c
504 #define ixPCIE_LC_PM_CNTL 0x140003d
505 #define ixPCIE_P_CNTL 0x1400040
506 #define ixPCIE_P_BUF_STATUS 0x1400041
507 #define ixPCIE_P_DECODER_STATUS 0x1400042
508 #define ixPCIE_P_MISC_STATUS 0x1400043
509 #define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050
510 #define ixPCIE_OBFF_CNTL 0x1400061
511 #define ixPCIE_TX_LTR_CNTL 0x1400060
512 #define ixPCIE_IDLE_STATUS 0x1400062
513 #define ixPCIE_PERF_COUNT_CNTL 0x1400080
514 #define ixPCIE_PERF_CNTL_TXCLK 0x1400081
515 #define ixPCIE_PERF_COUNT0_TXCLK 0x1400082
516 #define ixPCIE_PERF_COUNT1_TXCLK 0x1400083
517 #define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084
518 #define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085
519 #define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086
520 #define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087
521 #define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088
522 #define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089
523 #define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a
524 #define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b
525 #define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c
526 #define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d
527 #define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e
528 #define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f
529 #define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090
530 #define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091
531 #define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092
532 #define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093
533 #define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094
534 #define ixPCIE_PERF_CNTL_TXCLK2 0x1400095
535 #define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096
536 #define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097
537 #define ixPCIE_STRAP_F0 0x14000b0
538 #define ixPCIE_STRAP_F1 0x14000b1
539 #define ixPCIE_STRAP_F2 0x14000b2
540 #define ixPCIE_STRAP_F3 0x14000b3
541 #define ixPCIE_STRAP_F4 0x14000b4
542 #define ixPCIE_STRAP_F5 0x14000b5
543 #define ixPCIE_STRAP_F6 0x14000b6
544 #define ixPCIE_STRAP_MSIX 0x14000b7
545 #define ixPCIE_STRAP_MISC 0x14000c0
546 #define ixPCIE_STRAP_MISC2 0x14000c1
547 #define ixPCIE_STRAP_PI 0x14000c2
548 #define ixPCIE_STRAP_I2C_BD 0x14000c4
549 #define ixPCIE_PRBS_CLR 0x14000c8
550 #define ixPCIE_PRBS_STATUS1 0x14000c9
551 #define ixPCIE_PRBS_STATUS2 0x14000ca
552 #define ixPCIE_PRBS_FREERUN 0x14000cb
553 #define ixPCIE_PRBS_MISC 0x14000cc
554 #define ixPCIE_PRBS_USER_PATTERN 0x14000cd
555 #define ixPCIE_PRBS_LO_BITCNT 0x14000ce
556 #define ixPCIE_PRBS_HI_BITCNT 0x14000cf
557 #define ixPCIE_PRBS_ERRCNT_0 0x14000d0
558 #define ixPCIE_PRBS_ERRCNT_1 0x14000d1
559 #define ixPCIE_PRBS_ERRCNT_2 0x14000d2
560 #define ixPCIE_PRBS_ERRCNT_3 0x14000d3
561 #define ixPCIE_PRBS_ERRCNT_4 0x14000d4
562 #define ixPCIE_PRBS_ERRCNT_5 0x14000d5
563 #define ixPCIE_PRBS_ERRCNT_6 0x14000d6
564 #define ixPCIE_PRBS_ERRCNT_7 0x14000d7
565 #define ixPCIE_PRBS_ERRCNT_8 0x14000d8
566 #define ixPCIE_PRBS_ERRCNT_9 0x14000d9
567 #define ixPCIE_PRBS_ERRCNT_10 0x14000da
568 #define ixPCIE_PRBS_ERRCNT_11 0x14000db
569 #define ixPCIE_PRBS_ERRCNT_12 0x14000dc
570 #define ixPCIE_PRBS_ERRCNT_13 0x14000dd
571 #define ixPCIE_PRBS_ERRCNT_14 0x14000de
572 #define ixPCIE_PRBS_ERRCNT_15 0x14000df
573 #define ixPCIE_F0_DPA_CAP 0x14000e0
574 #define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4
575 #define ixPCIE_F0_DPA_CNTL 0x14000e5
576 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7
577 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8
578 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9
579 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea
580 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb
581 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec
582 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed
583 #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee
584 #define mmSWRST_COMMAND_STATUS 0x14a0
585 #define mmSWRST_GENERAL_CONTROL 0x14a1
586 #define mmSWRST_COMMAND_0 0x14a2
587 #define mmSWRST_COMMAND_1 0x14a3
588 #define mmSWRST_CONTROL_0 0x14a4
589 #define mmSWRST_CONTROL_1 0x14a5
590 #define mmSWRST_CONTROL_2 0x14a6
591 #define mmSWRST_CONTROL_3 0x14a7
592 #define mmSWRST_CONTROL_4 0x14a8
593 #define mmSWRST_CONTROL_5 0x14a9
594 #define mmSWRST_CONTROL_6 0x14aa
595 #define mmSWRST_EP_COMMAND_0 0x14ab
596 #define mmSWRST_EP_CONTROL_0 0x14ac
597 #define mmCPM_CONTROL 0x14b8
598 #define mmGSKT_CONTROL 0x14bf
599 #define ixLM_CONTROL 0x1400120
600 #define ixLM_PCIETXMUX0 0x1400121
601 #define ixLM_PCIETXMUX1 0x1400122
602 #define ixLM_PCIETXMUX2 0x1400123
603 #define ixLM_PCIETXMUX3 0x1400124
604 #define ixLM_PCIERXMUX0 0x1400125
605 #define ixLM_PCIERXMUX1 0x1400126
606 #define ixLM_PCIERXMUX2 0x1400127
607 #define ixLM_PCIERXMUX3 0x1400128
608 #define ixLM_LANEENABLE 0x1400129
609 #define ixLM_PRBSCONTROL 0x140012a
610 #define ixLM_POWERCONTROL 0x140012b
611 #define ixLM_POWERCONTROL1 0x140012c
612 #define ixLM_POWERCONTROL2 0x140012d
613 #define ixLM_POWERCONTROL3 0x140012e
614 #define ixLM_POWERCONTROL4 0x140012f
615 #define ixPB0_GLB_CTRL_REG0 0x1200004
616 #define ixPB0_GLB_CTRL_REG1 0x1200008
617 #define ixPB0_GLB_CTRL_REG2 0x120000c
618 #define ixPB0_GLB_CTRL_REG3 0x1200010
619 #define ixPB0_GLB_CTRL_REG4 0x1200014
620 #define ixPB0_GLB_CTRL_REG5 0x1200018
621 #define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x120001c
622 #define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x1200020
623 #define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x1200024
624 #define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x1200028
625 #define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x120002c
626 #define ixPB0_GLB_OVRD_REG0 0x1200030
627 #define ixPB0_GLB_OVRD_REG1 0x1200034
628 #define ixPB0_GLB_OVRD_REG2 0x1200038
629 #define ixPB0_HW_DEBUG 0x1202004
630 #define ixPB0_STRAP_GLB_REG0 0x1202020
631 #define ixPB0_STRAP_TX_REG0 0x1202024
632 #define ixPB0_STRAP_RX_REG0 0x1202028
633 #define ixPB0_STRAP_RX_REG1 0x120202c
634 #define ixPB0_STRAP_PLL_REG0 0x1202030
635 #define ixPB0_STRAP_PIN_REG0 0x1202034
636 #define ixPB0_STRAP_GLB_REG1 0x1202038
637 #define ixPB0_STRAP_GLB_REG2 0x120203c
638 #define ixPB0_DFT_JIT_INJ_REG0 0x1203000
639 #define ixPB0_DFT_JIT_INJ_REG1 0x1203004
640 #define ixPB0_DFT_JIT_INJ_REG2 0x1203008
641 #define ixPB0_DFT_DEBUG_CTRL_REG0 0x120300c
642 #define ixPB0_DFT_JIT_INJ_STAT_REG0 0x1203010
643 #define ixPB0_PLL_RO_GLB_CTRL_REG0 0x1204000
644 #define ixPB0_PLL_RO_GLB_OVRD_REG0 0x1204010
645 #define ixPB0_PLL_RO0_CTRL_REG0 0x1204440
646 #define ixPB0_PLL_RO0_OVRD_REG0 0x1204450
647 #define ixPB0_PLL_RO0_OVRD_REG1 0x1204454
648 #define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x1204460
649 #define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x1204464
650 #define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x1204468
651 #define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x120446c
652 #define ixPB0_PLL_LC0_CTRL_REG0 0x1204480
653 #define ixPB0_PLL_LC0_OVRD_REG0 0x1204490
654 #define ixPB0_PLL_LC0_OVRD_REG1 0x1204494
655 #define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x1204500
656 #define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x1204504
657 #define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x1204508
658 #define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x120450c
659 #define ixPB0_RX_GLB_CTRL_REG0 0x1206000
660 #define ixPB0_RX_GLB_CTRL_REG1 0x1206004
661 #define ixPB0_RX_GLB_CTRL_REG2 0x1206008
662 #define ixPB0_RX_GLB_CTRL_REG3 0x120600c
663 #define ixPB0_RX_GLB_CTRL_REG4 0x1206010
664 #define ixPB0_RX_GLB_CTRL_REG5 0x1206014
665 #define ixPB0_RX_GLB_CTRL_REG6 0x1206018
666 #define ixPB0_RX_GLB_CTRL_REG7 0x120601c
667 #define ixPB0_RX_GLB_CTRL_REG8 0x1206020
668 #define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x1206028
669 #define ixPB0_RX_GLB_OVRD_REG0 0x1206030
670 #define ixPB0_RX_GLB_OVRD_REG1 0x1206034
671 #define ixPB0_RX_LANE0_CTRL_REG0 0x1206440
672 #define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x1206448
673 #define ixPB0_RX_LANE1_CTRL_REG0 0x1206480
674 #define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x1206488
675 #define ixPB0_RX_LANE2_CTRL_REG0 0x1206500
676 #define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x1206508
677 #define ixPB0_RX_LANE3_CTRL_REG0 0x1206600
678 #define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x1206608
679 #define ixPB0_RX_LANE4_CTRL_REG0 0x1206800
680 #define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x1206848
681 #define ixPB0_RX_LANE5_CTRL_REG0 0x1206880
682 #define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x1206888
683 #define ixPB0_RX_LANE6_CTRL_REG0 0x1206900
684 #define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x1206908
685 #define ixPB0_RX_LANE7_CTRL_REG0 0x1206a00
686 #define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x1206a08
687 #define ixPB0_RX_LANE8_CTRL_REG0 0x1207440
688 #define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x1207448
689 #define ixPB0_RX_LANE9_CTRL_REG0 0x1207480
690 #define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x1207488
691 #define ixPB0_RX_LANE10_CTRL_REG0 0x1207500
692 #define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x1207508
693 #define ixPB0_RX_LANE11_CTRL_REG0 0x1207600
694 #define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x1207608
695 #define ixPB0_RX_LANE12_CTRL_REG0 0x1207840
696 #define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x1207848
697 #define ixPB0_RX_LANE13_CTRL_REG0 0x1207880
698 #define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x1207888
699 #define ixPB0_RX_LANE14_CTRL_REG0 0x1207900
700 #define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x1207908
701 #define ixPB0_RX_LANE15_CTRL_REG0 0x1207a00
702 #define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x1207a08
703 #define ixPB0_TX_GLB_CTRL_REG0 0x1208000
704 #define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x1208004
705 #define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x1208010
706 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x1208014
707 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x1208018
708 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x120801c
709 #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x1208020
710 #define ixPB0_TX_GLB_OVRD_REG0 0x1208030
711 #define ixPB0_TX_GLB_OVRD_REG1 0x1208034
712 #define ixPB0_TX_GLB_OVRD_REG2 0x1208038
713 #define ixPB0_TX_GLB_OVRD_REG3 0x120803c
714 #define ixPB0_TX_GLB_OVRD_REG4 0x1208040
715 #define ixPB0_TX_LANE0_CTRL_REG0 0x1208440
716 #define ixPB0_TX_LANE0_OVRD_REG0 0x1208444
717 #define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x1208448
718 #define ixPB0_TX_LANE1_CTRL_REG0 0x1208480
719 #define ixPB0_TX_LANE1_OVRD_REG0 0x1208484
720 #define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x1208488
721 #define ixPB0_TX_LANE2_CTRL_REG0 0x1208500
722 #define ixPB0_TX_LANE2_OVRD_REG0 0x1208504
723 #define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x1208508
724 #define ixPB0_TX_LANE3_CTRL_REG0 0x1208600
725 #define ixPB0_TX_LANE3_OVRD_REG0 0x1208604
726 #define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x1208608
727 #define ixPB0_TX_LANE4_CTRL_REG0 0x1208840
728 #define ixPB0_TX_LANE4_OVRD_REG0 0x1208844
729 #define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x1208848
730 #define ixPB0_TX_LANE5_CTRL_REG0 0x1208880
731 #define ixPB0_TX_LANE5_OVRD_REG0 0x1208884
732 #define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x1208888
733 #define ixPB0_TX_LANE6_CTRL_REG0 0x1208900
734 #define ixPB0_TX_LANE6_OVRD_REG0 0x1208904
735 #define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x1208908
736 #define ixPB0_TX_LANE7_CTRL_REG0 0x1208a00
737 #define ixPB0_TX_LANE7_OVRD_REG0 0x1208a04
738 #define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x1208a08
739 #define ixPB0_TX_LANE8_CTRL_REG0 0x1209440
740 #define ixPB0_TX_LANE8_OVRD_REG0 0x1209444
741 #define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x1209448
742 #define ixPB0_TX_LANE9_CTRL_REG0 0x1209480
743 #define ixPB0_TX_LANE9_OVRD_REG0 0x1209484
744 #define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x1209488
745 #define ixPB0_TX_LANE10_CTRL_REG0 0x1209500
746 #define ixPB0_TX_LANE10_OVRD_REG0 0x1209504
747 #define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x1209508
748 #define ixPB0_TX_LANE11_CTRL_REG0 0x1209600
749 #define ixPB0_TX_LANE11_OVRD_REG0 0x1209604
750 #define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x1209608
751 #define ixPB0_TX_LANE12_CTRL_REG0 0x1209840
752 #define ixPB0_TX_LANE12_OVRD_REG0 0x1209844
753 #define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x1209848
754 #define ixPB0_TX_LANE13_CTRL_REG0 0x1209880
755 #define ixPB0_TX_LANE13_OVRD_REG0 0x1209884
756 #define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x1209888
757 #define ixPB0_TX_LANE14_CTRL_REG0 0x1209900
758 #define ixPB0_TX_LANE14_OVRD_REG0 0x1209904
759 #define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x1209908
760 #define ixPB0_TX_LANE15_CTRL_REG0 0x1209a00
761 #define ixPB0_TX_LANE15_OVRD_REG0 0x1209a04
762 #define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x1209a08
763 #define ixPB1_GLB_CTRL_REG0 0x2200004
764 #define ixPB1_GLB_CTRL_REG1 0x2200008
765 #define ixPB1_GLB_CTRL_REG2 0x220000c
766 #define ixPB1_GLB_CTRL_REG3 0x2200010
767 #define ixPB1_GLB_CTRL_REG4 0x2200014
768 #define ixPB1_GLB_CTRL_REG5 0x2200018
769 #define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x220001c
770 #define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x2200020
771 #define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x2200024
772 #define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x2200028
773 #define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x220002c
774 #define ixPB1_GLB_OVRD_REG0 0x2200030
775 #define ixPB1_GLB_OVRD_REG1 0x2200034
776 #define ixPB1_GLB_OVRD_REG2 0x2200038
777 #define ixPB1_HW_DEBUG 0x2202004
778 #define ixPB1_STRAP_GLB_REG0 0x2202020
779 #define ixPB1_STRAP_TX_REG0 0x2202024
780 #define ixPB1_STRAP_RX_REG0 0x2202028
781 #define ixPB1_STRAP_RX_REG1 0x220202c
782 #define ixPB1_STRAP_PLL_REG0 0x2202030
783 #define ixPB1_STRAP_PIN_REG0 0x2202034
784 #define ixPB1_STRAP_GLB_REG1 0x2202038
785 #define ixPB1_STRAP_GLB_REG2 0x220203c
786 #define ixPB1_DFT_JIT_INJ_REG0 0x2203000
787 #define ixPB1_DFT_JIT_INJ_REG1 0x2203004
788 #define ixPB1_DFT_JIT_INJ_REG2 0x2203008
789 #define ixPB1_DFT_DEBUG_CTRL_REG0 0x220300c
790 #define ixPB1_DFT_JIT_INJ_STAT_REG0 0x2203010
791 #define ixPB1_PLL_RO_GLB_CTRL_REG0 0x2204000
792 #define ixPB1_PLL_RO_GLB_OVRD_REG0 0x2204010
793 #define ixPB1_PLL_RO0_CTRL_REG0 0x2204440
794 #define ixPB1_PLL_RO0_OVRD_REG0 0x2204450
795 #define ixPB1_PLL_RO0_OVRD_REG1 0x2204454
796 #define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x2204460
797 #define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x2204464
798 #define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x2204468
799 #define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x220446c
800 #define ixPB1_PLL_LC0_CTRL_REG0 0x2204480
801 #define ixPB1_PLL_LC0_OVRD_REG0 0x2204490
802 #define ixPB1_PLL_LC0_OVRD_REG1 0x2204494
803 #define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x2204500
804 #define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x2204504
805 #define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x2204508
806 #define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x220450c
807 #define ixPB1_RX_GLB_CTRL_REG0 0x2206000
808 #define ixPB1_RX_GLB_CTRL_REG1 0x2206004
809 #define ixPB1_RX_GLB_CTRL_REG2 0x2206008
810 #define ixPB1_RX_GLB_CTRL_REG3 0x220600c
811 #define ixPB1_RX_GLB_CTRL_REG4 0x2206010
812 #define ixPB1_RX_GLB_CTRL_REG5 0x2206014
813 #define ixPB1_RX_GLB_CTRL_REG6 0x2206018
814 #define ixPB1_RX_GLB_CTRL_REG7 0x220601c
815 #define ixPB1_RX_GLB_CTRL_REG8 0x2206020
816 #define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x2206028
817 #define ixPB1_RX_GLB_OVRD_REG0 0x2206030
818 #define ixPB1_RX_GLB_OVRD_REG1 0x2206034
819 #define ixPB1_RX_LANE0_CTRL_REG0 0x2206440
820 #define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x2206448
821 #define ixPB1_RX_LANE1_CTRL_REG0 0x2206480
822 #define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x2206488
823 #define ixPB1_RX_LANE2_CTRL_REG0 0x2206500
824 #define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x2206508
825 #define ixPB1_RX_LANE3_CTRL_REG0 0x2206600
826 #define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x2206608
827 #define ixPB1_RX_LANE4_CTRL_REG0 0x2206800
828 #define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x2206848
829 #define ixPB1_RX_LANE5_CTRL_REG0 0x2206880
830 #define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x2206888
831 #define ixPB1_RX_LANE6_CTRL_REG0 0x2206900
832 #define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x2206908
833 #define ixPB1_RX_LANE7_CTRL_REG0 0x2206a00
834 #define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x2206a08
835 #define ixPB1_RX_LANE8_CTRL_REG0 0x2207440
836 #define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x2207448
837 #define ixPB1_RX_LANE9_CTRL_REG0 0x2207480
838 #define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x2207488
839 #define ixPB1_RX_LANE10_CTRL_REG0 0x2207500
840 #define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x2207508
841 #define ixPB1_RX_LANE11_CTRL_REG0 0x2207600
842 #define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x2207608
843 #define ixPB1_RX_LANE12_CTRL_REG0 0x2207840
844 #define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x2207848
845 #define ixPB1_RX_LANE13_CTRL_REG0 0x2207880
846 #define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x2207888
847 #define ixPB1_RX_LANE14_CTRL_REG0 0x2207900
848 #define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x2207908
849 #define ixPB1_RX_LANE15_CTRL_REG0 0x2207a00
850 #define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x2207a08
851 #define ixPB1_TX_GLB_CTRL_REG0 0x2208000
852 #define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x2208004
853 #define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x2208010
854 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x2208014
855 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x2208018
856 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x220801c
857 #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x2208020
858 #define ixPB1_TX_GLB_OVRD_REG0 0x2208030
859 #define ixPB1_TX_GLB_OVRD_REG1 0x2208034
860 #define ixPB1_TX_GLB_OVRD_REG2 0x2208038
861 #define ixPB1_TX_GLB_OVRD_REG3 0x220803c
862 #define ixPB1_TX_GLB_OVRD_REG4 0x2208040
863 #define ixPB1_TX_LANE0_CTRL_REG0 0x2208440
864 #define ixPB1_TX_LANE0_OVRD_REG0 0x2208444
865 #define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x2208448
866 #define ixPB1_TX_LANE1_CTRL_REG0 0x2208480
867 #define ixPB1_TX_LANE1_OVRD_REG0 0x2208484
868 #define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x2208488
869 #define ixPB1_TX_LANE2_CTRL_REG0 0x2208500
870 #define ixPB1_TX_LANE2_OVRD_REG0 0x2208504
871 #define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x2208508
872 #define ixPB1_TX_LANE3_CTRL_REG0 0x2208600
873 #define ixPB1_TX_LANE3_OVRD_REG0 0x2208604
874 #define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x2208608
875 #define ixPB1_TX_LANE4_CTRL_REG0 0x2208840
876 #define ixPB1_TX_LANE4_OVRD_REG0 0x2208844
877 #define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x2208848
878 #define ixPB1_TX_LANE5_CTRL_REG0 0x2208880
879 #define ixPB1_TX_LANE5_OVRD_REG0 0x2208884
880 #define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x2208888
881 #define ixPB1_TX_LANE6_CTRL_REG0 0x2208900
882 #define ixPB1_TX_LANE6_OVRD_REG0 0x2208904
883 #define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x2208908
884 #define ixPB1_TX_LANE7_CTRL_REG0 0x2208a00
885 #define ixPB1_TX_LANE7_OVRD_REG0 0x2208a04
886 #define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x2208a08
887 #define ixPB1_TX_LANE8_CTRL_REG0 0x2209440
888 #define ixPB1_TX_LANE8_OVRD_REG0 0x2209444
889 #define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x2209448
890 #define ixPB1_TX_LANE9_CTRL_REG0 0x2209480
891 #define ixPB1_TX_LANE9_OVRD_REG0 0x2209484
892 #define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x2209488
893 #define ixPB1_TX_LANE10_CTRL_REG0 0x2209500
894 #define ixPB1_TX_LANE10_OVRD_REG0 0x2209504
895 #define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x2209508
896 #define ixPB1_TX_LANE11_CTRL_REG0 0x2209600
897 #define ixPB1_TX_LANE11_OVRD_REG0 0x2209604
898 #define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x2209608
899 #define ixPB1_TX_LANE12_CTRL_REG0 0x2209840
900 #define ixPB1_TX_LANE12_OVRD_REG0 0x2209844
901 #define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x2209848
902 #define ixPB1_TX_LANE13_CTRL_REG0 0x2209880
903 #define ixPB1_TX_LANE13_OVRD_REG0 0x2209884
904 #define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x2209888
905 #define ixPB1_TX_LANE14_CTRL_REG0 0x2209900
906 #define ixPB1_TX_LANE14_OVRD_REG0 0x2209904
907 #define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x2209908
908 #define ixPB1_TX_LANE15_CTRL_REG0 0x2209a00
909 #define ixPB1_TX_LANE15_OVRD_REG0 0x2209a04
910 #define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x2209a08
911 #define ixPB0_PIF_SCRATCH 0x1100001
912 #define ixPB0_PIF_HW_DEBUG 0x1100002
913 #define ixPB0_PIF_STRAP_0 0x1100003
914 #define ixPB0_PIF_CTRL 0x1100004
915 #define ixPB0_PIF_TX_CTRL 0x1100008
916 #define ixPB0_PIF_TX_CTRL2 0x1100009
917 #define ixPB0_PIF_RX_CTRL 0x110000a
918 #define ixPB0_PIF_RX_CTRL2 0x110000b
919 #define ixPB0_PIF_GLB_OVRD 0x110000c
920 #define ixPB0_PIF_GLB_OVRD2 0x110000d
921 #define ixPB0_PIF_BIF_CMD_STATUS 0x1100010
922 #define ixPB0_PIF_CMD_BUS_CTRL 0x1100011
923 #define ixPB0_PIF_CMD_BUS_GLB_OVRD 0x1100013
924 #define ixPB0_PIF_LANE0_OVRD 0x1100014
925 #define ixPB0_PIF_LANE0_OVRD2 0x1100015
926 #define ixPB0_PIF_LANE1_OVRD 0x1100016
927 #define ixPB0_PIF_LANE1_OVRD2 0x1100017
928 #define ixPB0_PIF_LANE2_OVRD 0x1100018
929 #define ixPB0_PIF_LANE2_OVRD2 0x1100019
930 #define ixPB0_PIF_LANE3_OVRD 0x110001a
931 #define ixPB0_PIF_LANE3_OVRD2 0x110001b
932 #define ixPB0_PIF_LANE4_OVRD 0x110001c
933 #define ixPB0_PIF_LANE4_OVRD2 0x110001d
934 #define ixPB0_PIF_LANE5_OVRD 0x110001e
935 #define ixPB0_PIF_LANE5_OVRD2 0x110001f
936 #define ixPB0_PIF_LANE6_OVRD 0x1100020
937 #define ixPB0_PIF_LANE6_OVRD2 0x1100021
938 #define ixPB0_PIF_LANE7_OVRD 0x1100022
939 #define ixPB0_PIF_LANE7_OVRD2 0x1100023
940 #define ixPB1_PIF_SCRATCH 0x2100001
941 #define ixPB1_PIF_HW_DEBUG 0x2100002
942 #define ixPB1_PIF_STRAP_0 0x2100003
943 #define ixPB1_PIF_CTRL 0x2100004
944 #define ixPB1_PIF_TX_CTRL 0x2100008
945 #define ixPB1_PIF_TX_CTRL2 0x2100009
946 #define ixPB1_PIF_RX_CTRL 0x210000a
947 #define ixPB1_PIF_RX_CTRL2 0x210000b
948 #define ixPB1_PIF_GLB_OVRD 0x210000c
949 #define ixPB1_PIF_GLB_OVRD2 0x210000d
950 #define ixPB1_PIF_BIF_CMD_STATUS 0x2100010
951 #define ixPB1_PIF_CMD_BUS_CTRL 0x2100011
952 #define ixPB1_PIF_CMD_BUS_GLB_OVRD 0x2100013
953 #define ixPB1_PIF_LANE0_OVRD 0x2100014
954 #define ixPB1_PIF_LANE0_OVRD2 0x2100015
955 #define ixPB1_PIF_LANE1_OVRD 0x2100016
956 #define ixPB1_PIF_LANE1_OVRD2 0x2100017
957 #define ixPB1_PIF_LANE2_OVRD 0x2100018
958 #define ixPB1_PIF_LANE2_OVRD2 0x2100019
959 #define ixPB1_PIF_LANE3_OVRD 0x210001a
960 #define ixPB1_PIF_LANE3_OVRD2 0x210001b
961 #define ixPB1_PIF_LANE4_OVRD 0x210001c
962 #define ixPB1_PIF_LANE4_OVRD2 0x210001d
963 #define ixPB1_PIF_LANE5_OVRD 0x210001e
964 #define ixPB1_PIF_LANE5_OVRD2 0x210001f
965 #define ixPB1_PIF_LANE6_OVRD 0x2100020
966 #define ixPB1_PIF_LANE6_OVRD2 0x2100021
967 #define ixPB1_PIF_LANE7_OVRD 0x2100022
968 #define ixPB1_PIF_LANE7_OVRD2 0x2100023
969 #define ixPCIEP_RESERVED 0x10010000
970 #define ixPCIEP_SCRATCH 0x10010001
971 #define ixPCIEP_HW_DEBUG 0x10010002
972 #define ixPCIEP_PORT_CNTL 0x10010010
973 #define ixPCIE_TX_CNTL 0x10010020
974 #define ixPCIE_TX_REQUESTER_ID 0x10010021
975 #define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022
976 #define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023
977 #define ixPCIE_TX_SEQ 0x10010024
978 #define ixPCIE_TX_REPLAY 0x10010025
979 #define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026
980 #define ixPCIE_TX_CREDITS_ADVT_P 0x10010030
981 #define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031
982 #define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032
983 #define ixPCIE_TX_CREDITS_INIT_P 0x10010033
984 #define ixPCIE_TX_CREDITS_INIT_NP 0x10010034
985 #define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035
986 #define ixPCIE_TX_CREDITS_STATUS 0x10010036
987 #define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037
988 #define ixPCIE_P_PORT_LANE_STATUS 0x10010050
989 #define ixPCIE_FC_P 0x10010060
990 #define ixPCIE_FC_NP 0x10010061
991 #define ixPCIE_FC_CPL 0x10010062
992 #define ixPCIE_ERR_CNTL 0x1001006a
993 #define ixPCIE_RX_CNTL 0x10010070
994 #define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071
995 #define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072
996 #define ixPCIE_RX_CNTL3 0x10010074
997 #define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080
998 #define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081
999 #define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082
1000 #define ixPCIEP_ERROR_INJECT_PHYSICAL 0x10010083
1001 #define ixPCIEP_ERROR_INJECT_TRANSACTION 0x10010084
1002 #define ixPCIEP_SRIOV_PRIV_CTRL 0x10010085
1003 #define ixPCIE_LC_CNTL 0x100100a0
1004 #define ixPCIE_LC_CNTL2 0x100100b1
1005 #define ixPCIE_LC_CNTL3 0x100100b5
1006 #define ixPCIE_LC_CNTL4 0x100100b6
1007 #define ixPCIE_LC_CNTL5 0x100100b7
1008 #define ixPCIE_LC_CNTL6 0x100100bb
1009 #define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2
1010 #define ixPCIE_LC_TRAINING_CNTL 0x100100a1
1011 #define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2
1012 #define ixPCIE_LC_N_FTS_CNTL 0x100100a3
1013 #define ixPCIE_LC_SPEED_CNTL 0x100100a4
1014 #define ixPCIE_LC_CDR_CNTL 0x100100b3
1015 #define ixPCIE_LC_LANE_CNTL 0x100100b4
1016 #define ixPCIE_LC_FORCE_COEFF 0x100100b8
1017 #define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9
1018 #define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba
1019 #define ixPCIE_LC_STATE0 0x100100a5
1020 #define ixPCIE_LC_STATE1 0x100100a6
1021 #define ixPCIE_LC_STATE2 0x100100a7
1022 #define ixPCIE_LC_STATE3 0x100100a8
1023 #define ixPCIE_LC_STATE4 0x100100a9
1024 #define ixPCIE_LC_STATE5 0x100100aa
1025 #define ixPCIEP_STRAP_LC 0x100100c0
1026 #define ixPCIEP_STRAP_MISC 0x100100c1
1027 #define ixPCIEP_BCH_ECC_CNTL 0x100100d0
1028 #define ixPCIEP_HPGI_PRIVATE 0x100100d2
1029 #define ixPCIEP_HPGI 0x100100da
1030 #define mmPCIEMSIX_VECT0_ADDR_LO 0x6000
1031 #define mmPCIEMSIX_VECT0_ADDR_HI 0x6001
1032 #define mmPCIEMSIX_VECT0_MSG_DATA 0x6002
1033 #define mmPCIEMSIX_VECT0_CONTROL 0x6003
1034 #define mmPCIEMSIX_VECT1_ADDR_LO 0x6004
1035 #define mmPCIEMSIX_VECT1_ADDR_HI 0x6005
1036 #define mmPCIEMSIX_VECT1_MSG_DATA 0x6006
1037 #define mmPCIEMSIX_VECT1_CONTROL 0x6007
1038 #define mmPCIEMSIX_VECT2_ADDR_LO 0x6008
1039 #define mmPCIEMSIX_VECT2_ADDR_HI 0x6009
1040 #define mmPCIEMSIX_VECT2_MSG_DATA 0x600a
1041 #define mmPCIEMSIX_VECT2_CONTROL 0x600b
1042 #define mmPCIEMSIX_VECT3_ADDR_LO 0x600c
1043 #define mmPCIEMSIX_VECT3_ADDR_HI 0x600d
1044 #define mmPCIEMSIX_VECT3_MSG_DATA 0x600e
1045 #define mmPCIEMSIX_VECT3_CONTROL 0x600f
1046 #define mmPCIEMSIX_PBA 0x6200
1047 #define mmBIF_RFE_SNOOP_REG 0x27
1048 #define mmBIF_RFE_WARMRST_CNTL 0x1459
1049 #define mmBIF_RFE_SOFTRST_CNTL 0x1441
1050 #define mmBIF_RFE_IMPRST_CNTL 0x1458
1051 #define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442
1052 #define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443
1053 #define mmBIF_PWDN_COMMAND 0x1444
1054 #define mmBIF_PWDN_STATUS 0x1445
1055 #define mmBIF_RFE_MST_BU_CMDSTATUS 0x1446
1056 #define mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS 0x1447
1057 #define mmBIF_RFE_MST_SMBUS_CMDSTATUS 0x1448
1058 #define mmBIF_RFE_MST_BX_CMDSTATUS 0x1449
1059 #define mmBIF_RFE_MST_TMOUT_STATUS 0x144b
1060 #define mmBIF_RFE_MMCFG_CNTL 0x144c
1061 #define mmBIF_CC_RFE_IMP_OVERRIDECNTL 0x1455
1062 #define mmBIF_IMPCTL_SMPLCNTL 0x1450
1063 #define mmBIF_IMPCTL_RXCNTL 0x1451
1064 #define mmBIF_IMPCTL_TXCNTL_pd 0x1452
1065 #define mmBIF_IMPCTL_TXCNTL_pu 0x1453
1066 #define mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD 0x1454
1068 #endif /* BIF_5_0_D_H */