2 * Copyright 2012-15 Advanced Micro Devices, Inc.
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26 #ifndef __DAL_LINK_SERVICE_TYPES_H__
27 #define __DAL_LINK_SERVICE_TYPES_H__
29 #include "grph_object_id.h"
30 #include "dal_types.h"
31 #include "irq_types.h"
33 /*struct mst_mgr_callback_object;*/
38 MAX_CONTROLLER_NUM = 6
42 DP_POWER_STATE_D0 = 1,
47 /* eDP version 1.1 or lower */
48 EDP_REVISION_11 = 0x00,
50 EDP_REVISION_12 = 0x01,
52 EDP_REVISION_13 = 0x02
56 LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/
59 enum link_training_result {
60 LINK_TRAINING_SUCCESS,
61 LINK_TRAINING_CR_FAIL_LANE0,
62 LINK_TRAINING_CR_FAIL_LANE1,
63 LINK_TRAINING_CR_FAIL_LANE23,
64 /* CR DONE bit is cleared during EQ step */
65 LINK_TRAINING_EQ_FAIL_CR,
66 /* other failure during EQ step */
67 LINK_TRAINING_EQ_FAIL_EQ,
68 LINK_TRAINING_LQA_FAIL,
71 struct link_training_settings {
72 struct dc_link_settings link_settings;
73 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
74 bool allow_invalid_msa_timing_param;
77 enum hw_dp_training_pattern {
78 HW_DP_TRAINING_PATTERN_1 = 0,
79 HW_DP_TRAINING_PATTERN_2,
80 HW_DP_TRAINING_PATTERN_3,
81 HW_DP_TRAINING_PATTERN_4
84 /*TODO: Move this enum test harness*/
86 enum dp_test_pattern {
87 /* Input data is pass through Scrambler
88 * and 8b10b Encoder straight to output*/
89 DP_TEST_PATTERN_VIDEO_MODE = 0,
91 /* phy test patterns*/
92 DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
93 DP_TEST_PATTERN_D102 = DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
94 DP_TEST_PATTERN_SYMBOL_ERROR,
95 DP_TEST_PATTERN_PRBS7,
96 DP_TEST_PATTERN_80BIT_CUSTOM,
97 DP_TEST_PATTERN_CP2520_1,
98 DP_TEST_PATTERN_CP2520_2,
99 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2,
100 DP_TEST_PATTERN_CP2520_3,
102 /* Link Training Patterns */
103 DP_TEST_PATTERN_TRAINING_PATTERN1,
104 DP_TEST_PATTERN_TRAINING_PATTERN2,
105 DP_TEST_PATTERN_TRAINING_PATTERN3,
106 DP_TEST_PATTERN_TRAINING_PATTERN4,
107 DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_TRAINING_PATTERN4,
109 /* link test patterns*/
110 DP_TEST_PATTERN_COLOR_SQUARES,
111 DP_TEST_PATTERN_COLOR_SQUARES_CEA,
112 DP_TEST_PATTERN_VERTICAL_BARS,
113 DP_TEST_PATTERN_HORIZONTAL_BARS,
114 DP_TEST_PATTERN_COLOR_RAMP,
116 /* audio test patterns*/
117 DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED,
118 DP_TEST_PATTERN_AUDIO_SAWTOOTH,
120 DP_TEST_PATTERN_UNSUPPORTED
125 DP_PANEL_MODE_DEFAULT,
126 /* standard mode for eDP */
128 /* external chips specific settings */
129 DP_PANEL_MODE_SPECIAL
132 /* DPCD_ADDR_TRAINING_LANEx_SET registers value */
133 union dpcd_training_lane_set {
135 #if defined(LITTLEENDIAN_CPU)
136 uint8_t VOLTAGE_SWING_SET:2;
137 uint8_t MAX_SWING_REACHED:1;
138 uint8_t PRE_EMPHASIS_SET:2;
139 uint8_t MAX_PRE_EMPHASIS_REACHED:1;
140 /* following is reserved in DP 1.1 */
141 uint8_t POST_CURSOR2_SET:2;
142 #elif defined(BIGENDIAN_CPU)
143 uint8_t POST_CURSOR2_SET:2;
144 uint8_t MAX_PRE_EMPHASIS_REACHED:1;
145 uint8_t PRE_EMPHASIS_SET:2;
146 uint8_t MAX_SWING_REACHED:1;
147 uint8_t VOLTAGE_SWING_SET:2;
149 #error ARCH not defined!
157 /* DP MST stream allocation (payload bandwidth number) */
158 struct dp_mst_stream_allocation {
160 /* number of slots required for the DP stream in
161 * transport packet */
165 /* DP MST stream allocation table */
166 struct dp_mst_stream_allocation_table {
167 /* number of DP video streams */
169 /* array of stream allocations */
170 struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
173 #endif /*__DAL_LINK_SERVICE_TYPES_H__*/