2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef __DAL_BIOS_PARSER_TYPES_H__
28 #define __DAL_BIOS_PARSER_TYPES_H__
30 #include "dm_services.h"
31 #include "include/signal_types.h"
32 #include "include/grph_object_ctrl_defs.h"
33 #include "include/gpio_types.h"
34 #include "include/link_service_types.h"
36 /* TODO: include signal_types.h and remove this enum */
38 AS_SIGNAL_TYPE_NONE = 0L, /* no signal */
42 AS_SIGNAL_TYPE_DISPLAY_PORT,
43 AS_SIGNAL_TYPE_GPU_PLL,
44 AS_SIGNAL_TYPE_UNKNOWN
48 BP_RESULT_OK = 0, /* There was no error */
49 BP_RESULT_BADINPUT, /*Bad input parameter */
50 BP_RESULT_BADBIOSTABLE, /* Bad BIOS table */
51 BP_RESULT_UNSUPPORTED, /* BIOS Table is not supported */
52 BP_RESULT_NORECORD, /* Record can't be found */
56 enum bp_encoder_control_action {
57 /* direct VBIOS translation! Just to simplify the translation */
58 ENCODER_CONTROL_DISABLE = 0,
59 ENCODER_CONTROL_ENABLE,
60 ENCODER_CONTROL_SETUP,
64 enum bp_transmitter_control_action {
65 /* direct VBIOS translation! Just to simplify the translation */
66 TRANSMITTER_CONTROL_DISABLE = 0,
67 TRANSMITTER_CONTROL_ENABLE,
68 TRANSMITTER_CONTROL_BACKLIGHT_OFF,
69 TRANSMITTER_CONTROL_BACKLIGHT_ON,
70 TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS,
71 TRANSMITTER_CONTROL_LCD_SETF_TEST_START,
72 TRANSMITTER_CONTROL_LCD_SELF_TEST_STOP,
73 TRANSMITTER_CONTROL_INIT,
74 TRANSMITTER_CONTROL_DEACTIVATE,
75 TRANSMITTER_CONTROL_ACTIAVATE,
76 TRANSMITTER_CONTROL_SETUP,
77 TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS,
78 /* ATOM_TRANSMITTER_ACTION_POWER_ON. This action is for eDP only
79 * (power up the panel)
81 TRANSMITTER_CONTROL_POWER_ON,
82 /* ATOM_TRANSMITTER_ACTION_POWER_OFF. This action is for eDP only
83 * (power down the panel)
85 TRANSMITTER_CONTROL_POWER_OFF
88 enum bp_external_encoder_control_action {
89 EXTERNAL_ENCODER_CONTROL_DISABLE = 0,
90 EXTERNAL_ENCODER_CONTROL_ENABLE = 1,
91 EXTERNAL_ENCODER_CONTROL_INIT = 0x7,
92 EXTERNAL_ENCODER_CONTROL_SETUP = 0xf,
93 EXTERNAL_ENCODER_CONTROL_UNBLANK = 0x10,
94 EXTERNAL_ENCODER_CONTROL_BLANK = 0x11,
97 enum bp_pipe_control_action {
98 ASIC_PIPE_DISABLE = 0,
103 struct bp_encoder_control {
104 enum bp_encoder_control_action action;
105 enum engine_id engine_id;
106 enum transmitter transmitter;
107 enum signal_type signal;
108 enum dc_lane_count lanes_number;
109 enum dc_color_depth color_depth;
110 bool enable_dp_audio;
111 uint32_t pixel_clock; /* khz */
114 struct bp_external_encoder_control {
115 enum bp_external_encoder_control_action action;
116 enum engine_id engine_id;
117 enum dc_link_rate link_rate;
118 enum dc_lane_count lanes_number;
119 enum signal_type signal;
120 enum dc_color_depth color_depth;
122 struct graphics_object_id encoder_id;
123 struct graphics_object_id connector_obj_id;
124 uint32_t pixel_clock; /* in KHz */
127 struct bp_crtc_source_select {
128 enum engine_id engine_id;
129 enum controller_id controller_id;
130 /* from GPU Tx aka asic_signal */
131 enum signal_type signal;
132 /* sink_signal may differ from asicSignal if Translator encoder */
133 enum signal_type sink_signal;
134 enum display_output_bit_depth display_output_bit_depth;
135 bool enable_dp_audio;
138 struct bp_transmitter_control {
139 enum bp_transmitter_control_action action;
140 enum engine_id engine_id;
141 enum transmitter transmitter; /* PhyId */
142 enum dc_lane_count lanes_number;
143 enum clock_source_id pll_id; /* needed for DCE 4.0 */
144 enum signal_type signal;
145 enum dc_color_depth color_depth; /* not used for DCE6.0 */
146 enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */
147 struct graphics_object_id connector_obj_id;
148 /* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should
149 * be pixel clock * deep_color_ratio (in KHz)
151 uint32_t pixel_clock;
152 uint32_t lane_select;
153 uint32_t lane_settings;
156 bool single_pll_mode;
159 struct bp_hw_crtc_timing_parameters {
160 enum controller_id controller_id;
161 /* horizontal part */
163 uint32_t h_addressable;
164 uint32_t h_overscan_left;
165 uint32_t h_overscan_right;
166 uint32_t h_sync_start;
167 uint32_t h_sync_width;
171 uint32_t v_addressable;
172 uint32_t v_overscan_top;
173 uint32_t v_overscan_bottom;
174 uint32_t v_sync_start;
175 uint32_t v_sync_width;
177 struct timing_flags {
178 uint32_t INTERLACE:1;
179 uint32_t PIXEL_REPETITION:4;
180 uint32_t HSYNC_POSITIVE_POLARITY:1;
181 uint32_t VSYNC_POSITIVE_POLARITY:1;
182 uint32_t HORZ_COUNT_BY_TWO:1;
186 struct bp_adjust_pixel_clock_parameters {
187 /* Input: Signal Type - to be converted to Encoder mode */
188 enum signal_type signal_type;
189 /* Input: Encoder object id */
190 struct graphics_object_id encoder_object_id;
191 /* Input: Pixel Clock (requested Pixel clock based on Video timing
192 * standard used) in KHz
194 uint32_t pixel_clock;
195 /* Output: Adjusted Pixel Clock (after VBIOS exec table) in KHz */
196 uint32_t adjusted_pixel_clock;
197 /* Output: If non-zero, this refDiv value should be used to calculate
198 * other ppll params */
199 uint32_t reference_divider;
200 /* Output: If non-zero, this postDiv value should be used to calculate
201 * other ppll params */
202 uint32_t pixel_clock_post_divider;
203 /* Input: Enable spread spectrum */
207 struct bp_pixel_clock_parameters {
208 enum controller_id controller_id; /* (Which CRTC uses this PLL) */
209 enum clock_source_id pll_id; /* Clock Source Id */
210 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */
211 enum signal_type signal_type;
212 /* Adjusted Pixel Clock (after VBIOS exec table)
213 * that becomes Target Pixel Clock (KHz) */
214 uint32_t target_pixel_clock;
215 /* Calculated Reference divider of Display PLL */
216 uint32_t reference_divider;
217 /* Calculated Feedback divider of Display PLL */
218 uint32_t feedback_divider;
219 /* Calculated Fractional Feedback divider of Display PLL */
220 uint32_t fractional_feedback_divider;
221 /* Calculated Pixel Clock Post divider of Display PLL */
222 uint32_t pixel_clock_post_divider;
223 struct graphics_object_id encoder_object_id; /* Encoder object id */
224 /* VBIOS returns a fixed display clock when DFS-bypass feature
225 * is enabled (KHz) */
226 uint32_t dfs_bypass_display_clock;
227 /* color depth to support HDMI deep color */
228 enum transmitter_color_depth color_depth;
230 struct program_pixel_clock_flags {
231 uint32_t FORCE_PROGRAMMING_OF_PLL:1;
232 /* Use Engine Clock as source for Display Clock when
234 uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1;
235 /* Use external reference clock (refDivSrc for PLL) */
236 uint32_t SET_EXTERNAL_REF_DIV_SRC:1;
237 /* Force program PHY PLL only */
238 uint32_t PROGRAM_PHY_PLL_ONLY:1;
239 /* Support for YUV420 */
240 uint32_t SUPPORT_YUV_420:1;
241 /* Use XTALIN reference clock source */
242 uint32_t SET_XTALIN_REF_SRC:1;
243 /* Use GENLK reference clock source */
244 uint32_t SET_GENLOCK_REF_DIV_SRC:1;
248 enum bp_dce_clock_type {
249 DCECLOCK_TYPE_DISPLAY_CLOCK = 0,
250 DCECLOCK_TYPE_DPREFCLK = 1
253 /* DCE Clock Parameters structure for SetDceClock Exec command table */
254 struct bp_set_dce_clock_parameters {
255 enum clock_source_id pll_id; /* Clock Source Id */
256 /* Display clock or DPREFCLK value */
257 uint32_t target_clock_frequency;
258 /* Clock to set: =0: DISPCLK =1: DPREFCLK =2: PIXCLK */
259 enum bp_dce_clock_type clock_type;
261 struct set_dce_clock_flags {
262 uint32_t USE_GENERICA_AS_SOURCE_FOR_DPREFCLK:1;
263 /* Use XTALIN reference clock source */
264 uint32_t USE_XTALIN_AS_SOURCE_FOR_DPREFCLK:1;
265 /* Use PCIE reference clock source */
266 uint32_t USE_PCIE_AS_SOURCE_FOR_DPREFCLK:1;
267 /* Use GENLK reference clock source */
268 uint32_t USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK:1;
272 struct spread_spectrum_flags {
273 /* 1 = Center Spread; 0 = down spread */
274 uint32_t CENTER_SPREAD:1;
275 /* 1 = external; 0 = internal */
276 uint32_t EXTERNAL_SS:1;
277 /* 1 = delta-sigma type parameter; 0 = ver1 */
281 struct bp_spread_spectrum_parameters {
282 enum clock_source_id pll_id;
284 uint32_t ds_frac_amount;
290 uint32_t range; /* In Hz unit */
293 uint32_t feedback_amount;
294 uint32_t nfrac_amount;
295 uint32_t ds_frac_size;
299 struct spread_spectrum_flags flags;
302 struct bp_encoder_cap_info {
303 uint32_t DP_HBR2_CAP:1;
304 uint32_t DP_HBR2_EN:1;
305 uint32_t DP_HBR3_EN:1;
306 uint32_t HDMI_6GB_EN:1;
307 uint32_t RESERVED:30;
310 #endif /*__DAL_BIOS_PARSER_TYPES_H__ */