2 * Copyright 2012-15 Advanced Micro Devices, Inc.
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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26 #include "dm_services.h"
29 * Pre-requisites: headers required by header of this unit
31 #include "include/i2caux_interface.h"
33 #include "i2c_engine.h"
39 #include "i2c_sw_engine.h"
42 * Post-requisites: headers required by this unit
52 static inline bool read_bit_from_ddc(
59 dal_gpio_get_value(ddc->pin_data, &value);
61 dal_gpio_get_value(ddc->pin_clock, &value);
66 static inline void write_bit_to_ddc(
71 uint32_t value = bit ? 1 : 0;
74 dal_gpio_set_value(ddc->pin_data, value);
76 dal_gpio_set_value(ddc->pin_clock, value);
79 static bool wait_for_scl_high(
80 struct dc_context *ctx,
82 uint16_t clock_delay_div_4)
84 uint32_t scl_retry = 0;
85 uint32_t scl_retry_max = I2C_SW_TIMEOUT_DELAY / clock_delay_div_4;
87 udelay(clock_delay_div_4);
89 /* 3 milliseconds delay
90 * to wake up some displays from "low power" state.
94 if (read_bit_from_ddc(ddc, SCL))
97 udelay(clock_delay_div_4);
100 } while (scl_retry <= scl_retry_max);
105 static bool start_sync(
106 struct dc_context *ctx,
107 struct ddc *ddc_handle,
108 uint16_t clock_delay_div_4)
112 /* The I2C communications start signal is:
113 * the SDA going low from high, while the SCL is high. */
115 write_bit_to_ddc(ddc_handle, SCL, true);
117 udelay(clock_delay_div_4);
120 write_bit_to_ddc(ddc_handle, SDA, true);
122 if (!read_bit_from_ddc(ddc_handle, SDA)) {
127 udelay(clock_delay_div_4);
129 write_bit_to_ddc(ddc_handle, SCL, true);
131 if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
134 write_bit_to_ddc(ddc_handle, SDA, false);
136 udelay(clock_delay_div_4);
138 write_bit_to_ddc(ddc_handle, SCL, false);
140 udelay(clock_delay_div_4);
143 } while (retry <= I2C_SW_RETRIES);
148 static bool stop_sync(
149 struct dc_context *ctx,
150 struct ddc *ddc_handle,
151 uint16_t clock_delay_div_4)
155 /* The I2C communications stop signal is:
156 * the SDA going high from low, while the SCL is high. */
158 write_bit_to_ddc(ddc_handle, SCL, false);
160 udelay(clock_delay_div_4);
162 write_bit_to_ddc(ddc_handle, SDA, false);
164 udelay(clock_delay_div_4);
166 write_bit_to_ddc(ddc_handle, SCL, true);
168 if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
171 write_bit_to_ddc(ddc_handle, SDA, true);
174 udelay(clock_delay_div_4);
176 if (read_bit_from_ddc(ddc_handle, SDA))
180 } while (retry <= 2);
185 static bool write_byte(
186 struct dc_context *ctx,
187 struct ddc *ddc_handle,
188 uint16_t clock_delay_div_4,
194 /* bits are transmitted serially, starting from MSB */
197 udelay(clock_delay_div_4);
199 write_bit_to_ddc(ddc_handle, SDA, (byte >> shift) & 1);
201 udelay(clock_delay_div_4);
203 write_bit_to_ddc(ddc_handle, SCL, true);
205 if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
208 write_bit_to_ddc(ddc_handle, SCL, false);
211 } while (shift >= 0);
213 /* The display sends ACK by preventing the SDA from going high
214 * after the SCL pulse we use to send our last data bit.
215 * If the SDA goes high after that bit, it's a NACK */
217 udelay(clock_delay_div_4);
219 write_bit_to_ddc(ddc_handle, SDA, true);
221 udelay(clock_delay_div_4);
223 write_bit_to_ddc(ddc_handle, SCL, true);
225 if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
230 ack = !read_bit_from_ddc(ddc_handle, SDA);
232 udelay(clock_delay_div_4 << 1);
234 write_bit_to_ddc(ddc_handle, SCL, false);
236 udelay(clock_delay_div_4 << 1);
241 static bool read_byte(
242 struct dc_context *ctx,
243 struct ddc *ddc_handle,
244 uint16_t clock_delay_div_4,
252 /* The data bits are read from MSB to LSB;
253 * bit is read while SCL is high */
256 write_bit_to_ddc(ddc_handle, SCL, true);
258 if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
261 if (read_bit_from_ddc(ddc_handle, SDA))
262 data |= (1 << shift);
264 write_bit_to_ddc(ddc_handle, SCL, false);
266 udelay(clock_delay_div_4 << 1);
269 } while (shift >= 0);
271 /* read only whole byte */
275 udelay(clock_delay_div_4);
277 /* send the acknowledge bit:
278 * SDA low means ACK, SDA high means NACK */
280 write_bit_to_ddc(ddc_handle, SDA, !more);
282 udelay(clock_delay_div_4);
284 write_bit_to_ddc(ddc_handle, SCL, true);
286 if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
289 write_bit_to_ddc(ddc_handle, SCL, false);
291 udelay(clock_delay_div_4);
293 write_bit_to_ddc(ddc_handle, SDA, true);
295 udelay(clock_delay_div_4);
300 static bool i2c_write(
301 struct dc_context *ctx,
302 struct ddc *ddc_handle,
303 uint16_t clock_delay_div_4,
310 if (!write_byte(ctx, ddc_handle, clock_delay_div_4, address))
314 if (!write_byte(ctx, ddc_handle, clock_delay_div_4, data[i]))
322 static bool i2c_read(
323 struct dc_context *ctx,
324 struct ddc *ddc_handle,
325 uint16_t clock_delay_div_4,
332 if (!write_byte(ctx, ddc_handle, clock_delay_div_4, address))
336 if (!read_byte(ctx, ddc_handle, clock_delay_div_4, data + i,
347 * Cast 'struct i2c_engine *'
348 * to 'struct i2c_sw_engine *'
350 #define FROM_I2C_ENGINE(ptr) \
351 container_of((ptr), struct i2c_sw_engine, base)
355 * Cast 'struct engine *'
356 * to 'struct i2c_sw_engine *'
358 #define FROM_ENGINE(ptr) \
359 FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
361 enum i2caux_engine_type dal_i2c_sw_engine_get_engine_type(
362 const struct engine *engine)
364 return I2CAUX_ENGINE_TYPE_I2C_SW;
367 bool dal_i2c_sw_engine_submit_request(
368 struct engine *engine,
369 struct i2caux_transaction_request *i2caux_request,
370 bool middle_of_transaction)
372 struct i2c_sw_engine *sw_engine = FROM_ENGINE(engine);
374 struct i2c_engine *base = &sw_engine->base;
376 struct i2c_request_transaction_data request;
377 bool operation_succeeded = false;
379 if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
380 request.action = middle_of_transaction ?
381 I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
382 I2CAUX_TRANSACTION_ACTION_I2C_READ;
383 else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
384 request.action = middle_of_transaction ?
385 I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
386 I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
388 i2caux_request->status =
389 I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
390 /* in DAL2, there was no "return false" */
394 request.address = (uint8_t)i2caux_request->payload.address;
395 request.length = i2caux_request->payload.length;
396 request.data = i2caux_request->payload.data;
398 base->funcs->submit_channel_request(base, &request);
400 if ((request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY) ||
401 (request.status == I2C_CHANNEL_OPERATION_FAILED))
402 i2caux_request->status =
403 I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY;
405 enum i2c_channel_operation_result operation_result;
409 base->funcs->get_channel_status(base, NULL);
411 switch (operation_result) {
412 case I2C_CHANNEL_OPERATION_SUCCEEDED:
413 i2caux_request->status =
414 I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
415 operation_succeeded = true;
417 case I2C_CHANNEL_OPERATION_NO_RESPONSE:
418 i2caux_request->status =
419 I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
421 case I2C_CHANNEL_OPERATION_TIMEOUT:
422 i2caux_request->status =
423 I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
425 case I2C_CHANNEL_OPERATION_FAILED:
426 i2caux_request->status =
427 I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
430 i2caux_request->status =
431 I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
434 } while (operation_result == I2C_CHANNEL_OPERATION_ENGINE_BUSY);
437 return operation_succeeded;
440 uint32_t dal_i2c_sw_engine_get_speed(
441 const struct i2c_engine *engine)
443 return FROM_I2C_ENGINE(engine)->speed;
446 void dal_i2c_sw_engine_set_speed(
447 struct i2c_engine *engine,
450 struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
454 sw_engine->speed = speed ? speed : I2CAUX_DEFAULT_I2C_SW_SPEED;
456 sw_engine->clock_delay = 1000 / sw_engine->speed;
458 if (sw_engine->clock_delay < 12)
459 sw_engine->clock_delay = 12;
462 bool dal_i2caux_i2c_sw_engine_acquire_engine(
463 struct i2c_engine *engine,
466 enum gpio_result result;
468 result = dal_ddc_open(ddc, GPIO_MODE_FAST_OUTPUT,
469 GPIO_DDC_CONFIG_TYPE_MODE_I2C);
471 if (result != GPIO_RESULT_OK)
474 engine->base.ddc = ddc;
479 void dal_i2c_sw_engine_submit_channel_request(
480 struct i2c_engine *engine,
481 struct i2c_request_transaction_data *req)
483 struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
485 struct ddc *ddc = engine->base.ddc;
486 uint16_t clock_delay_div_4 = sw_engine->clock_delay >> 2;
488 /* send sync (start / repeated start) */
490 bool result = start_sync(engine->base.ctx, ddc, clock_delay_div_4);
492 /* process payload */
495 switch (req->action) {
496 case I2CAUX_TRANSACTION_ACTION_I2C_WRITE:
497 case I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT:
498 result = i2c_write(engine->base.ctx, ddc, clock_delay_div_4,
499 req->address, req->length, req->data);
501 case I2CAUX_TRANSACTION_ACTION_I2C_READ:
502 case I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT:
503 result = i2c_read(engine->base.ctx, ddc, clock_delay_div_4,
504 req->address, req->length, req->data);
512 /* send stop if not 'mot' or operation failed */
515 (req->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
516 (req->action == I2CAUX_TRANSACTION_ACTION_I2C_READ))
517 if (!stop_sync(engine->base.ctx, ddc, clock_delay_div_4))
520 req->status = result ?
521 I2C_CHANNEL_OPERATION_SUCCEEDED :
522 I2C_CHANNEL_OPERATION_FAILED;
525 enum i2c_channel_operation_result dal_i2c_sw_engine_get_channel_status(
526 struct i2c_engine *engine,
527 uint8_t *returned_bytes)
529 /* No arbitration with VBIOS is performed since DCE 6.0 */
530 return I2C_CHANNEL_OPERATION_SUCCEEDED;
533 void dal_i2c_sw_engine_destruct(
534 struct i2c_sw_engine *engine)
536 dal_i2c_engine_destruct(&engine->base);
540 struct i2c_engine **ptr)
542 dal_i2c_sw_engine_destruct(FROM_I2C_ENGINE(*ptr));
548 static const struct i2c_engine_funcs i2c_engine_funcs = {
549 .acquire_engine = dal_i2caux_i2c_sw_engine_acquire_engine,
551 .get_speed = dal_i2c_sw_engine_get_speed,
552 .set_speed = dal_i2c_sw_engine_set_speed,
553 .setup_engine = dal_i2c_engine_setup_i2c_engine,
554 .submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
555 .process_channel_reply = dal_i2c_engine_process_channel_reply,
556 .get_channel_status = dal_i2c_sw_engine_get_channel_status,
559 static void release_engine(
560 struct engine *engine)
565 static const struct engine_funcs engine_funcs = {
566 .release_engine = release_engine,
567 .get_engine_type = dal_i2c_sw_engine_get_engine_type,
568 .acquire = dal_i2c_engine_acquire,
569 .submit_request = dal_i2c_sw_engine_submit_request,
572 void dal_i2c_sw_engine_construct(
573 struct i2c_sw_engine *engine,
574 const struct i2c_sw_engine_create_arg *arg)
576 dal_i2c_engine_construct(&engine->base, arg->ctx);
577 dal_i2c_sw_engine_set_speed(&engine->base, arg->default_speed);
578 engine->base.funcs = &i2c_engine_funcs;
579 engine->base.base.funcs = &engine_funcs;
582 struct i2c_engine *dal_i2c_sw_engine_create(
583 const struct i2c_sw_engine_create_arg *arg)
585 struct i2c_sw_engine *engine;
592 engine = kzalloc(sizeof(struct i2c_sw_engine), GFP_KERNEL);
599 dal_i2c_sw_engine_construct(engine, arg);
600 return &engine->base;