2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dml1_display_rq_dlg_calc.h"
27 #include "display_mode_lib.h"
29 #include "dml_inline_defs.h"
33 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
35 * It doesn't adhere to Linux kernel style and sometimes will do things in odd
36 * ways. Unless there is something clearly wrong with it the code should
37 * remain as-is as it provides us with a guarantee from HW that it is correct.
40 static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
42 unsigned int ret_val = 0;
44 if (source_format == dm_444_16) {
47 } else if (source_format == dm_444_32) {
50 } else if (source_format == dm_444_64) {
53 } else if (source_format == dm_420_8) {
58 } else if (source_format == dm_420_10) {
67 static bool is_dual_plane(enum source_format_class source_format)
71 if ((source_format == dm_420_8) || (source_format == dm_420_10))
77 static void get_blk256_size(
78 unsigned int *blk256_width,
79 unsigned int *blk256_height,
80 unsigned int bytes_per_element)
82 if (bytes_per_element == 1) {
85 } else if (bytes_per_element == 2) {
88 } else if (bytes_per_element == 4) {
91 } else if (bytes_per_element == 8) {
97 static double get_refcyc_per_delivery(
98 struct display_mode_lib *mode_lib,
99 double refclk_freq_in_mhz,
100 double pclk_freq_in_mhz,
101 unsigned int recout_width,
103 double hscale_pixel_rate,
104 unsigned int delivery_width,
105 unsigned int req_per_swath_ub)
107 double refcyc_per_delivery = 0.0;
110 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width
111 / pclk_freq_in_mhz / (double) req_per_swath_ub;
113 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width
114 / (double) hscale_pixel_rate / (double) req_per_swath_ub;
117 DTRACE("DLG: %s: refclk_freq_in_mhz = %3.2f", __func__, refclk_freq_in_mhz);
118 DTRACE("DLG: %s: pclk_freq_in_mhz = %3.2f", __func__, pclk_freq_in_mhz);
119 DTRACE("DLG: %s: recout_width = %d", __func__, recout_width);
120 DTRACE("DLG: %s: vratio = %3.2f", __func__, vratio);
121 DTRACE("DLG: %s: req_per_swath_ub = %d", __func__, req_per_swath_ub);
122 DTRACE("DLG: %s: refcyc_per_delivery= %3.2f", __func__, refcyc_per_delivery);
124 return refcyc_per_delivery;
128 static double get_vratio_pre(
129 struct display_mode_lib *mode_lib,
130 unsigned int max_num_sw,
131 unsigned int max_partial_sw,
132 unsigned int swath_height,
136 double prefill = dml_floor(vinit, 1);
137 double vratio_pre = 1.0;
139 vratio_pre = (max_num_sw * swath_height + max_partial_sw) / l_sw;
141 if (swath_height > 4) {
142 double tmp0 = (max_num_sw * swath_height) / (l_sw - (prefill - 3.0) / 2.0);
144 if (tmp0 > vratio_pre)
148 DTRACE("DLG: %s: max_num_sw = %0d", __func__, max_num_sw);
149 DTRACE("DLG: %s: max_partial_sw = %0d", __func__, max_partial_sw);
150 DTRACE("DLG: %s: swath_height = %0d", __func__, swath_height);
151 DTRACE("DLG: %s: vinit = %3.2f", __func__, vinit);
152 DTRACE("DLG: %s: vratio_pre = %3.2f", __func__, vratio_pre);
154 if (vratio_pre < 1.0) {
155 DTRACE("WARNING_DLG: %s: vratio_pre=%3.2f < 1.0, set to 1.0", __func__, vratio_pre);
159 if (vratio_pre > 4.0) {
161 "WARNING_DLG: %s: vratio_pre=%3.2f > 4.0 (max scaling ratio). set to 4.0",
170 static void get_swath_need(
171 struct display_mode_lib *mode_lib,
172 unsigned int *max_num_sw,
173 unsigned int *max_partial_sw,
174 unsigned int swath_height,
177 double prefill = dml_floor(vinit, 1);
178 unsigned int max_partial_sw_int;
180 DTRACE("DLG: %s: swath_height = %0d", __func__, swath_height);
181 DTRACE("DLG: %s: vinit = %3.2f", __func__, vinit);
183 ASSERT(prefill > 0.0 && prefill <= 8.0);
185 *max_num_sw = (unsigned int) (dml_ceil((prefill - 1.0) / (double) swath_height, 1) + 1.0); /* prefill has to be >= 1 */
189 ((unsigned int) (prefill - 2.0) % swath_height);
190 *max_partial_sw = (max_partial_sw_int < 1) ? 1 : max_partial_sw_int; /* ensure minimum of 1 is used */
192 DTRACE("DLG: %s: max_num_sw = %0d", __func__, *max_num_sw);
193 DTRACE("DLG: %s: max_partial_sw = %0d", __func__, *max_partial_sw);
196 static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
198 if (tile_size == dm_256k_tile)
200 else if (tile_size == dm_64k_tile)
206 static void extract_rq_sizing_regs(
207 struct display_mode_lib *mode_lib,
208 struct _vcs_dpi_display_data_rq_regs_st *rq_regs,
209 const struct _vcs_dpi_display_data_rq_sizing_params_st rq_sizing)
211 DTRACE("DLG: %s: rq_sizing param", __func__);
212 print__data_rq_sizing_params_st(mode_lib, rq_sizing);
214 rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
216 if (rq_sizing.min_chunk_bytes == 0)
217 rq_regs->min_chunk_size = 0;
219 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
221 rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
222 if (rq_sizing.min_meta_chunk_bytes == 0)
223 rq_regs->min_meta_chunk_size = 0;
225 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
227 rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
228 rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
231 void dml1_extract_rq_regs(
232 struct display_mode_lib *mode_lib,
233 struct _vcs_dpi_display_rq_regs_st *rq_regs,
234 const struct _vcs_dpi_display_rq_params_st rq_param)
236 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
237 unsigned int detile_buf_plane1_addr = 0;
239 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
241 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
243 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
244 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
246 /* FIXME: take the max between luma, chroma chunk size?
247 * okay for now, as we are setting chunk_bytes to 8kb anyways
249 if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { /*32kb */
250 rq_regs->drq_expansion_mode = 0;
252 rq_regs->drq_expansion_mode = 2;
254 rq_regs->prq_expansion_mode = 1;
255 rq_regs->mrq_expansion_mode = 1;
256 rq_regs->crq_expansion_mode = 1;
258 if (rq_param.yuv420) {
259 if ((double) rq_param.misc.rq_l.stored_swath_bytes
260 / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {
261 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); /* half to chroma */
263 detile_buf_plane1_addr = dml_round_to_multiple(
264 (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
266 0) / 64.0; /* 2/3 to chroma */
269 rq_regs->plane1_base_address = detile_buf_plane1_addr;
272 static void handle_det_buf_split(
273 struct display_mode_lib *mode_lib,
274 struct _vcs_dpi_display_rq_params_st *rq_param,
275 const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param)
277 unsigned int total_swath_bytes = 0;
278 unsigned int swath_bytes_l = 0;
279 unsigned int swath_bytes_c = 0;
280 unsigned int full_swath_bytes_packed_l = 0;
281 unsigned int full_swath_bytes_packed_c = 0;
284 bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
285 bool surf_vert = (pipe_src_param.source_scan == dm_vert);
286 unsigned int log2_swath_height_l = 0;
287 unsigned int log2_swath_height_c = 0;
288 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
290 full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
291 full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
293 if (rq_param->yuv420_10bpc) {
294 full_swath_bytes_packed_l = dml_round_to_multiple(
295 rq_param->misc.rq_l.full_swath_bytes * 2 / 3,
298 full_swath_bytes_packed_c = dml_round_to_multiple(
299 rq_param->misc.rq_c.full_swath_bytes * 2 / 3,
304 if (rq_param->yuv420) {
305 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
307 if (total_swath_bytes <= detile_buf_size_in_bytes) { /*full 256b request */
310 swath_bytes_l = full_swath_bytes_packed_l;
311 swath_bytes_c = full_swath_bytes_packed_c;
312 } else { /*128b request (for luma only for yuv420 8bpc) */
315 swath_bytes_l = full_swath_bytes_packed_l / 2;
316 swath_bytes_c = full_swath_bytes_packed_c;
319 /* Bug workaround, luma and chroma req size needs to be the same. (see: DEGVIDCN10-137)
320 * TODO: Remove after rtl fix
324 DTRACE("DLG: %s: bug workaround DEGVIDCN10-137", __func__);
327 /* Note: assumption, the config that pass in will fit into
328 * the detiled buffer.
331 total_swath_bytes = 2 * full_swath_bytes_packed_l;
333 if (total_swath_bytes <= detile_buf_size_in_bytes)
338 swath_bytes_l = total_swath_bytes;
341 rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
342 rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
345 log2_swath_height_l = 0;
346 log2_swath_height_c = 0;
347 } else if (!surf_vert) {
348 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
349 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
351 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
352 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
354 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
355 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
357 DTRACE("DLG: %s: req128_l = %0d", __func__, req128_l);
358 DTRACE("DLG: %s: req128_c = %0d", __func__, req128_c);
359 DTRACE("DLG: %s: full_swath_bytes_packed_l = %0d", __func__, full_swath_bytes_packed_l);
360 DTRACE("DLG: %s: full_swath_bytes_packed_c = %0d", __func__, full_swath_bytes_packed_c);
364 static void dml1_rq_dlg_get_row_heights(
365 struct display_mode_lib *mode_lib,
366 unsigned int *o_dpte_row_height,
367 unsigned int *o_meta_row_height,
368 unsigned int vp_width,
369 unsigned int data_pitch,
376 bool surf_linear = (tiling == dm_sw_linear);
377 bool surf_vert = (source_scan == dm_vert);
379 unsigned int bytes_per_element = get_bytes_per_element(
380 (enum source_format_class) source_format,
382 unsigned int log2_bytes_per_element = dml_log2(bytes_per_element);
383 unsigned int blk256_width = 0;
384 unsigned int blk256_height = 0;
386 unsigned int log2_blk256_height;
387 unsigned int blk_bytes;
388 unsigned int log2_blk_bytes;
389 unsigned int log2_blk_height;
390 unsigned int log2_blk_width;
391 unsigned int log2_meta_req_bytes;
392 unsigned int log2_meta_req_height;
393 unsigned int log2_meta_req_width;
394 unsigned int log2_meta_row_height;
395 unsigned int log2_vmpg_bytes;
396 unsigned int dpte_buf_in_pte_reqs;
397 unsigned int log2_vmpg_height;
398 unsigned int log2_vmpg_width;
399 unsigned int log2_dpte_req_height_ptes;
400 unsigned int log2_dpte_req_width_ptes;
401 unsigned int log2_dpte_req_height;
402 unsigned int log2_dpte_req_width;
403 unsigned int log2_dpte_row_height_linear;
404 unsigned int log2_dpte_row_height;
405 unsigned int dpte_req_width;
411 get_blk256_size(&blk256_width, &blk256_height, bytes_per_element);
414 log2_blk256_height = dml_log2((double) blk256_height);
415 blk_bytes = surf_linear ?
416 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
417 log2_blk_bytes = dml_log2((double) blk_bytes);
422 * "+" in log is multiply
423 * "-" in log is divide
424 * "/2" is like square root
425 * blk is vertical biased
427 if (tiling != dm_sw_linear)
428 log2_blk_height = log2_blk256_height
429 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
431 log2_blk_height = 0; /* blk height of 1 */
433 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
438 log2_meta_req_bytes = 6; /* meta request is 64b and is 8x8byte meta element */
440 /* each 64b meta request for dcn is 8x8 meta elements and
441 * a meta element covers one 256b block of the the data surface.
443 log2_meta_req_height = log2_blk256_height + 3; /* meta req is 8x8 */
444 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element
445 - log2_meta_req_height;
446 log2_meta_row_height = 0;
448 /* the dimensions of a meta row are meta_row_width x meta_row_height in elements.
449 * calculate upper bound of the meta_row_width
452 log2_meta_row_height = log2_meta_req_height;
454 log2_meta_row_height = log2_meta_req_width;
456 *o_meta_row_height = 1 << log2_meta_row_height;
461 log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
462 dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs;
464 log2_vmpg_height = 0;
466 log2_dpte_req_height_ptes = 0;
467 log2_dpte_req_width_ptes = 0;
468 log2_dpte_req_height = 0;
469 log2_dpte_req_width = 0;
470 log2_dpte_row_height_linear = 0;
471 log2_dpte_row_height = 0;
472 dpte_req_width = 0; /* 64b dpte req width in data element */
475 log2_vmpg_height = 0; /* one line high */
477 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
478 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
480 /* only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. */
481 if (log2_blk_bytes <= log2_vmpg_bytes)
482 log2_dpte_req_height_ptes = 0;
483 else if (log2_blk_height - log2_vmpg_height >= 2)
484 log2_dpte_req_height_ptes = 2;
486 log2_dpte_req_height_ptes = log2_blk_height - log2_vmpg_height;
487 log2_dpte_req_width_ptes = 3 - log2_dpte_req_height_ptes;
489 ASSERT((log2_dpte_req_width_ptes == 3 && log2_dpte_req_height_ptes == 0) || /* 8x1 */
490 (log2_dpte_req_width_ptes == 2 && log2_dpte_req_height_ptes == 1) || /* 4x2 */
491 (log2_dpte_req_width_ptes == 1 && log2_dpte_req_height_ptes == 2)); /* 2x4 */
493 /* the dpte request dimensions in data elements is dpte_req_width x dpte_req_height
494 * log2_wmpg_width is how much 1 pte represent, now trying to calculate how much 64b pte req represent
496 log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes;
497 log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes;
498 dpte_req_width = 1 << log2_dpte_req_width;
500 /* calculate pitch dpte row buffer can hold
501 * round the result down to a power of two.
504 log2_dpte_row_height_linear = dml_floor(
505 dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch),
508 ASSERT(log2_dpte_row_height_linear >= 3);
510 if (log2_dpte_row_height_linear > 7)
511 log2_dpte_row_height_linear = 7;
513 log2_dpte_row_height = log2_dpte_row_height_linear;
515 /* the upper bound of the dpte_row_width without dependency on viewport position follows. */
517 log2_dpte_row_height = log2_dpte_req_height;
519 log2_dpte_row_height =
520 (log2_blk_width < log2_dpte_req_width) ?
521 log2_blk_width : log2_dpte_req_width;
524 /* From programming guide:
525 * There is a special case of saving only half of ptes returned due to buffer space limits.
526 * this case applies to 4 and 8bpe in horizontal access of a vp_width greater than 2560+16
527 * when the pte request is 2x4 ptes (which happens when vmpg_bytes =4kb and tile blk_bytes >=64kb).
529 if (!surf_vert && vp_width > (2560 + 16) && bytes_per_element >= 4 && log2_vmpg_bytes == 12
530 && log2_blk_bytes >= 16)
531 log2_dpte_row_height = log2_dpte_row_height - 1; /*half of the full height */
533 *o_dpte_row_height = 1 << log2_dpte_row_height;
536 static void get_surf_rq_param(
537 struct display_mode_lib *mode_lib,
538 struct _vcs_dpi_display_data_rq_sizing_params_st *rq_sizing_param,
539 struct _vcs_dpi_display_data_rq_dlg_params_st *rq_dlg_param,
540 struct _vcs_dpi_display_data_rq_misc_params_st *rq_misc_param,
541 const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param,
545 unsigned int vp_width = 0;
546 unsigned int vp_height = 0;
547 unsigned int data_pitch = 0;
548 unsigned int meta_pitch = 0;
549 unsigned int ppe = mode_422 ? 2 : 1;
552 unsigned int bytes_per_element;
553 unsigned int log2_bytes_per_element;
554 unsigned int blk256_width;
555 unsigned int blk256_height;
556 unsigned int log2_blk256_width;
557 unsigned int log2_blk256_height;
558 unsigned int blk_bytes;
559 unsigned int log2_blk_bytes;
560 unsigned int log2_blk_height;
561 unsigned int log2_blk_width;
562 unsigned int log2_meta_req_bytes;
563 unsigned int log2_meta_req_height;
564 unsigned int log2_meta_req_width;
565 unsigned int meta_req_width;
566 unsigned int meta_req_height;
567 unsigned int log2_meta_row_height;
568 unsigned int meta_row_width_ub;
569 unsigned int log2_meta_chunk_bytes;
570 unsigned int log2_meta_chunk_height;
571 unsigned int log2_meta_chunk_width;
572 unsigned int log2_min_meta_chunk_bytes;
573 unsigned int min_meta_chunk_width;
574 unsigned int meta_chunk_width;
575 unsigned int meta_chunk_per_row_int;
576 unsigned int meta_row_remainder;
577 unsigned int meta_chunk_threshold;
578 unsigned int meta_blk_bytes;
579 unsigned int meta_blk_height;
580 unsigned int meta_blk_width;
581 unsigned int meta_surface_bytes;
582 unsigned int vmpg_bytes;
583 unsigned int meta_pte_req_per_frame_ub;
584 unsigned int meta_pte_bytes_per_frame_ub;
585 unsigned int log2_vmpg_bytes;
586 unsigned int dpte_buf_in_pte_reqs;
587 unsigned int log2_vmpg_height;
588 unsigned int log2_vmpg_width;
589 unsigned int log2_dpte_req_height_ptes;
590 unsigned int log2_dpte_req_width_ptes;
591 unsigned int log2_dpte_req_height;
592 unsigned int log2_dpte_req_width;
593 unsigned int log2_dpte_row_height_linear;
594 unsigned int log2_dpte_row_height;
595 unsigned int log2_dpte_group_width;
596 unsigned int dpte_row_width_ub;
597 unsigned int dpte_row_height;
598 unsigned int dpte_req_height;
599 unsigned int dpte_req_width;
600 unsigned int dpte_group_width;
601 unsigned int log2_dpte_group_bytes;
602 unsigned int log2_dpte_group_length;
603 unsigned int func_meta_row_height, func_dpte_row_height;
605 /* FIXME check if ppe apply for both luma and chroma in 422 case */
607 vp_width = pipe_src_param.viewport_width_c / ppe;
608 vp_height = pipe_src_param.viewport_height_c;
609 data_pitch = pipe_src_param.data_pitch_c;
610 meta_pitch = pipe_src_param.meta_pitch_c;
612 vp_width = pipe_src_param.viewport_width / ppe;
613 vp_height = pipe_src_param.viewport_height;
614 data_pitch = pipe_src_param.data_pitch;
615 meta_pitch = pipe_src_param.meta_pitch;
618 rq_sizing_param->chunk_bytes = 8192;
620 if (rq_sizing_param->chunk_bytes == 64 * 1024)
621 rq_sizing_param->min_chunk_bytes = 0;
623 rq_sizing_param->min_chunk_bytes = 1024;
625 rq_sizing_param->meta_chunk_bytes = 2048;
626 rq_sizing_param->min_meta_chunk_bytes = 256;
628 rq_sizing_param->mpte_group_bytes = 2048;
630 surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
631 surf_vert = (pipe_src_param.source_scan == dm_vert);
633 bytes_per_element = get_bytes_per_element(
634 (enum source_format_class) pipe_src_param.source_format,
636 log2_bytes_per_element = dml_log2(bytes_per_element);
641 blk256_width = 256 / bytes_per_element;
644 get_blk256_size(&blk256_width, &blk256_height, bytes_per_element);
647 DTRACE("DLG: %s: surf_linear = %d", __func__, surf_linear);
648 DTRACE("DLG: %s: surf_vert = %d", __func__, surf_vert);
649 DTRACE("DLG: %s: blk256_width = %d", __func__, blk256_width);
650 DTRACE("DLG: %s: blk256_height = %d", __func__, blk256_height);
652 log2_blk256_width = dml_log2((double) blk256_width);
653 log2_blk256_height = dml_log2((double) blk256_height);
655 surf_linear ? 256 : get_blk_size_bytes(
656 (enum source_macro_tile_size) pipe_src_param.macro_tile_size);
657 log2_blk_bytes = dml_log2((double) blk_bytes);
662 * "+" in log is multiply
663 * "-" in log is divide
664 * "/2" is like square root
665 * blk is vertical biased
667 if (pipe_src_param.sw_mode != dm_sw_linear)
668 log2_blk_height = log2_blk256_height
669 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
671 log2_blk_height = 0; /* blk height of 1 */
673 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
676 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
678 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width;
680 rq_dlg_param->swath_width_ub = dml_round_to_multiple(
684 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height;
688 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height
691 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width
694 rq_misc_param->blk256_height = blk256_height;
695 rq_misc_param->blk256_width = blk256_width;
700 log2_meta_req_bytes = 6; /* meta request is 64b and is 8x8byte meta element */
702 /* each 64b meta request for dcn is 8x8 meta elements and
703 * a meta element covers one 256b block of the the data surface.
705 log2_meta_req_height = log2_blk256_height + 3; /* meta req is 8x8 byte, each byte represent 1 blk256 */
706 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element
707 - log2_meta_req_height;
708 meta_req_width = 1 << log2_meta_req_width;
709 meta_req_height = 1 << log2_meta_req_height;
710 log2_meta_row_height = 0;
711 meta_row_width_ub = 0;
713 /* the dimensions of a meta row are meta_row_width x meta_row_height in elements.
714 * calculate upper bound of the meta_row_width
717 log2_meta_row_height = log2_meta_req_height;
718 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
720 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
722 log2_meta_row_height = log2_meta_req_width;
723 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1)
725 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
727 rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
729 log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
730 log2_meta_chunk_height = log2_meta_row_height;
732 /*full sized meta chunk width in unit of data elements */
733 log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element
734 - log2_meta_chunk_height;
735 log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
736 min_meta_chunk_width = 1
737 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element
738 - log2_meta_chunk_height);
739 meta_chunk_width = 1 << log2_meta_chunk_width;
740 meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
741 meta_row_remainder = meta_row_width_ub % meta_chunk_width;
742 meta_chunk_threshold = 0;
743 meta_blk_bytes = 4096;
744 meta_blk_height = blk256_height * 64;
745 meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height;
746 meta_surface_bytes = meta_pitch
747 * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1)
748 + meta_blk_height) * bytes_per_element / 256;
749 vmpg_bytes = mode_lib->soc.vmm_page_size_bytes;
750 meta_pte_req_per_frame_ub = (dml_round_to_multiple(
751 meta_surface_bytes - vmpg_bytes,
753 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
754 meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; /*64B mpte request */
755 rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
757 DTRACE("DLG: %s: meta_blk_height = %d", __func__, meta_blk_height);
758 DTRACE("DLG: %s: meta_blk_width = %d", __func__, meta_blk_width);
759 DTRACE("DLG: %s: meta_surface_bytes = %d", __func__, meta_surface_bytes);
760 DTRACE("DLG: %s: meta_pte_req_per_frame_ub = %d", __func__, meta_pte_req_per_frame_ub);
761 DTRACE("DLG: %s: meta_pte_bytes_per_frame_ub = %d", __func__, meta_pte_bytes_per_frame_ub);
764 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
766 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
768 if (meta_row_remainder <= meta_chunk_threshold)
769 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
771 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
773 rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
778 log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
779 dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs;
781 log2_vmpg_height = 0;
783 log2_dpte_req_height_ptes = 0;
784 log2_dpte_req_width_ptes = 0;
785 log2_dpte_req_height = 0;
786 log2_dpte_req_width = 0;
787 log2_dpte_row_height_linear = 0;
788 log2_dpte_row_height = 0;
789 log2_dpte_group_width = 0;
790 dpte_row_width_ub = 0;
792 dpte_req_height = 0; /* 64b dpte req height in data element */
793 dpte_req_width = 0; /* 64b dpte req width in data element */
794 dpte_group_width = 0;
795 log2_dpte_group_bytes = 0;
796 log2_dpte_group_length = 0;
799 log2_vmpg_height = 0; /* one line high */
801 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
802 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
804 /* only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. */
805 if (log2_blk_bytes <= log2_vmpg_bytes)
806 log2_dpte_req_height_ptes = 0;
807 else if (log2_blk_height - log2_vmpg_height >= 2)
808 log2_dpte_req_height_ptes = 2;
810 log2_dpte_req_height_ptes = log2_blk_height - log2_vmpg_height;
811 log2_dpte_req_width_ptes = 3 - log2_dpte_req_height_ptes;
813 /* Ensure we only have the 3 shapes */
814 ASSERT((log2_dpte_req_width_ptes == 3 && log2_dpte_req_height_ptes == 0) || /* 8x1 */
815 (log2_dpte_req_width_ptes == 2 && log2_dpte_req_height_ptes == 1) || /* 4x2 */
816 (log2_dpte_req_width_ptes == 1 && log2_dpte_req_height_ptes == 2)); /* 2x4 */
818 /* The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
819 * log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
820 * That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
822 log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes;
823 log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes;
824 dpte_req_height = 1 << log2_dpte_req_height;
825 dpte_req_width = 1 << log2_dpte_req_width;
827 /* calculate pitch dpte row buffer can hold
828 * round the result down to a power of two.
831 log2_dpte_row_height_linear = dml_floor(
832 dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch),
835 ASSERT(log2_dpte_row_height_linear >= 3);
837 if (log2_dpte_row_height_linear > 7)
838 log2_dpte_row_height_linear = 7;
840 log2_dpte_row_height = log2_dpte_row_height_linear;
841 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
843 /* For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
844 * the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
846 dpte_row_width_ub = dml_round_to_multiple(
847 data_pitch * dpte_row_height - 1,
850 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
852 /* for tiled mode, row height is the same as req height and row store up to vp size upper bound */
854 log2_dpte_row_height = log2_dpte_req_height;
855 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
857 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
859 log2_dpte_row_height =
860 (log2_blk_width < log2_dpte_req_width) ?
861 log2_blk_width : log2_dpte_req_width;
862 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
864 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
866 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
868 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64;
870 /* From programming guide:
871 * There is a special case of saving only half of ptes returned due to buffer space limits.
872 * this case applies to 4 and 8bpe in horizontal access of a vp_width greater than 2560+16
873 * when the pte request is 2x4 ptes (which happens when vmpg_bytes =4kb and tile blk_bytes >=64kb).
875 if (!surf_vert && vp_width > (2560 + 16) && bytes_per_element >= 4 && log2_vmpg_bytes == 12
876 && log2_blk_bytes >= 16) {
877 log2_dpte_row_height = log2_dpte_row_height - 1; /*half of the full height */
878 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
881 /* the dpte_group_bytes is reduced for the specific case of vertical
882 * access of a tile surface that has dpte request of 8x1 ptes.
884 if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) /*reduced, in this case, will have page fault within a group */
885 rq_sizing_param->dpte_group_bytes = 512;
888 rq_sizing_param->dpte_group_bytes = 2048;
890 /*since pte request size is 64byte, the number of data pte requests per full sized group is as follows. */
891 log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
892 log2_dpte_group_length = log2_dpte_group_bytes - 6; /*length in 64b requests */
894 /* full sized data pte group width in elements */
896 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
898 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
900 dpte_group_width = 1 << log2_dpte_group_width;
902 /* since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
903 * the upper bound for the dpte groups per row is as follows.
905 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil(
906 (double) dpte_row_width_ub / dpte_group_width,
909 dml1_rq_dlg_get_row_heights(
911 &func_dpte_row_height,
912 &func_meta_row_height,
915 pipe_src_param.source_format,
916 pipe_src_param.sw_mode,
917 pipe_src_param.macro_tile_size,
918 pipe_src_param.source_scan,
921 /* Just a check to make sure this function and the new one give the same
922 * result. The standalone get_row_heights() function is based off of the
923 * code in this function so the same changes need to be made to both.
925 if (rq_dlg_param->meta_row_height != func_meta_row_height) {
927 "MISMATCH: rq_dlg_param->meta_row_height = %d",
928 rq_dlg_param->meta_row_height);
929 DTRACE("MISMATCH: func_meta_row_height = %d", func_meta_row_height);
933 if (rq_dlg_param->dpte_row_height != func_dpte_row_height) {
935 "MISMATCH: rq_dlg_param->dpte_row_height = %d",
936 rq_dlg_param->dpte_row_height);
937 DTRACE("MISMATCH: func_dpte_row_height = %d", func_dpte_row_height);
942 void dml1_rq_dlg_get_rq_params(
943 struct display_mode_lib *mode_lib,
944 struct _vcs_dpi_display_rq_params_st *rq_param,
945 const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param)
947 /* get param for luma surface */
948 rq_param->yuv420 = pipe_src_param.source_format == dm_420_8
949 || pipe_src_param.source_format == dm_420_10;
950 rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10;
954 &(rq_param->sizing.rq_l),
955 &(rq_param->dlg.rq_l),
956 &(rq_param->misc.rq_l),
960 if (is_dual_plane((enum source_format_class) pipe_src_param.source_format)) {
961 /* get param for chroma surface */
964 &(rq_param->sizing.rq_c),
965 &(rq_param->dlg.rq_c),
966 &(rq_param->misc.rq_c),
971 /* calculate how to split the det buffer space between luma and chroma */
972 handle_det_buf_split(mode_lib, rq_param, pipe_src_param);
973 print__rq_params_st(mode_lib, *rq_param);
976 /* Note: currently taken in as is.
977 * Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
979 void dml1_rq_dlg_get_dlg_params(
980 struct display_mode_lib *mode_lib,
981 struct _vcs_dpi_display_dlg_regs_st *disp_dlg_regs,
982 struct _vcs_dpi_display_ttu_regs_st *disp_ttu_regs,
983 const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
984 const struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
985 const struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
986 const bool cstate_en,
987 const bool pstate_en,
992 unsigned int htotal = e2e_pipe_param.pipe.dest.htotal;
993 unsigned int hblank_end = e2e_pipe_param.pipe.dest.hblank_end;
994 unsigned int vblank_start = e2e_pipe_param.pipe.dest.vblank_start;
995 unsigned int vblank_end = e2e_pipe_param.pipe.dest.vblank_end;
996 bool interlaced = e2e_pipe_param.pipe.dest.interlaced;
997 unsigned int min_vblank = mode_lib->ip.min_vblank_lines;
999 double pclk_freq_in_mhz = e2e_pipe_param.pipe.dest.pixel_rate_mhz;
1000 double refclk_freq_in_mhz = e2e_pipe_param.clks_cfg.refclk_mhz;
1001 double dppclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dppclk_mhz;
1002 double dispclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dispclk_mhz;
1004 double ref_freq_to_pix_freq;
1005 double prefetch_xy_calc_in_dcfclk;
1006 double min_dcfclk_mhz;
1008 double min_ttu_vblank;
1009 double min_dst_y_ttu_vblank;
1010 unsigned int dlg_vblank_start;
1014 unsigned int access_dir;
1015 unsigned int bytes_per_element_l;
1016 unsigned int bytes_per_element_c;
1017 unsigned int vp_height_l;
1018 unsigned int vp_width_l;
1019 unsigned int vp_height_c;
1020 unsigned int vp_width_c;
1021 unsigned int htaps_l;
1022 unsigned int htaps_c;
1027 double line_time_in_us;
1032 unsigned int swath_height_l;
1033 unsigned int swath_width_ub_l;
1034 unsigned int dpte_bytes_per_row_ub_l;
1035 unsigned int dpte_groups_per_row_ub_l;
1036 unsigned int meta_pte_bytes_per_frame_ub_l;
1037 unsigned int meta_bytes_per_row_ub_l;
1038 unsigned int swath_height_c;
1039 unsigned int swath_width_ub_c;
1040 unsigned int dpte_bytes_per_row_ub_c;
1041 unsigned int dpte_groups_per_row_ub_c;
1042 unsigned int meta_chunks_per_row_ub_l;
1043 unsigned int vupdate_offset;
1044 unsigned int vupdate_width;
1045 unsigned int vready_offset;
1046 unsigned int dppclk_delay_subtotal;
1047 unsigned int dispclk_delay_subtotal;
1048 unsigned int pixel_rate_delay_subtotal;
1049 unsigned int vstartup_start;
1050 unsigned int dst_x_after_scaler;
1051 unsigned int dst_y_after_scaler;
1056 double dst_y_prefetch;
1058 unsigned int vm_bytes;
1059 unsigned int meta_row_bytes;
1060 unsigned int max_num_sw_l;
1061 unsigned int max_num_sw_c;
1062 unsigned int max_partial_sw_l;
1063 unsigned int max_partial_sw_c;
1068 unsigned int sw_bytes_ub_l;
1069 unsigned int sw_bytes_ub_c;
1070 unsigned int sw_bytes;
1071 unsigned int dpte_row_bytes;
1076 double dst_y_per_vm_vblank;
1077 double dst_y_per_row_vblank;
1078 double min_dst_y_per_vm_vblank;
1079 double min_dst_y_per_row_vblank;
1081 double vratio_pre_l;
1082 double vratio_pre_c;
1083 unsigned int req_per_swath_ub_l;
1084 unsigned int req_per_swath_ub_c;
1085 unsigned int meta_row_height_l;
1086 unsigned int swath_width_pixels_ub_l;
1087 unsigned int swath_width_pixels_ub_c;
1088 unsigned int scaler_rec_in_width_l;
1089 unsigned int scaler_rec_in_width_c;
1090 unsigned int dpte_row_height_l;
1091 unsigned int dpte_row_height_c;
1092 double hscale_pixel_rate_l;
1093 double hscale_pixel_rate_c;
1094 double min_hratio_fact_l;
1095 double min_hratio_fact_c;
1096 double refcyc_per_line_delivery_pre_l;
1097 double refcyc_per_line_delivery_pre_c;
1098 double refcyc_per_line_delivery_l;
1099 double refcyc_per_line_delivery_c;
1100 double refcyc_per_req_delivery_pre_l;
1101 double refcyc_per_req_delivery_pre_c;
1102 double refcyc_per_req_delivery_l;
1103 double refcyc_per_req_delivery_c;
1104 double refcyc_per_req_delivery_pre_cur0;
1105 double refcyc_per_req_delivery_cur0;
1106 unsigned int full_recout_width;
1107 double hratios_cur0;
1108 unsigned int cur0_src_width;
1109 enum cursor_bpp cur0_bpp;
1110 unsigned int cur0_req_size;
1111 unsigned int cur0_req_width;
1112 double cur0_width_ub;
1113 double cur0_req_per_width;
1114 double hactive_cur0;
1116 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
1117 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
1119 DTRACE("DLG: %s: cstate_en = %d", __func__, cstate_en);
1120 DTRACE("DLG: %s: pstate_en = %d", __func__, pstate_en);
1121 DTRACE("DLG: %s: vm_en = %d", __func__, vm_en);
1122 DTRACE("DLG: %s: iflip_en = %d", __func__, iflip_en);
1124 /* ------------------------- */
1125 /* Section 1.5.2.1: OTG dependent Params */
1126 /* ------------------------- */
1127 DTRACE("DLG: %s: dppclk_freq_in_mhz = %3.2f", __func__, dppclk_freq_in_mhz);
1128 DTRACE("DLG: %s: dispclk_freq_in_mhz = %3.2f", __func__, dispclk_freq_in_mhz);
1129 DTRACE("DLG: %s: refclk_freq_in_mhz = %3.2f", __func__, refclk_freq_in_mhz);
1130 DTRACE("DLG: %s: pclk_freq_in_mhz = %3.2f", __func__, pclk_freq_in_mhz);
1131 DTRACE("DLG: %s: interlaced = %d", __func__, interlaced);
1133 ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
1134 ASSERT(ref_freq_to_pix_freq < 4.0);
1135 disp_dlg_regs->ref_freq_to_pix_freq =
1136 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
1137 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
1139 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end
1140 * (double) ref_freq_to_pix_freq);
1141 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));
1142 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; /* 15 bits */
1144 prefetch_xy_calc_in_dcfclk = 24.0; /* FIXME: ip_param */
1145 min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
1146 t_calc_us = prefetch_xy_calc_in_dcfclk / min_dcfclk_mhz;
1147 min_ttu_vblank = dlg_sys_param.t_urg_wm_us;
1149 min_ttu_vblank = dml_max(dlg_sys_param.t_sr_wm_us, min_ttu_vblank);
1151 min_ttu_vblank = dml_max(dlg_sys_param.t_mclk_wm_us, min_ttu_vblank);
1152 min_ttu_vblank = min_ttu_vblank + t_calc_us;
1154 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
1155 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
1157 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start
1158 + min_dst_y_ttu_vblank) * dml_pow(2, 2));
1159 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
1161 DTRACE("DLG: %s: min_dcfclk_mhz = %3.2f", __func__, min_dcfclk_mhz);
1162 DTRACE("DLG: %s: min_ttu_vblank = %3.2f", __func__, min_ttu_vblank);
1164 "DLG: %s: min_dst_y_ttu_vblank = %3.2f",
1166 min_dst_y_ttu_vblank);
1167 DTRACE("DLG: %s: t_calc_us = %3.2f", __func__, t_calc_us);
1169 "DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x",
1171 disp_dlg_regs->min_dst_y_next_start);
1173 "DLG: %s: ref_freq_to_pix_freq = %3.2f",
1175 ref_freq_to_pix_freq);
1177 /* ------------------------- */
1178 /* Section 1.5.2.2: Prefetch, Active and TTU */
1179 /* ------------------------- */
1182 dcc_en = e2e_pipe_param.pipe.src.dcc;
1183 dual_plane = is_dual_plane(
1184 (enum source_format_class) e2e_pipe_param.pipe.src.source_format);
1185 mode_422 = 0; /* FIXME */
1186 access_dir = (e2e_pipe_param.pipe.src.source_scan == dm_vert); /* vp access direction: horizontal or vertical accessed */
1187 bytes_per_element_l = get_bytes_per_element(
1188 (enum source_format_class) e2e_pipe_param.pipe.src.source_format,
1190 bytes_per_element_c = get_bytes_per_element(
1191 (enum source_format_class) e2e_pipe_param.pipe.src.source_format,
1193 vp_height_l = e2e_pipe_param.pipe.src.viewport_height;
1194 vp_width_l = e2e_pipe_param.pipe.src.viewport_width;
1195 vp_height_c = e2e_pipe_param.pipe.src.viewport_height_c;
1196 vp_width_c = e2e_pipe_param.pipe.src.viewport_width_c;
1199 htaps_l = e2e_pipe_param.pipe.scale_taps.htaps;
1200 htaps_c = e2e_pipe_param.pipe.scale_taps.htaps_c;
1201 hratios_l = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio;
1202 hratios_c = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio_c;
1203 vratio_l = e2e_pipe_param.pipe.scale_ratio_depth.vscl_ratio;
1204 vratio_c = e2e_pipe_param.pipe.scale_ratio_depth.vscl_ratio_c;
1206 line_time_in_us = (htotal / pclk_freq_in_mhz);
1207 vinit_l = e2e_pipe_param.pipe.scale_ratio_depth.vinit;
1208 vinit_c = e2e_pipe_param.pipe.scale_ratio_depth.vinit_c;
1209 vinit_bot_l = e2e_pipe_param.pipe.scale_ratio_depth.vinit_bot;
1210 vinit_bot_c = e2e_pipe_param.pipe.scale_ratio_depth.vinit_bot_c;
1212 swath_height_l = rq_dlg_param.rq_l.swath_height;
1213 swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
1214 dpte_bytes_per_row_ub_l = rq_dlg_param.rq_l.dpte_bytes_per_row_ub;
1215 dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;
1216 meta_pte_bytes_per_frame_ub_l = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub;
1217 meta_bytes_per_row_ub_l = rq_dlg_param.rq_l.meta_bytes_per_row_ub;
1219 swath_height_c = rq_dlg_param.rq_c.swath_height;
1220 swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
1221 dpte_bytes_per_row_ub_c = rq_dlg_param.rq_c.dpte_bytes_per_row_ub;
1222 dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;
1224 meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;
1225 vupdate_offset = e2e_pipe_param.pipe.dest.vupdate_offset;
1226 vupdate_width = e2e_pipe_param.pipe.dest.vupdate_width;
1227 vready_offset = e2e_pipe_param.pipe.dest.vready_offset;
1229 dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
1230 dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
1231 pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz
1232 + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz;
1234 vstartup_start = e2e_pipe_param.pipe.dest.vstartup_start;
1237 vstartup_start = vstartup_start / 2;
1239 if (vstartup_start >= min_vblank) {
1241 "WARNING_DLG: %s: vblank_start=%d vblank_end=%d",
1246 "WARNING_DLG: %s: vstartup_start=%d should be less than min_vblank=%d",
1250 min_vblank = vstartup_start + 1;
1252 "WARNING_DLG: %s: vstartup_start=%d should be less than min_vblank=%d",
1258 dst_x_after_scaler = 0;
1259 dst_y_after_scaler = 0;
1261 if (e2e_pipe_param.pipe.src.is_hsplit)
1262 dst_x_after_scaler = pixel_rate_delay_subtotal
1263 + e2e_pipe_param.pipe.dest.recout_width;
1265 dst_x_after_scaler = pixel_rate_delay_subtotal;
1267 if (e2e_pipe_param.dout.output_format == dm_420)
1268 dst_y_after_scaler = 1;
1270 dst_y_after_scaler = 0;
1272 if (dst_x_after_scaler >= htotal) {
1273 dst_x_after_scaler = dst_x_after_scaler - htotal;
1274 dst_y_after_scaler = dst_y_after_scaler + 1;
1277 DTRACE("DLG: %s: htotal = %d", __func__, htotal);
1279 "DLG: %s: pixel_rate_delay_subtotal = %d",
1281 pixel_rate_delay_subtotal);
1282 DTRACE("DLG: %s: dst_x_after_scaler = %d", __func__, dst_x_after_scaler);
1283 DTRACE("DLG: %s: dst_y_after_scaler = %d", __func__, dst_y_after_scaler);
1285 line_wait = mode_lib->soc.urgent_latency_us;
1287 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
1289 line_wait = dml_max(
1290 mode_lib->soc.dram_clock_change_latency_us
1291 + mode_lib->soc.urgent_latency_us,
1293 line_wait = line_wait / line_time_in_us;
1295 line_o = (double) dst_y_after_scaler + dst_x_after_scaler / (double) htotal;
1296 line_setup = (double) (vupdate_offset + vupdate_width + vready_offset) / (double) htotal;
1297 line_calc = t_calc_us / line_time_in_us;
1300 "DLG: %s: soc.sr_enter_plus_exit_time_us = %3.2f",
1302 (double) mode_lib->soc.sr_enter_plus_exit_time_us);
1304 "DLG: %s: soc.dram_clock_change_latency_us = %3.2f",
1306 (double) mode_lib->soc.dram_clock_change_latency_us);
1308 "DLG: %s: soc.urgent_latency_us = %3.2f",
1310 mode_lib->soc.urgent_latency_us);
1312 DTRACE("DLG: %s: swath_height_l = %d", __func__, swath_height_l);
1314 DTRACE("DLG: %s: swath_height_c = %d", __func__, swath_height_c);
1317 "DLG: %s: t_srx_delay_us = %3.2f",
1319 (double) dlg_sys_param.t_srx_delay_us);
1320 DTRACE("DLG: %s: line_time_in_us = %3.2f", __func__, (double) line_time_in_us);
1321 DTRACE("DLG: %s: vupdate_offset = %d", __func__, vupdate_offset);
1322 DTRACE("DLG: %s: vupdate_width = %d", __func__, vupdate_width);
1323 DTRACE("DLG: %s: vready_offset = %d", __func__, vready_offset);
1324 DTRACE("DLG: %s: line_time_in_us = %3.2f", __func__, line_time_in_us);
1325 DTRACE("DLG: %s: line_wait = %3.2f", __func__, line_wait);
1326 DTRACE("DLG: %s: line_o = %3.2f", __func__, line_o);
1327 DTRACE("DLG: %s: line_setup = %3.2f", __func__, line_setup);
1328 DTRACE("DLG: %s: line_calc = %3.2f", __func__, line_calc);
1330 dst_y_prefetch = ((double) min_vblank - 1.0)
1331 - (line_setup + line_calc + line_wait + line_o);
1332 DTRACE("DLG: %s: dst_y_prefetch (before rnd) = %3.2f", __func__, dst_y_prefetch);
1333 ASSERT(dst_y_prefetch >= 2.0);
1335 dst_y_prefetch = dml_floor(4.0 * (dst_y_prefetch + 0.125), 1) / 4;
1336 DTRACE("DLG: %s: dst_y_prefetch (after rnd) = %3.2f", __func__, dst_y_prefetch);
1338 t_pre_us = dst_y_prefetch * line_time_in_us;
1342 if (dcc_en && vm_en)
1343 vm_bytes = meta_pte_bytes_per_frame_ub_l;
1345 meta_row_bytes = meta_bytes_per_row_ub_l;
1349 max_partial_sw_l = 0;
1350 max_partial_sw_c = 0;
1352 max_vinit_l = interlaced ? dml_max(vinit_l, vinit_bot_l) : vinit_l;
1353 max_vinit_c = interlaced ? dml_max(vinit_c, vinit_bot_c) : vinit_c;
1355 get_swath_need(mode_lib, &max_num_sw_l, &max_partial_sw_l, swath_height_l, max_vinit_l);
1364 lsw_l = max_num_sw_l * swath_height_l + max_partial_sw_l;
1365 lsw_c = max_num_sw_c * swath_height_c + max_partial_sw_c;
1366 sw_bytes_ub_l = lsw_l * swath_width_ub_l * bytes_per_element_l;
1367 sw_bytes_ub_c = lsw_c * swath_width_ub_c * bytes_per_element_c;
1373 dpte_row_bytes = dpte_bytes_per_row_ub_l + dpte_bytes_per_row_ub_c;
1375 dpte_row_bytes = dpte_bytes_per_row_ub_l;
1381 sw_bytes = sw_bytes_ub_l + sw_bytes_ub_c;
1383 sw_bytes = sw_bytes_ub_l;
1385 DTRACE("DLG: %s: sw_bytes_ub_l = %d", __func__, sw_bytes_ub_l);
1386 DTRACE("DLG: %s: sw_bytes_ub_c = %d", __func__, sw_bytes_ub_c);
1387 DTRACE("DLG: %s: sw_bytes = %d", __func__, sw_bytes);
1388 DTRACE("DLG: %s: vm_bytes = %d", __func__, vm_bytes);
1389 DTRACE("DLG: %s: meta_row_bytes = %d", __func__, meta_row_bytes);
1390 DTRACE("DLG: %s: dpte_row_bytes = %d", __func__, dpte_row_bytes);
1392 prefetch_bw = (vm_bytes + 2 * dpte_row_bytes + 2 * meta_row_bytes + sw_bytes) / t_pre_us;
1393 flip_bw = ((vm_bytes + dpte_row_bytes + meta_row_bytes) * dlg_sys_param.total_flip_bw)
1394 / (double) dlg_sys_param.total_flip_bytes;
1395 t_vm_us = line_time_in_us / 4.0;
1396 if (vm_en && dcc_en) {
1398 dlg_sys_param.t_extra_us,
1399 dml_max((double) vm_bytes / prefetch_bw, t_vm_us));
1401 if (iflip_en && !dual_plane) {
1402 t_vm_us = dml_max(mode_lib->soc.urgent_latency_us, t_vm_us);
1404 t_vm_us = dml_max(vm_bytes / flip_bw, t_vm_us);
1408 t_r0_us = dml_max(dlg_sys_param.t_extra_us - t_vm_us, line_time_in_us - t_vm_us);
1410 if (vm_en || dcc_en) {
1412 (double) (dpte_row_bytes + meta_row_bytes) / prefetch_bw,
1413 dlg_sys_param.t_extra_us);
1414 t_r0_us = dml_max((double) (line_time_in_us - t_vm_us), t_r0_us);
1416 if (iflip_en && !dual_plane) {
1417 t_r0_us = dml_max(mode_lib->soc.urgent_latency_us * 2.0, t_r0_us);
1420 (dpte_row_bytes + meta_row_bytes) / flip_bw,
1425 disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; /* in terms of line */
1426 disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; /* in terms of refclk */
1427 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));
1429 "DLG: %s: disp_dlg_regs->dst_y_after_scaler = 0x%0x",
1431 disp_dlg_regs->dst_y_after_scaler);
1433 "DLG: %s: disp_dlg_regs->refcyc_x_after_scaler = 0x%0x",
1435 disp_dlg_regs->refcyc_x_after_scaler);
1437 disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
1439 "DLG: %s: disp_dlg_regs->dst_y_prefetch = %d",
1441 disp_dlg_regs->dst_y_prefetch);
1443 dst_y_per_vm_vblank = 0.0;
1444 dst_y_per_row_vblank = 0.0;
1446 dst_y_per_vm_vblank = t_vm_us / line_time_in_us;
1447 dst_y_per_vm_vblank = dml_floor(4.0 * (dst_y_per_vm_vblank + 0.125), 1) / 4.0;
1448 disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
1450 dst_y_per_row_vblank = t_r0_us / line_time_in_us;
1451 dst_y_per_row_vblank = dml_floor(4.0 * (dst_y_per_row_vblank + 0.125), 1) / 4.0;
1452 disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
1454 DTRACE("DLG: %s: lsw_l = %d", __func__, lsw_l);
1455 DTRACE("DLG: %s: lsw_c = %d", __func__, lsw_c);
1456 DTRACE("DLG: %s: dpte_bytes_per_row_ub_l = %d", __func__, dpte_bytes_per_row_ub_l);
1457 DTRACE("DLG: %s: dpte_bytes_per_row_ub_c = %d", __func__, dpte_bytes_per_row_ub_c);
1459 DTRACE("DLG: %s: prefetch_bw = %3.2f", __func__, prefetch_bw);
1460 DTRACE("DLG: %s: flip_bw = %3.2f", __func__, flip_bw);
1461 DTRACE("DLG: %s: t_pre_us = %3.2f", __func__, t_pre_us);
1462 DTRACE("DLG: %s: t_vm_us = %3.2f", __func__, t_vm_us);
1463 DTRACE("DLG: %s: t_r0_us = %3.2f", __func__, t_r0_us);
1464 DTRACE("DLG: %s: dst_y_per_vm_vblank = %3.2f", __func__, dst_y_per_vm_vblank);
1465 DTRACE("DLG: %s: dst_y_per_row_vblank = %3.2f", __func__, dst_y_per_row_vblank);
1466 DTRACE("DLG: %s: dst_y_prefetch = %3.2f", __func__, dst_y_prefetch);
1468 min_dst_y_per_vm_vblank = 8.0;
1469 min_dst_y_per_row_vblank = 16.0;
1472 min_dst_y_per_vm_vblank = 100.0;
1473 min_dst_y_per_row_vblank = 100.0;
1476 ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank);
1477 ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank);
1479 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
1480 lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank);
1482 DTRACE("DLG: %s: lsw = %3.2f", __func__, lsw);
1484 vratio_pre_l = get_vratio_pre(
1493 vratio_pre_c = get_vratio_pre(
1501 DTRACE("DLG: %s: vratio_pre_l=%3.2f", __func__, vratio_pre_l);
1502 DTRACE("DLG: %s: vratio_pre_c=%3.2f", __func__, vratio_pre_c);
1504 ASSERT(vratio_pre_l <= 4.0);
1505 if (vratio_pre_l >= 4.0)
1506 disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 21) - 1;
1508 disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
1510 ASSERT(vratio_pre_c <= 4.0);
1511 if (vratio_pre_c >= 4.0)
1512 disp_dlg_regs->vratio_prefetch_c = (unsigned int) dml_pow(2, 21) - 1;
1514 disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
1516 disp_dlg_regs->refcyc_per_pte_group_vblank_l =
1517 (unsigned int) (dst_y_per_row_vblank * (double) htotal
1518 * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
1519 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));
1521 disp_dlg_regs->refcyc_per_pte_group_vblank_c =
1522 (unsigned int) (dst_y_per_row_vblank * (double) htotal
1523 * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c);
1524 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13));
1526 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
1527 (unsigned int) (dst_y_per_row_vblank * (double) htotal
1528 * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
1529 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));
1531 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c =
1532 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;/* dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now */
1535 req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;
1536 req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;
1537 meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;
1538 swath_width_pixels_ub_l = 0;
1539 swath_width_pixels_ub_c = 0;
1540 scaler_rec_in_width_l = 0;
1541 scaler_rec_in_width_c = 0;
1542 dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
1543 dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
1545 disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l
1546 / (double) vratio_l * dml_pow(2, 2));
1547 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));
1549 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c
1550 / (double) vratio_c * dml_pow(2, 2));
1551 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_c < (unsigned int) dml_pow(2, 17));
1553 disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
1554 / (double) vratio_l * dml_pow(2, 2));
1555 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));
1557 disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; /* dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now */
1559 disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l
1560 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
1561 / (double) dpte_groups_per_row_ub_l);
1562 if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
1563 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
1565 disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c
1566 / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq
1567 / (double) dpte_groups_per_row_ub_c);
1568 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
1569 disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
1571 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l
1572 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
1573 / (double) meta_chunks_per_row_ub_l);
1574 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
1575 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
1578 swath_width_pixels_ub_l = swath_width_ub_l * 2; /* *2 for 2 pixel per element */
1579 swath_width_pixels_ub_c = swath_width_ub_c * 2;
1581 swath_width_pixels_ub_l = swath_width_ub_l * 1;
1582 swath_width_pixels_ub_c = swath_width_ub_c * 1;
1585 hscale_pixel_rate_l = 0.;
1586 hscale_pixel_rate_c = 0.;
1587 min_hratio_fact_l = 1.0;
1588 min_hratio_fact_c = 1.0;
1591 min_hratio_fact_l = 2.0;
1592 else if (htaps_l <= 6) {
1593 if ((hratios_l * 2.0) > 4.0)
1594 min_hratio_fact_l = 4.0;
1596 min_hratio_fact_l = hratios_l * 2.0;
1598 if (hratios_l > 4.0)
1599 min_hratio_fact_l = 4.0;
1601 min_hratio_fact_l = hratios_l;
1604 hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
1607 min_hratio_fact_c = 2.0;
1608 else if (htaps_c <= 6) {
1609 if ((hratios_c * 2.0) > 4.0)
1610 min_hratio_fact_c = 4.0;
1612 min_hratio_fact_c = hratios_c * 2.0;
1614 if (hratios_c > 4.0)
1615 min_hratio_fact_c = 4.0;
1617 min_hratio_fact_c = hratios_c;
1620 hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
1622 refcyc_per_line_delivery_pre_l = 0.;
1623 refcyc_per_line_delivery_pre_c = 0.;
1624 refcyc_per_line_delivery_l = 0.;
1625 refcyc_per_line_delivery_c = 0.;
1627 refcyc_per_req_delivery_pre_l = 0.;
1628 refcyc_per_req_delivery_pre_c = 0.;
1629 refcyc_per_req_delivery_l = 0.;
1630 refcyc_per_req_delivery_c = 0.;
1631 refcyc_per_req_delivery_pre_cur0 = 0.;
1632 refcyc_per_req_delivery_cur0 = 0.;
1634 full_recout_width = 0;
1635 if (e2e_pipe_param.pipe.src.is_hsplit) {
1636 if (e2e_pipe_param.pipe.dest.full_recout_width == 0) {
1637 DTRACE("DLG: %s: Warningfull_recout_width not set in hsplit mode", __func__);
1638 full_recout_width = e2e_pipe_param.pipe.dest.recout_width * 2; /* assume half split for dcn1 */
1640 full_recout_width = e2e_pipe_param.pipe.dest.full_recout_width;
1642 full_recout_width = e2e_pipe_param.pipe.dest.recout_width;
1644 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(
1650 hscale_pixel_rate_l,
1651 swath_width_pixels_ub_l,
1654 refcyc_per_line_delivery_l = get_refcyc_per_delivery(
1660 hscale_pixel_rate_l,
1661 swath_width_pixels_ub_l,
1664 DTRACE("DLG: %s: full_recout_width = %d", __func__, full_recout_width);
1665 DTRACE("DLG: %s: hscale_pixel_rate_l = %3.2f", __func__, hscale_pixel_rate_l);
1667 "DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f",
1669 refcyc_per_line_delivery_pre_l);
1671 "DLG: %s: refcyc_per_line_delivery_l = %3.2f",
1673 refcyc_per_line_delivery_l);
1675 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(
1676 refcyc_per_line_delivery_pre_l,
1678 disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(
1679 refcyc_per_line_delivery_l,
1681 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));
1682 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));
1685 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(
1691 hscale_pixel_rate_c,
1692 swath_width_pixels_ub_c,
1695 refcyc_per_line_delivery_c = get_refcyc_per_delivery(
1701 hscale_pixel_rate_c,
1702 swath_width_pixels_ub_c,
1706 "DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f",
1708 refcyc_per_line_delivery_pre_c);
1710 "DLG: %s: refcyc_per_line_delivery_c = %3.2f",
1712 refcyc_per_line_delivery_c);
1714 disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(
1715 refcyc_per_line_delivery_pre_c,
1717 disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(
1718 refcyc_per_line_delivery_c,
1720 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));
1721 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));
1723 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
1725 /* TTU - Luma / Chroma */
1726 if (access_dir) { /* vertical access */
1727 scaler_rec_in_width_l = vp_height_l;
1728 scaler_rec_in_width_c = vp_height_c;
1730 scaler_rec_in_width_l = vp_width_l;
1731 scaler_rec_in_width_c = vp_width_c;
1734 refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(
1740 hscale_pixel_rate_l,
1741 scaler_rec_in_width_l,
1742 req_per_swath_ub_l); /* per req */
1743 refcyc_per_req_delivery_l = get_refcyc_per_delivery(
1749 hscale_pixel_rate_l,
1750 scaler_rec_in_width_l,
1751 req_per_swath_ub_l); /* per req */
1754 "DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f",
1756 refcyc_per_req_delivery_pre_l);
1758 "DLG: %s: refcyc_per_req_delivery_l = %3.2f",
1760 refcyc_per_req_delivery_l);
1762 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l
1764 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l
1767 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
1768 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
1771 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(
1777 hscale_pixel_rate_c,
1778 scaler_rec_in_width_c,
1779 req_per_swath_ub_c); /* per req */
1780 refcyc_per_req_delivery_c = get_refcyc_per_delivery(
1786 hscale_pixel_rate_c,
1787 scaler_rec_in_width_c,
1788 req_per_swath_ub_c); /* per req */
1791 "DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f",
1793 refcyc_per_req_delivery_pre_c);
1795 "DLG: %s: refcyc_per_req_delivery_c = %3.2f",
1797 refcyc_per_req_delivery_c);
1799 disp_ttu_regs->refcyc_per_req_delivery_pre_c =
1800 (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));
1801 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c
1804 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
1805 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
1809 hratios_cur0 = e2e_pipe_param.pipe.scale_ratio_depth.hscl_ratio;
1810 cur0_src_width = e2e_pipe_param.pipe.src.cur0_src_width; /* cursor source width */
1811 cur0_bpp = (enum cursor_bpp) e2e_pipe_param.pipe.src.cur0_bpp;
1814 cur0_width_ub = 0.0;
1815 cur0_req_per_width = 0.0;
1818 ASSERT(cur0_src_width <= 256);
1820 if (cur0_src_width > 0) {
1821 unsigned int cur0_bit_per_pixel = 0;
1823 if (cur0_bpp == dm_cur_2bit) {
1824 cur0_req_size = 64; /* byte */
1825 cur0_bit_per_pixel = 2;
1826 } else { /* 32bit */
1827 cur0_bit_per_pixel = 32;
1828 if (cur0_src_width >= 1 && cur0_src_width <= 16)
1830 else if (cur0_src_width >= 17 && cur0_src_width <= 31)
1831 cur0_req_size = 128;
1833 cur0_req_size = 256;
1836 cur0_req_width = (double) cur0_req_size / ((double) cur0_bit_per_pixel / 8.0);
1837 cur0_width_ub = dml_ceil((double) cur0_src_width / (double) cur0_req_width, 1)
1838 * (double) cur0_req_width;
1839 cur0_req_per_width = cur0_width_ub / (double) cur0_req_width;
1840 hactive_cur0 = (double) cur0_src_width / hratios_cur0; /* FIXME: oswin to think about what to do for cursor */
1842 if (vratio_pre_l <= 1.0) {
1843 refcyc_per_req_delivery_pre_cur0 = hactive_cur0 * ref_freq_to_pix_freq
1844 / (double) cur0_req_per_width;
1846 refcyc_per_req_delivery_pre_cur0 = (double) refclk_freq_in_mhz
1847 * (double) cur0_src_width / hscale_pixel_rate_l
1848 / (double) cur0_req_per_width;
1851 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 =
1852 (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
1853 ASSERT(refcyc_per_req_delivery_pre_cur0 < dml_pow(2, 13));
1855 if (vratio_l <= 1.0) {
1856 refcyc_per_req_delivery_cur0 = hactive_cur0 * ref_freq_to_pix_freq
1857 / (double) cur0_req_per_width;
1859 refcyc_per_req_delivery_cur0 = (double) refclk_freq_in_mhz
1860 * (double) cur0_src_width / hscale_pixel_rate_l
1861 / (double) cur0_req_per_width;
1864 DTRACE("DLG: %s: cur0_req_width = %d", __func__, cur0_req_width);
1866 "DLG: %s: cur0_width_ub = %3.2f",
1870 "DLG: %s: cur0_req_per_width = %3.2f",
1872 cur0_req_per_width);
1874 "DLG: %s: hactive_cur0 = %3.2f",
1878 "DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f",
1880 refcyc_per_req_delivery_pre_cur0);
1882 "DLG: %s: refcyc_per_req_delivery_cur0 = %3.2f",
1884 refcyc_per_req_delivery_cur0);
1886 disp_ttu_regs->refcyc_per_req_delivery_cur0 =
1887 (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));
1888 ASSERT(refcyc_per_req_delivery_cur0 < dml_pow(2, 13));
1890 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = 0;
1891 disp_ttu_regs->refcyc_per_req_delivery_cur0 = 0;
1895 disp_ttu_regs->qos_level_low_wm = 0;
1896 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
1897 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
1898 * ref_freq_to_pix_freq);
1899 ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
1901 disp_ttu_regs->qos_level_flip = 14;
1902 disp_ttu_regs->qos_level_fixed_l = 8;
1903 disp_ttu_regs->qos_level_fixed_c = 8;
1904 disp_ttu_regs->qos_level_fixed_cur0 = 8;
1905 disp_ttu_regs->qos_ramp_disable_l = 0;
1906 disp_ttu_regs->qos_ramp_disable_c = 0;
1907 disp_ttu_regs->qos_ramp_disable_cur0 = 0;
1909 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
1910 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
1912 print__ttu_regs_st(mode_lib, *disp_ttu_regs);
1913 print__dlg_regs_st(mode_lib, *disp_dlg_regs);