2 * Copyright 2017 Advanced Micro Devices, Inc.
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26 #ifndef DM_PP_SMU_IF__H
27 #define DM_PP_SMU_IF__H
30 * interface to PPLIB/SMU to setup clocks and pstate requirements on SoC
35 struct dc_context *ctx;
46 struct pp_smu_wm_set_range {
47 enum wm_set_id wm_inst;
48 uint32_t min_fill_clk_khz;
49 uint32_t max_fill_clk_khz;
50 uint32_t min_drain_clk_khz;
51 uint32_t max_drain_clk_khz;
54 struct pp_smu_wm_range_sets {
55 uint32_t num_reader_wm_sets;
56 struct pp_smu_wm_set_range reader_wm_sets[WM_SET_COUNT];
58 uint32_t num_writer_wm_sets;
59 struct pp_smu_wm_set_range writer_wm_sets[WM_SET_COUNT];
62 struct pp_smu_display_requirement_rv {
63 /* PPSMC_MSG_SetDisplayCount: count
64 * 0 triggers S0i2 optimization
66 unsigned int display_count;
68 /* PPSMC_MSG_SetHardMinFclkByFreq: khz
69 * FCLK will vary with DPM, but never below requested hard min
71 unsigned int hard_min_fclk_khz;
73 /* PPSMC_MSG_SetHardMinDcefclkByFreq: khz
74 * fixed clock at requested freq, either from FCH bypass or DFS
76 unsigned int hard_min_dcefclk_khz;
78 /* PPSMC_MSG_SetMinDeepSleepDcefclk: mhz
79 * when DF is in cstate, dcf clock is further divided down
80 * to just above given frequency
82 unsigned int min_deep_sleep_dcefclk_mhz;
85 struct pp_smu_funcs_rv {
88 void (*set_display_requirement)(struct pp_smu *pp,
89 struct pp_smu_display_requirement_rv *req);
91 /* which SMU message? are reader and writer WM separate SMU msg? */
92 void (*set_wm_ranges)(struct pp_smu *pp,
93 struct pp_smu_wm_range_sets *ranges);
95 void (*set_pme_wa_enable)(struct pp_smu *pp);
99 struct pp_smu_funcs_rv {
101 /* PPSMC_MSG_SetDisplayCount
102 * 0 triggers S0i2 optimization
104 void (*set_display_count)(struct pp_smu *pp, int count);
106 /* PPSMC_MSG_SetHardMinFclkByFreq
107 * FCLK will vary with DPM, but never below requested hard min
109 void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int khz);
111 /* PPSMC_MSG_SetHardMinDcefclkByFreq
112 * fixed clock at requested freq, either from FCH bypass or DFS
114 void (*set_hard_min_dcefclk_by_freq)(struct pp_smu *pp, int khz);
116 /* PPSMC_MSG_SetMinDeepSleepDcefclk
117 * when DF is in cstate, dcf clock is further divided down
118 * to just above given frequency
120 void (*set_min_deep_sleep_dcefclk)(struct pp_smu *pp, int mhz);
123 * watermark range table
126 /* todo: functional/feature
127 * PPSMC_MSG_SetHardMinSocclkByFreq: required to support DWB
132 #endif /* DM_PP_SMU_IF__H */