drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dc.h"
  28
  29 #include "resource.h"
  30 #include "include/irq_service_interface.h"
  31 #include "dcn10/dcn10_resource.h"
  32
  33 #include "dcn10/dcn10_ipp.h"
  34 #include "dcn10/dcn10_mpc.h"
  35 #include "irq/dcn10/irq_service_dcn10.h"
  36 #include "dcn10/dcn10_dpp.h"
  37 #include "dcn10_optc.h"
  38 #include "dcn10/dcn10_hw_sequencer.h"
  39 #include "dce110/dce110_hw_sequencer.h"
  40 #include "dcn10/dcn10_opp.h"
  41 #include "dcn10/dcn10_link_encoder.h"
  42 #include "dcn10/dcn10_stream_encoder.h"
  43 #include "dce/dce_clocks.h"
  44 #include "dce/dce_clock_source.h"
  45 #include "dce/dce_audio.h"
  46 #include "dce/dce_hwseq.h"
  47 #include "../virtual/virtual_stream_encoder.h"
  48 #include "dce110/dce110_resource.h"
  49 #include "dce112/dce112_resource.h"
  50 #include "dcn10_hubp.h"
  51 #include "dcn10_hubbub.h"
  52
  53 #include "soc15_hw_ip.h"
  54 #include "vega10_ip_offset.h"
  55
  56 #include "dcn/dcn_1_0_offset.h"
  57 #include "dcn/dcn_1_0_sh_mask.h"
  58
  59 #include "nbio/nbio_7_0_offset.h"
  60
  61 #include "mmhub/mmhub_9_1_offset.h"
  62 #include "mmhub/mmhub_9_1_sh_mask.h"
  63
  64 #include "reg_helper.h"
  65 #include "dce/dce_abm.h"
  66 #include "dce/dce_dmcu.h"
  67 #include "dce/dce_aux.h"
  68
  69 const struct _vcs_dpi_ip_params_st dcn1_0_ip = {
  70         .rob_buffer_size_kbytes = 64,
  71         .det_buffer_size_kbytes = 164,
  72         .dpte_buffer_size_in_pte_reqs = 42,
  73         .dpp_output_buffer_pixels = 2560,
  74         .opp_output_buffer_lines = 1,
  75         .pixel_chunk_size_kbytes = 8,
  76         .pte_enable = 1,
  77         .pte_chunk_size_kbytes = 2,
  78         .meta_chunk_size_kbytes = 2,
  79         .writeback_chunk_size_kbytes = 2,
  80         .line_buffer_size_bits = 589824,
  81         .max_line_buffer_lines = 12,
  82         .IsLineBufferBppFixed = 0,
  83         .LineBufferFixedBpp = -1,
  84         .writeback_luma_buffer_size_kbytes = 12,
  85         .writeback_chroma_buffer_size_kbytes = 8,
  86         .max_num_dpp = 4,
  87         .max_num_wb = 2,
  88         .max_dchub_pscl_bw_pix_per_clk = 4,
  89         .max_pscl_lb_bw_pix_per_clk = 2,
  90         .max_lb_vscl_bw_pix_per_clk = 4,
  91         .max_vscl_hscl_bw_pix_per_clk = 4,
  92         .max_hscl_ratio = 4,
  93         .max_vscl_ratio = 4,
  94         .hscl_mults = 4,
  95         .vscl_mults = 4,
  96         .max_hscl_taps = 8,
  97         .max_vscl_taps = 8,
  98         .dispclk_ramp_margin_percent = 1,
  99         .underscan_factor = 1.10,
 100         .min_vblank_lines = 14,
 101         .dppclk_delay_subtotal = 90,
 102         .dispclk_delay_subtotal = 42,
 103         .dcfclk_cstate_latency = 10,
 104         .max_inter_dcn_tile_repeaters = 8,
 105         .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0,
 106         .bug_forcing_LC_req_same_size_fixed = 0,
 107 };
 108
 109 const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = {
 110         .sr_exit_time_us = 9.0,
 111         .sr_enter_plus_exit_time_us = 11.0,
 112         .urgent_latency_us = 4.0,
 113         .writeback_latency_us = 12.0,
 114         .ideal_dram_bw_after_urgent_percent = 80.0,
 115         .max_request_size_bytes = 256,
 116         .downspread_percent = 0.5,
 117         .dram_page_open_time_ns = 50.0,
 118         .dram_rw_turnaround_time_ns = 17.5,
 119         .dram_return_buffer_per_channel_bytes = 8192,
 120         .round_trip_ping_latency_dcfclk_cycles = 128,
 121         .urgent_out_of_order_return_per_channel_bytes = 256,
 122         .channel_interleave_bytes = 256,
 123         .num_banks = 8,
 124         .num_chans = 2,
 125         .vmm_page_size_bytes = 4096,
 126         .dram_clock_change_latency_us = 17.0,
 127         .writeback_dram_clock_change_latency_us = 23.0,
 128         .return_bus_width_bytes = 64,
 129 };
 130
 131 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
 132         #define mmDP0_DP_DPHY_INTERNAL_CTRL             0x210f
 133         #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 134         #define mmDP1_DP_DPHY_INTERNAL_CTRL             0x220f
 135         #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 136         #define mmDP2_DP_DPHY_INTERNAL_CTRL             0x230f
 137         #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 138         #define mmDP3_DP_DPHY_INTERNAL_CTRL             0x240f
 139         #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 140         #define mmDP4_DP_DPHY_INTERNAL_CTRL             0x250f
 141         #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 142         #define mmDP5_DP_DPHY_INTERNAL_CTRL             0x260f
 143         #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 144         #define mmDP6_DP_DPHY_INTERNAL_CTRL             0x270f
 145         #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 146 #endif
 147
 148
 149 enum dcn10_clk_src_array_id {
 150         DCN10_CLK_SRC_PLL0,
 151         DCN10_CLK_SRC_PLL1,
 152         DCN10_CLK_SRC_PLL2,
 153         DCN10_CLK_SRC_PLL3,
 154         DCN10_CLK_SRC_TOTAL
 155 };
 156
 157 /* begin *********************
 158  * macros to expend register list macro defined in HW object header file */
 159
 160 /* DCN */
 161 #define BASE_INNER(seg) \
 162         DCE_BASE__INST0_SEG ## seg
 163
 164 #define BASE(seg) \
 165         BASE_INNER(seg)
 166
 167 #define SR(reg_name)\
 168                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 169                                         mm ## reg_name
 170
 171 #define SRI(reg_name, block, id)\
 172         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 173                                         mm ## block ## id ## _ ## reg_name
 174
 175
 176 #define SRII(reg_name, block, id)\
 177         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 178                                         mm ## block ## id ## _ ## reg_name
 179
 180 /* NBIO */
 181 #define NBIO_BASE_INNER(seg) \
 182         NBIF_BASE__INST0_SEG ## seg
 183
 184 #define NBIO_BASE(seg) \
 185         NBIO_BASE_INNER(seg)
 186
 187 #define NBIO_SR(reg_name)\
 188                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) +  \
 189                                         mm ## reg_name
 190
 191 /* MMHUB */
 192 #define MMHUB_BASE_INNER(seg) \
 193         MMHUB_BASE__INST0_SEG ## seg
 194
 195 #define MMHUB_BASE(seg) \
 196         MMHUB_BASE_INNER(seg)
 197
 198 #define MMHUB_SR(reg_name)\
 199                 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) +  \
 200                                         mm ## reg_name
 201
 202 /* macros to expend register list macro defined in HW object header file
 203  * end *********************/
 204
 205
 206 static const struct dce_dmcu_registers dmcu_regs = {
 207                 DMCU_DCN10_REG_LIST()
 208 };
 209
 210 static const struct dce_dmcu_shift dmcu_shift = {
 211                 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 212 };
 213
 214 static const struct dce_dmcu_mask dmcu_mask = {
 215                 DMCU_MASK_SH_LIST_DCN10(_MASK)
 216 };
 217
 218 static const struct dce_abm_registers abm_regs = {
 219                 ABM_DCN10_REG_LIST(0)
 220 };
 221
 222 static const struct dce_abm_shift abm_shift = {
 223                 ABM_MASK_SH_LIST_DCN10(__SHIFT)
 224 };
 225
 226 static const struct dce_abm_mask abm_mask = {
 227                 ABM_MASK_SH_LIST_DCN10(_MASK)
 228 };
 229
 230 #define stream_enc_regs(id)\
 231 [id] = {\
 232         SE_DCN_REG_LIST(id)\
 233 }
 234
 235 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 236         stream_enc_regs(0),
 237         stream_enc_regs(1),
 238         stream_enc_regs(2),
 239         stream_enc_regs(3),
 240 };
 241
 242 static const struct dcn10_stream_encoder_shift se_shift = {
 243                 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
 244 };
 245
 246 static const struct dcn10_stream_encoder_mask se_mask = {
 247                 SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
 248 };
 249
 250 #define audio_regs(id)\
 251 [id] = {\
 252                 AUD_COMMON_REG_LIST(id)\
 253 }
 254
 255 static const struct dce_audio_registers audio_regs[] = {
 256         audio_regs(0),
 257         audio_regs(1),
 258         audio_regs(2),
 259         audio_regs(3),
 260 };
 261
 262 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 263                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 264                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 265                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 266
 267 static const struct dce_audio_shift audio_shift = {
 268                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 269 };
 270
 271 static const struct dce_aduio_mask audio_mask = {
 272                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 273 };
 274
 275 #define aux_regs(id)\
 276 [id] = {\
 277         AUX_REG_LIST(id)\
 278 }
 279
 280 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 281                 aux_regs(0),
 282                 aux_regs(1),
 283                 aux_regs(2),
 284                 aux_regs(3)
 285 };
 286
 287 #define hpd_regs(id)\
 288 [id] = {\
 289         HPD_REG_LIST(id)\
 290 }
 291
 292 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 293                 hpd_regs(0),
 294                 hpd_regs(1),
 295                 hpd_regs(2),
 296                 hpd_regs(3)
 297 };
 298
 299 #define link_regs(id)\
 300 [id] = {\
 301         LE_DCN10_REG_LIST(id), \
 302         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 303 }
 304
 305 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 306         link_regs(0),
 307         link_regs(1),
 308         link_regs(2),
 309         link_regs(3)
 310 };
 311
 312 static const struct dcn10_link_enc_shift le_shift = {
 313                 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT)
 314 };
 315
 316 static const struct dcn10_link_enc_mask le_mask = {
 317                 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
 318 };
 319
 320 #define ipp_regs(id)\
 321 [id] = {\
 322         IPP_REG_LIST_DCN10(id),\
 323 }
 324
 325 static const struct dcn10_ipp_registers ipp_regs[] = {
 326         ipp_regs(0),
 327         ipp_regs(1),
 328         ipp_regs(2),
 329         ipp_regs(3),
 330 };
 331
 332 static const struct dcn10_ipp_shift ipp_shift = {
 333                 IPP_MASK_SH_LIST_DCN10(__SHIFT)
 334 };
 335
 336 static const struct dcn10_ipp_mask ipp_mask = {
 337                 IPP_MASK_SH_LIST_DCN10(_MASK),
 338 };
 339
 340 #define opp_regs(id)\
 341 [id] = {\
 342         OPP_REG_LIST_DCN10(id),\
 343 }
 344
 345 static const struct dcn10_opp_registers opp_regs[] = {
 346         opp_regs(0),
 347         opp_regs(1),
 348         opp_regs(2),
 349         opp_regs(3),
 350 };
 351
 352 static const struct dcn10_opp_shift opp_shift = {
 353                 OPP_MASK_SH_LIST_DCN10(__SHIFT)
 354 };
 355
 356 static const struct dcn10_opp_mask opp_mask = {
 357                 OPP_MASK_SH_LIST_DCN10(_MASK),
 358 };
 359
 360 #define aux_engine_regs(id)\
 361 [id] = {\
 362         AUX_COMMON_REG_LIST(id), \
 363         .AUX_RESET_MASK = 0 \
 364 }
 365
 366 static const struct dce110_aux_registers aux_engine_regs[] = {
 367                 aux_engine_regs(0),
 368                 aux_engine_regs(1),
 369                 aux_engine_regs(2),
 370                 aux_engine_regs(3),
 371                 aux_engine_regs(4),
 372                 aux_engine_regs(5)
 373 };
 374
 375 #define tf_regs(id)\
 376 [id] = {\
 377         TF_REG_LIST_DCN10(id),\
 378 }
 379
 380 static const struct dcn_dpp_registers tf_regs[] = {
 381         tf_regs(0),
 382         tf_regs(1),
 383         tf_regs(2),
 384         tf_regs(3),
 385 };
 386
 387 static const struct dcn_dpp_shift tf_shift = {
 388         TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
 389         TF_DEBUG_REG_LIST_SH_DCN10
 390
 391 };
 392
 393 static const struct dcn_dpp_mask tf_mask = {
 394         TF_REG_LIST_SH_MASK_DCN10(_MASK),
 395         TF_DEBUG_REG_LIST_MASK_DCN10
 396 };
 397
 398 static const struct dcn_mpc_registers mpc_regs = {
 399                 MPC_COMMON_REG_LIST_DCN1_0(0),
 400                 MPC_COMMON_REG_LIST_DCN1_0(1),
 401                 MPC_COMMON_REG_LIST_DCN1_0(2),
 402                 MPC_COMMON_REG_LIST_DCN1_0(3),
 403                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),
 404                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),
 405                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),
 406                 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)
 407 };
 408
 409 static const struct dcn_mpc_shift mpc_shift = {
 410         MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
 411 };
 412
 413 static const struct dcn_mpc_mask mpc_mask = {
 414         MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),
 415 };
 416
 417 #define tg_regs(id)\
 418 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
 419
 420 static const struct dcn_optc_registers tg_regs[] = {
 421         tg_regs(0),
 422         tg_regs(1),
 423         tg_regs(2),
 424         tg_regs(3),
 425 };
 426
 427 static const struct dcn_optc_shift tg_shift = {
 428         TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
 429 };
 430
 431 static const struct dcn_optc_mask tg_mask = {
 432         TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
 433 };
 434
 435
 436 static const struct bios_registers bios_regs = {
 437                 NBIO_SR(BIOS_SCRATCH_3),
 438                 NBIO_SR(BIOS_SCRATCH_6)
 439 };
 440
 441 #define hubp_regs(id)\
 442 [id] = {\
 443         HUBP_REG_LIST_DCN10(id)\
 444 }
 445
 446
 447 static const struct dcn_mi_registers hubp_regs[] = {
 448         hubp_regs(0),
 449         hubp_regs(1),
 450         hubp_regs(2),
 451         hubp_regs(3),
 452 };
 453
 454 static const struct dcn_mi_shift hubp_shift = {
 455                 HUBP_MASK_SH_LIST_DCN10(__SHIFT)
 456 };
 457
 458 static const struct dcn_mi_mask hubp_mask = {
 459                 HUBP_MASK_SH_LIST_DCN10(_MASK)
 460 };
 461
 462
 463 static const struct dcn_hubbub_registers hubbub_reg = {
 464                 HUBBUB_REG_LIST_DCN10(0)
 465 };
 466
 467 static const struct dcn_hubbub_shift hubbub_shift = {
 468                 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
 469 };
 470
 471 static const struct dcn_hubbub_mask hubbub_mask = {
 472                 HUBBUB_MASK_SH_LIST_DCN10(_MASK)
 473 };
 474
 475 #define clk_src_regs(index, pllid)\
 476 [index] = {\
 477         CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
 478 }
 479
 480 static const struct dce110_clk_src_regs clk_src_regs[] = {
 481         clk_src_regs(0, A),
 482         clk_src_regs(1, B),
 483         clk_src_regs(2, C),
 484         clk_src_regs(3, D)
 485 };
 486
 487 static const struct dce110_clk_src_shift cs_shift = {
 488                 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
 489 };
 490
 491 static const struct dce110_clk_src_mask cs_mask = {
 492                 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
 493 };
 494
 495
 496 static const struct resource_caps res_cap = {
 497                 .num_timing_generator = 4,
 498                 .num_opp = 4,
 499                 .num_video_plane = 4,
 500                 .num_audio = 4,
 501                 .num_stream_encoder = 4,
 502                 .num_pll = 4,
 503 };
 504
 505 static const struct dc_debug_options debug_defaults_drv = {
 506                 .sanity_checks = true,
 507                 .disable_dmcu = true,
 508                 .force_abm_enable = false,
 509                 .timing_trace = false,
 510                 .clock_trace = true,
 511
 512                 /* raven smu dones't allow 0 disp clk,
 513                  * smu min disp clk limit is 50Mhz
 514                  * keep min disp clk 100Mhz avoid smu hang
 515                  */
 516                 .min_disp_clk_khz = 100000,
 517
 518                 .disable_pplib_clock_request = false,
 519                 .disable_pplib_wm_range = false,
 520                 .pplib_wm_report_mode = WM_REPORT_DEFAULT,
 521                 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 522                 .force_single_disp_pipe_split = true,
 523                 .disable_dcc = DCC_ENABLE,
 524                 .voltage_align_fclk = true,
 525                 .disable_stereo_support = true,
 526                 .vsr_support = true,
 527                 .performance_trace = false,
 528                 .az_endpoint_mute_only = true,
 529                 .recovery_enabled = false, /*enable this by default after testing.*/
 530                 .max_downscale_src_width = 3840,
 531 };
 532
 533 static const struct dc_debug_options debug_defaults_diags = {
 534                 .disable_dmcu = true,
 535                 .force_abm_enable = false,
 536                 .timing_trace = true,
 537                 .clock_trace = true,
 538                 .disable_stutter = true,
 539                 .disable_pplib_clock_request = true,
 540                 .disable_pplib_wm_range = true
 541 };
 542
 543 static void dcn10_dpp_destroy(struct dpp **dpp)
 544 {
 545         kfree(TO_DCN10_DPP(*dpp));
 546         *dpp = NULL;
 547 }
 548
 549 static struct dpp *dcn10_dpp_create(
 550         struct dc_context *ctx,
 551         uint32_t inst)
 552 {
 553         struct dcn10_dpp *dpp =
 554                 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL);
 555
 556         if (!dpp)
 557                 return NULL;
 558
 559         dpp1_construct(dpp, ctx, inst,
 560                        &tf_regs[inst], &tf_shift, &tf_mask);
 561         return &dpp->base;
 562 }
 563
 564 static struct input_pixel_processor *dcn10_ipp_create(
 565         struct dc_context *ctx, uint32_t inst)
 566 {
 567         struct dcn10_ipp *ipp =
 568                 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
 569
 570         if (!ipp) {
 571                 BREAK_TO_DEBUGGER();
 572                 return NULL;
 573         }
 574
 575         dcn10_ipp_construct(ipp, ctx, inst,
 576                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 577         return &ipp->base;
 578 }
 579
 580
 581 static struct output_pixel_processor *dcn10_opp_create(
 582         struct dc_context *ctx, uint32_t inst)
 583 {
 584         struct dcn10_opp *opp =
 585                 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL);
 586
 587         if (!opp) {
 588                 BREAK_TO_DEBUGGER();
 589                 return NULL;
 590         }
 591
 592         dcn10_opp_construct(opp, ctx, inst,
 593                         &opp_regs[inst], &opp_shift, &opp_mask);
 594         return &opp->base;
 595 }
 596
 597 struct aux_engine *dcn10_aux_engine_create(
 598         struct dc_context *ctx,
 599         uint32_t inst)
 600 {
 601         struct aux_engine_dce110 *aux_engine =
 602                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 603
 604         if (!aux_engine)
 605                 return NULL;
 606
 607         dce110_aux_engine_construct(aux_engine, ctx, inst,
 608                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 609                                     &aux_engine_regs[inst]);
 610
 611         return &aux_engine->base;
 612 }
 613
 614 static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
 615 {
 616         struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
 617                                           GFP_KERNEL);
 618
 619         if (!mpc10)
 620                 return NULL;
 621
 622         dcn10_mpc_construct(mpc10, ctx,
 623                         &mpc_regs,
 624                         &mpc_shift,
 625                         &mpc_mask,
 626                         4);
 627
 628         return &mpc10->base;
 629 }
 630
 631 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
 632 {
 633         struct hubbub *hubbub = kzalloc(sizeof(struct hubbub),
 634                                           GFP_KERNEL);
 635
 636         if (!hubbub)
 637                 return NULL;
 638
 639         hubbub1_construct(hubbub, ctx,
 640                         &hubbub_reg,
 641                         &hubbub_shift,
 642                         &hubbub_mask);
 643
 644         return hubbub;
 645 }
 646
 647 static struct timing_generator *dcn10_timing_generator_create(
 648                 struct dc_context *ctx,
 649                 uint32_t instance)
 650 {
 651         struct optc *tgn10 =
 652                 kzalloc(sizeof(struct optc), GFP_KERNEL);
 653
 654         if (!tgn10)
 655                 return NULL;
 656
 657         tgn10->base.inst = instance;
 658         tgn10->base.ctx = ctx;
 659
 660         tgn10->tg_regs = &tg_regs[instance];
 661         tgn10->tg_shift = &tg_shift;
 662         tgn10->tg_mask = &tg_mask;
 663
 664         dcn10_timing_generator_init(tgn10);
 665
 666         return &tgn10->base;
 667 }
 668
 669 static const struct encoder_feature_support link_enc_feature = {
 670                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 671                 .max_hdmi_pixel_clock = 600000,
 672                 .ycbcr420_supported = true,
 673                 .flags.bits.IS_HBR2_CAPABLE = true,
 674                 .flags.bits.IS_HBR3_CAPABLE = true,
 675                 .flags.bits.IS_TPS3_CAPABLE = true,
 676                 .flags.bits.IS_TPS4_CAPABLE = true,
 677                 .flags.bits.IS_YCBCR_CAPABLE = true
 678 };
 679
 680 struct link_encoder *dcn10_link_encoder_create(
 681         const struct encoder_init_data *enc_init_data)
 682 {
 683         struct dcn10_link_encoder *enc10 =
 684                 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
 685
 686         if (!enc10)
 687                 return NULL;
 688
 689         dcn10_link_encoder_construct(enc10,
 690                                       enc_init_data,
 691                                       &link_enc_feature,
 692                                       &link_enc_regs[enc_init_data->transmitter],
 693                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 694                                       &link_enc_hpd_regs[enc_init_data->hpd_source],
 695                                       &le_shift,
 696                                       &le_mask);
 697
 698         return &enc10->base;
 699 }
 700
 701 struct clock_source *dcn10_clock_source_create(
 702         struct dc_context *ctx,
 703         struct dc_bios *bios,
 704         enum clock_source_id id,
 705         const struct dce110_clk_src_regs *regs,
 706         bool dp_clk_src)
 707 {
 708         struct dce110_clk_src *clk_src =
 709                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 710
 711         if (!clk_src)
 712                 return NULL;
 713
 714         if (dce110_clk_src_construct(clk_src, ctx, bios, id,
 715                         regs, &cs_shift, &cs_mask)) {
 716                 clk_src->base.dp_clk_src = dp_clk_src;
 717                 return &clk_src->base;
 718         }
 719
 720         BREAK_TO_DEBUGGER();
 721         return NULL;
 722 }
 723
 724 static void read_dce_straps(
 725         struct dc_context *ctx,
 726         struct resource_straps *straps)
 727 {
 728         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
 729                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
 730 }
 731
 732 static struct audio *create_audio(
 733                 struct dc_context *ctx, unsigned int inst)
 734 {
 735         return dce_audio_create(ctx, inst,
 736                         &audio_regs[inst], &audio_shift, &audio_mask);
 737 }
 738
 739 static struct stream_encoder *dcn10_stream_encoder_create(
 740         enum engine_id eng_id,
 741         struct dc_context *ctx)
 742 {
 743         struct dcn10_stream_encoder *enc1 =
 744                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
 745
 746         if (!enc1)
 747                 return NULL;
 748
 749         dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
 750                                         &stream_enc_regs[eng_id],
 751                                         &se_shift, &se_mask);
 752         return &enc1->base;
 753 }
 754
 755 static const struct dce_hwseq_registers hwseq_reg = {
 756                 HWSEQ_DCN1_REG_LIST()
 757 };
 758
 759 static const struct dce_hwseq_shift hwseq_shift = {
 760                 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
 761 };
 762
 763 static const struct dce_hwseq_mask hwseq_mask = {
 764                 HWSEQ_DCN1_MASK_SH_LIST(_MASK)
 765 };
 766
 767 static struct dce_hwseq *dcn10_hwseq_create(
 768         struct dc_context *ctx)
 769 {
 770         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 771
 772         if (hws) {
 773                 hws->ctx = ctx;
 774                 hws->regs = &hwseq_reg;
 775                 hws->shifts = &hwseq_shift;
 776                 hws->masks = &hwseq_mask;
 777                 hws->wa.DEGVIDCN10_253 = true;
 778                 hws->wa.false_optc_underflow = true;
 779                 hws->wa.DEGVIDCN10_254 = true;
 780         }
 781         return hws;
 782 }
 783
 784 static const struct resource_create_funcs res_create_funcs = {
 785         .read_dce_straps = read_dce_straps,
 786         .create_audio = create_audio,
 787         .create_stream_encoder = dcn10_stream_encoder_create,
 788         .create_hwseq = dcn10_hwseq_create,
 789 };
 790
 791 static const struct resource_create_funcs res_create_maximus_funcs = {
 792         .read_dce_straps = NULL,
 793         .create_audio = NULL,
 794         .create_stream_encoder = NULL,
 795         .create_hwseq = dcn10_hwseq_create,
 796 };
 797
 798 void dcn10_clock_source_destroy(struct clock_source **clk_src)
 799 {
 800         kfree(TO_DCE110_CLK_SRC(*clk_src));
 801         *clk_src = NULL;
 802 }
 803
 804 static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx)
 805 {
 806         struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
 807
 808         if (!pp_smu)
 809                 return pp_smu;
 810
 811         dm_pp_get_funcs_rv(ctx, pp_smu);
 812         return pp_smu;
 813 }
 814
 815 static void destruct(struct dcn10_resource_pool *pool)
 816 {
 817         unsigned int i;
 818
 819         for (i = 0; i < pool->base.stream_enc_count; i++) {
 820                 if (pool->base.stream_enc[i] != NULL) {
 821                         /* TODO: free dcn version of stream encoder once implemented
 822                          * rather than using virtual stream encoder
 823                          */
 824                         kfree(pool->base.stream_enc[i]);
 825                         pool->base.stream_enc[i] = NULL;
 826                 }
 827         }
 828
 829         if (pool->base.mpc != NULL) {
 830                 kfree(TO_DCN10_MPC(pool->base.mpc));
 831                 pool->base.mpc = NULL;
 832         }
 833
 834         if (pool->base.hubbub != NULL) {
 835                 kfree(pool->base.hubbub);
 836                 pool->base.hubbub = NULL;
 837         }
 838
 839         for (i = 0; i < pool->base.pipe_count; i++) {
 840                 if (pool->base.opps[i] != NULL)
 841                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
 842
 843                 if (pool->base.dpps[i] != NULL)
 844                         dcn10_dpp_destroy(&pool->base.dpps[i]);
 845
 846                 if (pool->base.ipps[i] != NULL)
 847                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
 848
 849                 if (pool->base.hubps[i] != NULL) {
 850                         kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
 851                         pool->base.hubps[i] = NULL;
 852                 }
 853
 854                 if (pool->base.irqs != NULL) {
 855                         dal_irq_service_destroy(&pool->base.irqs);
 856                 }
 857
 858                 if (pool->base.timing_generators[i] != NULL)    {
 859                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
 860                         pool->base.timing_generators[i] = NULL;
 861                 }
 862
 863                 if (pool->base.engines[i] != NULL)
 864                         pool->base.engines[i]->funcs->destroy_engine(&pool->base.engines[i]);
 865         }
 866
 867         for (i = 0; i < pool->base.stream_enc_count; i++)
 868                 kfree(pool->base.stream_enc[i]);
 869
 870         for (i = 0; i < pool->base.audio_count; i++) {
 871                 if (pool->base.audios[i])
 872                         dce_aud_destroy(&pool->base.audios[i]);
 873         }
 874
 875         for (i = 0; i < pool->base.clk_src_count; i++) {
 876                 if (pool->base.clock_sources[i] != NULL) {
 877                         dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
 878                         pool->base.clock_sources[i] = NULL;
 879                 }
 880         }
 881
 882         if (pool->base.dp_clock_source != NULL) {
 883                 dcn10_clock_source_destroy(&pool->base.dp_clock_source);
 884                 pool->base.dp_clock_source = NULL;
 885         }
 886
 887         if (pool->base.abm != NULL)
 888                 dce_abm_destroy(&pool->base.abm);
 889
 890         if (pool->base.dmcu != NULL)
 891                 dce_dmcu_destroy(&pool->base.dmcu);
 892
 893         if (pool->base.dccg != NULL)
 894                 dce_dccg_destroy(&pool->base.dccg);
 895
 896         kfree(pool->base.pp_smu);
 897 }
 898
 899 static struct hubp *dcn10_hubp_create(
 900         struct dc_context *ctx,
 901         uint32_t inst)
 902 {
 903         struct dcn10_hubp *hubp1 =
 904                 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL);
 905
 906         if (!hubp1)
 907                 return NULL;
 908
 909         dcn10_hubp_construct(hubp1, ctx, inst,
 910                              &hubp_regs[inst], &hubp_shift, &hubp_mask);
 911         return &hubp1->base;
 912 }
 913
 914 static void get_pixel_clock_parameters(
 915         const struct pipe_ctx *pipe_ctx,
 916         struct pixel_clk_params *pixel_clk_params)
 917 {
 918         const struct dc_stream_state *stream = pipe_ctx->stream;
 919         pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
 920         pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
 921         pixel_clk_params->signal_type = pipe_ctx->stream->signal;
 922         pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
 923         /* TODO: un-hardcode*/
 924         pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
 925                 LINK_RATE_REF_FREQ_IN_KHZ;
 926         pixel_clk_params->flags.ENABLE_SS = 0;
 927         pixel_clk_params->color_depth =
 928                 stream->timing.display_color_depth;
 929         pixel_clk_params->flags.DISPLAY_BLANKED = 1;
 930         pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
 931
 932         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 933                 pixel_clk_params->color_depth = COLOR_DEPTH_888;
 934
 935         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
 936                 pixel_clk_params->requested_pix_clk  /= 2;
 937
 938 }
 939
 940 static void build_clamping_params(struct dc_stream_state *stream)
 941 {
 942         stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
 943         stream->clamping.c_depth = stream->timing.display_color_depth;
 944         stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
 945 }
 946
 947 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
 948 {
 949
 950         get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
 951
 952         pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
 953                 pipe_ctx->clock_source,
 954                 &pipe_ctx->stream_res.pix_clk_params,
 955                 &pipe_ctx->pll_settings);
 956
 957         pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
 958
 959         resource_build_bit_depth_reduction_params(pipe_ctx->stream,
 960                                         &pipe_ctx->stream->bit_depth_params);
 961         build_clamping_params(pipe_ctx->stream);
 962 }
 963
 964 static enum dc_status build_mapped_resource(
 965                 const struct dc *dc,
 966                 struct dc_state *context,
 967                 struct dc_stream_state *stream)
 968 {
 969         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
 970
 971         /*TODO Seems unneeded anymore */
 972         /*      if (old_context && resource_is_stream_unchanged(old_context, stream)) {
 973                         if (stream != NULL && old_context->streams[i] != NULL) {
 974                                  todo: shouldn't have to copy missing parameter here
 975                                 resource_build_bit_depth_reduction_params(stream,
 976                                                 &stream->bit_depth_params);
 977                                 stream->clamping.pixel_encoding =
 978                                                 stream->timing.pixel_encoding;
 979
 980                                 resource_build_bit_depth_reduction_params(stream,
 981                                                                 &stream->bit_depth_params);
 982                                 build_clamping_params(stream);
 983
 984                                 continue;
 985                         }
 986                 }
 987         */
 988
 989         if (!pipe_ctx)
 990                 return DC_ERROR_UNEXPECTED;
 991
 992         build_pipe_hw_param(pipe_ctx);
 993         return DC_OK;
 994 }
 995
 996 enum dc_status dcn10_add_stream_to_ctx(
 997                 struct dc *dc,
 998                 struct dc_state *new_ctx,
 999                 struct dc_stream_state *dc_stream)
1000 {
1001         enum dc_status result = DC_ERROR_UNEXPECTED;
1002
1003         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1004
1005         if (result == DC_OK)
1006                 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1007
1008
1009         if (result == DC_OK)
1010                 result = build_mapped_resource(dc, new_ctx, dc_stream);
1011
1012         return result;
1013 }
1014
1015 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
1016                 struct dc_state *context,
1017                 const struct resource_pool *pool,
1018                 struct dc_stream_state *stream)
1019 {
1020         struct resource_context *res_ctx = &context->res_ctx;
1021         struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1022         struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool);
1023
1024         if (!head_pipe) {
1025                 ASSERT(0);
1026                 return NULL;
1027         }
1028
1029         if (!idle_pipe)
1030                 return NULL;
1031
1032         idle_pipe->stream = head_pipe->stream;
1033         idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1034         idle_pipe->stream_res.abm = head_pipe->stream_res.abm;
1035         idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1036
1037         idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1038         idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1039         idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1040         idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1041
1042         return idle_pipe;
1043 }
1044
1045 static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
1046                 const struct dc_dcc_surface_param *input,
1047                 struct dc_surface_dcc_cap *output)
1048 {
1049         return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1050                         dc->res_pool->hubbub,
1051                         input,
1052                         output);
1053 }
1054
1055 static void dcn10_destroy_resource_pool(struct resource_pool **pool)
1056 {
1057         struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
1058
1059         destruct(dcn10_pool);
1060         kfree(dcn10_pool);
1061         *pool = NULL;
1062 }
1063
1064 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
1065 {
1066         if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1067                         && caps->max_video_width != 0
1068                         && plane_state->src_rect.width > caps->max_video_width)
1069                 return DC_FAIL_SURFACE_VALIDATE;
1070
1071         return DC_OK;
1072 }
1073
1074 static const struct dc_cap_funcs cap_funcs = {
1075         .get_dcc_compression_cap = dcn10_get_dcc_compression_cap
1076 };
1077
1078 static const struct resource_funcs dcn10_res_pool_funcs = {
1079         .destroy = dcn10_destroy_resource_pool,
1080         .link_enc_create = dcn10_link_encoder_create,
1081         .validate_bandwidth = dcn_validate_bandwidth,
1082         .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
1083         .validate_plane = dcn10_validate_plane,
1084         .add_stream_to_ctx = dcn10_add_stream_to_ctx
1085 };
1086
1087 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1088 {
1089         uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1090         /* RV1 support max 4 pipes */
1091         value = value & 0xf;
1092         return value;
1093 }
1094
1095 static bool construct(
1096         uint8_t num_virtual_links,
1097         struct dc *dc,
1098         struct dcn10_resource_pool *pool)
1099 {
1100         int i;
1101         int j;
1102         struct dc_context *ctx = dc->ctx;
1103         uint32_t pipe_fuses = read_pipe_fuses(ctx);
1104
1105         ctx->dc_bios->regs = &bios_regs;
1106
1107         pool->base.res_cap = &res_cap;
1108         pool->base.funcs = &dcn10_res_pool_funcs;
1109
1110         /*
1111          * TODO fill in from actual raven resource when we create
1112          * more than virtual encoder
1113          */
1114
1115         /*************************************************
1116          *  Resource + asic cap harcoding                *
1117          *************************************************/
1118         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1119
1120         /* max pipe num for ASIC before check pipe fuses */
1121         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1122
1123         dc->caps.max_video_width = 3840;
1124         dc->caps.max_downscale_ratio = 200;
1125         dc->caps.i2c_speed_in_khz = 100;
1126         dc->caps.max_cursor_size = 256;
1127         dc->caps.max_slave_planes = 1;
1128         dc->caps.is_apu = true;
1129         dc->caps.post_blend_color_processing = false;
1130         /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
1131         dc->caps.force_dp_tps4_for_cp2520 = true;
1132
1133         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1134                 dc->debug = debug_defaults_drv;
1135         else
1136                 dc->debug = debug_defaults_diags;
1137
1138         /*************************************************
1139          *  Create resources                             *
1140          *************************************************/
1141
1142         pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
1143                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1144                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1145                                 &clk_src_regs[0], false);
1146         pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
1147                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1148                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1149                                 &clk_src_regs[1], false);
1150         pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
1151                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1152                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1153                                 &clk_src_regs[2], false);
1154         pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1155                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1156                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1157                                 &clk_src_regs[3], false);
1158
1159         pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
1160
1161         pool->base.dp_clock_source =
1162                         dcn10_clock_source_create(ctx, ctx->dc_bios,
1163                                 CLOCK_SOURCE_ID_DP_DTO,
1164                                 /* todo: not reuse phy_pll registers */
1165                                 &clk_src_regs[0], true);
1166
1167         for (i = 0; i < pool->base.clk_src_count; i++) {
1168                 if (pool->base.clock_sources[i] == NULL) {
1169                         dm_error("DC: failed to create clock sources!\n");
1170                         BREAK_TO_DEBUGGER();
1171                         goto fail;
1172                 }
1173         }
1174
1175         pool->base.dccg = dcn1_dccg_create(ctx);
1176         if (pool->base.dccg == NULL) {
1177                 dm_error("DC: failed to create display clock!\n");
1178                 BREAK_TO_DEBUGGER();
1179                 goto fail;
1180         }
1181
1182         pool->base.dmcu = dcn10_dmcu_create(ctx,
1183                         &dmcu_regs,
1184                         &dmcu_shift,
1185                         &dmcu_mask);
1186         if (pool->base.dmcu == NULL) {
1187                 dm_error("DC: failed to create dmcu!\n");
1188                 BREAK_TO_DEBUGGER();
1189                 goto fail;
1190         }
1191
1192         pool->base.abm = dce_abm_create(ctx,
1193                         &abm_regs,
1194                         &abm_shift,
1195                         &abm_mask);
1196         if (pool->base.abm == NULL) {
1197                 dm_error("DC: failed to create abm!\n");
1198                 BREAK_TO_DEBUGGER();
1199                 goto fail;
1200         }
1201
1202         dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1);
1203         memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
1204         memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
1205
1206         if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1207                 dc->dcn_soc->urgent_latency = 3;
1208                 dc->debug.disable_dmcu = true;
1209                 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
1210         }
1211
1212
1213         dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
1214         ASSERT(dc->dcn_soc->number_of_channels < 3);
1215         if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/
1216                 dc->dcn_soc->number_of_channels = 2;
1217
1218         if (dc->dcn_soc->number_of_channels == 1) {
1219                 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
1220                 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
1221                 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
1222                 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
1223                 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1224                         dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
1225                 }
1226         }
1227
1228         pool->base.pp_smu = dcn10_pp_smu_create(ctx);
1229
1230         if (!dc->debug.disable_pplib_clock_request)
1231                 dcn_bw_update_from_pplib(dc);
1232         dcn_bw_sync_calcs_and_dml(dc);
1233         if (!dc->debug.disable_pplib_wm_range) {
1234                 dc->res_pool = &pool->base;
1235                 dcn_bw_notify_pplib_of_wm_ranges(dc);
1236         }
1237
1238         {
1239                 struct irq_service_init_data init_data;
1240                 init_data.ctx = dc->ctx;
1241                 pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
1242                 if (!pool->base.irqs)
1243                         goto fail;
1244         }
1245
1246         /* index to valid pipe resource  */
1247         j = 0;
1248         /* mem input -> ipp -> dpp -> opp -> TG */
1249         for (i = 0; i < pool->base.pipe_count; i++) {
1250                 /* if pipe is disabled, skip instance of HW pipe,
1251                  * i.e, skip ASIC register instance
1252                  */
1253                 if ((pipe_fuses & (1 << i)) != 0)
1254                         continue;
1255
1256                 pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
1257                 if (pool->base.hubps[j] == NULL) {
1258                         BREAK_TO_DEBUGGER();
1259                         dm_error(
1260                                 "DC: failed to create memory input!\n");
1261                         goto fail;
1262                 }
1263
1264                 pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
1265                 if (pool->base.ipps[j] == NULL) {
1266                         BREAK_TO_DEBUGGER();
1267                         dm_error(
1268                                 "DC: failed to create input pixel processor!\n");
1269                         goto fail;
1270                 }
1271
1272                 pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
1273                 if (pool->base.dpps[j] == NULL) {
1274                         BREAK_TO_DEBUGGER();
1275                         dm_error(
1276                                 "DC: failed to create dpp!\n");
1277                         goto fail;
1278                 }
1279
1280                 pool->base.opps[j] = dcn10_opp_create(ctx, i);
1281                 if (pool->base.opps[j] == NULL) {
1282                         BREAK_TO_DEBUGGER();
1283                         dm_error(
1284                                 "DC: failed to create output pixel processor!\n");
1285                         goto fail;
1286                 }
1287
1288                 pool->base.timing_generators[j] = dcn10_timing_generator_create(
1289                                 ctx, i);
1290                 if (pool->base.timing_generators[j] == NULL) {
1291                         BREAK_TO_DEBUGGER();
1292                         dm_error("DC: failed to create tg!\n");
1293                         goto fail;
1294                 }
1295
1296                 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
1297                 if (pool->base.engines[i] == NULL) {
1298                         BREAK_TO_DEBUGGER();
1299                         dm_error(
1300                                 "DC:failed to create aux engine!!\n");
1301                         goto fail;
1302                 }
1303
1304                 /* check next valid pipe */
1305                 j++;
1306         }
1307
1308         /* valid pipe num */
1309         pool->base.pipe_count = j;
1310         pool->base.timing_generator_count = j;
1311
1312         /* within dml lib, it is hard code to 4. If ASIC pipe is fused,
1313          * the value may be changed
1314          */
1315         dc->dml.ip.max_num_dpp = pool->base.pipe_count;
1316         dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
1317
1318         pool->base.mpc = dcn10_mpc_create(ctx);
1319         if (pool->base.mpc == NULL) {
1320                 BREAK_TO_DEBUGGER();
1321                 dm_error("DC: failed to create mpc!\n");
1322                 goto fail;
1323         }
1324
1325         pool->base.hubbub = dcn10_hubbub_create(ctx);
1326         if (pool->base.hubbub == NULL) {
1327                 BREAK_TO_DEBUGGER();
1328                 dm_error("DC: failed to create hubbub!\n");
1329                 goto fail;
1330         }
1331
1332         if (!resource_construct(num_virtual_links, dc, &pool->base,
1333                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1334                         &res_create_funcs : &res_create_maximus_funcs)))
1335                         goto fail;
1336
1337         dcn10_hw_sequencer_construct(dc);
1338         dc->caps.max_planes =  pool->base.pipe_count;
1339
1340         dc->cap_funcs = cap_funcs;
1341
1342         return true;
1343
1344 fail:
1345
1346         destruct(pool);
1347
1348         return false;
1349 }
1350
1351 struct resource_pool *dcn10_create_resource_pool(
1352                 uint8_t num_virtual_links,
1353                 struct dc *dc)
1354 {
1355         struct dcn10_resource_pool *pool =
1356                 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL);
1357
1358         if (!pool)
1359                 return NULL;
1360
1361         if (construct(num_virtual_links, dc, pool))
1362                 return &pool->base;
1363
1364         kfree(pool);
1365         BREAK_TO_DEBUGGER();
1366         return NULL;
1367 }