2 * Copyright 2012-16 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "dm_services.h"
27 #include "dce/dce_11_0_d.h"
28 #include "dce/dce_11_0_sh_mask.h"
29 /* TODO: this needs to be looked at, used by Stella's workaround*/
30 #include "gmc/gmc_8_2_d.h"
31 #include "gmc/gmc_8_2_sh_mask.h"
33 #include "include/logger_interface.h"
34 #include "inc/dce_calcs.h"
36 #include "dce/dce_mem_input.h"
38 static void set_flip_control(
39 struct dce_mem_input *mem_input110,
45 mem_input110->base.ctx,
48 set_reg_field_value(value, 1,
50 GRPH_SURFACE_UPDATE_PENDING_MODE);
53 mem_input110->base.ctx,
59 static void program_pri_addr_c(
60 struct dce_mem_input *mem_input110,
61 PHYSICAL_ADDRESS_LOC address)
65 /*high register MUST be programmed first*/
66 temp = address.high_part &
67 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK;
69 set_reg_field_value(value, temp,
70 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C,
71 GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C);
74 mem_input110->base.ctx,
75 mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C,
80 temp = address.low_part >>
81 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT;
83 set_reg_field_value(value, temp,
84 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C,
85 GRPH_PRIMARY_SURFACE_ADDRESS_C);
88 mem_input110->base.ctx,
89 mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C,
94 static void program_pri_addr_l(
95 struct dce_mem_input *mem_input110,
96 PHYSICAL_ADDRESS_LOC address)
101 /*high register MUST be programmed first*/
102 temp = address.high_part &
103 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK;
105 set_reg_field_value(value, temp,
106 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L,
107 GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L);
110 mem_input110->base.ctx,
111 mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L,
116 temp = address.low_part >>
117 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT;
119 set_reg_field_value(value, temp,
120 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L,
121 GRPH_PRIMARY_SURFACE_ADDRESS_L);
124 mem_input110->base.ctx,
125 mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L,
129 static void program_addr(
130 struct dce_mem_input *mem_input110,
131 const struct dc_plane_address *addr)
133 switch (addr->type) {
134 case PLN_ADDR_TYPE_GRAPHICS:
139 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
142 addr->video_progressive.chroma_addr);
145 addr->video_progressive.luma_addr);
153 static void enable(struct dce_mem_input *mem_input110)
157 value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_ENABLE);
158 set_reg_field_value(value, 1, UNP_GRPH_ENABLE, GRPH_ENABLE);
159 dm_write_reg(mem_input110->base.ctx,
164 static void program_tiling(
165 struct dce_mem_input *mem_input110,
166 const union dc_tiling_info *info,
167 const enum surface_pixel_format pixel_format)
171 set_reg_field_value(value, info->gfx8.num_banks,
172 UNP_GRPH_CONTROL, GRPH_NUM_BANKS);
174 set_reg_field_value(value, info->gfx8.bank_width,
175 UNP_GRPH_CONTROL, GRPH_BANK_WIDTH_L);
177 set_reg_field_value(value, info->gfx8.bank_height,
178 UNP_GRPH_CONTROL, GRPH_BANK_HEIGHT_L);
180 set_reg_field_value(value, info->gfx8.tile_aspect,
181 UNP_GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT_L);
183 set_reg_field_value(value, info->gfx8.tile_split,
184 UNP_GRPH_CONTROL, GRPH_TILE_SPLIT_L);
186 set_reg_field_value(value, info->gfx8.tile_mode,
187 UNP_GRPH_CONTROL, GRPH_MICRO_TILE_MODE_L);
189 set_reg_field_value(value, info->gfx8.pipe_config,
190 UNP_GRPH_CONTROL, GRPH_PIPE_CONFIG);
192 set_reg_field_value(value, info->gfx8.array_mode,
193 UNP_GRPH_CONTROL, GRPH_ARRAY_MODE);
195 set_reg_field_value(value, 1,
196 UNP_GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE);
198 set_reg_field_value(value, 0,
199 UNP_GRPH_CONTROL, GRPH_Z);
202 mem_input110->base.ctx,
208 set_reg_field_value(value, info->gfx8.bank_width_c,
209 UNP_GRPH_CONTROL_C, GRPH_BANK_WIDTH_C);
211 set_reg_field_value(value, info->gfx8.bank_height_c,
212 UNP_GRPH_CONTROL_C, GRPH_BANK_HEIGHT_C);
214 set_reg_field_value(value, info->gfx8.tile_aspect_c,
215 UNP_GRPH_CONTROL_C, GRPH_MACRO_TILE_ASPECT_C);
217 set_reg_field_value(value, info->gfx8.tile_split_c,
218 UNP_GRPH_CONTROL_C, GRPH_TILE_SPLIT_C);
220 set_reg_field_value(value, info->gfx8.tile_mode_c,
221 UNP_GRPH_CONTROL_C, GRPH_MICRO_TILE_MODE_C);
224 mem_input110->base.ctx,
225 mmUNP_GRPH_CONTROL_C,
229 static void program_size_and_rotation(
230 struct dce_mem_input *mem_input110,
231 enum dc_rotation_angle rotation,
232 const union plane_size *plane_size)
235 union plane_size local_size = *plane_size;
237 if (rotation == ROTATION_ANGLE_90 ||
238 rotation == ROTATION_ANGLE_270) {
240 swap(local_size.video.luma_size.x,
241 local_size.video.luma_size.y);
242 swap(local_size.video.luma_size.width,
243 local_size.video.luma_size.height);
244 swap(local_size.video.chroma_size.x,
245 local_size.video.chroma_size.y);
246 swap(local_size.video.chroma_size.width,
247 local_size.video.chroma_size.height);
251 set_reg_field_value(value, local_size.video.luma_pitch,
252 UNP_GRPH_PITCH_L, GRPH_PITCH_L);
255 mem_input110->base.ctx,
260 set_reg_field_value(value, local_size.video.chroma_pitch,
261 UNP_GRPH_PITCH_C, GRPH_PITCH_C);
263 mem_input110->base.ctx,
268 set_reg_field_value(value, 0,
269 UNP_GRPH_X_START_L, GRPH_X_START_L);
271 mem_input110->base.ctx,
272 mmUNP_GRPH_X_START_L,
276 set_reg_field_value(value, 0,
277 UNP_GRPH_X_START_C, GRPH_X_START_C);
279 mem_input110->base.ctx,
280 mmUNP_GRPH_X_START_C,
284 set_reg_field_value(value, 0,
285 UNP_GRPH_Y_START_L, GRPH_Y_START_L);
287 mem_input110->base.ctx,
288 mmUNP_GRPH_Y_START_L,
292 set_reg_field_value(value, 0,
293 UNP_GRPH_Y_START_C, GRPH_Y_START_C);
295 mem_input110->base.ctx,
296 mmUNP_GRPH_Y_START_C,
300 set_reg_field_value(value, local_size.video.luma_size.x +
301 local_size.video.luma_size.width,
302 UNP_GRPH_X_END_L, GRPH_X_END_L);
304 mem_input110->base.ctx,
309 set_reg_field_value(value, local_size.video.chroma_size.x +
310 local_size.video.chroma_size.width,
311 UNP_GRPH_X_END_C, GRPH_X_END_C);
313 mem_input110->base.ctx,
318 set_reg_field_value(value, local_size.video.luma_size.y +
319 local_size.video.luma_size.height,
320 UNP_GRPH_Y_END_L, GRPH_Y_END_L);
322 mem_input110->base.ctx,
327 set_reg_field_value(value, local_size.video.chroma_size.y +
328 local_size.video.chroma_size.height,
329 UNP_GRPH_Y_END_C, GRPH_Y_END_C);
331 mem_input110->base.ctx,
337 case ROTATION_ANGLE_90:
338 set_reg_field_value(value, 3,
339 UNP_HW_ROTATION, ROTATION_ANGLE);
341 case ROTATION_ANGLE_180:
342 set_reg_field_value(value, 2,
343 UNP_HW_ROTATION, ROTATION_ANGLE);
345 case ROTATION_ANGLE_270:
346 set_reg_field_value(value, 1,
347 UNP_HW_ROTATION, ROTATION_ANGLE);
350 set_reg_field_value(value, 0,
351 UNP_HW_ROTATION, ROTATION_ANGLE);
356 mem_input110->base.ctx,
361 static void program_pixel_format(
362 struct dce_mem_input *mem_input110,
363 enum surface_pixel_format format)
365 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
371 mem_input110->base.ctx,
375 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
379 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
383 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
384 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
388 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
389 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
390 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
394 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
395 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
396 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
418 mem_input110->base.ctx,
423 mem_input110->base.ctx,
424 mmUNP_GRPH_CONTROL_EXP);
430 UNP_GRPH_CONTROL_EXP,
433 mem_input110->base.ctx,
434 mmUNP_GRPH_CONTROL_EXP,
438 /* Video 422 and 420 needs UNP_GRPH_CONTROL_EXP programmed */
440 uint8_t video_format;
443 mem_input110->base.ctx,
444 mmUNP_GRPH_CONTROL_EXP);
447 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
450 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
461 UNP_GRPH_CONTROL_EXP,
465 mem_input110->base.ctx,
466 mmUNP_GRPH_CONTROL_EXP,
471 bool dce_mem_input_v_is_surface_pending(struct mem_input *mem_input)
473 struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
476 value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_UPDATE);
478 if (get_reg_field_value(value, UNP_GRPH_UPDATE,
479 GRPH_SURFACE_UPDATE_PENDING))
482 mem_input->current_address = mem_input->request_address;
486 bool dce_mem_input_v_program_surface_flip_and_addr(
487 struct mem_input *mem_input,
488 const struct dc_plane_address *address,
491 struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
493 set_flip_control(mem_input110, flip_immediate);
494 program_addr(mem_input110,
497 mem_input->request_address = *address;
502 /* Scatter Gather param tables */
503 static const unsigned int dvmm_Hw_Setting_2DTiling[4][9] = {
504 { 8, 64, 64, 8, 8, 1, 4, 0, 0},
505 { 16, 64, 32, 8, 16, 1, 8, 0, 0},
506 { 32, 32, 32, 16, 16, 1, 8, 0, 0},
507 { 64, 8, 32, 16, 16, 1, 8, 0, 0}, /* fake */
510 static const unsigned int dvmm_Hw_Setting_1DTiling[4][9] = {
511 { 8, 512, 8, 1, 0, 1, 0, 0, 0}, /* 0 for invalid */
512 { 16, 256, 8, 2, 0, 1, 0, 0, 0},
513 { 32, 128, 8, 4, 0, 1, 0, 0, 0},
514 { 64, 64, 8, 4, 0, 1, 0, 0, 0}, /* fake */
517 static const unsigned int dvmm_Hw_Setting_Linear[4][9] = {
518 { 8, 4096, 1, 8, 0, 1, 0, 0, 0},
519 { 16, 2048, 1, 8, 0, 1, 0, 0, 0},
520 { 32, 1024, 1, 8, 0, 1, 0, 0, 0},
521 { 64, 512, 1, 8, 0, 1, 0, 0, 0}, /* new for 64bpp from HW */
524 /* Helper to get table entry from surface info */
525 static const unsigned int *get_dvmm_hw_setting(
526 union dc_tiling_info *tiling_info,
527 enum surface_pixel_format format,
530 enum bits_per_pixel {
537 if (format >= SURFACE_PIXEL_FORMAT_INVALID)
539 else if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
540 bpp = chroma ? bpp_16 : bpp_8;
544 switch (tiling_info->gfx8.array_mode) {
545 case DC_ARRAY_1D_TILED_THIN1:
546 case DC_ARRAY_1D_TILED_THICK:
547 case DC_ARRAY_PRT_TILED_THIN1:
548 return dvmm_Hw_Setting_1DTiling[bpp];
549 case DC_ARRAY_2D_TILED_THIN1:
550 case DC_ARRAY_2D_TILED_THICK:
551 case DC_ARRAY_2D_TILED_X_THICK:
552 case DC_ARRAY_PRT_2D_TILED_THIN1:
553 case DC_ARRAY_PRT_2D_TILED_THICK:
554 return dvmm_Hw_Setting_2DTiling[bpp];
555 case DC_ARRAY_LINEAR_GENERAL:
556 case DC_ARRAY_LINEAR_ALLIGNED:
557 return dvmm_Hw_Setting_Linear[bpp];
559 return dvmm_Hw_Setting_2DTiling[bpp];
563 void dce_mem_input_v_program_pte_vm(
564 struct mem_input *mem_input,
565 enum surface_pixel_format format,
566 union dc_tiling_info *tiling_info,
567 enum dc_rotation_angle rotation)
569 struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
570 const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false);
571 const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true);
573 unsigned int page_width = 0;
574 unsigned int page_height = 0;
575 unsigned int page_width_chroma = 0;
576 unsigned int page_height_chroma = 0;
577 unsigned int temp_page_width = pte[1];
578 unsigned int temp_page_height = pte[2];
579 unsigned int min_pte_before_flip = 0;
580 unsigned int min_pte_before_flip_chroma = 0;
583 while ((temp_page_width >>= 1) != 0)
585 while ((temp_page_height >>= 1) != 0)
588 temp_page_width = pte_chroma[1];
589 temp_page_height = pte_chroma[2];
590 while ((temp_page_width >>= 1) != 0)
592 while ((temp_page_height >>= 1) != 0)
593 page_height_chroma++;
596 case ROTATION_ANGLE_90:
597 case ROTATION_ANGLE_270:
598 min_pte_before_flip = pte[4];
599 min_pte_before_flip_chroma = pte_chroma[4];
602 min_pte_before_flip = pte[3];
603 min_pte_before_flip_chroma = pte_chroma[3];
607 value = dm_read_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT);
608 /* TODO: un-hardcode requestlimit */
609 set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L);
610 set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C);
611 dm_write_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT, value);
613 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL);
614 set_reg_field_value(value, page_width, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH);
615 set_reg_field_value(value, page_height, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT);
616 set_reg_field_value(value, min_pte_before_flip, UNP_DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP);
617 dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL, value);
619 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL);
620 set_reg_field_value(value, pte[5], UNP_DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK);
621 set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING);
622 dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL, value);
624 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C);
625 set_reg_field_value(value, page_width_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_WIDTH_C);
626 set_reg_field_value(value, page_height_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_HEIGHT_C);
627 set_reg_field_value(value, min_pte_before_flip_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_MIN_PTE_BEFORE_FLIP_C);
628 dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C, value);
630 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C);
631 set_reg_field_value(value, pte_chroma[5], UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_PTE_REQ_PER_CHUNK_C);
632 set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_MAX_PTE_REQ_OUTSTANDING_C);
633 dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C, value);
636 void dce_mem_input_v_program_surface_config(
637 struct mem_input *mem_input,
638 enum surface_pixel_format format,
639 union dc_tiling_info *tiling_info,
640 union plane_size *plane_size,
641 enum dc_rotation_angle rotation,
642 struct dc_plane_dcc_param *dcc,
643 bool horizotal_mirror)
645 struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
647 enable(mem_input110);
648 program_tiling(mem_input110, tiling_info, format);
649 program_size_and_rotation(mem_input110, rotation, plane_size);
650 program_pixel_format(mem_input110, format);
653 static void program_urgency_watermark(
654 const struct dc_context *ctx,
655 const uint32_t urgency_addr,
656 const uint32_t wm_addr,
657 struct dce_watermarks marks_low,
658 uint32_t total_dest_line_time_ns)
661 uint32_t urgency_cntl = 0;
662 uint32_t wm_mask_cntl = 0;
664 /*Write mask to enable reading/writing of watermark set A*/
665 wm_mask_cntl = dm_read_reg(ctx, wm_addr);
666 set_reg_field_value(wm_mask_cntl,
668 DPGV0_WATERMARK_MASK_CONTROL,
669 URGENCY_WATERMARK_MASK);
670 dm_write_reg(ctx, wm_addr, wm_mask_cntl);
672 urgency_cntl = dm_read_reg(ctx, urgency_addr);
677 DPGV0_PIPE_URGENCY_CONTROL,
678 URGENCY_LOW_WATERMARK);
682 total_dest_line_time_ns,
683 DPGV0_PIPE_URGENCY_CONTROL,
684 URGENCY_HIGH_WATERMARK);
685 dm_write_reg(ctx, urgency_addr, urgency_cntl);
687 /*Write mask to enable reading/writing of watermark set B*/
688 wm_mask_cntl = dm_read_reg(ctx, wm_addr);
689 set_reg_field_value(wm_mask_cntl,
691 DPGV0_WATERMARK_MASK_CONTROL,
692 URGENCY_WATERMARK_MASK);
693 dm_write_reg(ctx, wm_addr, wm_mask_cntl);
695 urgency_cntl = dm_read_reg(ctx, urgency_addr);
697 set_reg_field_value(urgency_cntl,
699 DPGV0_PIPE_URGENCY_CONTROL,
700 URGENCY_LOW_WATERMARK);
702 set_reg_field_value(urgency_cntl,
703 total_dest_line_time_ns,
704 DPGV0_PIPE_URGENCY_CONTROL,
705 URGENCY_HIGH_WATERMARK);
707 dm_write_reg(ctx, urgency_addr, urgency_cntl);
710 static void program_urgency_watermark_l(
711 const struct dc_context *ctx,
712 struct dce_watermarks marks_low,
713 uint32_t total_dest_line_time_ns)
715 program_urgency_watermark(
717 mmDPGV0_PIPE_URGENCY_CONTROL,
718 mmDPGV0_WATERMARK_MASK_CONTROL,
720 total_dest_line_time_ns);
723 static void program_urgency_watermark_c(
724 const struct dc_context *ctx,
725 struct dce_watermarks marks_low,
726 uint32_t total_dest_line_time_ns)
728 program_urgency_watermark(
730 mmDPGV1_PIPE_URGENCY_CONTROL,
731 mmDPGV1_WATERMARK_MASK_CONTROL,
733 total_dest_line_time_ns);
736 static void program_stutter_watermark(
737 const struct dc_context *ctx,
738 const uint32_t stutter_addr,
739 const uint32_t wm_addr,
740 struct dce_watermarks marks)
743 uint32_t stutter_cntl = 0;
744 uint32_t wm_mask_cntl = 0;
746 /*Write mask to enable reading/writing of watermark set A*/
748 wm_mask_cntl = dm_read_reg(ctx, wm_addr);
749 set_reg_field_value(wm_mask_cntl,
751 DPGV0_WATERMARK_MASK_CONTROL,
752 STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
753 dm_write_reg(ctx, wm_addr, wm_mask_cntl);
755 stutter_cntl = dm_read_reg(ctx, stutter_addr);
757 if (ctx->dc->debug.disable_stutter) {
758 set_reg_field_value(stutter_cntl,
760 DPGV0_PIPE_STUTTER_CONTROL,
763 set_reg_field_value(stutter_cntl,
765 DPGV0_PIPE_STUTTER_CONTROL,
769 set_reg_field_value(stutter_cntl,
771 DPGV0_PIPE_STUTTER_CONTROL,
774 /*Write watermark set A*/
775 set_reg_field_value(stutter_cntl,
777 DPGV0_PIPE_STUTTER_CONTROL,
778 STUTTER_EXIT_SELF_REFRESH_WATERMARK);
779 dm_write_reg(ctx, stutter_addr, stutter_cntl);
781 /*Write mask to enable reading/writing of watermark set B*/
782 wm_mask_cntl = dm_read_reg(ctx, wm_addr);
783 set_reg_field_value(wm_mask_cntl,
785 DPGV0_WATERMARK_MASK_CONTROL,
786 STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
787 dm_write_reg(ctx, wm_addr, wm_mask_cntl);
789 stutter_cntl = dm_read_reg(ctx, stutter_addr);
790 /*Write watermark set B*/
791 set_reg_field_value(stutter_cntl,
793 DPGV0_PIPE_STUTTER_CONTROL,
794 STUTTER_EXIT_SELF_REFRESH_WATERMARK);
795 dm_write_reg(ctx, stutter_addr, stutter_cntl);
798 static void program_stutter_watermark_l(
799 const struct dc_context *ctx,
800 struct dce_watermarks marks)
802 program_stutter_watermark(ctx,
803 mmDPGV0_PIPE_STUTTER_CONTROL,
804 mmDPGV0_WATERMARK_MASK_CONTROL,
808 static void program_stutter_watermark_c(
809 const struct dc_context *ctx,
810 struct dce_watermarks marks)
812 program_stutter_watermark(ctx,
813 mmDPGV1_PIPE_STUTTER_CONTROL,
814 mmDPGV1_WATERMARK_MASK_CONTROL,
818 static void program_nbp_watermark(
819 const struct dc_context *ctx,
820 const uint32_t wm_mask_ctrl_addr,
821 const uint32_t nbp_pstate_ctrl_addr,
822 struct dce_watermarks marks)
826 /* Write mask to enable reading/writing of watermark set A */
828 value = dm_read_reg(ctx, wm_mask_ctrl_addr);
833 DPGV0_WATERMARK_MASK_CONTROL,
834 NB_PSTATE_CHANGE_WATERMARK_MASK);
835 dm_write_reg(ctx, wm_mask_ctrl_addr, value);
837 value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
842 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
843 NB_PSTATE_CHANGE_ENABLE);
847 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
848 NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
852 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
853 NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
854 dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
856 /* Write watermark set A */
857 value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
861 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
862 NB_PSTATE_CHANGE_WATERMARK);
863 dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
865 /* Write mask to enable reading/writing of watermark set B */
866 value = dm_read_reg(ctx, wm_mask_ctrl_addr);
870 DPGV0_WATERMARK_MASK_CONTROL,
871 NB_PSTATE_CHANGE_WATERMARK_MASK);
872 dm_write_reg(ctx, wm_mask_ctrl_addr, value);
874 value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
878 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
879 NB_PSTATE_CHANGE_ENABLE);
883 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
884 NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
888 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
889 NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
890 dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
892 /* Write watermark set B */
893 value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
897 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
898 NB_PSTATE_CHANGE_WATERMARK);
899 dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
902 static void program_nbp_watermark_l(
903 const struct dc_context *ctx,
904 struct dce_watermarks marks)
906 program_nbp_watermark(ctx,
907 mmDPGV0_WATERMARK_MASK_CONTROL,
908 mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
912 static void program_nbp_watermark_c(
913 const struct dc_context *ctx,
914 struct dce_watermarks marks)
916 program_nbp_watermark(ctx,
917 mmDPGV1_WATERMARK_MASK_CONTROL,
918 mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL,
922 void dce_mem_input_v_program_display_marks(
923 struct mem_input *mem_input,
924 struct dce_watermarks nbp,
925 struct dce_watermarks stutter,
926 struct dce_watermarks stutter_enter,
927 struct dce_watermarks urgent,
928 uint32_t total_dest_line_time_ns)
930 program_urgency_watermark_l(
933 total_dest_line_time_ns);
935 program_nbp_watermark_l(
939 program_stutter_watermark_l(
945 void dce_mem_input_program_chroma_display_marks(
946 struct mem_input *mem_input,
947 struct dce_watermarks nbp,
948 struct dce_watermarks stutter,
949 struct dce_watermarks urgent,
950 uint32_t total_dest_line_time_ns)
952 program_urgency_watermark_c(
955 total_dest_line_time_ns);
957 program_nbp_watermark_c(
961 program_stutter_watermark_c(
966 void dce110_allocate_mem_input_v(
967 struct mem_input *mi,
968 uint32_t h_total,/* for current stream */
969 uint32_t v_total,/* for current stream */
970 uint32_t pix_clk_khz,/* for current stream */
971 uint32_t total_stream_num)
976 if (pix_clk_khz != 0) {
977 addr = mmDPGV0_PIPE_ARBITRATION_CONTROL1;
978 value = dm_read_reg(mi->ctx, addr);
979 pix_dur = 1000000000ULL / pix_clk_khz;
983 DPGV0_PIPE_ARBITRATION_CONTROL1,
985 dm_write_reg(mi->ctx, addr, value);
987 addr = mmDPGV1_PIPE_ARBITRATION_CONTROL1;
988 value = dm_read_reg(mi->ctx, addr);
989 pix_dur = 1000000000ULL / pix_clk_khz;
993 DPGV1_PIPE_ARBITRATION_CONTROL1,
995 dm_write_reg(mi->ctx, addr, value);
997 addr = mmDPGV0_PIPE_ARBITRATION_CONTROL2;
999 dm_write_reg(mi->ctx, addr, value);
1001 addr = mmDPGV1_PIPE_ARBITRATION_CONTROL2;
1003 dm_write_reg(mi->ctx, addr, value);
1008 void dce110_free_mem_input_v(
1009 struct mem_input *mi,
1010 uint32_t total_stream_num)
1014 static const struct mem_input_funcs dce110_mem_input_v_funcs = {
1015 .mem_input_program_display_marks =
1016 dce_mem_input_v_program_display_marks,
1017 .mem_input_program_chroma_display_marks =
1018 dce_mem_input_program_chroma_display_marks,
1019 .allocate_mem_input = dce110_allocate_mem_input_v,
1020 .free_mem_input = dce110_free_mem_input_v,
1021 .mem_input_program_surface_flip_and_addr =
1022 dce_mem_input_v_program_surface_flip_and_addr,
1023 .mem_input_program_pte_vm =
1024 dce_mem_input_v_program_pte_vm,
1025 .mem_input_program_surface_config =
1026 dce_mem_input_v_program_surface_config,
1027 .mem_input_is_flip_pending =
1028 dce_mem_input_v_is_surface_pending
1030 /*****************************************/
1031 /* Constructor, Destructor */
1032 /*****************************************/
1034 void dce110_mem_input_v_construct(
1035 struct dce_mem_input *dce_mi,
1036 struct dc_context *ctx)
1038 dce_mi->base.funcs = &dce110_mem_input_v_funcs;
1039 dce_mi->base.ctx = ctx;