drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "dce/dce_11_0_d.h"
  29 #include "dce/dce_11_0_sh_mask.h"
  30 #include "gmc/gmc_8_2_sh_mask.h"
  31 #include "gmc/gmc_8_2_d.h"
  32
  33 #include "include/logger_interface.h"
  34
  35 #include "dce110_compressor.h"
  36
  37 #define DC_LOGGER \
  38                 cp110->base.ctx->logger
  39 #define DCP_REG(reg)\
  40         (reg + cp110->offsets.dcp_offset)
  41 #define DMIF_REG(reg)\
  42         (reg + cp110->offsets.dmif_offset)
  43
  44 static const struct dce110_compressor_reg_offsets reg_offsets[] = {
  45 {
  46         .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
  47         .dmif_offset =
  48                 (mmDMIF_PG0_DPG_PIPE_DPM_CONTROL
  49                         - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
  50 },
  51 {
  52         .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
  53         .dmif_offset =
  54                 (mmDMIF_PG1_DPG_PIPE_DPM_CONTROL
  55                         - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
  56 },
  57 {
  58         .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
  59         .dmif_offset =
  60                 (mmDMIF_PG2_DPG_PIPE_DPM_CONTROL
  61                         - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
  62 }
  63 };
  64
  65 static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;
  66
  67 enum fbc_idle_force {
  68         /* Bit 0 - Display registers updated */
  69         FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001,
  70
  71         /* Bit 2 - FBC_GRPH_COMP_EN register updated */
  72         FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002,
  73         /* Bit 3 - FBC_SRC_SEL register updated */
  74         FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004,
  75         /* Bit 4 - FBC_MIN_COMPRESSION register updated */
  76         FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008,
  77         /* Bit 5 - FBC_ALPHA_COMP_EN register updated */
  78         FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010,
  79         /* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */
  80         FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020,
  81         /* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */
  82         FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040,
  83
  84         /* Bit 24 - Memory write to region 0 defined by MC registers. */
  85         FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000,
  86         /* Bit 25 - Memory write to region 1 defined by MC registers */
  87         FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000,
  88         /* Bit 26 - Memory write to region 2 defined by MC registers */
  89         FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000,
  90         /* Bit 27 - Memory write to region 3 defined by MC registers. */
  91         FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000,
  92
  93         /* Bit 28 - Memory write from any client other than MCIF */
  94         FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000,
  95         /* Bit 29 - CG statics screen signal is inactive */
  96         FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000,
  97 };
  98
  99
 100 static uint32_t align_to_chunks_number_per_line(uint32_t pixels)
 101 {
 102         return 256 * ((pixels + 255) / 256);
 103 }
 104
 105 static void reset_lb_on_vblank(struct dc_context *ctx)
 106 {
 107         uint32_t value, frame_count;
 108         uint32_t retry = 0;
 109         uint32_t status_pos =
 110                         dm_read_reg(ctx, mmCRTC_STATUS_POSITION);
 111
 112
 113         /* Only if CRTC is enabled and counter is moving we wait for one frame. */
 114         if (status_pos != dm_read_reg(ctx, mmCRTC_STATUS_POSITION)) {
 115                 /* Resetting LB on VBlank */
 116                 value = dm_read_reg(ctx, mmLB_SYNC_RESET_SEL);
 117                 set_reg_field_value(value, 3, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL);
 118                 set_reg_field_value(value, 1, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL2);
 119                 dm_write_reg(ctx, mmLB_SYNC_RESET_SEL, value);
 120
 121                 frame_count = dm_read_reg(ctx, mmCRTC_STATUS_FRAME_COUNT);
 122
 123
 124                 for (retry = 10000; retry > 0; retry--) {
 125                         if (frame_count != dm_read_reg(ctx, mmCRTC_STATUS_FRAME_COUNT))
 126                                 break;
 127                         udelay(10);
 128                 }
 129                 if (!retry)
 130                         dm_error("Frame count did not increase for 100ms.\n");
 131
 132                 /* Resetting LB on VBlank */
 133                 value = dm_read_reg(ctx, mmLB_SYNC_RESET_SEL);
 134                 set_reg_field_value(value, 2, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL);
 135                 set_reg_field_value(value, 0, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL2);
 136                 dm_write_reg(ctx, mmLB_SYNC_RESET_SEL, value);
 137
 138         }
 139
 140 }
 141
 142 static void wait_for_fbc_state_changed(
 143         struct dce110_compressor *cp110,
 144         bool enabled)
 145 {
 146         uint32_t counter = 0;
 147         uint32_t addr = mmFBC_STATUS;
 148         uint32_t value;
 149
 150         while (counter < 1000) {
 151                 value = dm_read_reg(cp110->base.ctx, addr);
 152                 if (get_reg_field_value(
 153                         value,
 154                         FBC_STATUS,
 155                         FBC_ENABLE_STATUS) == enabled)
 156                         break;
 157                 udelay(100);
 158                 counter++;
 159         }
 160
 161         if (counter == 1000) {
 162                 DC_LOG_WARNING("%s: wait counter exceeded, changes to HW not applied",
 163                         __func__);
 164         } else {
 165                 DC_LOG_SYNC("FBC status changed to %d", enabled);
 166         }
 167
 168
 169 }
 170
 171 void dce110_compressor_power_up_fbc(struct compressor *compressor)
 172 {
 173         uint32_t value;
 174         uint32_t addr;
 175
 176         addr = mmFBC_CNTL;
 177         value = dm_read_reg(compressor->ctx, addr);
 178         set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
 179         set_reg_field_value(value, 1, FBC_CNTL, FBC_EN);
 180         set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE);
 181         if (compressor->options.bits.CLK_GATING_DISABLED == 1) {
 182                 /* HW needs to do power measurement comparison. */
 183                 set_reg_field_value(
 184                         value,
 185                         0,
 186                         FBC_CNTL,
 187                         FBC_COMP_CLK_GATE_EN);
 188         }
 189         dm_write_reg(compressor->ctx, addr, value);
 190
 191         addr = mmFBC_COMP_MODE;
 192         value = dm_read_reg(compressor->ctx, addr);
 193         set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN);
 194         set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN);
 195         set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN);
 196         dm_write_reg(compressor->ctx, addr, value);
 197
 198         addr = mmFBC_COMP_CNTL;
 199         value = dm_read_reg(compressor->ctx, addr);
 200         set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN);
 201         dm_write_reg(compressor->ctx, addr, value);
 202         /*FBC_MIN_COMPRESSION 0 ==> 2:1 */
 203         /*                    1 ==> 4:1 */
 204         /*                    2 ==> 8:1 */
 205         /*                  0xF ==> 1:1 */
 206         set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION);
 207         dm_write_reg(compressor->ctx, addr, value);
 208         compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1;
 209
 210         value = 0;
 211         dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
 212
 213         value = 0xFFFFFF;
 214         dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
 215 }
 216
 217 void dce110_compressor_enable_fbc(
 218         struct compressor *compressor,
 219         struct compr_addr_and_pitch_params *params)
 220 {
 221         struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
 222
 223         if (compressor->options.bits.FBC_SUPPORT &&
 224                 (!dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL))) {
 225
 226                 uint32_t addr;
 227                 uint32_t value, misc_value;
 228
 229
 230                 addr = mmFBC_CNTL;
 231                 value = dm_read_reg(compressor->ctx, addr);
 232                 set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
 233                 set_reg_field_value(
 234                         value,
 235                         params->inst,
 236                         FBC_CNTL, FBC_SRC_SEL);
 237                 dm_write_reg(compressor->ctx, addr, value);
 238
 239                 /* Keep track of enum controller_id FBC is attached to */
 240                 compressor->is_enabled = true;
 241                 compressor->attached_inst = params->inst;
 242                 cp110->offsets = reg_offsets[params->inst];
 243
 244                 /* Toggle it as there is bug in HW */
 245                 set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
 246                 dm_write_reg(compressor->ctx, addr, value);
 247
 248                 /* FBC usage with scatter & gather for dce110 */
 249                 misc_value = dm_read_reg(compressor->ctx, mmFBC_MISC);
 250
 251                 set_reg_field_value(misc_value, 1,
 252                                 FBC_MISC, FBC_INVALIDATE_ON_ERROR);
 253                 set_reg_field_value(misc_value, 1,
 254                                 FBC_MISC, FBC_DECOMPRESS_ERROR_CLEAR);
 255                 set_reg_field_value(misc_value, 0x14,
 256                                 FBC_MISC, FBC_SLOW_REQ_INTERVAL);
 257
 258                 dm_write_reg(compressor->ctx, mmFBC_MISC, misc_value);
 259
 260                 /* Enable FBC */
 261                 set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
 262                 dm_write_reg(compressor->ctx, addr, value);
 263
 264                 wait_for_fbc_state_changed(cp110, true);
 265         }
 266 }
 267
 268 void dce110_compressor_disable_fbc(struct compressor *compressor)
 269 {
 270         struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
 271
 272         if (compressor->options.bits.FBC_SUPPORT) {
 273                 if (dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {
 274                         uint32_t reg_data;
 275                         /* Turn off compression */
 276                         reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
 277                         set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
 278                         dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
 279
 280                         /* Reset enum controller_id to undefined */
 281                         compressor->attached_inst = 0;
 282                         compressor->is_enabled = false;
 283
 284                         wait_for_fbc_state_changed(cp110, false);
 285                 }
 286
 287                 /* Sync line buffer  - dce100/110 only*/
 288                 reset_lb_on_vblank(compressor->ctx);
 289         }
 290 }
 291
 292 bool dce110_compressor_is_fbc_enabled_in_hw(
 293         struct compressor *compressor,
 294         uint32_t *inst)
 295 {
 296         /* Check the hardware register */
 297         uint32_t value;
 298
 299         value = dm_read_reg(compressor->ctx, mmFBC_STATUS);
 300         if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {
 301                 if (inst != NULL)
 302                         *inst = compressor->attached_inst;
 303                 return true;
 304         }
 305
 306         value = dm_read_reg(compressor->ctx, mmFBC_MISC);
 307         if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) {
 308                 value = dm_read_reg(compressor->ctx, mmFBC_CNTL);
 309
 310                 if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
 311                         if (inst != NULL)
 312                                 *inst =
 313                                         compressor->attached_inst;
 314                         return true;
 315                 }
 316         }
 317         return false;
 318 }
 319
 320
 321 void dce110_compressor_program_compressed_surface_address_and_pitch(
 322         struct compressor *compressor,
 323         struct compr_addr_and_pitch_params *params)
 324 {
 325         struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
 326         uint32_t value = 0;
 327         uint32_t fbc_pitch = 0;
 328         uint32_t compressed_surf_address_low_part =
 329                 compressor->compr_surface_address.addr.low_part;
 330
 331         /* Clear content first. */
 332         dm_write_reg(
 333                 compressor->ctx,
 334                 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
 335                 0);
 336         dm_write_reg(compressor->ctx,
 337                 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0);
 338
 339         /* Write address, HIGH has to be first. */
 340         dm_write_reg(compressor->ctx,
 341                 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
 342                 compressor->compr_surface_address.addr.high_part);
 343         dm_write_reg(compressor->ctx,
 344                 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS),
 345                 compressed_surf_address_low_part);
 346
 347         fbc_pitch = align_to_chunks_number_per_line(params->source_view_width);
 348
 349         if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
 350                 fbc_pitch = fbc_pitch / 8;
 351         else
 352                 DC_LOG_WARNING("%s: Unexpected DCE11 compression ratio",
 353                         __func__);
 354
 355         /* Clear content first. */
 356         dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);
 357
 358         /* Write FBC Pitch. */
 359         set_reg_field_value(
 360                 value,
 361                 fbc_pitch,
 362                 GRPH_COMPRESS_PITCH,
 363                 GRPH_COMPRESS_PITCH);
 364         dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);
 365
 366 }
 367
 368 void dce110_compressor_set_fbc_invalidation_triggers(
 369         struct compressor *compressor,
 370         uint32_t fbc_trigger)
 371 {
 372         /* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19)
 373          * for DCE 11 regions cannot be used - does not work with S/G
 374          */
 375         uint32_t addr = mmFBC_CLIENT_REGION_MASK;
 376         uint32_t value = dm_read_reg(compressor->ctx, addr);
 377
 378         set_reg_field_value(
 379                 value,
 380                 0,
 381                 FBC_CLIENT_REGION_MASK,
 382                 FBC_MEMORY_REGION_MASK);
 383         dm_write_reg(compressor->ctx, addr, value);
 384
 385         /* Setup events when to clear all CSM entries (effectively marking
 386          * current compressed data invalid)
 387          * For DCE 11 CSM metadata 11111 means - "Not Compressed"
 388          * Used as the initial value of the metadata sent to the compressor
 389          * after invalidation, to indicate that the compressor should attempt
 390          * to compress all chunks on the current pass.  Also used when the chunk
 391          * is not successfully written to memory.
 392          * When this CSM value is detected, FBC reads from the uncompressed
 393          * buffer. Set events according to passed in value, these events are
 394          * valid for DCE11:
 395          *     - bit  0 - display register updated
 396          *     - bit 28 - memory write from any client except from MCIF
 397          *     - bit 29 - CG static screen signal is inactive
 398          * In addition, DCE11.1 also needs to set new DCE11.1 specific events
 399          * that are used to trigger invalidation on certain register changes,
 400          * for example enabling of Alpha Compression may trigger invalidation of
 401          * FBC once bit is set. These events are as follows:
 402          *      - Bit 2 - FBC_GRPH_COMP_EN register updated
 403          *      - Bit 3 - FBC_SRC_SEL register updated
 404          *      - Bit 4 - FBC_MIN_COMPRESSION register updated
 405          *      - Bit 5 - FBC_ALPHA_COMP_EN register updated
 406          *      - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated
 407          *      - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated
 408          */
 409         addr = mmFBC_IDLE_FORCE_CLEAR_MASK;
 410         value = dm_read_reg(compressor->ctx, addr);
 411         set_reg_field_value(
 412                 value,
 413                 fbc_trigger |
 414                 FBC_IDLE_FORCE_GRPH_COMP_EN |
 415                 FBC_IDLE_FORCE_SRC_SEL_CHANGE |
 416                 FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE |
 417                 FBC_IDLE_FORCE_ALPHA_COMP_EN |
 418                 FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN |
 419                 FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF,
 420                 FBC_IDLE_FORCE_CLEAR_MASK,
 421                 FBC_IDLE_FORCE_CLEAR_MASK);
 422         dm_write_reg(compressor->ctx, addr, value);
 423 }
 424
 425 struct compressor *dce110_compressor_create(struct dc_context *ctx)
 426 {
 427         struct dce110_compressor *cp110 =
 428                 kzalloc(sizeof(struct dce110_compressor), GFP_KERNEL);
 429
 430         if (!cp110)
 431                 return NULL;
 432
 433         dce110_compressor_construct(cp110, ctx);
 434         return &cp110->base;
 435 }
 436
 437 void dce110_compressor_destroy(struct compressor **compressor)
 438 {
 439         kfree(TO_DCE110_COMPRESSOR(*compressor));
 440         *compressor = NULL;
 441 }
 442
 443 bool dce110_get_required_compressed_surfacesize(struct fbc_input_info fbc_input_info,
 444                                                 struct fbc_requested_compressed_size size)
 445 {
 446         bool result = false;
 447
 448         unsigned int max_x = FBC_MAX_X, max_y = FBC_MAX_Y;
 449
 450         get_max_support_fbc_buffersize(&max_x, &max_y);
 451
 452         if (fbc_input_info.dynamic_fbc_buffer_alloc == 0) {
 453                 /*
 454                  * For DCE11 here use Max HW supported size:  HW Support up to 3840x2400 resolution
 455                  * or 18000 chunks.
 456                  */
 457                 size.preferred_size = size.min_size = align_to_chunks_number_per_line(max_x) * max_y * 4;  /* (For FBC when LPT not supported). */
 458                 size.preferred_size_alignment = size.min_size_alignment = 0x100;       /* For FBC when LPT not supported */
 459                 size.bits.preferred_must_be_framebuffer_pool = 1;
 460                 size.bits.min_must_be_framebuffer_pool = 1;
 461
 462                 result = true;
 463         }
 464         /*
 465          * Maybe to add registry key support with optional size here to override above
 466          * for debugging purposes
 467          */
 468
 469         return result;
 470 }
 471
 472
 473 void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y)
 474 {
 475         *max_x = FBC_MAX_X;
 476         *max_y = FBC_MAX_Y;
 477
 478         /* if (m_smallLocalFrameBufferMemory == 1)
 479          * {
 480          *      *max_x = FBC_MAX_X_SG;
 481          *      *max_y = FBC_MAX_Y_SG;
 482          * }
 483          */
 484 }
 485
 486
 487 unsigned int controller_id_to_index(enum controller_id controller_id)
 488 {
 489         unsigned int index = 0;
 490
 491         switch (controller_id) {
 492         case CONTROLLER_ID_D0:
 493                 index = 0;
 494                 break;
 495         case CONTROLLER_ID_D1:
 496                 index = 1;
 497                 break;
 498         case CONTROLLER_ID_D2:
 499                 index = 2;
 500                 break;
 501         case CONTROLLER_ID_D3:
 502                 index = 3;
 503                 break;
 504         default:
 505                 break;
 506         }
 507         return index;
 508 }
 509
 510
 511 static const struct compressor_funcs dce110_compressor_funcs = {
 512         .power_up_fbc = dce110_compressor_power_up_fbc,
 513         .enable_fbc = dce110_compressor_enable_fbc,
 514         .disable_fbc = dce110_compressor_disable_fbc,
 515         .set_fbc_invalidation_triggers = dce110_compressor_set_fbc_invalidation_triggers,
 516         .surface_address_and_pitch = dce110_compressor_program_compressed_surface_address_and_pitch,
 517         .is_fbc_enabled_in_hw = dce110_compressor_is_fbc_enabled_in_hw
 518 };
 519
 520
 521 void dce110_compressor_construct(struct dce110_compressor *compressor,
 522         struct dc_context *ctx)
 523 {
 524
 525         compressor->base.options.raw = 0;
 526         compressor->base.options.bits.FBC_SUPPORT = true;
 527
 528         /* for dce 11 always use one dram channel for lpt */
 529         compressor->base.lpt_channels_num = 1;
 530         compressor->base.options.bits.DUMMY_BACKEND = false;
 531
 532         /*
 533          * check if this system has more than 1 dram channel; if only 1 then lpt
 534          * should not be supported
 535          */
 536
 537
 538         compressor->base.options.bits.CLK_GATING_DISABLED = false;
 539
 540         compressor->base.ctx = ctx;
 541         compressor->base.embedded_panel_h_size = 0;
 542         compressor->base.embedded_panel_v_size = 0;
 543         compressor->base.memory_bus_width = ctx->asic_id.vram_width;
 544         compressor->base.allocated_size = 0;
 545         compressor->base.preferred_requested_size = 0;
 546         compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
 547         compressor->base.banks_num = 0;
 548         compressor->base.raw_size = 0;
 549         compressor->base.channel_interleave_size = 0;
 550         compressor->base.dram_channels_num = 0;
 551         compressor->base.lpt_channels_num = 0;
 552         compressor->base.attached_inst = 0;
 553         compressor->base.is_enabled = false;
 554         compressor->base.funcs = &dce110_compressor_funcs;
 555
 556 }
 557