drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "dm_services.h"
  26 #include "dc.h"
  27 #include "core_types.h"
  28 #include "hw_sequencer.h"
  29 #include "dce100_hw_sequencer.h"
  30 #include "resource.h"
  31
  32 #include "dce110/dce110_hw_sequencer.h"
  33
  34 /* include DCE10 register header files */
  35 #include "dce/dce_10_0_d.h"
  36 #include "dce/dce_10_0_sh_mask.h"
  37
  38 struct dce100_hw_seq_reg_offsets {
  39         uint32_t blnd;
  40         uint32_t crtc;
  41 };
  42
  43 static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
  44 {
  45         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  46 },
  47 {
  48         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  49 },
  50 {
  51         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  52 },
  53 {
  54         .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  55 },
  56 {
  57         .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  58 },
  59 {
  60         .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
  61 }
  62 };
  63
  64 #define HW_REG_CRTC(reg, id)\
  65         (reg + reg_offsets[id].crtc)
  66
  67 /*******************************************************************************
  68  * Private definitions
  69  ******************************************************************************/
  70 /***************************PIPE_CONTROL***********************************/
  71
  72 bool dce100_enable_display_power_gating(
  73         struct dc *dc,
  74         uint8_t controller_id,
  75         struct dc_bios *dcb,
  76         enum pipe_gating_control power_gating)
  77 {
  78         enum bp_result bp_result = BP_RESULT_OK;
  79         enum bp_pipe_control_action cntl;
  80         struct dc_context *ctx = dc->ctx;
  81
  82         if (power_gating == PIPE_GATING_CONTROL_INIT)
  83                 cntl = ASIC_PIPE_INIT;
  84         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
  85                 cntl = ASIC_PIPE_ENABLE;
  86         else
  87                 cntl = ASIC_PIPE_DISABLE;
  88
  89         if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){
  90
  91                 bp_result = dcb->funcs->enable_disp_power_gating(
  92                                                 dcb, controller_id + 1, cntl);
  93
  94                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
  95                  * by default when command table is called
  96                  */
  97                 dm_write_reg(ctx,
  98                         HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id),
  99                         0);
 100         }
 101
 102         if (bp_result == BP_RESULT_OK)
 103                 return true;
 104         else
 105                 return false;
 106 }
 107
 108 static void dce100_pplib_apply_display_requirements(
 109         struct dc *dc,
 110         struct dc_state *context)
 111 {
 112         struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
 113
 114         pp_display_cfg->avail_mclk_switch_time_us =
 115                                                 dce110_get_min_vblank_time_us(context);
 116         /*pp_display_cfg->min_memory_clock_khz = context->bw.dce.yclk_khz
 117                 / MEMORY_TYPE_MULTIPLIER;*/
 118
 119         dce110_fill_display_configs(context, pp_display_cfg);
 120
 121         if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
 122                         struct dm_pp_display_configuration)) !=  0)
 123                 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
 124
 125         dc->prev_display_config = *pp_display_cfg;
 126 }
 127
 128 /* unit: in_khz before mode set, get pixel clock from context. ASIC register
 129  * may not be programmed yet
 130  */
 131 static uint32_t get_max_pixel_clock_for_all_paths(
 132         struct dc *dc,
 133         struct dc_state *context)
 134 {
 135         uint32_t max_pix_clk = 0;
 136         int i;
 137
 138         for (i = 0; i < MAX_PIPES; i++) {
 139                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 140
 141                 if (pipe_ctx->stream == NULL)
 142                         continue;
 143
 144                 /* do not check under lay */
 145                 if (pipe_ctx->top_pipe)
 146                         continue;
 147
 148                 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)
 149                         max_pix_clk =
 150                                 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
 151         }
 152         return max_pix_clk;
 153 }
 154
 155 void dce100_set_bandwidth(
 156                 struct dc *dc,
 157                 struct dc_state *context,
 158                 bool decrease_allowed)
 159 {
 160         struct dc_clocks req_clks;
 161
 162         req_clks.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100;
 163         req_clks.phyclk_khz = get_max_pixel_clock_for_all_paths(dc, context);
 164
 165         dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
 166
 167         dc->res_pool->dccg->funcs->update_clocks(
 168                         dc->res_pool->dccg,
 169                         &req_clks,
 170                         decrease_allowed);
 171
 172         dce100_pplib_apply_display_requirements(dc, context);
 173 }
 174
 175
 176 /**************************************************************************/
 177
 178 void dce100_hw_sequencer_construct(struct dc *dc)
 179 {
 180         dce110_hw_sequencer_construct(dc);
 181
 182         dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
 183         dc->hwss.set_bandwidth = dce100_set_bandwidth;
 184         dc->hwss.pplib_apply_display_requirements =
 185                         dce100_pplib_apply_display_requirements;
 186 }
 187