2 * Copyright 2012-16 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
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27 #ifndef _DCE_CLOCKS_H_
28 #define _DCE_CLOCKS_H_
30 #include "display_clock.h"
32 #define CLK_COMMON_REG_LIST_DCE_BASE() \
33 .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
34 .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
36 #define CLK_COMMON_REG_LIST_DCN_BASE() \
37 SR(DENTIST_DISPCLK_CNTL)
39 #define CLK_SF(reg_name, field_name, post_fix)\
40 .field_name = reg_name ## __ ## field_name ## post_fix
42 #define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
43 CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
44 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
46 #define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
47 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
48 CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
50 #define CLK_REG_FIELD_LIST(type) \
51 type DPREFCLK_SRC_SEL; \
52 type DENTIST_DPREFCLK_WDIVIDER; \
53 type DENTIST_DISPCLK_WDIVIDER; \
54 type DENTIST_DISPCLK_CHG_DONE;
57 CLK_REG_FIELD_LIST(uint8_t)
61 CLK_REG_FIELD_LIST(uint32_t)
64 struct dccg_registers {
65 uint32_t DPREFCLK_CNTL;
66 uint32_t DENTIST_DISPCLK_CNTL;
71 const struct dccg_registers *regs;
72 const struct dccg_shift *clk_shift;
73 const struct dccg_mask *clk_mask;
75 struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
77 int dentist_vco_freq_khz;
79 /* Cache the status of DFS-bypass feature*/
80 bool dfs_bypass_enabled;
81 /* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
82 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
83 int dfs_bypass_disp_clk;
85 /* Flag for Enabled SS on DPREFCLK */
87 /* DPREFCLK SS percentage (if down-spread enabled) */
88 int dprefclk_ss_percentage;
89 /* DPREFCLK SS percentage Divider (100 or 1000) */
90 int dprefclk_ss_divider;
94 struct dccg *dce_dccg_create(
95 struct dc_context *ctx,
96 const struct dccg_registers *regs,
97 const struct dccg_shift *clk_shift,
98 const struct dccg_mask *clk_mask);
100 struct dccg *dce110_dccg_create(
101 struct dc_context *ctx,
102 const struct dccg_registers *regs,
103 const struct dccg_shift *clk_shift,
104 const struct dccg_mask *clk_mask);
106 struct dccg *dce112_dccg_create(
107 struct dc_context *ctx,
108 const struct dccg_registers *regs,
109 const struct dccg_shift *clk_shift,
110 const struct dccg_mask *clk_mask);
112 struct dccg *dce120_dccg_create(struct dc_context *ctx);
114 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
115 struct dccg *dcn1_dccg_create(struct dc_context *ctx);
118 void dce_dccg_destroy(struct dccg **dccg);
120 #endif /* _DCE_CLOCKS_H_ */