drivers/gpu/drm/amd/display/dc/dce/dce_audio.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "reg_helper.h"
  27 #include "dce_audio.h"
  28 #include "dce/dce_11_0_d.h"
  29 #include "dce/dce_11_0_sh_mask.h"
  30
  31 #define DCE_AUD(audio)\
  32         container_of(audio, struct dce_audio, base)
  33
  34 #define CTX \
  35         aud->base.ctx
  36
  37 #define DC_LOGGER_INIT()
  38
  39 #define REG(reg)\
  40         (aud->regs->reg)
  41
  42 #undef FN
  43 #define FN(reg_name, field_name) \
  44         aud->shifts->field_name, aud->masks->field_name
  45
  46 #define IX_REG(reg)\
  47         ix ## reg
  48
  49 #define AZ_REG_READ(reg_name) \
  50                 read_indirect_azalia_reg(audio, IX_REG(reg_name))
  51
  52 #define AZ_REG_WRITE(reg_name, value) \
  53                 write_indirect_azalia_reg(audio, IX_REG(reg_name), value)
  54
  55 static void write_indirect_azalia_reg(struct audio *audio,
  56         uint32_t reg_index,
  57         uint32_t reg_data)
  58 {
  59         struct dce_audio *aud = DCE_AUD(audio);
  60
  61         /* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
  62         REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
  63                         AZALIA_ENDPOINT_REG_INDEX, reg_index);
  64
  65         /* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
  66         REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,
  67                         AZALIA_ENDPOINT_REG_DATA, reg_data);
  68
  69         DC_LOG_HW_AUDIO("AUDIO:write_indirect_azalia_reg: index: %u  data: %u\n",
  70                 reg_index, reg_data);
  71 }
  72
  73 static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index)
  74 {
  75         struct dce_audio *aud = DCE_AUD(audio);
  76
  77         uint32_t value = 0;
  78
  79         /* AZALIA_F0_CODEC_ENDPOINT_INDEX  endpoint index  */
  80         REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
  81                         AZALIA_ENDPOINT_REG_INDEX, reg_index);
  82
  83         /* AZALIA_F0_CODEC_ENDPOINT_DATA  endpoint data  */
  84         value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
  85
  86         DC_LOG_HW_AUDIO("AUDIO:read_indirect_azalia_reg: index: %u  data: %u\n",
  87                 reg_index, value);
  88
  89         return value;
  90 }
  91
  92 static bool is_audio_format_supported(
  93         const struct audio_info *audio_info,
  94         enum audio_format_code audio_format_code,
  95         uint32_t *format_index)
  96 {
  97         uint32_t index;
  98         uint32_t max_channe_index = 0;
  99         bool found = false;
 100
 101         if (audio_info == NULL)
 102                 return found;
 103
 104         /* pass through whole array */
 105         for (index = 0; index < audio_info->mode_count; index++) {
 106                 if (audio_info->modes[index].format_code == audio_format_code) {
 107                         if (found) {
 108                                 /* format has multiply entries, choose one with
 109                                  *  highst number of channels */
 110                                 if (audio_info->modes[index].channel_count >
 111                 audio_info->modes[max_channe_index].channel_count) {
 112                                         max_channe_index = index;
 113                                 }
 114                         } else {
 115                                 /* format found, save it's index */
 116                                 found = true;
 117                                 max_channe_index = index;
 118                         }
 119                 }
 120         }
 121
 122         /* return index */
 123         if (found && format_index != NULL)
 124                 *format_index = max_channe_index;
 125
 126         return found;
 127 }
 128
 129 /*For HDMI, calculate if specified sample rates can fit into a given timing */
 130 static void check_audio_bandwidth_hdmi(
 131         const struct audio_crtc_info *crtc_info,
 132         uint32_t channel_count,
 133         union audio_sample_rates *sample_rates)
 134 {
 135         uint32_t samples;
 136         uint32_t  h_blank;
 137         bool limit_freq_to_48_khz = false;
 138         bool limit_freq_to_88_2_khz = false;
 139         bool limit_freq_to_96_khz = false;
 140         bool limit_freq_to_174_4_khz = false;
 141
 142         /* For two channels supported return whatever sink support,unmodified*/
 143         if (channel_count > 2) {
 144
 145                 /* Based on HDMI spec 1.3 Table 7.5 */
 146                 if ((crtc_info->requested_pixel_clock <= 27000) &&
 147                 (crtc_info->v_active <= 576) &&
 148                 !(crtc_info->interlaced) &&
 149                 !(crtc_info->pixel_repetition == 2 ||
 150                 crtc_info->pixel_repetition == 4)) {
 151                         limit_freq_to_48_khz = true;
 152
 153                 } else if ((crtc_info->requested_pixel_clock <= 27000) &&
 154                                 (crtc_info->v_active <= 576) &&
 155                                 (crtc_info->interlaced) &&
 156                                 (crtc_info->pixel_repetition == 2)) {
 157                         limit_freq_to_88_2_khz = true;
 158
 159                 } else if ((crtc_info->requested_pixel_clock <= 54000) &&
 160                                 (crtc_info->v_active <= 576) &&
 161                                 !(crtc_info->interlaced)) {
 162                         limit_freq_to_174_4_khz = true;
 163                 }
 164         }
 165
 166         /* Also do some calculation for the available Audio Bandwidth for the
 167          * 8 ch (i.e. for the Layout 1 => ch > 2)
 168          */
 169         h_blank = crtc_info->h_total - crtc_info->h_active;
 170
 171         if (crtc_info->pixel_repetition)
 172                 h_blank *= crtc_info->pixel_repetition;
 173
 174         /*based on HDMI spec 1.3 Table 7.5 */
 175         h_blank -= 58;
 176         /*for Control Period */
 177         h_blank -= 16;
 178
 179         samples = h_blank * 10;
 180         /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
 181          * of Audio samples per line multiplied by 10 - Layout 1)
 182          */
 183         samples /= 32;
 184         samples *= crtc_info->v_active;
 185         /*Number of samples multiplied by 10, per second */
 186         samples *= crtc_info->refresh_rate;
 187         /*Number of Audio samples per second */
 188         samples /= 10;
 189
 190         /* @todo do it after deep color is implemented
 191          * 8xx - deep color bandwidth scaling
 192          * Extra bandwidth is avaliable in deep color b/c link runs faster than
 193          * pixel rate. This has the effect of allowing more tmds characters to
 194          * be transmitted during blank
 195          */
 196
 197         switch (crtc_info->color_depth) {
 198         case COLOR_DEPTH_888:
 199                 samples *= 4;
 200                 break;
 201         case COLOR_DEPTH_101010:
 202                 samples *= 5;
 203                 break;
 204         case COLOR_DEPTH_121212:
 205                 samples *= 6;
 206                 break;
 207         default:
 208                 samples *= 4;
 209                 break;
 210         }
 211
 212         samples /= 4;
 213
 214         /*check limitation*/
 215         if (samples < 88200)
 216                 limit_freq_to_48_khz = true;
 217         else if (samples < 96000)
 218                 limit_freq_to_88_2_khz = true;
 219         else if (samples < 176400)
 220                 limit_freq_to_96_khz = true;
 221         else if (samples < 192000)
 222                 limit_freq_to_174_4_khz = true;
 223
 224         if (sample_rates != NULL) {
 225                 /* limit frequencies */
 226                 if (limit_freq_to_174_4_khz)
 227                         sample_rates->rate.RATE_192 = 0;
 228
 229                 if (limit_freq_to_96_khz) {
 230                         sample_rates->rate.RATE_192 = 0;
 231                         sample_rates->rate.RATE_176_4 = 0;
 232                 }
 233                 if (limit_freq_to_88_2_khz) {
 234                         sample_rates->rate.RATE_192 = 0;
 235                         sample_rates->rate.RATE_176_4 = 0;
 236                         sample_rates->rate.RATE_96 = 0;
 237                 }
 238                 if (limit_freq_to_48_khz) {
 239                         sample_rates->rate.RATE_192 = 0;
 240                         sample_rates->rate.RATE_176_4 = 0;
 241                         sample_rates->rate.RATE_96 = 0;
 242                         sample_rates->rate.RATE_88_2 = 0;
 243                 }
 244         }
 245 }
 246
 247 /*For DP SST, calculate if specified sample rates can fit into a given timing */
 248 static void check_audio_bandwidth_dpsst(
 249         const struct audio_crtc_info *crtc_info,
 250         uint32_t channel_count,
 251         union audio_sample_rates *sample_rates)
 252 {
 253         /* do nothing */
 254 }
 255
 256 /*For DP MST, calculate if specified sample rates can fit into a given timing */
 257 static void check_audio_bandwidth_dpmst(
 258         const struct audio_crtc_info *crtc_info,
 259         uint32_t channel_count,
 260         union audio_sample_rates *sample_rates)
 261 {
 262         /* do nothing  */
 263 }
 264
 265 static void check_audio_bandwidth(
 266         const struct audio_crtc_info *crtc_info,
 267         uint32_t channel_count,
 268         enum signal_type signal,
 269         union audio_sample_rates *sample_rates)
 270 {
 271         switch (signal) {
 272         case SIGNAL_TYPE_HDMI_TYPE_A:
 273                 check_audio_bandwidth_hdmi(
 274                         crtc_info, channel_count, sample_rates);
 275                 break;
 276         case SIGNAL_TYPE_EDP:
 277         case SIGNAL_TYPE_DISPLAY_PORT:
 278                 check_audio_bandwidth_dpsst(
 279                         crtc_info, channel_count, sample_rates);
 280                 break;
 281         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 282                 check_audio_bandwidth_dpmst(
 283                         crtc_info, channel_count, sample_rates);
 284                 break;
 285         default:
 286                 break;
 287         }
 288 }
 289
 290 /* expose/not expose HBR capability to Audio driver */
 291 static void set_high_bit_rate_capable(
 292         struct audio *audio,
 293         bool capable)
 294 {
 295         uint32_t value = 0;
 296
 297         /* set high bit rate audio capable*/
 298         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR);
 299
 300         set_reg_field_value(value, capable,
 301                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
 302                 HBR_CAPABLE);
 303
 304         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value);
 305 }
 306
 307 /* set video latency in in ms/2+1 */
 308 static void set_video_latency(
 309         struct audio *audio,
 310         int latency_in_ms)
 311 {
 312         uint32_t value = 0;
 313
 314         if ((latency_in_ms < 0) || (latency_in_ms > 255))
 315                 return;
 316
 317         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
 318
 319         set_reg_field_value(value, latency_in_ms,
 320                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
 321                 VIDEO_LIPSYNC);
 322
 323         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
 324                 value);
 325 }
 326
 327 /* set audio latency in in ms/2+1 */
 328 static void set_audio_latency(
 329         struct audio *audio,
 330         int latency_in_ms)
 331 {
 332         uint32_t value = 0;
 333
 334         if (latency_in_ms < 0)
 335                 latency_in_ms = 0;
 336
 337         if (latency_in_ms > 255)
 338                 latency_in_ms = 255;
 339
 340         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
 341
 342         set_reg_field_value(value, latency_in_ms,
 343                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
 344                 AUDIO_LIPSYNC);
 345
 346         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
 347                 value);
 348 }
 349
 350 void dce_aud_az_enable(struct audio *audio)
 351 {
 352         uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 353         DC_LOGGER_INIT();
 354
 355         set_reg_field_value(value, 1,
 356                             AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 357                             CLOCK_GATING_DISABLE);
 358         set_reg_field_value(value, 1,
 359                             AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 360                             AUDIO_ENABLED);
 361
 362         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 363         set_reg_field_value(value, 0,
 364                         AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 365                         CLOCK_GATING_DISABLE);
 366         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 367
 368         DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_enable: index: %u  data: 0x%x\n",
 369                         audio->inst, value);
 370 }
 371
 372 void dce_aud_az_disable(struct audio *audio)
 373 {
 374         uint32_t value;
 375         DC_LOGGER_INIT();
 376
 377         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 378         set_reg_field_value(value, 1,
 379                         AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 380                         CLOCK_GATING_DISABLE);
 381         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 382
 383         set_reg_field_value(value, 0,
 384                 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 385                 AUDIO_ENABLED);
 386         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 387
 388         set_reg_field_value(value, 0,
 389                         AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 390                         CLOCK_GATING_DISABLE);
 391         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 392         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 393         DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_disable: index: %u  data: 0x%x\n",
 394                         audio->inst, value);
 395 }
 396
 397 void dce_aud_az_configure(
 398         struct audio *audio,
 399         enum signal_type signal,
 400         const struct audio_crtc_info *crtc_info,
 401         const struct audio_info *audio_info)
 402 {
 403         struct dce_audio *aud = DCE_AUD(audio);
 404
 405         uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;
 406         uint32_t value;
 407         uint32_t field = 0;
 408         enum audio_format_code audio_format_code;
 409         uint32_t format_index;
 410         uint32_t index;
 411         bool is_ac3_supported = false;
 412         union audio_sample_rates sample_rate;
 413         uint32_t strlen = 0;
 414         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 415         set_reg_field_value(value, 1,
 416                         AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 417                         CLOCK_GATING_DISABLE);
 418         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 419
 420         /* Speaker Allocation */
 421         /*
 422         uint32_t value;
 423         uint32_t field = 0;*/
 424         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
 425
 426         set_reg_field_value(value,
 427                 speakers,
 428                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 429                 SPEAKER_ALLOCATION);
 430
 431         /* LFE_PLAYBACK_LEVEL = LFEPBL
 432          * LFEPBL = 0 : Unknown or refer to other information
 433          * LFEPBL = 1 : 0dB playback
 434          * LFEPBL = 2 : +10dB playback
 435          * LFE_BL = 3 : Reserved
 436          */
 437         set_reg_field_value(value,
 438                 0,
 439                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 440                 LFE_PLAYBACK_LEVEL);
 441         /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only.
 442          *  why are we writing to it?  DCE8 does not write this */
 443
 444
 445         set_reg_field_value(value,
 446                 0,
 447                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 448                 HDMI_CONNECTION);
 449
 450         set_reg_field_value(value,
 451                 0,
 452                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 453                 DP_CONNECTION);
 454
 455         field = get_reg_field_value(value,
 456                         AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 457                         EXTRA_CONNECTION_INFO);
 458
 459         field &= ~0x1;
 460
 461         set_reg_field_value(value,
 462                 field,
 463                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 464                 EXTRA_CONNECTION_INFO);
 465
 466         /* set audio for output signal */
 467         switch (signal) {
 468         case SIGNAL_TYPE_HDMI_TYPE_A:
 469                 set_reg_field_value(value,
 470                         1,
 471                         AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 472                         HDMI_CONNECTION);
 473
 474                 break;
 475
 476         case SIGNAL_TYPE_EDP:
 477         case SIGNAL_TYPE_DISPLAY_PORT:
 478         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 479                 set_reg_field_value(value,
 480                         1,
 481                         AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
 482                         DP_CONNECTION);
 483                 break;
 484         default:
 485                 BREAK_TO_DEBUGGER();
 486                 break;
 487         }
 488
 489         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value);
 490
 491         /*  Audio Descriptors   */
 492         /* pass through all formats */
 493         for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
 494                         format_index++) {
 495                 audio_format_code =
 496                         (AUDIO_FORMAT_CODE_FIRST + format_index);
 497
 498                 /* those are unsupported, skip programming */
 499                 if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO ||
 500                         audio_format_code == AUDIO_FORMAT_CODE_DST)
 501                         continue;
 502
 503                 value = 0;
 504
 505                 /* check if supported */
 506                 if (is_audio_format_supported(
 507                                 audio_info, audio_format_code, &index)) {
 508                         const struct audio_mode *audio_mode =
 509                                         &audio_info->modes[index];
 510                         union audio_sample_rates sample_rates =
 511                                         audio_mode->sample_rates;
 512                         uint8_t byte2 = audio_mode->max_bit_rate;
 513
 514                         /* adjust specific properties */
 515                         switch (audio_format_code) {
 516                         case AUDIO_FORMAT_CODE_LINEARPCM: {
 517                                 check_audio_bandwidth(
 518                                         crtc_info,
 519                                         audio_mode->channel_count,
 520                                         signal,
 521                                         &sample_rates);
 522
 523                                 byte2 = audio_mode->sample_size;
 524
 525                                 set_reg_field_value(value,
 526                                                 sample_rates.all,
 527                                                 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
 528                                                 SUPPORTED_FREQUENCIES_STEREO);
 529                                 }
 530                                 break;
 531                         case AUDIO_FORMAT_CODE_AC3:
 532                                 is_ac3_supported = true;
 533                                 break;
 534                         case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS:
 535                         case AUDIO_FORMAT_CODE_DTS_HD:
 536                         case AUDIO_FORMAT_CODE_MAT_MLP:
 537                         case AUDIO_FORMAT_CODE_DST:
 538                         case AUDIO_FORMAT_CODE_WMAPRO:
 539                                 byte2 = audio_mode->vendor_specific;
 540                                 break;
 541                         default:
 542                                 break;
 543                         }
 544
 545                         /* fill audio format data */
 546                         set_reg_field_value(value,
 547                                         audio_mode->channel_count - 1,
 548                                         AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
 549                                         MAX_CHANNELS);
 550
 551                         set_reg_field_value(value,
 552                                         sample_rates.all,
 553                                         AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
 554                                         SUPPORTED_FREQUENCIES);
 555
 556                         set_reg_field_value(value,
 557                                         byte2,
 558                                         AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
 559                                         DESCRIPTOR_BYTE_2);
 560                 } /* if */
 561
 562                 AZ_REG_WRITE(
 563                                 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index,
 564                                 value);
 565         } /* for */
 566
 567         if (is_ac3_supported)
 568                 /* todo: this reg global.  why program global register? */
 569                 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
 570                                 0x05);
 571
 572         /* check for 192khz/8-Ch support for HBR requirements */
 573         sample_rate.all = 0;
 574         sample_rate.rate.RATE_192 = 1;
 575
 576         check_audio_bandwidth(
 577                 crtc_info,
 578                 8,
 579                 signal,
 580                 &sample_rate);
 581
 582         set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192);
 583
 584         /* Audio and Video Lipsync */
 585         set_video_latency(audio, audio_info->video_latency);
 586         set_audio_latency(audio, audio_info->audio_latency);
 587
 588         value = 0;
 589         set_reg_field_value(value, audio_info->manufacture_id,
 590                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
 591                 MANUFACTURER_ID);
 592
 593         set_reg_field_value(value, audio_info->product_id,
 594                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
 595                 PRODUCT_ID);
 596
 597         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
 598                 value);
 599
 600         value = 0;
 601
 602         /*get display name string length */
 603         while (audio_info->display_name[strlen++] != '\0') {
 604                 if (strlen >=
 605                 MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS)
 606                         break;
 607                 }
 608         set_reg_field_value(value, strlen,
 609                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
 610                 SINK_DESCRIPTION_LEN);
 611
 612         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
 613                 value);
 614         DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n",
 615                 audio->inst, value, audio_info->display_name);
 616
 617         /*
 618         *write the port ID:
 619         *PORT_ID0 = display index
 620         *PORT_ID1 = 16bit BDF
 621         *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function)
 622         */
 623
 624         value = 0;
 625
 626         set_reg_field_value(value, audio_info->port_id[0],
 627                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
 628                 PORT_ID0);
 629
 630         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value);
 631
 632         value = 0;
 633         set_reg_field_value(value, audio_info->port_id[1],
 634                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
 635                 PORT_ID1);
 636
 637         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value);
 638
 639         /*write the 18 char monitor string */
 640
 641         value = 0;
 642         set_reg_field_value(value, audio_info->display_name[0],
 643                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
 644                 DESCRIPTION0);
 645
 646         set_reg_field_value(value, audio_info->display_name[1],
 647                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
 648                 DESCRIPTION1);
 649
 650         set_reg_field_value(value, audio_info->display_name[2],
 651                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
 652                 DESCRIPTION2);
 653
 654         set_reg_field_value(value, audio_info->display_name[3],
 655                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
 656                 DESCRIPTION3);
 657
 658         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value);
 659
 660         value = 0;
 661         set_reg_field_value(value, audio_info->display_name[4],
 662                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
 663                 DESCRIPTION4);
 664
 665         set_reg_field_value(value, audio_info->display_name[5],
 666                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
 667                 DESCRIPTION5);
 668
 669         set_reg_field_value(value, audio_info->display_name[6],
 670                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
 671                 DESCRIPTION6);
 672
 673         set_reg_field_value(value, audio_info->display_name[7],
 674                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
 675                 DESCRIPTION7);
 676
 677         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value);
 678
 679         value = 0;
 680         set_reg_field_value(value, audio_info->display_name[8],
 681                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
 682                 DESCRIPTION8);
 683
 684         set_reg_field_value(value, audio_info->display_name[9],
 685                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
 686                 DESCRIPTION9);
 687
 688         set_reg_field_value(value, audio_info->display_name[10],
 689                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
 690                 DESCRIPTION10);
 691
 692         set_reg_field_value(value, audio_info->display_name[11],
 693                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
 694                 DESCRIPTION11);
 695
 696         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value);
 697
 698         value = 0;
 699         set_reg_field_value(value, audio_info->display_name[12],
 700                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
 701                 DESCRIPTION12);
 702
 703         set_reg_field_value(value, audio_info->display_name[13],
 704                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
 705                 DESCRIPTION13);
 706
 707         set_reg_field_value(value, audio_info->display_name[14],
 708                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
 709                 DESCRIPTION14);
 710
 711         set_reg_field_value(value, audio_info->display_name[15],
 712                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
 713                 DESCRIPTION15);
 714
 715         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value);
 716
 717         value = 0;
 718         set_reg_field_value(value, audio_info->display_name[16],
 719                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
 720                 DESCRIPTION16);
 721
 722         set_reg_field_value(value, audio_info->display_name[17],
 723                 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
 724                 DESCRIPTION17);
 725
 726         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value);
 727         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 728         set_reg_field_value(value, 0,
 729                         AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 730                         CLOCK_GATING_DISABLE);
 731         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 732 }
 733
 734 /*
 735 * todo: wall clk related functionality probably belong to clock_src.
 736 */
 737
 738 /* search pixel clock value for Azalia HDMI Audio */
 739 static void get_azalia_clock_info_hdmi(
 740         uint32_t crtc_pixel_clock_in_khz,
 741         uint32_t actual_pixel_clock_in_khz,
 742         struct azalia_clock_info *azalia_clock_info)
 743 {
 744         /* audio_dto_phase= 24 * 10,000;
 745          *   24MHz in [100Hz] units */
 746         azalia_clock_info->audio_dto_phase =
 747                         24 * 10000;
 748
 749         /* audio_dto_module = PCLKFrequency * 10,000;
 750          *  [khz] -> [100Hz] */
 751         azalia_clock_info->audio_dto_module =
 752                         actual_pixel_clock_in_khz * 10;
 753 }
 754
 755 static void get_azalia_clock_info_dp(
 756         uint32_t requested_pixel_clock_in_khz,
 757         const struct audio_pll_info *pll_info,
 758         struct azalia_clock_info *azalia_clock_info)
 759 {
 760         /* Reported dpDtoSourceClockInkhz value for
 761          * DCE8 already adjusted for SS, do not need any
 762          * adjustment here anymore
 763          */
 764
 765         /*audio_dto_phase = 24 * 10,000;
 766          * 24MHz in [100Hz] units */
 767         azalia_clock_info->audio_dto_phase = 24 * 10000;
 768
 769         /*audio_dto_module = dpDtoSourceClockInkhz * 10,000;
 770          *  [khz] ->[100Hz] */
 771         azalia_clock_info->audio_dto_module =
 772                 pll_info->dp_dto_source_clock_in_khz * 10;
 773 }
 774
 775 void dce_aud_wall_dto_setup(
 776         struct audio *audio,
 777         enum signal_type signal,
 778         const struct audio_crtc_info *crtc_info,
 779         const struct audio_pll_info *pll_info)
 780 {
 781         struct dce_audio *aud = DCE_AUD(audio);
 782
 783         struct azalia_clock_info clock_info = { 0 };
 784
 785         if (dc_is_hdmi_signal(signal)) {
 786                 uint32_t src_sel;
 787
 788                 /*DTO0 Programming goal:
 789                 -generate 24MHz, 128*Fs from 24MHz
 790                 -use DTO0 when an active HDMI port is connected
 791                 (optionally a DP is connected) */
 792
 793                 /* calculate DTO settings */
 794                 get_azalia_clock_info_hdmi(
 795                         crtc_info->requested_pixel_clock,
 796                         crtc_info->calculated_pixel_clock,
 797                         &clock_info);
 798
 799                 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock = %d"\
 800                                 "calculated_pixel_clock =%d\n"\
 801                                 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
 802                                 crtc_info->requested_pixel_clock,\
 803                                 crtc_info->calculated_pixel_clock,\
 804                                 clock_info.audio_dto_module,\
 805                                 clock_info.audio_dto_phase);
 806
 807                 /* On TN/SI, Program DTO source select and DTO select before
 808                 programming DTO modulo and DTO phase. These bits must be
 809                 programmed first, otherwise there will be no HDMI audio at boot
 810                 up. This is a HW sequence change (different from old ASICs).
 811                 Caution when changing this programming sequence.
 812
 813                 HDMI enabled, using DTO0
 814                 program master CRTC for DTO0 */
 815                 src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
 816                 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
 817                         DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
 818                         DCCG_AUDIO_DTO_SEL, 0);
 819
 820                 /* module */
 821                 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
 822                         DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
 823
 824                 /* phase */
 825                 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
 826                         DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
 827         } else {
 828                 /*DTO1 Programming goal:
 829                 -generate 24MHz, 512*Fs, 128*Fs from 24MHz
 830                 -default is to used DTO1, and switch to DTO0 when an audio
 831                 master HDMI port is connected
 832                 -use as default for DP
 833
 834                 calculate DTO settings */
 835                 get_azalia_clock_info_dp(
 836                         crtc_info->requested_pixel_clock,
 837                         pll_info,
 838                         &clock_info);
 839
 840                 /* Program DTO select before programming DTO modulo and DTO
 841                 phase. default to use DTO1 */
 842
 843                 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
 844                                 DCCG_AUDIO_DTO_SEL, 1);
 845
 846                 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
 847                         DCCG_AUDIO_DTO_SEL, 1);
 848                         /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
 849                          * Select 512fs for DP TODO: web register definition
 850                          * does not match register header file
 851                          * DCE11 version it's commented out while DCE8 it's set to 1
 852                         */
 853
 854                 /* module */
 855                 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
 856                                 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
 857
 858                 /* phase */
 859                 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
 860                                 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
 861
 862                 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
 863                                 DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1);
 864
 865         }
 866 }
 867
 868 static bool dce_aud_endpoint_valid(struct audio *audio)
 869 {
 870         uint32_t value;
 871         uint32_t port_connectivity;
 872
 873         value = AZ_REG_READ(
 874                         AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
 875
 876         port_connectivity = get_reg_field_value(value,
 877                         AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
 878                         PORT_CONNECTIVITY);
 879
 880         return !(port_connectivity == 1);
 881 }
 882
 883 /* initialize HW state */
 884 void dce_aud_hw_init(
 885                 struct audio *audio)
 886 {
 887         uint32_t value;
 888         struct dce_audio *aud = DCE_AUD(audio);
 889
 890         /* we only need to program the following registers once, so we only do
 891         it for the inst 0*/
 892         if (audio->inst != 0)
 893                 return;
 894
 895         /* Suport R5 - 32khz
 896          * Suport R6 - 44.1khz
 897          * Suport R7 - 48khz
 898          */
 899         /*disable clock gating before write to endpoint register*/
 900         value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
 901         set_reg_field_value(value, 1,
 902                         AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 903                         CLOCK_GATING_DISABLE);
 904         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 905         REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
 906                         AUDIO_RATE_CAPABILITIES, 0x70);
 907
 908         /*Keep alive bit to verify HW block in BU. */
 909         REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
 910                         CLKSTOP, 1,
 911                         EPSS, 1);
 912         set_reg_field_value(value, 0,
 913                         AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
 914                         CLOCK_GATING_DISABLE);
 915         AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 916 }
 917
 918 static const struct audio_funcs funcs = {
 919         .endpoint_valid = dce_aud_endpoint_valid,
 920         .hw_init = dce_aud_hw_init,
 921         .wall_dto_setup = dce_aud_wall_dto_setup,
 922         .az_enable = dce_aud_az_enable,
 923         .az_disable = dce_aud_az_disable,
 924         .az_configure = dce_aud_az_configure,
 925         .destroy = dce_aud_destroy,
 926 };
 927 void dce_aud_destroy(struct audio **audio)
 928 {
 929         struct dce_audio *aud = DCE_AUD(*audio);
 930
 931         kfree(aud);
 932         *audio = NULL;
 933 }
 934
 935 struct audio *dce_audio_create(
 936                 struct dc_context *ctx,
 937                 unsigned int inst,
 938                 const struct dce_audio_registers *reg,
 939                 const struct dce_audio_shift *shifts,
 940                 const struct dce_aduio_mask *masks
 941                 )
 942 {
 943         struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
 944
 945         if (audio == NULL) {
 946                 ASSERT_CRITICAL(audio);
 947                 return NULL;
 948         }
 949
 950         audio->base.ctx = ctx;
 951         audio->base.inst = inst;
 952         audio->base.funcs = &funcs;
 953
 954         audio->regs = reg;
 955         audio->shifts = shifts;
 956         audio->masks = masks;
 957         return &audio->base;
 958 }
 959