drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

   1 /*
   2  * Copyright 2012-16 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dce_abm.h"
  27 #include "dm_services.h"
  28 #include "reg_helper.h"
  29 #include "fixed31_32.h"
  30 #include "dc.h"
  31
  32 #include "atom.h"
  33
  34
  35 #define TO_DCE_ABM(abm)\
  36         container_of(abm, struct dce_abm, base)
  37
  38 #define REG(reg) \
  39         (abm_dce->regs->reg)
  40
  41 #undef FN
  42 #define FN(reg_name, field_name) \
  43         abm_dce->abm_shift->field_name, abm_dce->abm_mask->field_name
  44
  45 #define DC_LOGGER \
  46         abm->ctx->logger
  47 #define CTX \
  48         abm_dce->base.ctx
  49
  50 #define MCP_ABM_LEVEL_SET 0x65
  51 #define MCP_ABM_PIPE_SET 0x66
  52 #define MCP_BL_SET 0x67
  53
  54 #define MCP_DISABLE_ABM_IMMEDIATELY 255
  55
  56
  57 static unsigned int get_current_backlight_16_bit(struct dce_abm *abm_dce)
  58 {
  59         uint64_t current_backlight;
  60         uint32_t round_result;
  61         uint32_t pwm_period_cntl, bl_period, bl_int_count;
  62         uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en;
  63         uint32_t bl_period_mask, bl_pwm_mask;
  64
  65         pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);
  66         REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
  67         REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
  68
  69         bl_pwm_cntl = REG_READ(BL_PWM_CNTL);
  70         REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm));
  71         REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);
  72
  73         if (bl_int_count == 0)
  74                 bl_int_count = 16;
  75
  76         bl_period_mask = (1 << bl_int_count) - 1;
  77         bl_period &= bl_period_mask;
  78
  79         bl_pwm_mask = bl_period_mask << (16 - bl_int_count);
  80
  81         if (fractional_duty_cycle_en == 0)
  82                 bl_pwm &= bl_pwm_mask;
  83         else
  84                 bl_pwm &= 0xFFFF;
  85
  86         current_backlight = bl_pwm << (1 + bl_int_count);
  87
  88         if (bl_period == 0)
  89                 bl_period = 0xFFFF;
  90
  91         current_backlight = div_u64(current_backlight, bl_period);
  92         current_backlight = (current_backlight + 1) >> 1;
  93
  94         current_backlight = (uint64_t)(current_backlight) * bl_period;
  95
  96         round_result = (uint32_t)(current_backlight & 0xFFFFFFFF);
  97
  98         round_result = (round_result >> (bl_int_count-1)) & 1;
  99
 100         current_backlight >>= bl_int_count;
 101         current_backlight += round_result;
 102
 103         return (uint32_t)(current_backlight);
 104 }
 105
 106 static void driver_set_backlight_level(struct dce_abm *abm_dce, uint32_t level)
 107 {
 108         uint32_t backlight_24bit;
 109         uint32_t backlight_17bit;
 110         uint32_t backlight_16bit;
 111         uint32_t masked_pwm_period;
 112         uint8_t rounding_bit;
 113         uint8_t bit_count;
 114         uint64_t active_duty_cycle;
 115         uint32_t pwm_period_bitcnt;
 116
 117         /*
 118          * 1. Convert 8-bit value to 17 bit U1.16 format
 119          * (1 integer, 16 fractional bits)
 120          */
 121
 122         /* 1.1 multiply 8 bit value by 0x10101 to get a 24 bit value,
 123          * effectively multiplying value by 256/255
 124          * eg. for a level of 0xEF, backlight_24bit = 0xEF * 0x10101 = 0xEFEFEF
 125          */
 126         backlight_24bit = level * 0x10101;
 127
 128         /* 1.2 The upper 16 bits of the 24 bit value is the fraction, lower 8
 129          * used for rounding, take most significant bit of fraction for
 130          * rounding, e.g. for 0xEFEFEF, rounding bit is 1
 131          */
 132         rounding_bit = (backlight_24bit >> 7) & 1;
 133
 134         /* 1.3 Add the upper 16 bits of the 24 bit value with the rounding bit
 135          * resulting in a 17 bit value e.g. 0xEFF0 = (0xEFEFEF >> 8) + 1
 136          */
 137         backlight_17bit = (backlight_24bit >> 8) + rounding_bit;
 138
 139         /*
 140          * 2. Find  16 bit backlight active duty cycle, where 0 <= backlight
 141          * active duty cycle <= backlight period
 142          */
 143
 144         /* 2.1 Apply bitmask for backlight period value based on value of BITCNT
 145          */
 146         REG_GET_2(BL_PWM_PERIOD_CNTL,
 147                         BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt,
 148                         BL_PWM_PERIOD, &masked_pwm_period);
 149
 150         if (pwm_period_bitcnt == 0)
 151                 bit_count = 16;
 152         else
 153                 bit_count = pwm_period_bitcnt;
 154
 155         /* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */
 156         masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1);
 157
 158         /* 2.2 Calculate integer active duty cycle required upper 16 bits
 159          * contain integer component, lower 16 bits contain fractional component
 160          * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24
 161          */
 162         active_duty_cycle = backlight_17bit * masked_pwm_period;
 163
 164         /* 2.3 Calculate 16 bit active duty cycle from integer and fractional
 165          * components shift by bitCount then mask 16 bits and add rounding bit
 166          * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0
 167          */
 168         backlight_16bit = active_duty_cycle >> bit_count;
 169         backlight_16bit &= 0xFFFF;
 170         backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1;
 171
 172         /*
 173          * 3. Program register with updated value
 174          */
 175
 176         /* 3.1 Lock group 2 backlight registers */
 177
 178         REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK,
 179                         BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1,
 180                         BL_PWM_GRP1_REG_LOCK, 1);
 181
 182         // 3.2 Write new active duty cycle
 183         REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit);
 184
 185         /* 3.3 Unlock group 2 backlight registers */
 186         REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
 187                         BL_PWM_GRP1_REG_LOCK, 0);
 188
 189         /* 5.4.4 Wait for pending bit to be cleared */
 190         REG_WAIT(BL_PWM_GRP1_REG_LOCK,
 191                         BL_PWM_GRP1_REG_UPDATE_PENDING, 0,
 192                         1, 10000);
 193 }
 194
 195 static void dmcu_set_backlight_level(
 196         struct dce_abm *abm_dce,
 197         uint32_t level,
 198         uint32_t frame_ramp,
 199         uint32_t controller_id)
 200 {
 201         unsigned int backlight_16_bit = (level * 0x10101) >> 8;
 202         unsigned int backlight_17_bit = backlight_16_bit +
 203                                 (((backlight_16_bit & 0x80) >> 7) & 1);
 204         uint32_t rampingBoundary = 0xFFFF;
 205         uint32_t s2;
 206
 207         /* set ramping boundary */
 208         REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary);
 209
 210         /* setDMCUParam_Pipe */
 211         REG_UPDATE_2(MASTER_COMM_CMD_REG,
 212                         MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_PIPE_SET,
 213                         MASTER_COMM_CMD_REG_BYTE1, controller_id);
 214
 215         /* notifyDMCUMsg */
 216         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 217
 218         /* waitDMCUReadyForCmd */
 219         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
 220                         0, 1, 80000);
 221
 222         /* setDMCUParam_BL */
 223         REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_17_bit);
 224
 225         /* write ramp */
 226         if (controller_id == 0)
 227                 frame_ramp = 0;
 228         REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp);
 229
 230         /* setDMCUParam_Cmd */
 231         REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET);
 232
 233         /* notifyDMCUMsg */
 234         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 235
 236         /* UpdateRequestedBacklightLevel */
 237         s2 = REG_READ(BIOS_SCRATCH_2);
 238
 239         s2 &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
 240         level &= (ATOM_S2_CURRENT_BL_LEVEL_MASK >>
 241                                 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
 242         s2 |= (level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
 243
 244         REG_WRITE(BIOS_SCRATCH_2, s2);
 245
 246         /* waitDMCUReadyForCmd */
 247         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
 248                         0, 1, 80000);
 249 }
 250
 251 static void dce_abm_init(struct abm *abm)
 252 {
 253         struct dce_abm *abm_dce = TO_DCE_ABM(abm);
 254         unsigned int backlight = get_current_backlight_16_bit(abm_dce);
 255
 256         REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103);
 257         REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101);
 258         REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103);
 259         REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101);
 260         REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101);
 261
 262         REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0,
 263                         ABM1_HG_NUM_OF_BINS_SEL, 0,
 264                         ABM1_HG_VMAX_SEL, 1,
 265                         ABM1_HG_BIN_BITWIDTH_SIZE_SEL, 0);
 266
 267         REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0,
 268                         ABM1_IPCSC_COEFF_SEL_R, 2,
 269                         ABM1_IPCSC_COEFF_SEL_G, 4,
 270                         ABM1_IPCSC_COEFF_SEL_B, 2);
 271
 272         REG_UPDATE(BL1_PWM_CURRENT_ABM_LEVEL,
 273                         BL1_PWM_CURRENT_ABM_LEVEL, backlight);
 274
 275         REG_UPDATE(BL1_PWM_TARGET_ABM_LEVEL,
 276                         BL1_PWM_TARGET_ABM_LEVEL, backlight);
 277
 278         REG_UPDATE(BL1_PWM_USER_LEVEL,
 279                         BL1_PWM_USER_LEVEL, backlight);
 280
 281         REG_UPDATE_2(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES,
 282                         ABM1_LS_MIN_PIXEL_VALUE_THRES, 0,
 283                         ABM1_LS_MAX_PIXEL_VALUE_THRES, 1000);
 284
 285         REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0,
 286                         ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, 1,
 287                         ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, 1,
 288                         ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1);
 289 }
 290
 291 static unsigned int dce_abm_get_current_backlight_8_bit(struct abm *abm)
 292 {
 293         struct dce_abm *abm_dce = TO_DCE_ABM(abm);
 294         unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
 295
 296         return (backlight >> 8);
 297 }
 298
 299 static bool dce_abm_set_level(struct abm *abm, uint32_t level)
 300 {
 301         struct dce_abm *abm_dce = TO_DCE_ABM(abm);
 302
 303         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
 304                         1, 80000);
 305
 306         /* setDMCUParam_ABMLevel */
 307         REG_UPDATE_2(MASTER_COMM_CMD_REG,
 308                         MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET,
 309                         MASTER_COMM_CMD_REG_BYTE2, level);
 310
 311         /* notifyDMCUMsg */
 312         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 313
 314         return true;
 315 }
 316
 317 static bool dce_abm_immediate_disable(struct abm *abm)
 318 {
 319         struct dce_abm *abm_dce = TO_DCE_ABM(abm);
 320
 321         REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
 322                         1, 80000);
 323
 324         /* setDMCUParam_ABMLevel */
 325         REG_UPDATE_2(MASTER_COMM_CMD_REG,
 326                         MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET,
 327                         MASTER_COMM_CMD_REG_BYTE2, MCP_DISABLE_ABM_IMMEDIATELY);
 328
 329         /* notifyDMCUMsg */
 330         REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 331
 332         abm->stored_backlight_registers.BL_PWM_CNTL =
 333                 REG_READ(BL_PWM_CNTL);
 334         abm->stored_backlight_registers.BL_PWM_CNTL2 =
 335                 REG_READ(BL_PWM_CNTL2);
 336         abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
 337                 REG_READ(BL_PWM_PERIOD_CNTL);
 338
 339         REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
 340                 &abm->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
 341         return true;
 342 }
 343
 344 static bool dce_abm_init_backlight(struct abm *abm)
 345 {
 346         struct dce_abm *abm_dce = TO_DCE_ABM(abm);
 347         uint32_t value;
 348
 349         /* It must not be 0, so we have to restore them
 350          * Bios bug w/a - period resets to zero,
 351          * restoring to cache values which is always correct
 352          */
 353         REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
 354         if (value == 0 || value == 1) {
 355                 if (abm->stored_backlight_registers.BL_PWM_CNTL != 0) {
 356                         REG_WRITE(BL_PWM_CNTL,
 357                                 abm->stored_backlight_registers.BL_PWM_CNTL);
 358                         REG_WRITE(BL_PWM_CNTL2,
 359                                 abm->stored_backlight_registers.BL_PWM_CNTL2);
 360                         REG_WRITE(BL_PWM_PERIOD_CNTL,
 361                                 abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
 362                         REG_UPDATE(LVTMA_PWRSEQ_REF_DIV,
 363                                 BL_PWM_REF_DIV,
 364                                 abm->stored_backlight_registers.
 365                                 LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
 366                 } else {
 367                         /* TODO: Note: This should not really happen since VBIOS
 368                          * should have initialized PWM registers on boot.
 369                          */
 370                         REG_WRITE(BL_PWM_CNTL, 0xC000FA00);
 371                         REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
 372                 }
 373         } else {
 374                 abm->stored_backlight_registers.BL_PWM_CNTL =
 375                                 REG_READ(BL_PWM_CNTL);
 376                 abm->stored_backlight_registers.BL_PWM_CNTL2 =
 377                                 REG_READ(BL_PWM_CNTL2);
 378                 abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
 379                                 REG_READ(BL_PWM_PERIOD_CNTL);
 380
 381                 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
 382                                 &abm->stored_backlight_registers.
 383                                 LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
 384         }
 385
 386         /* Have driver take backlight control
 387          * TakeBacklightControl(true)
 388          */
 389         value = REG_READ(BIOS_SCRATCH_2);
 390         value |= ATOM_S2_VRI_BRIGHT_ENABLE;
 391         REG_WRITE(BIOS_SCRATCH_2, value);
 392
 393         /* Enable the backlight output */
 394         REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
 395
 396         /* Unlock group 2 backlight registers */
 397         REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
 398                         BL_PWM_GRP1_REG_LOCK, 0);
 399
 400         return true;
 401 }
 402
 403 static bool dce_abm_set_backlight_level(
 404                 struct abm *abm,
 405                 unsigned int backlight_level,
 406                 unsigned int frame_ramp,
 407                 unsigned int controller_id,
 408                 bool use_smooth_brightness)
 409 {
 410         struct dce_abm *abm_dce = TO_DCE_ABM(abm);
 411
 412         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
 413                         backlight_level, backlight_level);
 414
 415         /* If DMCU is in reset state, DMCU is uninitialized */
 416         if (use_smooth_brightness)
 417                 dmcu_set_backlight_level(abm_dce,
 418                                 backlight_level,
 419                                 frame_ramp,
 420                                 controller_id);
 421         else
 422                 driver_set_backlight_level(abm_dce, backlight_level);
 423
 424         return true;
 425 }
 426
 427 static const struct abm_funcs dce_funcs = {
 428         .abm_init = dce_abm_init,
 429         .set_abm_level = dce_abm_set_level,
 430         .init_backlight = dce_abm_init_backlight,
 431         .set_backlight_level = dce_abm_set_backlight_level,
 432         .get_current_backlight_8_bit = dce_abm_get_current_backlight_8_bit,
 433         .set_abm_immediate_disable = dce_abm_immediate_disable
 434 };
 435
 436 static void dce_abm_construct(
 437         struct dce_abm *abm_dce,
 438         struct dc_context *ctx,
 439         const struct dce_abm_registers *regs,
 440         const struct dce_abm_shift *abm_shift,
 441         const struct dce_abm_mask *abm_mask)
 442 {
 443         struct abm *base = &abm_dce->base;
 444
 445         base->ctx = ctx;
 446         base->funcs = &dce_funcs;
 447         base->stored_backlight_registers.BL_PWM_CNTL = 0;
 448         base->stored_backlight_registers.BL_PWM_CNTL2 = 0;
 449         base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0;
 450         base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0;
 451
 452         abm_dce->regs = regs;
 453         abm_dce->abm_shift = abm_shift;
 454         abm_dce->abm_mask = abm_mask;
 455 }
 456
 457 struct abm *dce_abm_create(
 458         struct dc_context *ctx,
 459         const struct dce_abm_registers *regs,
 460         const struct dce_abm_shift *abm_shift,
 461         const struct dce_abm_mask *abm_mask)
 462 {
 463         struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
 464
 465         if (abm_dce == NULL) {
 466                 BREAK_TO_DEBUGGER();
 467                 return NULL;
 468         }
 469
 470         dce_abm_construct(abm_dce, ctx, regs, abm_shift, abm_mask);
 471
 472         abm_dce->base.funcs = &dce_funcs;
 473
 474         return &abm_dce->base;
 475 }
 476
 477 void dce_abm_destroy(struct abm **abm)
 478 {
 479         struct dce_abm *abm_dce = TO_DCE_ABM(*abm);
 480
 481         abm_dce->base.funcs->set_abm_immediate_disable(*abm);
 482
 483         kfree(abm_dce);
 484         *abm = NULL;
 485 }