drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dce_calcs.h"
  28 #include "dc.h"
  29 #include "core_types.h"
  30 #include "dal_asic_id.h"
  31 #include "calcs_logger.h"
  32
  33 /*
  34  * NOTE:
  35  *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
  36  *
  37  * It doesn't adhere to Linux kernel style and sometimes will do things in odd
  38  * ways. Unless there is something clearly wrong with it the code should
  39  * remain as-is as it provides us with a guarantee from HW that it is correct.
  40  */
  41
  42 /*******************************************************************************
  43  * Private Functions
  44  ******************************************************************************/
  45
  46 static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asic_id)
  47 {
  48         switch (asic_id.chip_family) {
  49
  50         case FAMILY_CZ:
  51                 if (ASIC_REV_IS_STONEY(asic_id.hw_internal_rev))
  52                         return BW_CALCS_VERSION_STONEY;
  53                 return BW_CALCS_VERSION_CARRIZO;
  54
  55         case FAMILY_VI:
  56                 if (ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
  57                         return BW_CALCS_VERSION_POLARIS12;
  58                 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev))
  59                         return BW_CALCS_VERSION_POLARIS10;
  60                 if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev))
  61                         return BW_CALCS_VERSION_POLARIS11;
  62                 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
  63                         return BW_CALCS_VERSION_VEGAM;
  64                 return BW_CALCS_VERSION_INVALID;
  65
  66         case FAMILY_AI:
  67                 return BW_CALCS_VERSION_VEGA10;
  68
  69         default:
  70                 return BW_CALCS_VERSION_INVALID;
  71         }
  72 }
  73
  74 static void calculate_bandwidth(
  75         const struct bw_calcs_dceip *dceip,
  76         const struct bw_calcs_vbios *vbios,
  77         struct bw_calcs_data *data)
  78
  79 {
  80         const int32_t pixels_per_chunk = 512;
  81         const int32_t high = 2;
  82         const int32_t mid = 1;
  83         const int32_t low = 0;
  84         const uint32_t s_low = 0;
  85         const uint32_t s_mid1 = 1;
  86         const uint32_t s_mid2 = 2;
  87         const uint32_t s_mid3 = 3;
  88         const uint32_t s_mid4 = 4;
  89         const uint32_t s_mid5 = 5;
  90         const uint32_t s_mid6 = 6;
  91         const uint32_t s_high = 7;
  92         const uint32_t dmif_chunk_buff_margin = 1;
  93
  94         uint32_t max_chunks_fbc_mode;
  95         int32_t num_cursor_lines;
  96
  97         int32_t i, j, k;
  98         struct bw_fixed yclk[3];
  99         struct bw_fixed sclk[8];
 100         bool d0_underlay_enable;
 101         bool d1_underlay_enable;
 102         bool fbc_enabled;
 103         bool lpt_enabled;
 104         enum bw_defines sclk_message;
 105         enum bw_defines yclk_message;
 106         enum bw_defines v_filter_init_mode[maximum_number_of_surfaces];
 107         enum bw_defines tiling_mode[maximum_number_of_surfaces];
 108         enum bw_defines surface_type[maximum_number_of_surfaces];
 109         enum bw_defines voltage;
 110         enum bw_defines pipe_check;
 111         enum bw_defines hsr_check;
 112         enum bw_defines vsr_check;
 113         enum bw_defines lb_size_check;
 114         enum bw_defines fbc_check;
 115         enum bw_defines rotation_check;
 116         enum bw_defines mode_check;
 117         enum bw_defines nbp_state_change_enable_blank;
 118         /*initialize variables*/
 119         int32_t number_of_displays_enabled = 0;
 120         int32_t number_of_displays_enabled_with_margin = 0;
 121         int32_t number_of_aligned_displays_with_no_margin = 0;
 122
 123         yclk[low] = vbios->low_yclk;
 124         yclk[mid] = vbios->mid_yclk;
 125         yclk[high] = vbios->high_yclk;
 126         sclk[s_low] = vbios->low_sclk;
 127         sclk[s_mid1] = vbios->mid1_sclk;
 128         sclk[s_mid2] = vbios->mid2_sclk;
 129         sclk[s_mid3] = vbios->mid3_sclk;
 130         sclk[s_mid4] = vbios->mid4_sclk;
 131         sclk[s_mid5] = vbios->mid5_sclk;
 132         sclk[s_mid6] = vbios->mid6_sclk;
 133         sclk[s_high] = vbios->high_sclk;
 134         /*''''''''''''''''''*/
 135         /* surface assignment:*/
 136         /* 0: d0 underlay or underlay luma*/
 137         /* 1: d0 underlay chroma*/
 138         /* 2: d1 underlay or underlay luma*/
 139         /* 3: d1 underlay chroma*/
 140         /* 4: d0 graphics*/
 141         /* 5: d1 graphics*/
 142         /* 6: d2 graphics*/
 143         /* 7: d3 graphics, same mode as d2*/
 144         /* 8: d4 graphics, same mode as d2*/
 145         /* 9: d5 graphics, same mode as d2*/
 146         /* ...*/
 147         /* maximum_number_of_surfaces-2: d1 display_write_back420 luma*/
 148         /* maximum_number_of_surfaces-1: d1 display_write_back420 chroma*/
 149         /* underlay luma and chroma surface parameters from spreadsheet*/
 150
 151
 152
 153
 154         if (data->d0_underlay_mode == bw_def_none) { d0_underlay_enable = 0; }
 155         else {
 156                 d0_underlay_enable = 1;
 157         }
 158         if (data->d1_underlay_mode == bw_def_none) { d1_underlay_enable = 0; }
 159         else {
 160                 d1_underlay_enable = 1;
 161         }
 162         data->number_of_underlay_surfaces = d0_underlay_enable + d1_underlay_enable;
 163         switch (data->underlay_surface_type) {
 164         case bw_def_420:
 165                 surface_type[0] = bw_def_underlay420_luma;
 166                 surface_type[2] = bw_def_underlay420_luma;
 167                 data->bytes_per_pixel[0] = 1;
 168                 data->bytes_per_pixel[2] = 1;
 169                 surface_type[1] = bw_def_underlay420_chroma;
 170                 surface_type[3] = bw_def_underlay420_chroma;
 171                 data->bytes_per_pixel[1] = 2;
 172                 data->bytes_per_pixel[3] = 2;
 173                 data->lb_size_per_component[0] = dceip->underlay420_luma_lb_size_per_component;
 174                 data->lb_size_per_component[1] = dceip->underlay420_chroma_lb_size_per_component;
 175                 data->lb_size_per_component[2] = dceip->underlay420_luma_lb_size_per_component;
 176                 data->lb_size_per_component[3] = dceip->underlay420_chroma_lb_size_per_component;
 177                 break;
 178         case bw_def_422:
 179                 surface_type[0] = bw_def_underlay422;
 180                 surface_type[2] = bw_def_underlay422;
 181                 data->bytes_per_pixel[0] = 2;
 182                 data->bytes_per_pixel[2] = 2;
 183                 data->lb_size_per_component[0] = dceip->underlay422_lb_size_per_component;
 184                 data->lb_size_per_component[2] = dceip->underlay422_lb_size_per_component;
 185                 break;
 186         default:
 187                 surface_type[0] = bw_def_underlay444;
 188                 surface_type[2] = bw_def_underlay444;
 189                 data->bytes_per_pixel[0] = 4;
 190                 data->bytes_per_pixel[2] = 4;
 191                 data->lb_size_per_component[0] = dceip->lb_size_per_component444;
 192                 data->lb_size_per_component[2] = dceip->lb_size_per_component444;
 193                 break;
 194         }
 195         if (d0_underlay_enable) {
 196                 switch (data->underlay_surface_type) {
 197                 case bw_def_420:
 198                         data->enable[0] = 1;
 199                         data->enable[1] = 1;
 200                         break;
 201                 default:
 202                         data->enable[0] = 1;
 203                         data->enable[1] = 0;
 204                         break;
 205                 }
 206         }
 207         else {
 208                 data->enable[0] = 0;
 209                 data->enable[1] = 0;
 210         }
 211         if (d1_underlay_enable) {
 212                 switch (data->underlay_surface_type) {
 213                 case bw_def_420:
 214                         data->enable[2] = 1;
 215                         data->enable[3] = 1;
 216                         break;
 217                 default:
 218                         data->enable[2] = 1;
 219                         data->enable[3] = 0;
 220                         break;
 221                 }
 222         }
 223         else {
 224                 data->enable[2] = 0;
 225                 data->enable[3] = 0;
 226         }
 227         data->use_alpha[0] = 0;
 228         data->use_alpha[1] = 0;
 229         data->use_alpha[2] = 0;
 230         data->use_alpha[3] = 0;
 231         data->scatter_gather_enable_for_pipe[0] = vbios->scatter_gather_enable;
 232         data->scatter_gather_enable_for_pipe[1] = vbios->scatter_gather_enable;
 233         data->scatter_gather_enable_for_pipe[2] = vbios->scatter_gather_enable;
 234         data->scatter_gather_enable_for_pipe[3] = vbios->scatter_gather_enable;
 235         /*underlay0 same and graphics display pipe0*/
 236         data->interlace_mode[0] = data->interlace_mode[4];
 237         data->interlace_mode[1] = data->interlace_mode[4];
 238         /*underlay1 same and graphics display pipe1*/
 239         data->interlace_mode[2] = data->interlace_mode[5];
 240         data->interlace_mode[3] = data->interlace_mode[5];
 241         /*underlay0 same and graphics display pipe0*/
 242         data->h_total[0] = data->h_total[4];
 243         data->v_total[0] = data->v_total[4];
 244         data->h_total[1] = data->h_total[4];
 245         data->v_total[1] = data->v_total[4];
 246         /*underlay1 same and graphics display pipe1*/
 247         data->h_total[2] = data->h_total[5];
 248         data->v_total[2] = data->v_total[5];
 249         data->h_total[3] = data->h_total[5];
 250         data->v_total[3] = data->v_total[5];
 251         /*underlay0 same and graphics display pipe0*/
 252         data->pixel_rate[0] = data->pixel_rate[4];
 253         data->pixel_rate[1] = data->pixel_rate[4];
 254         /*underlay1 same and graphics display pipe1*/
 255         data->pixel_rate[2] = data->pixel_rate[5];
 256         data->pixel_rate[3] = data->pixel_rate[5];
 257         if ((data->underlay_tiling_mode == bw_def_array_linear_general || data->underlay_tiling_mode == bw_def_array_linear_aligned)) {
 258                 tiling_mode[0] = bw_def_linear;
 259                 tiling_mode[1] = bw_def_linear;
 260                 tiling_mode[2] = bw_def_linear;
 261                 tiling_mode[3] = bw_def_linear;
 262         }
 263         else {
 264                 tiling_mode[0] = bw_def_landscape;
 265                 tiling_mode[1] = bw_def_landscape;
 266                 tiling_mode[2] = bw_def_landscape;
 267                 tiling_mode[3] = bw_def_landscape;
 268         }
 269         data->lb_bpc[0] = data->underlay_lb_bpc;
 270         data->lb_bpc[1] = data->underlay_lb_bpc;
 271         data->lb_bpc[2] = data->underlay_lb_bpc;
 272         data->lb_bpc[3] = data->underlay_lb_bpc;
 273         data->compression_rate[0] = bw_int_to_fixed(1);
 274         data->compression_rate[1] = bw_int_to_fixed(1);
 275         data->compression_rate[2] = bw_int_to_fixed(1);
 276         data->compression_rate[3] = bw_int_to_fixed(1);
 277         data->access_one_channel_only[0] = 0;
 278         data->access_one_channel_only[1] = 0;
 279         data->access_one_channel_only[2] = 0;
 280         data->access_one_channel_only[3] = 0;
 281         data->cursor_width_pixels[0] = bw_int_to_fixed(0);
 282         data->cursor_width_pixels[1] = bw_int_to_fixed(0);
 283         data->cursor_width_pixels[2] = bw_int_to_fixed(0);
 284         data->cursor_width_pixels[3] = bw_int_to_fixed(0);
 285         /* graphics surface parameters from spreadsheet*/
 286         fbc_enabled = 0;
 287         lpt_enabled = 0;
 288         for (i = 4; i <= maximum_number_of_surfaces - 3; i++) {
 289                 if (i < data->number_of_displays + 4) {
 290                         if (i == 4 && data->d0_underlay_mode == bw_def_underlay_only) {
 291                                 data->enable[i] = 0;
 292                                 data->use_alpha[i] = 0;
 293                         }
 294                         else if (i == 4 && data->d0_underlay_mode == bw_def_blend) {
 295                                 data->enable[i] = 1;
 296                                 data->use_alpha[i] = 1;
 297                         }
 298                         else if (i == 4) {
 299                                 data->enable[i] = 1;
 300                                 data->use_alpha[i] = 0;
 301                         }
 302                         else if (i == 5 && data->d1_underlay_mode == bw_def_underlay_only) {
 303                                 data->enable[i] = 0;
 304                                 data->use_alpha[i] = 0;
 305                         }
 306                         else if (i == 5 && data->d1_underlay_mode == bw_def_blend) {
 307                                 data->enable[i] = 1;
 308                                 data->use_alpha[i] = 1;
 309                         }
 310                         else {
 311                                 data->enable[i] = 1;
 312                                 data->use_alpha[i] = 0;
 313                         }
 314                 }
 315                 else {
 316                         data->enable[i] = 0;
 317                         data->use_alpha[i] = 0;
 318                 }
 319                 data->scatter_gather_enable_for_pipe[i] = vbios->scatter_gather_enable;
 320                 surface_type[i] = bw_def_graphics;
 321                 data->lb_size_per_component[i] = dceip->lb_size_per_component444;
 322                 if (data->graphics_tiling_mode == bw_def_array_linear_general || data->graphics_tiling_mode == bw_def_array_linear_aligned) {
 323                         tiling_mode[i] = bw_def_linear;
 324                 }
 325                 else {
 326                         tiling_mode[i] = bw_def_tiled;
 327                 }
 328                 data->lb_bpc[i] = data->graphics_lb_bpc;
 329                 if ((data->fbc_en[i] == 1 && (dceip->argb_compression_support || data->d0_underlay_mode != bw_def_blended))) {
 330                         data->compression_rate[i] = bw_int_to_fixed(vbios->average_compression_rate);
 331                         data->access_one_channel_only[i] = data->lpt_en[i];
 332                 }
 333                 else {
 334                         data->compression_rate[i] = bw_int_to_fixed(1);
 335                         data->access_one_channel_only[i] = 0;
 336                 }
 337                 if (data->fbc_en[i] == 1) {
 338                         fbc_enabled = 1;
 339                         if (data->lpt_en[i] == 1) {
 340                                 lpt_enabled = 1;
 341                         }
 342                 }
 343                 data->cursor_width_pixels[i] = bw_int_to_fixed(vbios->cursor_width);
 344         }
 345         /* display_write_back420*/
 346         data->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 2] = 0;
 347         data->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 1] = 0;
 348         if (data->d1_display_write_back_dwb_enable == 1) {
 349                 data->enable[maximum_number_of_surfaces - 2] = 1;
 350                 data->enable[maximum_number_of_surfaces - 1] = 1;
 351         }
 352         else {
 353                 data->enable[maximum_number_of_surfaces - 2] = 0;
 354                 data->enable[maximum_number_of_surfaces - 1] = 0;
 355         }
 356         surface_type[maximum_number_of_surfaces - 2] = bw_def_display_write_back420_luma;
 357         surface_type[maximum_number_of_surfaces - 1] = bw_def_display_write_back420_chroma;
 358         data->lb_size_per_component[maximum_number_of_surfaces - 2] = dceip->underlay420_luma_lb_size_per_component;
 359         data->lb_size_per_component[maximum_number_of_surfaces - 1] = dceip->underlay420_chroma_lb_size_per_component;
 360         data->bytes_per_pixel[maximum_number_of_surfaces - 2] = 1;
 361         data->bytes_per_pixel[maximum_number_of_surfaces - 1] = 2;
 362         data->interlace_mode[maximum_number_of_surfaces - 2] = data->interlace_mode[5];
 363         data->interlace_mode[maximum_number_of_surfaces - 1] = data->interlace_mode[5];
 364         data->h_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
 365         data->h_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
 366         data->v_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
 367         data->v_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
 368         data->rotation_angle[maximum_number_of_surfaces - 2] = bw_int_to_fixed(0);
 369         data->rotation_angle[maximum_number_of_surfaces - 1] = bw_int_to_fixed(0);
 370         tiling_mode[maximum_number_of_surfaces - 2] = bw_def_linear;
 371         tiling_mode[maximum_number_of_surfaces - 1] = bw_def_linear;
 372         data->lb_bpc[maximum_number_of_surfaces - 2] = 8;
 373         data->lb_bpc[maximum_number_of_surfaces - 1] = 8;
 374         data->compression_rate[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
 375         data->compression_rate[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
 376         data->access_one_channel_only[maximum_number_of_surfaces - 2] = 0;
 377         data->access_one_channel_only[maximum_number_of_surfaces - 1] = 0;
 378         /*assume display pipe1 has dwb enabled*/
 379         data->h_total[maximum_number_of_surfaces - 2] = data->h_total[5];
 380         data->h_total[maximum_number_of_surfaces - 1] = data->h_total[5];
 381         data->v_total[maximum_number_of_surfaces - 2] = data->v_total[5];
 382         data->v_total[maximum_number_of_surfaces - 1] = data->v_total[5];
 383         data->pixel_rate[maximum_number_of_surfaces - 2] = data->pixel_rate[5];
 384         data->pixel_rate[maximum_number_of_surfaces - 1] = data->pixel_rate[5];
 385         data->src_width[maximum_number_of_surfaces - 2] = data->src_width[5];
 386         data->src_width[maximum_number_of_surfaces - 1] = data->src_width[5];
 387         data->src_height[maximum_number_of_surfaces - 2] = data->src_height[5];
 388         data->src_height[maximum_number_of_surfaces - 1] = data->src_height[5];
 389         data->pitch_in_pixels[maximum_number_of_surfaces - 2] = data->src_width[5];
 390         data->pitch_in_pixels[maximum_number_of_surfaces - 1] = data->src_width[5];
 391         data->h_scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
 392         data->h_scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
 393         data->v_scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
 394         data->v_scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
 395         data->stereo_mode[maximum_number_of_surfaces - 2] = bw_def_mono;
 396         data->stereo_mode[maximum_number_of_surfaces - 1] = bw_def_mono;
 397         data->cursor_width_pixels[maximum_number_of_surfaces - 2] = bw_int_to_fixed(0);
 398         data->cursor_width_pixels[maximum_number_of_surfaces - 1] = bw_int_to_fixed(0);
 399         data->use_alpha[maximum_number_of_surfaces - 2] = 0;
 400         data->use_alpha[maximum_number_of_surfaces - 1] = 0;
 401         /*mode check calculations:*/
 402         /* mode within dce ip capabilities*/
 403         /* fbc*/
 404         /* hsr*/
 405         /* vsr*/
 406         /* lb size*/
 407         /*effective scaling source and ratios:*/
 408         /*for graphics, non-stereo, non-interlace surfaces when the size of the source and destination are the same, only one tap is used*/
 409         /*420 chroma has half the width, height, horizontal and vertical scaling ratios than luma*/
 410         /*rotating a graphic or underlay surface swaps the width, height, horizontal and vertical scaling ratios*/
 411         /*in top-bottom stereo mode there is 2:1 vertical downscaling for each eye*/
 412         /*in side-by-side stereo mode there is 2:1 horizontal downscaling for each eye*/
 413         /*in interlace mode there is 2:1 vertical downscaling for each field*/
 414         /*in panning or bezel adjustment mode the source width has an extra 128 pixels*/
 415         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 416                 if (data->enable[i]) {
 417                         if (bw_equ(data->h_scale_ratio[i], bw_int_to_fixed(1)) && bw_equ(data->v_scale_ratio[i], bw_int_to_fixed(1)) && surface_type[i] == bw_def_graphics && data->stereo_mode[i] == bw_def_mono && data->interlace_mode[i] == 0) {
 418                                 data->h_taps[i] = bw_int_to_fixed(1);
 419                                 data->v_taps[i] = bw_int_to_fixed(1);
 420                         }
 421                         if (surface_type[i] == bw_def_display_write_back420_chroma || surface_type[i] == bw_def_underlay420_chroma) {
 422                                 data->pitch_in_pixels_after_surface_type[i] = bw_div(data->pitch_in_pixels[i], bw_int_to_fixed(2));
 423                                 data->src_width_after_surface_type = bw_div(data->src_width[i], bw_int_to_fixed(2));
 424                                 data->src_height_after_surface_type = bw_div(data->src_height[i], bw_int_to_fixed(2));
 425                                 data->hsr_after_surface_type = bw_div(data->h_scale_ratio[i], bw_int_to_fixed(2));
 426                                 data->vsr_after_surface_type = bw_div(data->v_scale_ratio[i], bw_int_to_fixed(2));
 427                         }
 428                         else {
 429                                 data->pitch_in_pixels_after_surface_type[i] = data->pitch_in_pixels[i];
 430                                 data->src_width_after_surface_type = data->src_width[i];
 431                                 data->src_height_after_surface_type = data->src_height[i];
 432                                 data->hsr_after_surface_type = data->h_scale_ratio[i];
 433                                 data->vsr_after_surface_type = data->v_scale_ratio[i];
 434                         }
 435                         if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) && surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
 436                                 data->src_width_after_rotation = data->src_height_after_surface_type;
 437                                 data->src_height_after_rotation = data->src_width_after_surface_type;
 438                                 data->hsr_after_rotation = data->vsr_after_surface_type;
 439                                 data->vsr_after_rotation = data->hsr_after_surface_type;
 440                         }
 441                         else {
 442                                 data->src_width_after_rotation = data->src_width_after_surface_type;
 443                                 data->src_height_after_rotation = data->src_height_after_surface_type;
 444                                 data->hsr_after_rotation = data->hsr_after_surface_type;
 445                                 data->vsr_after_rotation = data->vsr_after_surface_type;
 446                         }
 447                         switch (data->stereo_mode[i]) {
 448                         case bw_def_top_bottom:
 449                                 data->source_width_pixels[i] = data->src_width_after_rotation;
 450                                 data->source_height_pixels = bw_mul(bw_int_to_fixed(2), data->src_height_after_rotation);
 451                                 data->hsr_after_stereo = data->hsr_after_rotation;
 452                                 data->vsr_after_stereo = bw_mul(bw_int_to_fixed(1), data->vsr_after_rotation);
 453                                 break;
 454                         case bw_def_side_by_side:
 455                                 data->source_width_pixels[i] = bw_mul(bw_int_to_fixed(2), data->src_width_after_rotation);
 456                                 data->source_height_pixels = data->src_height_after_rotation;
 457                                 data->hsr_after_stereo = bw_mul(bw_int_to_fixed(1), data->hsr_after_rotation);
 458                                 data->vsr_after_stereo = data->vsr_after_rotation;
 459                                 break;
 460                         default:
 461                                 data->source_width_pixels[i] = data->src_width_after_rotation;
 462                                 data->source_height_pixels = data->src_height_after_rotation;
 463                                 data->hsr_after_stereo = data->hsr_after_rotation;
 464                                 data->vsr_after_stereo = data->vsr_after_rotation;
 465                                 break;
 466                         }
 467                         data->hsr[i] = data->hsr_after_stereo;
 468                         if (data->interlace_mode[i]) {
 469                                 data->vsr[i] = bw_mul(data->vsr_after_stereo, bw_int_to_fixed(2));
 470                         }
 471                         else {
 472                                 data->vsr[i] = data->vsr_after_stereo;
 473                         }
 474                         if (data->panning_and_bezel_adjustment != bw_def_none) {
 475                                 data->source_width_rounded_up_to_chunks[i] = bw_add(bw_floor2(bw_sub(data->source_width_pixels[i], bw_int_to_fixed(1)), bw_int_to_fixed(128)), bw_int_to_fixed(256));
 476                         }
 477                         else {
 478                                 data->source_width_rounded_up_to_chunks[i] = bw_ceil2(data->source_width_pixels[i], bw_int_to_fixed(128));
 479                         }
 480                         data->source_height_rounded_up_to_chunks[i] = data->source_height_pixels;
 481                 }
 482         }
 483         /*mode support checks:*/
 484         /*the number of graphics and underlay pipes is limited by the ip support*/
 485         /*maximum horizontal and vertical scale ratio is 4, and should not exceed the number of taps*/
 486         /*for downscaling with the pre-downscaler, the horizontal scale ratio must be more than the ceiling of one quarter of the number of taps*/
 487         /*the pre-downscaler reduces the line buffer source by the horizontal scale ratio*/
 488         /*the number of lines in the line buffer has to exceed the number of vertical taps*/
 489         /*the size of the line in the line buffer is the product of the source width and the bits per component, rounded up to a multiple of 48*/
 490         /*the size of the line in the line buffer in the case of 10 bit per component is the product of the source width rounded up to multiple of 8 and 30.023438 / 3, rounded up to a multiple of 48*/
 491         /*the size of the line in the line buffer in the case of 8 bit per component is the product of the source width rounded up to multiple of 8 and 30.023438 / 3, rounded up to a multiple of 48*/
 492         /*frame buffer compression is not supported with stereo mode, rotation, or non- 888 formats*/
 493         /*rotation is not supported with linear of stereo modes*/
 494         if (dceip->number_of_graphics_pipes >= data->number_of_displays && dceip->number_of_underlay_pipes >= data->number_of_underlay_surfaces && !(dceip->display_write_back_supported == 0 && data->d1_display_write_back_dwb_enable == 1)) {
 495                 pipe_check = bw_def_ok;
 496         }
 497         else {
 498                 pipe_check = bw_def_notok;
 499         }
 500         hsr_check = bw_def_ok;
 501         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 502                 if (data->enable[i]) {
 503                         if (bw_neq(data->hsr[i], bw_int_to_fixed(1))) {
 504                                 if (bw_mtn(data->hsr[i], bw_int_to_fixed(4))) {
 505                                         hsr_check = bw_def_hsr_mtn_4;
 506                                 }
 507                                 else {
 508                                         if (bw_mtn(data->hsr[i], data->h_taps[i])) {
 509                                                 hsr_check = bw_def_hsr_mtn_h_taps;
 510                                         }
 511                                         else {
 512                                                 if (dceip->pre_downscaler_enabled == 1 && bw_mtn(data->hsr[i], bw_int_to_fixed(1)) && bw_leq(data->hsr[i], bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)))) {
 513                                                         hsr_check = bw_def_ceiling__h_taps_div_4___meq_hsr;
 514                                                 }
 515                                         }
 516                                 }
 517                         }
 518                 }
 519         }
 520         vsr_check = bw_def_ok;
 521         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 522                 if (data->enable[i]) {
 523                         if (bw_neq(data->vsr[i], bw_int_to_fixed(1))) {
 524                                 if (bw_mtn(data->vsr[i], bw_int_to_fixed(4))) {
 525                                         vsr_check = bw_def_vsr_mtn_4;
 526                                 }
 527                                 else {
 528                                         if (bw_mtn(data->vsr[i], data->v_taps[i])) {
 529                                                 vsr_check = bw_def_vsr_mtn_v_taps;
 530                                         }
 531                                 }
 532                         }
 533                 }
 534         }
 535         lb_size_check = bw_def_ok;
 536         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 537                 if (data->enable[i]) {
 538                         if ((dceip->pre_downscaler_enabled && bw_mtn(data->hsr[i], bw_int_to_fixed(1)))) {
 539                                 data->source_width_in_lb = bw_div(data->source_width_pixels[i], data->hsr[i]);
 540                         }
 541                         else {
 542                                 data->source_width_in_lb = data->source_width_pixels[i];
 543                         }
 544                         switch (data->lb_bpc[i]) {
 545                         case 8:
 546                                 data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(2401171875ul, 100000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48));
 547                                 break;
 548                         case 10:
 549                                 data->lb_line_pitch = bw_ceil2(bw_mul(bw_div(bw_frc_to_fixed(300234375, 10000000), bw_int_to_fixed(3)), bw_ceil2(data->source_width_in_lb, bw_int_to_fixed(8))), bw_int_to_fixed(48));
 550                                 break;
 551                         default:
 552                                 data->lb_line_pitch = bw_ceil2(bw_mul(bw_int_to_fixed(data->lb_bpc[i]), data->source_width_in_lb), bw_int_to_fixed(48));
 553                                 break;
 554                         }
 555                         data->lb_partitions[i] = bw_floor2(bw_div(data->lb_size_per_component[i], data->lb_line_pitch), bw_int_to_fixed(1));
 556                         /*clamp the partitions to the maxium number supported by the lb*/
 557                         if ((surface_type[i] != bw_def_graphics || dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1)) {
 558                                 data->lb_partitions_max[i] = bw_int_to_fixed(10);
 559                         }
 560                         else {
 561                                 data->lb_partitions_max[i] = bw_int_to_fixed(7);
 562                         }
 563                         data->lb_partitions[i] = bw_min2(data->lb_partitions_max[i], data->lb_partitions[i]);
 564                         if (bw_mtn(bw_add(data->v_taps[i], bw_int_to_fixed(1)), data->lb_partitions[i])) {
 565                                 lb_size_check = bw_def_notok;
 566                         }
 567                 }
 568         }
 569         fbc_check = bw_def_ok;
 570         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 571                 if (data->enable[i] && data->fbc_en[i] == 1 && (bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270)) || data->stereo_mode[i] != bw_def_mono || data->bytes_per_pixel[i] != 4)) {
 572                         fbc_check = bw_def_invalid_rotation_or_bpp_or_stereo;
 573                 }
 574         }
 575         rotation_check = bw_def_ok;
 576         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 577                 if (data->enable[i]) {
 578                         if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) && (tiling_mode[i] == bw_def_linear || data->stereo_mode[i] != bw_def_mono)) {
 579                                 rotation_check = bw_def_invalid_linear_or_stereo_mode;
 580                         }
 581                 }
 582         }
 583         if (pipe_check == bw_def_ok && hsr_check == bw_def_ok && vsr_check == bw_def_ok && lb_size_check == bw_def_ok && fbc_check == bw_def_ok && rotation_check == bw_def_ok) {
 584                 mode_check = bw_def_ok;
 585         }
 586         else {
 587                 mode_check = bw_def_notok;
 588         }
 589         /*number of memory channels for write-back client*/
 590         data->number_of_dram_wrchannels = vbios->number_of_dram_channels;
 591         data->number_of_dram_channels = vbios->number_of_dram_channels;
 592         /*modify number of memory channels if lpt mode is enabled*/
 593         /* low power tiling mode register*/
 594         /* 0 = use channel 0*/
 595         /* 1 = use channel 0 and 1*/
 596         /* 2 = use channel 0,1,2,3*/
 597         if ((fbc_enabled == 1 && lpt_enabled == 1)) {
 598                 if (vbios->memory_type == bw_def_hbm)
 599                         data->dram_efficiency = bw_frc_to_fixed(5, 10);
 600                 else
 601                         data->dram_efficiency = bw_int_to_fixed(1);
 602
 603
 604                 if (dceip->low_power_tiling_mode == 0) {
 605                         data->number_of_dram_channels = 1;
 606                 }
 607                 else if (dceip->low_power_tiling_mode == 1) {
 608                         data->number_of_dram_channels = 2;
 609                 }
 610                 else if (dceip->low_power_tiling_mode == 2) {
 611                         data->number_of_dram_channels = 4;
 612                 }
 613                 else {
 614                         data->number_of_dram_channels = 1;
 615                 }
 616         }
 617         else {
 618                 if (vbios->memory_type == bw_def_hbm)
 619                         data->dram_efficiency = bw_frc_to_fixed(5, 10);
 620                 else
 621                         data->dram_efficiency = bw_frc_to_fixed(8, 10);
 622         }
 623         /*memory request size and latency hiding:*/
 624         /*request size is normally 64 byte, 2-line interleaved, with full latency hiding*/
 625         /*the display write-back requests are single line*/
 626         /*for tiled graphics surfaces, or undelay surfaces with width higher than the maximum size for full efficiency, request size is 32 byte in 8 and 16 bpp or if the rotation is orthogonal to the tiling grain. only half is useful of the bytes in the request size in 8 bpp or in 32 bpp if the rotation is orthogonal to the tiling grain.*/
 627         /*for undelay surfaces with width lower than the maximum size for full efficiency, requests are 4-line interleaved in 16bpp if the rotation is parallel to the tiling grain, and 8-line interleaved with 4-line latency hiding in 8bpp or if the rotation is orthogonal to the tiling grain.*/
 628         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 629                 if (data->enable[i]) {
 630                         if ((bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270)))) {
 631                                 if ((i < 4)) {
 632                                         /*underlay portrait tiling mode is not supported*/
 633                                         data->orthogonal_rotation[i] = 1;
 634                                 }
 635                                 else {
 636                                         /*graphics portrait tiling mode*/
 637                                         if (data->graphics_micro_tile_mode == bw_def_rotated_micro_tiling) {
 638                                                 data->orthogonal_rotation[i] = 0;
 639                                         }
 640                                         else {
 641                                                 data->orthogonal_rotation[i] = 1;
 642                                         }
 643                                 }
 644                         }
 645                         else {
 646                                 if ((i < 4)) {
 647                                         /*underlay landscape tiling mode is only supported*/
 648                                         if (data->underlay_micro_tile_mode == bw_def_display_micro_tiling) {
 649                                                 data->orthogonal_rotation[i] = 0;
 650                                         }
 651                                         else {
 652                                                 data->orthogonal_rotation[i] = 1;
 653                                         }
 654                                 }
 655                                 else {
 656                                         /*graphics landscape tiling mode*/
 657                                         if (data->graphics_micro_tile_mode == bw_def_display_micro_tiling) {
 658                                                 data->orthogonal_rotation[i] = 0;
 659                                         }
 660                                         else {
 661                                                 data->orthogonal_rotation[i] = 1;
 662                                         }
 663                                 }
 664                         }
 665                         if (bw_equ(data->rotation_angle[i], bw_int_to_fixed(90)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(270))) {
 666                                 data->underlay_maximum_source_efficient_for_tiling = dceip->underlay_maximum_height_efficient_for_tiling;
 667                         }
 668                         else {
 669                                 data->underlay_maximum_source_efficient_for_tiling = dceip->underlay_maximum_width_efficient_for_tiling;
 670                         }
 671                         if (surface_type[i] == bw_def_display_write_back420_luma || surface_type[i] == bw_def_display_write_back420_chroma) {
 672                                 data->bytes_per_request[i] = bw_int_to_fixed(64);
 673                                 data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
 674                                 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(1);
 675                                 data->latency_hiding_lines[i] = bw_int_to_fixed(1);
 676                         }
 677                         else if (tiling_mode[i] == bw_def_linear) {
 678                                 data->bytes_per_request[i] = bw_int_to_fixed(64);
 679                                 data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
 680                                 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
 681                                 data->latency_hiding_lines[i] = bw_int_to_fixed(2);
 682                         }
 683                         else {
 684                                 if (surface_type[i] == bw_def_graphics || (bw_mtn(data->source_width_rounded_up_to_chunks[i], bw_ceil2(data->underlay_maximum_source_efficient_for_tiling, bw_int_to_fixed(256))))) {
 685                                         switch (data->bytes_per_pixel[i]) {
 686                                         case 8:
 687                                                 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
 688                                                 data->latency_hiding_lines[i] = bw_int_to_fixed(2);
 689                                                 if (data->orthogonal_rotation[i]) {
 690                                                         data->bytes_per_request[i] = bw_int_to_fixed(32);
 691                                                         data->useful_bytes_per_request[i] = bw_int_to_fixed(32);
 692                                                 }
 693                                                 else {
 694                                                         data->bytes_per_request[i] = bw_int_to_fixed(64);
 695                                                         data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
 696                                                 }
 697                                                 break;
 698                                         case 4:
 699                                                 if (data->orthogonal_rotation[i]) {
 700                                                         data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
 701                                                         data->latency_hiding_lines[i] = bw_int_to_fixed(2);
 702                                                         data->bytes_per_request[i] = bw_int_to_fixed(32);
 703                                                         data->useful_bytes_per_request[i] = bw_int_to_fixed(16);
 704                                                 }
 705                                                 else {
 706                                                         data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
 707                                                         data->latency_hiding_lines[i] = bw_int_to_fixed(2);
 708                                                         data->bytes_per_request[i] = bw_int_to_fixed(64);
 709                                                         data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
 710                                                 }
 711                                                 break;
 712                                         case 2:
 713                                                 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
 714                                                 data->latency_hiding_lines[i] = bw_int_to_fixed(2);
 715                                                 data->bytes_per_request[i] = bw_int_to_fixed(32);
 716                                                 data->useful_bytes_per_request[i] = bw_int_to_fixed(32);
 717                                                 break;
 718                                         default:
 719                                                 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
 720                                                 data->latency_hiding_lines[i] = bw_int_to_fixed(2);
 721                                                 data->bytes_per_request[i] = bw_int_to_fixed(32);
 722                                                 data->useful_bytes_per_request[i] = bw_int_to_fixed(16);
 723                                                 break;
 724                                         }
 725                                 }
 726                                 else {
 727                                         data->bytes_per_request[i] = bw_int_to_fixed(64);
 728                                         data->useful_bytes_per_request[i] = bw_int_to_fixed(64);
 729                                         if (data->orthogonal_rotation[i]) {
 730                                                 data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(8);
 731                                                 data->latency_hiding_lines[i] = bw_int_to_fixed(4);
 732                                         }
 733                                         else {
 734                                                 switch (data->bytes_per_pixel[i]) {
 735                                                 case 4:
 736                                                         data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(2);
 737                                                         data->latency_hiding_lines[i] = bw_int_to_fixed(2);
 738                                                         break;
 739                                                 case 2:
 740                                                         data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(4);
 741                                                         data->latency_hiding_lines[i] = bw_int_to_fixed(4);
 742                                                         break;
 743                                                 default:
 744                                                         data->lines_interleaved_in_mem_access[i] = bw_int_to_fixed(8);
 745                                                         data->latency_hiding_lines[i] = bw_int_to_fixed(4);
 746                                                         break;
 747                                                 }
 748                                         }
 749                                 }
 750                         }
 751                 }
 752         }
 753         /*requested peak bandwidth:*/
 754         /*the peak request-per-second bandwidth is the product of the maximum source lines in per line out in the beginning*/
 755         /*and in the middle of the frame, the ratio of the source width to the line time, the ratio of line interleaving*/
 756         /*in memory to lines of latency hiding, and the ratio of bytes per pixel to useful bytes per request.*/
 757         /**/
 758         /*if the dmif data buffer size holds more than vta_ps worth of source lines, then only vsr is used.*/
 759         /*the peak bandwidth is the peak request-per-second bandwidth times the request size.*/
 760         /**/
 761         /*the line buffer lines in per line out in the beginning of the frame is the vertical filter initialization value*/
 762         /*rounded up to even and divided by the line times for initialization, which is normally three.*/
 763         /*the line buffer lines in per line out in the middle of the frame is at least one, or the vertical scale ratio,*/
 764         /*rounded up to line pairs if not doing line buffer prefetching.*/
 765         /**/
 766         /*the non-prefetching rounding up of the vertical scale ratio can also be done up to 1 (for a 0,2 pattern), 4/3 (for a 0,2,2 pattern),*/
 767         /*6/4 (for a 0,2,2,2 pattern), or 3 (for a 2,4 pattern).*/
 768         /**/
 769         /*the scaler vertical filter initialization value is calculated by the hardware as the floor of the average of the*/
 770         /*vertical scale ratio and the number of vertical taps increased by one.  add one more for possible odd line*/
 771         /*panning/bezel adjustment mode.*/
 772         /**/
 773         /*for the bottom interlace field an extra 50% of the vertical scale ratio is considered for this calculation.*/
 774         /*in top-bottom stereo mode software has to set the filter initialization value manually and explicitly limit it to 4.*/
 775         /*furthermore, there is only one line time for initialization.*/
 776         /**/
 777         /*line buffer prefetching is done when the number of lines in the line buffer exceeds the number of taps plus*/
 778         /*the ceiling of the vertical scale ratio.*/
 779         /**/
 780         /*multi-line buffer prefetching is only done in the graphics pipe when the scaler is disabled or when upscaling and the vsr <= 0.8.'*/
 781         /**/
 782         /*the horizontal blank and chunk granularity factor is indirectly used indicate the interval of time required to transfer the source pixels.*/
 783         /*the denominator of this term represents the total number of destination output pixels required for the input source pixels.*/
 784         /*it applies when the lines in per line out is not 2 or 4.  it does not apply when there is a line buffer between the scl and blnd.*/
 785         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 786                 if (data->enable[i]) {
 787                         data->v_filter_init[i] = bw_floor2(bw_div((bw_add(bw_add(bw_add(bw_int_to_fixed(1), data->v_taps[i]), data->vsr[i]), bw_mul(bw_mul(bw_int_to_fixed(data->interlace_mode[i]), bw_frc_to_fixed(5, 10)), data->vsr[i]))), bw_int_to_fixed(2)), bw_int_to_fixed(1));
 788                         if (data->panning_and_bezel_adjustment == bw_def_any_lines) {
 789                                 data->v_filter_init[i] = bw_add(data->v_filter_init[i], bw_int_to_fixed(1));
 790                         }
 791                         if (data->stereo_mode[i] == bw_def_top_bottom) {
 792                                 v_filter_init_mode[i] = bw_def_manual;
 793                                 data->v_filter_init[i] = bw_min2(data->v_filter_init[i], bw_int_to_fixed(4));
 794                         }
 795                         else {
 796                                 v_filter_init_mode[i] = bw_def_auto;
 797                         }
 798                         if (data->stereo_mode[i] == bw_def_top_bottom) {
 799                                 data->num_lines_at_frame_start = bw_int_to_fixed(1);
 800                         }
 801                         else {
 802                                 data->num_lines_at_frame_start = bw_int_to_fixed(3);
 803                         }
 804                         if ((bw_mtn(data->vsr[i], bw_int_to_fixed(1)) && surface_type[i] == bw_def_graphics) || data->panning_and_bezel_adjustment == bw_def_any_lines) {
 805                                 data->line_buffer_prefetch[i] = 0;
 806                         }
 807                         else if ((((dceip->underlay_downscale_prefetch_enabled == 1 && surface_type[i] != bw_def_graphics) || surface_type[i] == bw_def_graphics) && (bw_mtn(data->lb_partitions[i], bw_add(data->v_taps[i], bw_ceil2(data->vsr[i], bw_int_to_fixed(1))))))) {
 808                                 data->line_buffer_prefetch[i] = 1;
 809                         }
 810                         else {
 811                                 data->line_buffer_prefetch[i] = 0;
 812                         }
 813                         data->lb_lines_in_per_line_out_in_beginning_of_frame[i] = bw_div(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->num_lines_at_frame_start);
 814                         if (data->line_buffer_prefetch[i] == 1) {
 815                                 data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_max2(bw_int_to_fixed(1), data->vsr[i]);
 816                         }
 817                         else if (bw_leq(data->vsr[i], bw_int_to_fixed(1))) {
 818                                 data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(1);
 819                         } else if (bw_leq(data->vsr[i],
 820                                         bw_frc_to_fixed(4, 3))) {
 821                                 data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_div(bw_int_to_fixed(4), bw_int_to_fixed(3));
 822                         } else if (bw_leq(data->vsr[i],
 823                                         bw_frc_to_fixed(6, 4))) {
 824                                 data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_div(bw_int_to_fixed(6), bw_int_to_fixed(4));
 825                         }
 826                         else if (bw_leq(data->vsr[i], bw_int_to_fixed(2))) {
 827                                 data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(2);
 828                         }
 829                         else if (bw_leq(data->vsr[i], bw_int_to_fixed(3))) {
 830                                 data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(3);
 831                         }
 832                         else {
 833                                 data->lb_lines_in_per_line_out_in_middle_of_frame[i] = bw_int_to_fixed(4);
 834                         }
 835                         if (data->line_buffer_prefetch[i] == 1 || bw_equ(data->lb_lines_in_per_line_out_in_middle_of_frame[i], bw_int_to_fixed(2)) || bw_equ(data->lb_lines_in_per_line_out_in_middle_of_frame[i], bw_int_to_fixed(4))) {
 836                                 data->horizontal_blank_and_chunk_granularity_factor[i] = bw_int_to_fixed(1);
 837                         }
 838                         else {
 839                                 data->horizontal_blank_and_chunk_granularity_factor[i] = bw_div(data->h_total[i], (bw_div((bw_add(data->h_total[i], bw_div((bw_sub(data->source_width_pixels[i], bw_int_to_fixed(dceip->chunk_width))), data->hsr[i]))), bw_int_to_fixed(2))));
 840                         }
 841                         data->request_bandwidth[i] = bw_div(bw_mul(bw_div(bw_mul(bw_div(bw_mul(bw_max2(data->lb_lines_in_per_line_out_in_beginning_of_frame[i], data->lb_lines_in_per_line_out_in_middle_of_frame[i]), data->source_width_rounded_up_to_chunks[i]), (bw_div(data->h_total[i], data->pixel_rate[i]))), bw_int_to_fixed(data->bytes_per_pixel[i])), data->useful_bytes_per_request[i]), data->lines_interleaved_in_mem_access[i]), data->latency_hiding_lines[i]);
 842                         data->display_bandwidth[i] = bw_mul(data->request_bandwidth[i], data->bytes_per_request[i]);
 843                 }
 844         }
 845         /*outstanding chunk request limit*/
 846         /*if underlay buffer sharing is enabled, the data buffer size for underlay in 422 or 444 is the sum of the luma and chroma data buffer sizes.*/
 847         /*underlay buffer sharing mode is only permitted in orthogonal rotation modes.*/
 848         /**/
 849         /*if there is only one display enabled, the dmif data buffer size for the graphics surface is increased by concatenating the adjacent buffers.*/
 850         /**/
 851         /*the memory chunk size in bytes is 1024 for the writeback, and 256 times the memory line interleaving and the bytes per pixel for graphics*/
 852         /*and underlay.*/
 853         /**/
 854         /*the pipe chunk size uses 2 for line interleaving, except for the write back, in which case it is 1.*/
 855         /*graphics and underlay data buffer size is adjusted (limited) using the outstanding chunk request limit if there is more than one*/
 856         /*display enabled or if the dmif request buffer is not large enough for the total data buffer size.*/
 857         /*the outstanding chunk request limit is the ceiling of the adjusted data buffer size divided by the chunk size in bytes*/
 858         /*the adjusted data buffer size is the product of the display bandwidth and the minimum effective data buffer size in terms of time,*/
 859         /*rounded up to the chunk size in bytes, but should not exceed the original data buffer size*/
 860         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 861                 if (data->enable[i]) {
 862                         if ((dceip->dmif_pipe_en_fbc_chunk_tracker + 3 == i && fbc_enabled == 0 && tiling_mode[i] != bw_def_linear)) {
 863                                 data->max_chunks_non_fbc_mode[i] = 128 - dmif_chunk_buff_margin;
 864                         }
 865                         else {
 866                                 data->max_chunks_non_fbc_mode[i] = 16 - dmif_chunk_buff_margin;
 867                         }
 868                 }
 869                 if (data->fbc_en[i] == 1) {
 870                         max_chunks_fbc_mode = 128 - dmif_chunk_buff_margin;
 871                 }
 872         }
 873         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 874                 if (data->enable[i]) {
 875                         switch (surface_type[i]) {
 876                         case bw_def_display_write_back420_luma:
 877                                 data->data_buffer_size[i] = bw_int_to_fixed(dceip->display_write_back420_luma_mcifwr_buffer_size);
 878                                 break;
 879                         case bw_def_display_write_back420_chroma:
 880                                 data->data_buffer_size[i] = bw_int_to_fixed(dceip->display_write_back420_chroma_mcifwr_buffer_size);
 881                                 break;
 882                         case bw_def_underlay420_luma:
 883                                 data->data_buffer_size[i] = bw_int_to_fixed(dceip->underlay_luma_dmif_size);
 884                                 break;
 885                         case bw_def_underlay420_chroma:
 886                                 data->data_buffer_size[i] = bw_div(bw_int_to_fixed(dceip->underlay_chroma_dmif_size), bw_int_to_fixed(2));
 887                                 break;
 888                         case bw_def_underlay422:case bw_def_underlay444:
 889                                 if (data->orthogonal_rotation[i] == 0) {
 890                                         data->data_buffer_size[i] = bw_int_to_fixed(dceip->underlay_luma_dmif_size);
 891                                 }
 892                                 else {
 893                                         data->data_buffer_size[i] = bw_add(bw_int_to_fixed(dceip->underlay_luma_dmif_size), bw_int_to_fixed(dceip->underlay_chroma_dmif_size));
 894                                 }
 895                                 break;
 896                         default:
 897                                 if (data->fbc_en[i] == 1) {
 898                                         /*data_buffer_size(i) = max_dmif_buffer_allocated * graphics_dmif_size*/
 899                                         if (data->number_of_displays == 1) {
 900                                                 data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(max_chunks_fbc_mode), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_mul(bw_int_to_fixed(dceip->max_dmif_buffer_allocated), bw_int_to_fixed(dceip->graphics_dmif_size)));
 901                                         }
 902                                         else {
 903                                                 data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(max_chunks_fbc_mode), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_int_to_fixed(dceip->graphics_dmif_size));
 904                                         }
 905                                 }
 906                                 else {
 907                                         /*the effective dmif buffer size in non-fbc mode is limited by the 16 entry chunk tracker*/
 908                                         if (data->number_of_displays == 1) {
 909                                                 data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(data->max_chunks_non_fbc_mode[i]), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_mul(bw_int_to_fixed(dceip->max_dmif_buffer_allocated), bw_int_to_fixed(dceip->graphics_dmif_size)));
 910                                         }
 911                                         else {
 912                                                 data->data_buffer_size[i] = bw_min2(bw_mul(bw_mul(bw_int_to_fixed(data->max_chunks_non_fbc_mode[i]), bw_int_to_fixed(pixels_per_chunk)), bw_int_to_fixed(data->bytes_per_pixel[i])), bw_int_to_fixed(dceip->graphics_dmif_size));
 913                                         }
 914                                 }
 915                                 break;
 916                         }
 917                         if (surface_type[i] == bw_def_display_write_back420_luma || surface_type[i] == bw_def_display_write_back420_chroma) {
 918                                 data->memory_chunk_size_in_bytes[i] = bw_int_to_fixed(1024);
 919                                 data->pipe_chunk_size_in_bytes[i] = bw_int_to_fixed(1024);
 920                         }
 921                         else {
 922                                 data->memory_chunk_size_in_bytes[i] = bw_mul(bw_mul(bw_int_to_fixed(dceip->chunk_width), data->lines_interleaved_in_mem_access[i]), bw_int_to_fixed(data->bytes_per_pixel[i]));
 923                                 data->pipe_chunk_size_in_bytes[i] = bw_mul(bw_mul(bw_int_to_fixed(dceip->chunk_width), bw_int_to_fixed(dceip->lines_interleaved_into_lb)), bw_int_to_fixed(data->bytes_per_pixel[i]));
 924                         }
 925                 }
 926         }
 927         data->min_dmif_size_in_time = bw_int_to_fixed(9999);
 928         data->min_mcifwr_size_in_time = bw_int_to_fixed(9999);
 929         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 930                 if (data->enable[i]) {
 931                         if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
 932                                 if (bw_ltn(bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]), data->min_dmif_size_in_time)) {
 933                                         data->min_dmif_size_in_time = bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]);
 934                                 }
 935                         }
 936                         else {
 937                                 if (bw_ltn(bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]), data->min_mcifwr_size_in_time)) {
 938                                         data->min_mcifwr_size_in_time = bw_div(bw_div(bw_mul(data->data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]), data->display_bandwidth[i]);
 939                                 }
 940                         }
 941                 }
 942         }
 943         data->total_requests_for_dmif_size = bw_int_to_fixed(0);
 944         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 945                 if (data->enable[i] && surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
 946                         data->total_requests_for_dmif_size = bw_add(data->total_requests_for_dmif_size, bw_div(data->data_buffer_size[i], data->useful_bytes_per_request[i]));
 947                 }
 948         }
 949         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 950                 if (data->enable[i]) {
 951                         if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma && dceip->limit_excessive_outstanding_dmif_requests && (data->number_of_displays > 1 || bw_mtn(data->total_requests_for_dmif_size, dceip->dmif_request_buffer_size))) {
 952                                 data->adjusted_data_buffer_size[i] = bw_min2(data->data_buffer_size[i], bw_ceil2(bw_mul(data->min_dmif_size_in_time, data->display_bandwidth[i]), data->memory_chunk_size_in_bytes[i]));
 953                         }
 954                         else {
 955                                 data->adjusted_data_buffer_size[i] = data->data_buffer_size[i];
 956                         }
 957                 }
 958         }
 959         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 960                 if (data->enable[i]) {
 961                         if (data->number_of_displays == 1 && data->number_of_underlay_surfaces == 0) {
 962                                 /*set maximum chunk limit if only one graphic pipe is enabled*/
 963                                 data->outstanding_chunk_request_limit[i] = bw_int_to_fixed(127);
 964                         }
 965                         else {
 966                                 data->outstanding_chunk_request_limit[i] = bw_ceil2(bw_div(data->adjusted_data_buffer_size[i], data->pipe_chunk_size_in_bytes[i]), bw_int_to_fixed(1));
 967                                 /*clamp maximum chunk limit in the graphic display pipe*/
 968                                 if (i >= 4) {
 969                                         data->outstanding_chunk_request_limit[i] = bw_max2(bw_int_to_fixed(127), data->outstanding_chunk_request_limit[i]);
 970                                 }
 971                         }
 972                 }
 973         }
 974         /*outstanding pte request limit*/
 975         /*in tiling mode with no rotation the sg pte requests are 8 useful pt_es, the sg row height is the page height and the sg page width x height is 64x64 for 8bpp, 64x32 for 16 bpp, 32x32 for 32 bpp*/
 976         /*in tiling mode with rotation the sg pte requests are only one useful pte, and the sg row height is also the page height, but the sg page width and height are swapped*/
 977         /*in linear mode the pte requests are 8 useful pt_es, the sg page width is 4096 divided by the bytes per pixel, the sg page height is 1, but there is just one row whose height is the lines of pte prefetching*/
 978         /*the outstanding pte request limit is obtained by multiplying the outstanding chunk request limit by the peak pte request to eviction limiting ratio, rounding up to integer, multiplying by the pte requests per chunk, and rounding up to integer again*/
 979         /*if not using peak pte request to eviction limiting, the outstanding pte request limit is the pte requests in the vblank*/
 980         /*the pte requests in the vblank is the product of the number of pte request rows times the number of pte requests in a row*/
 981         /*the number of pte requests in a row is the quotient of the source width divided by 256, multiplied by the pte requests per chunk, rounded up to even, multiplied by the scatter-gather row height and divided by the scatter-gather page height*/
 982         /*the pte requests per chunk is 256 divided by the scatter-gather page width and the useful pt_es per pte request*/
 983         if (data->number_of_displays > 1 || (bw_neq(data->rotation_angle[4], bw_int_to_fixed(0)) && bw_neq(data->rotation_angle[4], bw_int_to_fixed(180)))) {
 984                 data->peak_pte_request_to_eviction_ratio_limiting = dceip->peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display;
 985         }
 986         else {
 987                 data->peak_pte_request_to_eviction_ratio_limiting = dceip->peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation;
 988         }
 989         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
 990                 if (data->enable[i] && data->scatter_gather_enable_for_pipe[i] == 1) {
 991                         if (tiling_mode[i] == bw_def_linear) {
 992                                 data->useful_pte_per_pte_request = bw_int_to_fixed(8);
 993                                 data->scatter_gather_page_width[i] = bw_div(bw_int_to_fixed(4096), bw_int_to_fixed(data->bytes_per_pixel[i]));
 994                                 data->scatter_gather_page_height[i] = bw_int_to_fixed(1);
 995                                 data->scatter_gather_pte_request_rows = bw_int_to_fixed(1);
 996                                 data->scatter_gather_row_height = bw_int_to_fixed(dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode);
 997                         }
 998                         else if (bw_equ(data->rotation_angle[i], bw_int_to_fixed(0)) || bw_equ(data->rotation_angle[i], bw_int_to_fixed(180))) {
 999                                 data->useful_pte_per_pte_request = bw_int_to_fixed(8);
1000                                 switch (data->bytes_per_pixel[i]) {
1001                                 case 4:
1002                                         data->scatter_gather_page_width[i] = bw_int_to_fixed(32);
1003                                         data->scatter_gather_page_height[i] = bw_int_to_fixed(32);
1004                                         break;
1005                                 case 2:
1006                                         data->scatter_gather_page_width[i] = bw_int_to_fixed(64);
1007                                         data->scatter_gather_page_height[i] = bw_int_to_fixed(32);
1008                                         break;
1009                                 default:
1010                                         data->scatter_gather_page_width[i] = bw_int_to_fixed(64);
1011                                         data->scatter_gather_page_height[i] = bw_int_to_fixed(64);
1012                                         break;
1013                                 }
1014                                 data->scatter_gather_pte_request_rows = bw_int_to_fixed(dceip->scatter_gather_pte_request_rows_in_tiling_mode);
1015                                 data->scatter_gather_row_height = data->scatter_gather_page_height[i];
1016                         }
1017                         else {
1018                                 data->useful_pte_per_pte_request = bw_int_to_fixed(1);
1019                                 switch (data->bytes_per_pixel[i]) {
1020                                 case 4:
1021                                         data->scatter_gather_page_width[i] = bw_int_to_fixed(32);
1022                                         data->scatter_gather_page_height[i] = bw_int_to_fixed(32);
1023                                         break;
1024                                 case 2:
1025                                         data->scatter_gather_page_width[i] = bw_int_to_fixed(32);
1026                                         data->scatter_gather_page_height[i] = bw_int_to_fixed(64);
1027                                         break;
1028                                 default:
1029                                         data->scatter_gather_page_width[i] = bw_int_to_fixed(64);
1030                                         data->scatter_gather_page_height[i] = bw_int_to_fixed(64);
1031                                         break;
1032                                 }
1033                                 data->scatter_gather_pte_request_rows = bw_int_to_fixed(dceip->scatter_gather_pte_request_rows_in_tiling_mode);
1034                                 data->scatter_gather_row_height = data->scatter_gather_page_height[i];
1035                         }
1036                         data->pte_request_per_chunk[i] = bw_div(bw_div(bw_int_to_fixed(dceip->chunk_width), data->scatter_gather_page_width[i]), data->useful_pte_per_pte_request);
1037                         data->scatter_gather_pte_requests_in_row[i] = bw_div(bw_mul(bw_ceil2(bw_mul(bw_div(data->source_width_rounded_up_to_chunks[i], bw_int_to_fixed(dceip->chunk_width)), data->pte_request_per_chunk[i]), bw_int_to_fixed(1)), data->scatter_gather_row_height), data->scatter_gather_page_height[i]);
1038                         data->scatter_gather_pte_requests_in_vblank = bw_mul(data->scatter_gather_pte_request_rows, data->scatter_gather_pte_requests_in_row[i]);
1039                         if (bw_equ(data->peak_pte_request_to_eviction_ratio_limiting, bw_int_to_fixed(0))) {
1040                                 data->scatter_gather_pte_request_limit[i] = data->scatter_gather_pte_requests_in_vblank;
1041                         }
1042                         else {
1043                                 data->scatter_gather_pte_request_limit[i] = bw_max2(dceip->minimum_outstanding_pte_request_limit, bw_min2(data->scatter_gather_pte_requests_in_vblank, bw_ceil2(bw_mul(bw_mul(bw_div(bw_ceil2(data->adjusted_data_buffer_size[i], data->memory_chunk_size_in_bytes[i]), data->memory_chunk_size_in_bytes[i]), data->pte_request_per_chunk[i]), data->peak_pte_request_to_eviction_ratio_limiting), bw_int_to_fixed(1))));
1044                         }
1045                 }
1046         }
1047         /*pitch padding recommended for efficiency in linear mode*/
1048         /*in linear mode graphics or underlay with scatter gather, a pitch that is a multiple of the channel interleave (256 bytes) times the channel-bank rotation is not efficient*/
1049         /*if that is the case it is recommended to pad the pitch by at least 256 pixels*/
1050         data->inefficient_linear_pitch_in_bytes = bw_mul(bw_mul(bw_int_to_fixed(256), bw_int_to_fixed(vbios->number_of_dram_banks)), bw_int_to_fixed(data->number_of_dram_channels));
1051
1052         /*pixel transfer time*/
1053         /*the dmif and mcifwr yclk(pclk) required is the one that allows the transfer of all pipe's data buffer size in memory in the time for data transfer*/
1054         /*for dmif, pte and cursor requests have to be included.*/
1055         /*the dram data requirement is doubled when the data request size in bytes is less than the dram channel width times the burst size (8)*/
1056         /*the dram data requirement is also multiplied by the number of channels in the case of low power tiling*/
1057         /*the page close-open time is determined by trc and the number of page close-opens*/
1058         /*in tiled mode graphics or underlay with scatter-gather enabled the bytes per page close-open is the product of the memory line interleave times the maximum of the scatter-gather page width and the product of the tile width (8 pixels) times the number of channels times the number of banks.*/
1059         /*in linear mode graphics or underlay with scatter-gather enabled and inefficient pitch, the bytes per page close-open is the line request alternation slice, because different lines are in completely different 4k address bases.*/
1060         /*otherwise, the bytes page close-open is the chunk size because that is the arbitration slice.*/
1061         /*pte requests are grouped by pte requests per chunk if that is more than 1. each group costs a page close-open time for dmif reads*/
1062         /*cursor requests outstanding are limited to a group of two source lines. each group costs a page close-open time for dmif reads*/
1063         /*the display reads and writes time for data transfer is the minimum data or cursor buffer size in time minus the mc urgent latency*/
1064         /*the mc urgent latency is experienced more than one time if the number of dmif requests in the data buffer exceeds the request buffer size plus the request slots reserved for dmif in the dram channel arbiter queues*/
1065         /*the dispclk required is the maximum for all surfaces of the maximum of the source pixels for first output pixel times the throughput factor, divided by the pixels per dispclk, and divided by the minimum latency hiding minus the dram speed/p-state change latency minus the burst time, and the source pixels for last output pixel, times the throughput factor, divided by the pixels per dispclk, and divided by the minimum latency hiding minus the dram speed/p-state change latency minus the burst time, plus the active time.*/
1066         /*the data burst time is the maximum of the total page close-open time, total dmif/mcifwr buffer size in memory divided by the dram bandwidth, and the total dmif/mcifwr buffer size in memory divided by the 32 byte sclk data bus bandwidth, each multiplied by its efficiency.*/
1067         /*the source line transfer time is the maximum for all surfaces of the maximum of the burst time plus the urgent latency times the floor of the data required divided by the buffer size for the fist pixel, and the burst time plus the urgent latency times the floor of the data required divided by the buffer size for the last pixel plus the active time.*/
1068         /*the source pixels for the first output pixel is 512 if the scaler vertical filter initialization value is greater than 2, and it is 4 times the source width if it is greater than 4.*/
1069         /*the source pixels for the last output pixel is the source width times the scaler vertical filter initialization value rounded up to even*/
1070         /*the source data for these pixels is the number of pixels times the bytes per pixel times the bytes per request divided by the useful bytes per request.*/
1071         data->cursor_total_data = bw_int_to_fixed(0);
1072         data->cursor_total_request_groups = bw_int_to_fixed(0);
1073         data->scatter_gather_total_pte_requests = bw_int_to_fixed(0);
1074         data->scatter_gather_total_pte_request_groups = bw_int_to_fixed(0);
1075         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1076                 if (data->enable[i]) {
1077                         data->cursor_total_data = bw_add(data->cursor_total_data, bw_mul(bw_mul(bw_int_to_fixed(2), data->cursor_width_pixels[i]), bw_int_to_fixed(4)));
1078                         if (dceip->large_cursor == 1) {
1079                                 data->cursor_total_request_groups = bw_add(data->cursor_total_request_groups, bw_int_to_fixed((dceip->cursor_max_outstanding_group_num + 1)));
1080                         }
1081                         else {
1082                                 data->cursor_total_request_groups = bw_add(data->cursor_total_request_groups, bw_ceil2(bw_div(data->cursor_width_pixels[i], dceip->cursor_chunk_width), bw_int_to_fixed(1)));
1083                         }
1084                         if (data->scatter_gather_enable_for_pipe[i]) {
1085                                 data->scatter_gather_total_pte_requests = bw_add(data->scatter_gather_total_pte_requests, data->scatter_gather_pte_request_limit[i]);
1086                                 data->scatter_gather_total_pte_request_groups = bw_add(data->scatter_gather_total_pte_request_groups, bw_ceil2(bw_div(data->scatter_gather_pte_request_limit[i], bw_ceil2(data->pte_request_per_chunk[i], bw_int_to_fixed(1))), bw_int_to_fixed(1)));
1087                         }
1088                 }
1089         }
1090         data->tile_width_in_pixels = bw_int_to_fixed(8);
1091         data->dmif_total_number_of_data_request_page_close_open = bw_int_to_fixed(0);
1092         data->mcifwr_total_number_of_data_request_page_close_open = bw_int_to_fixed(0);
1093         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1094                 if (data->enable[i]) {
1095                         if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] != bw_def_linear) {
1096                                 data->bytes_per_page_close_open = bw_mul(data->lines_interleaved_in_mem_access[i], bw_max2(bw_mul(bw_mul(bw_mul(bw_int_to_fixed(data->bytes_per_pixel[i]), data->tile_width_in_pixels), bw_int_to_fixed(vbios->number_of_dram_banks)), bw_int_to_fixed(data->number_of_dram_channels)), bw_mul(bw_int_to_fixed(data->bytes_per_pixel[i]), data->scatter_gather_page_width[i])));
1097                         }
1098                         else if (data->scatter_gather_enable_for_pipe[i] == 1 && tiling_mode[i] == bw_def_linear && bw_equ(bw_mod((bw_mul(data->pitch_in_pixels_after_surface_type[i], bw_int_to_fixed(data->bytes_per_pixel[i]))), data->inefficient_linear_pitch_in_bytes), bw_int_to_fixed(0))) {
1099                                 data->bytes_per_page_close_open = dceip->linear_mode_line_request_alternation_slice;
1100                         }
1101                         else {
1102                                 data->bytes_per_page_close_open = data->memory_chunk_size_in_bytes[i];
1103                         }
1104                         if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1105                                 data->dmif_total_number_of_data_request_page_close_open = bw_add(data->dmif_total_number_of_data_request_page_close_open, bw_div(bw_ceil2(data->adjusted_data_buffer_size[i], data->memory_chunk_size_in_bytes[i]), data->bytes_per_page_close_open));
1106                         }
1107                         else {
1108                                 data->mcifwr_total_number_of_data_request_page_close_open = bw_add(data->mcifwr_total_number_of_data_request_page_close_open, bw_div(bw_ceil2(data->adjusted_data_buffer_size[i], data->memory_chunk_size_in_bytes[i]), data->bytes_per_page_close_open));
1109                         }
1110                 }
1111         }
1112         data->dmif_total_page_close_open_time = bw_div(bw_mul((bw_add(bw_add(data->dmif_total_number_of_data_request_page_close_open, data->scatter_gather_total_pte_request_groups), data->cursor_total_request_groups)), vbios->trc), bw_int_to_fixed(1000));
1113         data->mcifwr_total_page_close_open_time = bw_div(bw_mul(data->mcifwr_total_number_of_data_request_page_close_open, vbios->trc), bw_int_to_fixed(1000));
1114         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1115                 if (data->enable[i]) {
1116                         data->adjusted_data_buffer_size_in_memory[i] = bw_div(bw_mul(data->adjusted_data_buffer_size[i], data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
1117                 }
1118         }
1119         data->total_requests_for_adjusted_dmif_size = bw_int_to_fixed(0);
1120         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1121                 if (data->enable[i]) {
1122                         if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1123                                 data->total_requests_for_adjusted_dmif_size = bw_add(data->total_requests_for_adjusted_dmif_size, bw_div(data->adjusted_data_buffer_size[i], data->useful_bytes_per_request[i]));
1124                         }
1125                 }
1126         }
1127         data->total_dmifmc_urgent_trips = bw_ceil2(bw_div(data->total_requests_for_adjusted_dmif_size, (bw_add(dceip->dmif_request_buffer_size, bw_int_to_fixed(vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel * data->number_of_dram_channels)))), bw_int_to_fixed(1));
1128         data->total_dmifmc_urgent_latency = bw_mul(vbios->dmifmc_urgent_latency, data->total_dmifmc_urgent_trips);
1129         data->total_display_reads_required_data = bw_int_to_fixed(0);
1130         data->total_display_reads_required_dram_access_data = bw_int_to_fixed(0);
1131         data->total_display_writes_required_data = bw_int_to_fixed(0);
1132         data->total_display_writes_required_dram_access_data = bw_int_to_fixed(0);
1133         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1134                 if (data->enable[i]) {
1135                         if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1136                                 data->display_reads_required_data = data->adjusted_data_buffer_size_in_memory[i];
1137                                 /*for hbm memories, each channel is split into 2 pseudo-channels that are each 64 bits in width.  each*/
1138                                 /*pseudo-channel may be read independently of one another.*/
1139                                 /*the read burst length (bl) for hbm memories is 4, so each read command will access 32 bytes of data.*/
1140                                 /*the 64 or 32 byte sized data is stored in one pseudo-channel.*/
1141                                 /*it will take 4 memclk cycles or 8 yclk cycles to fetch 64 bytes of data from the hbm memory (2 read commands).*/
1142                                 /*it will take 2 memclk cycles or 4 yclk cycles to fetch 32 bytes of data from the hbm memory (1 read command).*/
1143                                 /*for gddr5/ddr4 memories, there is additional overhead if the size of the request is smaller than 64 bytes.*/
1144                                 /*the read burst length (bl) for gddr5/ddr4 memories is 8, regardless of the size of the data request.*/
1145                                 /*therefore it will require 8 cycles to fetch 64 or 32 bytes of data from the memory.*/
1146                                 /*the memory efficiency will be 50% for the 32 byte sized data.*/
1147                                 if (vbios->memory_type == bw_def_hbm) {
1148                                         data->display_reads_required_dram_access_data = data->adjusted_data_buffer_size_in_memory[i];
1149                                 }
1150                                 else {
1151                                         data->display_reads_required_dram_access_data = bw_mul(data->adjusted_data_buffer_size_in_memory[i], bw_ceil2(bw_div(bw_int_to_fixed((8 * vbios->dram_channel_width_in_bits / 8)), data->bytes_per_request[i]), bw_int_to_fixed(1)));
1152                                 }
1153                                 data->total_display_reads_required_data = bw_add(data->total_display_reads_required_data, data->display_reads_required_data);
1154                                 data->total_display_reads_required_dram_access_data = bw_add(data->total_display_reads_required_dram_access_data, data->display_reads_required_dram_access_data);
1155                         }
1156                         else {
1157                                 data->total_display_writes_required_data = bw_add(data->total_display_writes_required_data, data->adjusted_data_buffer_size_in_memory[i]);
1158                                 data->total_display_writes_required_dram_access_data = bw_add(data->total_display_writes_required_dram_access_data, bw_mul(data->adjusted_data_buffer_size_in_memory[i], bw_ceil2(bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits), data->bytes_per_request[i]), bw_int_to_fixed(1))));
1159                         }
1160                 }
1161         }
1162         data->total_display_reads_required_data = bw_add(bw_add(data->total_display_reads_required_data, data->cursor_total_data), bw_mul(data->scatter_gather_total_pte_requests, bw_int_to_fixed(64)));
1163         data->total_display_reads_required_dram_access_data = bw_add(bw_add(data->total_display_reads_required_dram_access_data, data->cursor_total_data), bw_mul(data->scatter_gather_total_pte_requests, bw_int_to_fixed(64)));
1164         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1165                 if (data->enable[i]) {
1166                         if (bw_mtn(data->v_filter_init[i], bw_int_to_fixed(4))) {
1167                                 data->src_pixels_for_first_output_pixel[i] = bw_mul(bw_int_to_fixed(4), data->source_width_rounded_up_to_chunks[i]);
1168                         }
1169                         else {
1170                                 if (bw_mtn(data->v_filter_init[i], bw_int_to_fixed(2))) {
1171                                         data->src_pixels_for_first_output_pixel[i] = bw_int_to_fixed(512);
1172                                 }
1173                                 else {
1174                                         data->src_pixels_for_first_output_pixel[i] = bw_int_to_fixed(0);
1175                                 }
1176                         }
1177                         data->src_data_for_first_output_pixel[i] = bw_div(bw_mul(bw_mul(data->src_pixels_for_first_output_pixel[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
1178                         data->src_pixels_for_last_output_pixel[i] = bw_mul(data->source_width_rounded_up_to_chunks[i], bw_max2(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), bw_mul(bw_ceil2(data->vsr[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->horizontal_blank_and_chunk_granularity_factor[i])));
1179                         data->src_data_for_last_output_pixel[i] = bw_div(bw_mul(bw_mul(bw_mul(data->source_width_rounded_up_to_chunks[i], bw_max2(bw_ceil2(data->v_filter_init[i], bw_int_to_fixed(dceip->lines_interleaved_into_lb)), data->lines_interleaved_in_mem_access[i])), bw_int_to_fixed(data->bytes_per_pixel[i])), data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
1180                         data->active_time[i] = bw_div(bw_div(data->source_width_rounded_up_to_chunks[i], data->hsr[i]), data->pixel_rate[i]);
1181                 }
1182         }
1183         for (i = 0; i <= 2; i++) {
1184                 for (j = 0; j <= 7; j++) {
1185                         data->dmif_burst_time[i][j] = bw_max3(data->dmif_total_page_close_open_time, bw_div(data->total_display_reads_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels)))), bw_div(data->total_display_reads_required_data, (bw_mul(bw_mul(sclk[j], vbios->data_return_bus_width), bw_frc_to_fixed(dceip->percent_of_ideal_port_bw_received_after_urgent_latency, 100)))));
1186                         if (data->d1_display_write_back_dwb_enable == 1) {
1187                                 data->mcifwr_burst_time[i][j] = bw_max3(data->mcifwr_total_page_close_open_time, bw_div(data->total_display_writes_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_wrchannels)))), bw_div(data->total_display_writes_required_data, (bw_mul(sclk[j], vbios->data_return_bus_width))));
1188                         }
1189                 }
1190         }
1191         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1192                 for (j = 0; j <= 2; j++) {
1193                         for (k = 0; k <= 7; k++) {
1194                                 if (data->enable[i]) {
1195                                         if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1196                                                 /*time to transfer data from the dmif buffer to the lb.  since the mc to dmif transfer time overlaps*/
1197                                                 /*with the dmif to lb transfer time, only time to transfer the last chunk  is considered.*/
1198                                                 data->dmif_buffer_transfer_time[i] = bw_mul(data->source_width_rounded_up_to_chunks[i], (bw_div(dceip->lb_write_pixels_per_dispclk, (bw_div(vbios->low_voltage_max_dispclk, dceip->display_pipe_throughput_factor)))));
1199                                                 data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_add(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->dmif_buffer_transfer_time[i]), data->active_time[i]));
1200                                                 /*during an mclk switch the requests from the dce ip are stored in the gmc/arb.  these requests should be serviced immediately*/
1201                                                 /*after the mclk switch sequence and not incur an urgent latency penalty.  it is assumed that the gmc/arb can hold up to 256 requests*/
1202                                                 /*per memory channel.  if the dce ip is urgent after the mclk switch sequence, all pending requests and subsequent requests should be*/
1203                                                 /*immediately serviced without a gap in the urgent requests.*/
1204                                                 /*the latency incurred would be the time to issue the requests and return the data for the first or last output pixel.*/
1205                                                 if (surface_type[i] == bw_def_graphics) {
1206                                                         switch (data->lb_bpc[i]) {
1207                                                         case 6:
1208                                                                 data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency6_bit_per_component;
1209                                                                 break;
1210                                                         case 8:
1211                                                                 data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency8_bit_per_component;
1212                                                                 break;
1213                                                         case 10:
1214                                                                 data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency10_bit_per_component;
1215                                                                 break;
1216                                                         default:
1217                                                                 data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency12_bit_per_component;
1218                                                                 break;
1219                                                         }
1220                                                         if (data->use_alpha[i] == 1) {
1221                                                                 data->v_scaler_efficiency = bw_min2(data->v_scaler_efficiency, dceip->alpha_vscaler_efficiency);
1222                                                         }
1223                                                 }
1224                                                 else {
1225                                                         switch (data->lb_bpc[i]) {
1226                                                         case 6:
1227                                                                 data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency6_bit_per_component;
1228                                                                 break;
1229                                                         case 8:
1230                                                                 data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency8_bit_per_component;
1231                                                                 break;
1232                                                         case 10:
1233                                                                 data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency10_bit_per_component;
1234                                                                 break;
1235                                                         default:
1236                                                                 data->v_scaler_efficiency = bw_int_to_fixed(3);
1237                                                                 break;
1238                                                         }
1239                                                 }
1240                                                 if (dceip->pre_downscaler_enabled && bw_mtn(data->hsr[i], bw_int_to_fixed(1))) {
1241                                                         data->scaler_limits_factor = bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_div(data->source_width_rounded_up_to_chunks[i], data->h_total[i]));
1242                                                 }
1243                                                 else {
1244                                                         data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1))));
1245                                                 }
1246                                                 data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_mul(bw_int_to_fixed(2), bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]))))));
1247                                         }
1248                                         else {
1249                                                 data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]));
1250                                                 /*during an mclk switch the requests from the dce ip are stored in the gmc/arb.  these requests should be serviced immediately*/
1251                                                 /*after the mclk switch sequence and not incur an urgent latency penalty.  it is assumed that the gmc/arb can hold up to 256 requests*/
1252                                                 /*per memory channel.  if the dce ip is urgent after the mclk switch sequence, all pending requests and subsequent requests should be*/
1253                                                 /*immediately serviced without a gap in the urgent requests.*/
1254                                                 /*the latency incurred would be the time to issue the requests and return the data for the first or last output pixel.*/
1255                                                 data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i])))));
1256                                         }
1257                                 }
1258                         }
1259                 }
1260         }
1261         /*cpu c-state and p-state change enable*/
1262         /*for cpu p-state change to be possible for a yclk(pclk) and sclk level the dispclk required has to be enough for the blackout duration*/
1263         /*for cpu c-state change to be possible for a yclk(pclk) and sclk level the dispclk required has to be enough for the blackout duration and recovery*/
1264         /*condition for the blackout duration:*/
1265         /* minimum latency hiding > blackout duration + dmif burst time + line source transfer time*/
1266         /*condition for the blackout recovery:*/
1267         /* recovery time >  dmif burst time + 2 * urgent latency*/
1268         /* recovery time > (display bw * blackout duration  + (2 * urgent latency + dmif burst time)*dispclk - dmif size )*/
1269         /*                  / (dispclk - display bw)*/
1270         /*the minimum latency hiding is the minimum for all pipes of one screen line time, plus one more line time if doing lb prefetch, plus the dmif data buffer size equivalent in time, minus the urgent latency.*/
1271         /*the minimum latency hiding is  further limited by the cursor.  the cursor latency hiding is the number of lines of the cursor buffer, minus one if the downscaling is less than two, or minus three if it is more*/
1272
1273         /*initialize variables*/
1274         number_of_displays_enabled = 0;
1275         number_of_displays_enabled_with_margin = 0;
1276         for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1277                 if (data->enable[k]) {
1278                         number_of_displays_enabled = number_of_displays_enabled + 1;
1279                 }
1280                 data->display_pstate_change_enable[k] = 0;
1281         }
1282         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1283                 if (data->enable[i]) {
1284                         if ((bw_equ(dceip->stutter_and_dram_clock_state_change_gated_before_cursor, bw_int_to_fixed(0)) && bw_mtn(data->cursor_width_pixels[i], bw_int_to_fixed(0)))) {
1285                                 if (bw_ltn(data->vsr[i], bw_int_to_fixed(2))) {
1286                                         data->cursor_latency_hiding[i] = bw_div(bw_div(bw_mul((bw_sub(dceip->cursor_dcp_buffer_lines, bw_int_to_fixed(1))), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]);
1287                                 }
1288                                 else {
1289                                         data->cursor_latency_hiding[i] = bw_div(bw_div(bw_mul((bw_sub(dceip->cursor_dcp_buffer_lines, bw_int_to_fixed(3))), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]);
1290                                 }
1291                         }
1292                         else {
1293                                 data->cursor_latency_hiding[i] = bw_int_to_fixed(9999);
1294                         }
1295                 }
1296         }
1297         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1298                 if (data->enable[i]) {
1299                         if (dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1 && (bw_equ(data->vsr[i], bw_int_to_fixed(1)) || (bw_leq(data->vsr[i], bw_frc_to_fixed(8, 10)) && bw_leq(data->v_taps[i], bw_int_to_fixed(2)) && data->lb_bpc[i] == 8)) && surface_type[i] == bw_def_graphics) {
1300                                 if (number_of_displays_enabled > 2)
1301                                         data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_sub(data->lb_partitions[i], bw_int_to_fixed(2)), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);
1302                                 else
1303                                         data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_sub(data->lb_partitions[i], bw_int_to_fixed(1)), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);
1304                         }
1305                         else {
1306                                 data->minimum_latency_hiding[i] = bw_sub(bw_div(bw_mul((bw_div((bw_add(bw_int_to_fixed(1 + data->line_buffer_prefetch[i]), bw_div(bw_div(data->data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_pixels[i]))), data->vsr[i])), data->h_total[i]), data->pixel_rate[i]), data->total_dmifmc_urgent_latency);
1307                         }
1308                         data->minimum_latency_hiding_with_cursor[i] = bw_min2(data->minimum_latency_hiding[i], data->cursor_latency_hiding[i]);
1309                 }
1310         }
1311         for (i = 0; i <= 2; i++) {
1312                 for (j = 0; j <= 7; j++) {
1313                         data->blackout_duration_margin[i][j] = bw_int_to_fixed(9999);
1314                         data->dispclk_required_for_blackout_duration[i][j] = bw_int_to_fixed(0);
1315                         data->dispclk_required_for_blackout_recovery[i][j] = bw_int_to_fixed(0);
1316                         for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1317                                 if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0))) {
1318                                         if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
1319                                                 data->blackout_duration_margin[i][j] = bw_min2(data->blackout_duration_margin[i][j], bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->line_source_transfer_time[k][i][j]));
1320                                                 data->dispclk_required_for_blackout_duration[i][j] = bw_max3(data->dispclk_required_for_blackout_duration[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->active_time[k]))));
1321                                                 if (bw_leq(vbios->maximum_blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j]))) {
1322                                                         data->dispclk_required_for_blackout_recovery[i][j] = bw_int_to_fixed(9999);
1323                                                 }
1324                                                 else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) {
1325                                                         data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, bw_sub(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k]));
1326                                                 }
1327                                         }
1328                                         else {
1329                                                 data->blackout_duration_margin[i][j] = bw_min2(data->blackout_duration_margin[i][j], bw_sub(bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->line_source_transfer_time[k][i][j]));
1330                                                 data->dispclk_required_for_blackout_duration[i][j] = bw_max3(data->dispclk_required_for_blackout_duration[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->active_time[k]))));
1331                                                 if (bw_ltn(vbios->maximum_blackout_recovery_time, bw_add(bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]))) {
1332                                                         data->dispclk_required_for_blackout_recovery[i][j] = bw_int_to_fixed(9999);
1333                                                 }
1334                                                 else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) {
1335                                                         data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, (bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j]))))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k]));
1336                                                 }
1337                                         }
1338                                 }
1339                         }
1340                 }
1341         }
1342         if (bw_mtn(data->blackout_duration_margin[high][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[high][s_high], vbios->high_voltage_max_dispclk)) {
1343                 data->cpup_state_change_enable = bw_def_yes;
1344                 if (bw_ltn(data->dispclk_required_for_blackout_recovery[high][s_high], vbios->high_voltage_max_dispclk)) {
1345                         data->cpuc_state_change_enable = bw_def_yes;
1346                 }
1347                 else {
1348                         data->cpuc_state_change_enable = bw_def_no;
1349                 }
1350         }
1351         else {
1352                 data->cpup_state_change_enable = bw_def_no;
1353                 data->cpuc_state_change_enable = bw_def_no;
1354         }
1355         /*nb p-state change enable*/
1356         /*for dram speed/p-state change to be possible for a yclk(pclk) and sclk level there has to be positive margin and the dispclk required has to be*/
1357         /*below the maximum.*/
1358         /*the dram speed/p-state change margin is the minimum for all surfaces of the maximum latency hiding minus the dram speed/p-state change latency,*/
1359         /*minus the dmif burst time, minus the source line transfer time*/
1360         /*the maximum latency hiding is the minimum latency hiding plus one source line used for de-tiling in the line buffer, plus half the urgent latency*/
1361         /*if stutter and dram clock state change are gated before cursor then the cursor latency hiding does not limit stutter or dram clock state change*/
1362         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1363                 if (data->enable[i]) {
1364                         if (dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1) {
1365                                 data->maximum_latency_hiding[i] = bw_add(data->minimum_latency_hiding[i], bw_mul(bw_frc_to_fixed(5, 10), data->total_dmifmc_urgent_latency));
1366                         }
1367                         else {
1368                                 /*maximum_latency_hiding(i) = minimum_latency_hiding(i) + 1 / vsr(i) * h_total(i) / pixel_rate(i) + 0.5 * total_dmifmc_urgent_latency*/
1369                                 data->maximum_latency_hiding[i] = bw_add(data->minimum_latency_hiding[i], bw_mul(bw_frc_to_fixed(5, 10), data->total_dmifmc_urgent_latency));
1370                         }
1371                         data->maximum_latency_hiding_with_cursor[i] = bw_min2(data->maximum_latency_hiding[i], data->cursor_latency_hiding[i]);
1372                 }
1373         }
1374         for (i = 0; i <= 2; i++) {
1375                 for (j = 0; j <= 7; j++) {
1376                         data->min_dram_speed_change_margin[i][j] = bw_int_to_fixed(9999);
1377                         data->dram_speed_change_margin = bw_int_to_fixed(9999);
1378                         data->dispclk_required_for_dram_speed_change[i][j] = bw_int_to_fixed(0);
1379                         data->num_displays_with_margin[i][j] = 0;
1380                         for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1381                                 if (data->enable[k]) {
1382                                         if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
1383                                                 data->dram_speed_change_margin = bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]);
1384                                                 if ((bw_mtn(data->dram_speed_change_margin, bw_int_to_fixed(0)) && bw_ltn(data->dram_speed_change_margin, bw_int_to_fixed(9999)))) {
1385                                                         /*determine the minimum dram clock change margin for each set of clock frequencies*/
1386                                                         data->min_dram_speed_change_margin[i][j] = bw_min2(data->min_dram_speed_change_margin[i][j], data->dram_speed_change_margin);
1387                                                         /*compute the maximum clock frequuency required for the dram clock change at each set of clock frequencies*/
1388                                                         data->dispclk_required_for_dram_speed_change_pipe[i][j] = bw_max2(bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->active_time[k]))));
1389                                                         if ((bw_ltn(data->dispclk_required_for_dram_speed_change_pipe[i][j], vbios->high_voltage_max_dispclk))) {
1390                                                                 data->display_pstate_change_enable[k] = 1;
1391                                                                 data->num_displays_with_margin[i][j] = data->num_displays_with_margin[i][j] + 1;
1392                                                                 data->dispclk_required_for_dram_speed_change[i][j] = bw_max2(data->dispclk_required_for_dram_speed_change[i][j], data->dispclk_required_for_dram_speed_change_pipe[i][j]);
1393                                                         }
1394                                                 }
1395                                         }
1396                                         else {
1397                                                 data->dram_speed_change_margin = bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]);
1398                                                 if ((bw_mtn(data->dram_speed_change_margin, bw_int_to_fixed(0)) && bw_ltn(data->dram_speed_change_margin, bw_int_to_fixed(9999)))) {
1399                                                         /*determine the minimum dram clock change margin for each display pipe*/
1400                                                         data->min_dram_speed_change_margin[i][j] = bw_min2(data->min_dram_speed_change_margin[i][j], data->dram_speed_change_margin);
1401                                                         /*compute the maximum clock frequuency required for the dram clock change at each set of clock frequencies*/
1402                                                         data->dispclk_required_for_dram_speed_change_pipe[i][j] = bw_max2(bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][j]), data->active_time[k]))));
1403                                                         if ((bw_ltn(data->dispclk_required_for_dram_speed_change_pipe[i][j], vbios->high_voltage_max_dispclk))) {
1404                                                                 data->display_pstate_change_enable[k] = 1;
1405                                                                 data->num_displays_with_margin[i][j] = data->num_displays_with_margin[i][j] + 1;
1406                                                                 data->dispclk_required_for_dram_speed_change[i][j] = bw_max2(data->dispclk_required_for_dram_speed_change[i][j], data->dispclk_required_for_dram_speed_change_pipe[i][j]);
1407                                                         }
1408                                                 }
1409                                         }
1410                                 }
1411                         }
1412                 }
1413         }
1414         /*determine the number of displays with margin to switch in the v_active region*/
1415         for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1416                 if (data->enable[k] == 1 && data->display_pstate_change_enable[k] == 1) {
1417                         number_of_displays_enabled_with_margin = number_of_displays_enabled_with_margin + 1;
1418                 }
1419         }
1420         /*determine the number of displays that don't have any dram clock change margin, but*/
1421         /*have the same resolution.  these displays can switch in a common vblank region if*/
1422         /*their frames are aligned.*/
1423         data->min_vblank_dram_speed_change_margin = bw_int_to_fixed(9999);
1424         for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1425                 if (data->enable[k]) {
1426                         if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
1427                                 data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
1428                                 data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]);
1429                         }
1430                         else {
1431                                 data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->mcifwr_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]);
1432                                 data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]);
1433                         }
1434                 }
1435         }
1436         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1437                 data->displays_with_same_mode[i] = bw_int_to_fixed(0);
1438                 if (data->enable[i] == 1 && data->display_pstate_change_enable[i] == 0 && bw_mtn(data->v_blank_dram_speed_change_margin[i], bw_int_to_fixed(0))) {
1439                         for (j = 0; j <= maximum_number_of_surfaces - 1; j++) {
1440                                 if ((i == j || data->display_synchronization_enabled) && (data->enable[j] == 1 && bw_equ(data->source_width_rounded_up_to_chunks[i], data->source_width_rounded_up_to_chunks[j]) && bw_equ(data->source_height_rounded_up_to_chunks[i], data->source_height_rounded_up_to_chunks[j]) && bw_equ(data->vsr[i], data->vsr[j]) && bw_equ(data->hsr[i], data->hsr[j]) && bw_equ(data->pixel_rate[i], data->pixel_rate[j]))) {
1441                                         data->displays_with_same_mode[i] = bw_add(data->displays_with_same_mode[i], bw_int_to_fixed(1));
1442                                 }
1443                         }
1444                 }
1445         }
1446         /*compute the maximum number of aligned displays with no margin*/
1447         number_of_aligned_displays_with_no_margin = 0;
1448         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1449                 number_of_aligned_displays_with_no_margin = bw_fixed_to_int(bw_max2(bw_int_to_fixed(number_of_aligned_displays_with_no_margin), data->displays_with_same_mode[i]));
1450         }
1451         /*dram clock change is possible, if all displays have positive margin except for one display or a group of*/
1452         /*aligned displays with the same timing.*/
1453         /*the display(s) with the negative margin can be switched in the v_blank region while the other*/
1454         /*displays are in v_blank or v_active.*/
1455         if (number_of_displays_enabled_with_margin > 0 && (number_of_displays_enabled_with_margin + number_of_aligned_displays_with_no_margin) == number_of_displays_enabled && bw_mtn(data->min_dram_speed_change_margin[high][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[high][s_high], bw_int_to_fixed(9999)) && bw_ltn(data->dispclk_required_for_dram_speed_change[high][s_high], vbios->high_voltage_max_dispclk)) {
1456                 data->nbp_state_change_enable = bw_def_yes;
1457         }
1458         else {
1459                 data->nbp_state_change_enable = bw_def_no;
1460         }
1461         /*dram clock change is possible only in vblank if all displays are aligned and have no margin*/
1462         if (number_of_aligned_displays_with_no_margin == number_of_displays_enabled) {
1463                 nbp_state_change_enable_blank = bw_def_yes;
1464         }
1465         else {
1466                 nbp_state_change_enable_blank = bw_def_no;
1467         }
1468
1469         /*average bandwidth*/
1470         /*the average bandwidth with no compression is the vertical active time is the source width times the bytes per pixel divided by the line time, multiplied by the vertical scale ratio and the ratio of bytes per request divided by the useful bytes per request.*/
1471         /*the average bandwidth with compression is the same, divided by the compression ratio*/
1472         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1473                 if (data->enable[i]) {
1474                         data->average_bandwidth_no_compression[i] = bw_div(bw_mul(bw_mul(bw_div(bw_mul(data->source_width_rounded_up_to_chunks[i], bw_int_to_fixed(data->bytes_per_pixel[i])), (bw_div(data->h_total[i], data->pixel_rate[i]))), data->vsr[i]), data->bytes_per_request[i]), data->useful_bytes_per_request[i]);
1475                         data->average_bandwidth[i] = bw_div(data->average_bandwidth_no_compression[i], data->compression_rate[i]);
1476                 }
1477         }
1478         data->total_average_bandwidth_no_compression = bw_int_to_fixed(0);
1479         data->total_average_bandwidth = bw_int_to_fixed(0);
1480         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1481                 if (data->enable[i]) {
1482                         data->total_average_bandwidth_no_compression = bw_add(data->total_average_bandwidth_no_compression, data->average_bandwidth_no_compression[i]);
1483                         data->total_average_bandwidth = bw_add(data->total_average_bandwidth, data->average_bandwidth[i]);
1484                 }
1485         }
1486
1487         /*required yclk(pclk)*/
1488         /*yclk requirement only makes sense if the dmif and mcifwr data total page close-open time is less than the time for data transfer and the total pte requests fit in the scatter-gather saw queque size*/
1489         /*if that is the case, the yclk requirement is the maximum of the ones required by dmif and mcifwr, and the high/low yclk(pclk) is chosen accordingly*/
1490         /*high yclk(pclk) has to be selected when dram speed/p-state change is not possible.*/
1491         data->min_cursor_memory_interface_buffer_size_in_time = bw_int_to_fixed(9999);
1492         /* number of cursor lines stored in the cursor data return buffer*/
1493         num_cursor_lines = 0;
1494         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1495                 if (data->enable[i]) {
1496                         if (bw_mtn(data->cursor_width_pixels[i], bw_int_to_fixed(0))) {
1497                                 /*compute number of cursor lines stored in data return buffer*/
1498                                 if (bw_leq(data->cursor_width_pixels[i], bw_int_to_fixed(64)) && dceip->large_cursor == 1) {
1499                                         num_cursor_lines = 4;
1500                                 }
1501                                 else {
1502                                         num_cursor_lines = 2;
1503                                 }
1504                                 data->min_cursor_memory_interface_buffer_size_in_time = bw_min2(data->min_cursor_memory_interface_buffer_size_in_time, bw_div(bw_mul(bw_div(bw_int_to_fixed(num_cursor_lines), data->vsr[i]), data->h_total[i]), data->pixel_rate[i]));
1505                         }
1506                 }
1507         }
1508         /*compute minimum time to read one chunk from the dmif buffer*/
1509         if (number_of_displays_enabled > 2) {
1510                 data->chunk_request_delay = 0;
1511         }
1512         else {
1513                 data->chunk_request_delay = bw_fixed_to_int(bw_div(bw_int_to_fixed(512), vbios->high_voltage_max_dispclk));
1514         }
1515         data->min_read_buffer_size_in_time = bw_min2(data->min_cursor_memory_interface_buffer_size_in_time, data->min_dmif_size_in_time);
1516         data->display_reads_time_for_data_transfer = bw_sub(bw_sub(data->min_read_buffer_size_in_time, data->total_dmifmc_urgent_latency), bw_int_to_fixed(data->chunk_request_delay));
1517         data->display_writes_time_for_data_transfer = bw_sub(data->min_mcifwr_size_in_time, vbios->mcifwrmc_urgent_latency);
1518         data->dmif_required_dram_bandwidth = bw_div(data->total_display_reads_required_dram_access_data, data->display_reads_time_for_data_transfer);
1519         data->mcifwr_required_dram_bandwidth = bw_div(data->total_display_writes_required_dram_access_data, data->display_writes_time_for_data_transfer);
1520         data->required_dmifmc_urgent_latency_for_page_close_open = bw_div((bw_sub(data->min_read_buffer_size_in_time, data->dmif_total_page_close_open_time)), data->total_dmifmc_urgent_trips);
1521         data->required_mcifmcwr_urgent_latency = bw_sub(data->min_mcifwr_size_in_time, data->mcifwr_total_page_close_open_time);
1522         if (bw_mtn(data->scatter_gather_total_pte_requests, dceip->maximum_total_outstanding_pte_requests_allowed_by_saw)) {
1523                 data->required_dram_bandwidth_gbyte_per_second = bw_int_to_fixed(9999);
1524                 yclk_message = bw_def_exceeded_allowed_outstanding_pte_req_queue_size;
1525                 data->y_clk_level = high;
1526                 data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1527         }
1528         else if (bw_mtn(vbios->dmifmc_urgent_latency, data->required_dmifmc_urgent_latency_for_page_close_open) || bw_mtn(vbios->mcifwrmc_urgent_latency, data->required_mcifmcwr_urgent_latency)) {
1529                 data->required_dram_bandwidth_gbyte_per_second = bw_int_to_fixed(9999);
1530                 yclk_message = bw_def_exceeded_allowed_page_close_open;
1531                 data->y_clk_level = high;
1532                 data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1533         }
1534         else {
1535                 data->required_dram_bandwidth_gbyte_per_second = bw_div(bw_max2(data->dmif_required_dram_bandwidth, data->mcifwr_required_dram_bandwidth), bw_int_to_fixed(1000));
1536                 if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation, 100),yclk[low]),bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits),bw_int_to_fixed(8))),bw_int_to_fixed(vbios->number_of_dram_channels)))
1537                                 && bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[low]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels))) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[low][s_high], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[low][s_high], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[low][s_high], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[low][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[low][s_high], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[low][s_high], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[low][s_high] == number_of_displays_enabled_with_margin))) {
1538                         yclk_message = bw_fixed_to_int(vbios->low_yclk);
1539                         data->y_clk_level = low;
1540                         data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[low]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1541                 }
1542                 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation, 100),yclk[mid]),bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits),bw_int_to_fixed(8))),bw_int_to_fixed(vbios->number_of_dram_channels)))
1543                                 && bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[mid]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels))) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[mid][s_high], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[mid][s_high], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[mid][s_high], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[mid][s_high], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[mid][s_high], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[mid][s_high], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[mid][s_high] == number_of_displays_enabled_with_margin))) {
1544                         yclk_message = bw_fixed_to_int(vbios->mid_yclk);
1545                         data->y_clk_level = mid;
1546                         data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[mid]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1547                 }
1548                 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation, 100),yclk[high]),bw_div(bw_int_to_fixed(vbios->dram_channel_width_in_bits),bw_int_to_fixed(8))),bw_int_to_fixed(vbios->number_of_dram_channels)))
1549                                 && bw_ltn(bw_mul(data->required_dram_bandwidth_gbyte_per_second, bw_int_to_fixed(1000)), bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels)))) {
1550                         yclk_message = bw_fixed_to_int(vbios->high_yclk);
1551                         data->y_clk_level = high;
1552                         data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1553                 }
1554                 else {
1555                         yclk_message = bw_def_exceeded_allowed_maximum_bw;
1556                         data->y_clk_level = high;
1557                         data->dram_bandwidth = bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[high]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels));
1558                 }
1559         }
1560         /*required sclk*/
1561         /*sclk requirement only makes sense if the total pte requests fit in the scatter-gather saw queque size*/
1562         /*if that is the case, the sclk requirement is the maximum of the ones required by dmif and mcifwr, and the high/mid/low sclk is chosen accordingly, unless that choice results in foresaking dram speed/nb p-state change.*/
1563         /*the dmif and mcifwr sclk required is the one that allows the transfer of all pipe's data buffer size through the sclk bus in the time for data transfer*/
1564         /*for dmif, pte and cursor requests have to be included.*/
1565         data->dmif_required_sclk = bw_div(bw_div(data->total_display_reads_required_data, data->display_reads_time_for_data_transfer), (bw_mul(vbios->data_return_bus_width, bw_frc_to_fixed(dceip->percent_of_ideal_port_bw_received_after_urgent_latency, 100))));
1566         data->mcifwr_required_sclk = bw_div(bw_div(data->total_display_writes_required_data, data->display_writes_time_for_data_transfer), vbios->data_return_bus_width);
1567         if (bw_mtn(data->scatter_gather_total_pte_requests, dceip->maximum_total_outstanding_pte_requests_allowed_by_saw)) {
1568                 data->required_sclk = bw_int_to_fixed(9999);
1569                 sclk_message = bw_def_exceeded_allowed_outstanding_pte_req_queue_size;
1570                 data->sclk_level = s_high;
1571         }
1572         else if (bw_mtn(vbios->dmifmc_urgent_latency, data->required_dmifmc_urgent_latency_for_page_close_open) || bw_mtn(vbios->mcifwrmc_urgent_latency, data->required_mcifmcwr_urgent_latency)) {
1573                 data->required_sclk = bw_int_to_fixed(9999);
1574                 sclk_message = bw_def_exceeded_allowed_page_close_open;
1575                 data->sclk_level = s_high;
1576         }
1577         else {
1578                 data->required_sclk = bw_max2(data->dmif_required_sclk, data->mcifwr_required_sclk);
1579                 if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[low]),vbios->data_return_bus_width))
1580                                 && bw_ltn(data->required_sclk, sclk[s_low]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_low], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_low], vbios->low_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_low] == number_of_displays_enabled_with_margin))) {
1581                         sclk_message = bw_def_low;
1582                         data->sclk_level = s_low;
1583                         data->required_sclk = vbios->low_sclk;
1584                 }
1585                 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[mid]),vbios->data_return_bus_width))
1586                                 && bw_ltn(data->required_sclk, sclk[s_mid1]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid1], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid1] == number_of_displays_enabled_with_margin))) {
1587                         sclk_message = bw_def_mid;
1588                         data->sclk_level = s_mid1;
1589                         data->required_sclk = vbios->mid1_sclk;
1590                 }
1591                 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid2]),vbios->data_return_bus_width))
1592                                 && bw_ltn(data->required_sclk, sclk[s_mid2]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid2], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid2] == number_of_displays_enabled_with_margin))) {
1593                         sclk_message = bw_def_mid;
1594                         data->sclk_level = s_mid2;
1595                         data->required_sclk = vbios->mid2_sclk;
1596                 }
1597                 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid3]),vbios->data_return_bus_width))
1598                                 && bw_ltn(data->required_sclk, sclk[s_mid3]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid3], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid3] == number_of_displays_enabled_with_margin))) {
1599                         sclk_message = bw_def_mid;
1600                         data->sclk_level = s_mid3;
1601                         data->required_sclk = vbios->mid3_sclk;
1602                 }
1603                 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid4]),vbios->data_return_bus_width))
1604                                 && bw_ltn(data->required_sclk, sclk[s_mid4]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid4], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid4] == number_of_displays_enabled_with_margin))) {
1605                         sclk_message = bw_def_mid;
1606                         data->sclk_level = s_mid4;
1607                         data->required_sclk = vbios->mid4_sclk;
1608                 }
1609                 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid5]),vbios->data_return_bus_width))
1610                                 && bw_ltn(data->required_sclk, sclk[s_mid5]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid5], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid5] == number_of_displays_enabled_with_margin))) {
1611                         sclk_message = bw_def_mid;
1612                         data->sclk_level = s_mid5;
1613                         data->required_sclk = vbios->mid5_sclk;
1614                 }
1615                 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid6]),vbios->data_return_bus_width))
1616                                 && bw_ltn(data->required_sclk, sclk[s_mid6]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid6] == number_of_displays_enabled_with_margin))) {
1617                         sclk_message = bw_def_mid;
1618                         data->sclk_level = s_mid6;
1619                         data->required_sclk = vbios->mid6_sclk;
1620                 }
1621                 else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_high]),vbios->data_return_bus_width))
1622                                 && bw_ltn(data->required_sclk, sclk[s_high])) {
1623                         sclk_message = bw_def_high;
1624                         data->sclk_level = s_high;
1625                         data->required_sclk = vbios->high_sclk;
1626                 }
1627                 else if (bw_meq(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_high]),vbios->data_return_bus_width))
1628                                 && bw_ltn(data->required_sclk, sclk[s_high])) {
1629                         sclk_message = bw_def_high;
1630                         data->sclk_level = s_high;
1631                         data->required_sclk = vbios->high_sclk;
1632                 }
1633                 else {
1634                         sclk_message = bw_def_exceeded_allowed_maximum_sclk;
1635                         data->sclk_level = s_high;
1636                         /*required_sclk = high_sclk*/
1637                 }
1638         }
1639         /*dispclk*/
1640         /*if dispclk is set to the maximum, ramping is not required.  dispclk required without ramping is less than the dispclk required with ramping.*/
1641         /*if dispclk required without ramping is more than the maximum dispclk, that is the dispclk required, and the mode is not supported*/
1642         /*if that does not happen, but dispclk required with ramping is more than the maximum dispclk, dispclk required is just the maximum dispclk*/
1643         /*if that does not happen either, dispclk required is the dispclk required with ramping.*/
1644         /*dispclk required without ramping is the maximum of the one required for display pipe pixel throughput, for scaler throughput, for total read request thrrougput and for dram/np p-state change if enabled.*/
1645         /*the display pipe pixel throughput is the maximum of lines in per line out in the beginning of the frame and lines in per line out in the middle of the frame multiplied by the horizontal blank and chunk granularity factor, altogether multiplied by the ratio of the source width to the line time, divided by the line buffer pixels per dispclk throughput, and multiplied by the display pipe throughput factor.*/
1646         /*the horizontal blank and chunk granularity factor is the ratio of the line time divided by the line time minus half the horizontal blank and chunk time.  it applies when the lines in per line out is not 2 or 4.*/
1647         /*the dispclk required for scaler throughput is the product of the pixel rate and the scaling limits factor.*/
1648         /*the dispclk required for total read request throughput is the product of the peak request-per-second bandwidth and the dispclk cycles per request, divided by the request efficiency.*/
1649         /*for the dispclk required with ramping, instead of multiplying just the pipe throughput by the display pipe throughput factor, we multiply the scaler and pipe throughput by the ramping factor.*/
1650         /*the scaling limits factor is the product of the horizontal scale ratio, and the ratio of the vertical taps divided by the scaler efficiency clamped to at least 1.*/
1651         /*the scaling limits factor itself it also clamped to at least 1*/
1652         /*if doing downscaling with the pre-downscaler enabled, the horizontal scale ratio should not be considered above (use "1")*/
1653         data->downspread_factor = bw_add(bw_int_to_fixed(1), bw_div(vbios->down_spread_percentage, bw_int_to_fixed(100)));
1654         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1655                 if (data->enable[i]) {
1656                         if (surface_type[i] == bw_def_graphics) {
1657                                 switch (data->lb_bpc[i]) {
1658                                 case 6:
1659                                         data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency6_bit_per_component;
1660                                         break;
1661                                 case 8:
1662                                         data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency8_bit_per_component;
1663                                         break;
1664                                 case 10:
1665                                         data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency10_bit_per_component;
1666                                         break;
1667                                 default:
1668                                         data->v_scaler_efficiency = dceip->graphics_vscaler_efficiency12_bit_per_component;
1669                                         break;
1670                                 }
1671                                 if (data->use_alpha[i] == 1) {
1672                                         data->v_scaler_efficiency = bw_min2(data->v_scaler_efficiency, dceip->alpha_vscaler_efficiency);
1673                                 }
1674                         }
1675                         else {
1676                                 switch (data->lb_bpc[i]) {
1677                                 case 6:
1678                                         data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency6_bit_per_component;
1679                                         break;
1680                                 case 8:
1681                                         data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency8_bit_per_component;
1682                                         break;
1683                                 case 10:
1684                                         data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency10_bit_per_component;
1685                                         break;
1686                                 default:
1687                                         data->v_scaler_efficiency = dceip->underlay_vscaler_efficiency12_bit_per_component;
1688                                         break;
1689                                 }
1690                         }
1691                         if (dceip->pre_downscaler_enabled && bw_mtn(data->hsr[i], bw_int_to_fixed(1))) {
1692                                 data->scaler_limits_factor = bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_div(data->source_width_rounded_up_to_chunks[i], data->h_total[i]));
1693                         }
1694                         else {
1695                                 data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1))));
1696                         }
1697                         data->display_pipe_pixel_throughput = bw_div(bw_div(bw_mul(bw_max2(data->lb_lines_in_per_line_out_in_beginning_of_frame[i], bw_mul(data->lb_lines_in_per_line_out_in_middle_of_frame[i], data->horizontal_blank_and_chunk_granularity_factor[i])), data->source_width_rounded_up_to_chunks[i]), (bw_div(data->h_total[i], data->pixel_rate[i]))), dceip->lb_write_pixels_per_dispclk);
1698                         data->dispclk_required_without_ramping[i] = bw_mul(data->downspread_factor, bw_max2(bw_mul(data->pixel_rate[i], data->scaler_limits_factor), bw_mul(dceip->display_pipe_throughput_factor, data->display_pipe_pixel_throughput)));
1699                         data->dispclk_required_with_ramping[i] = bw_mul(dceip->dispclk_ramping_factor, bw_max2(bw_mul(data->pixel_rate[i], data->scaler_limits_factor), data->display_pipe_pixel_throughput));
1700                 }
1701         }
1702         data->total_dispclk_required_with_ramping = bw_int_to_fixed(0);
1703         data->total_dispclk_required_without_ramping = bw_int_to_fixed(0);
1704         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1705                 if (data->enable[i]) {
1706                         if (bw_ltn(data->total_dispclk_required_with_ramping, data->dispclk_required_with_ramping[i])) {
1707                                 data->total_dispclk_required_with_ramping = data->dispclk_required_with_ramping[i];
1708                         }
1709                         if (bw_ltn(data->total_dispclk_required_without_ramping, data->dispclk_required_without_ramping[i])) {
1710                                 data->total_dispclk_required_without_ramping = data->dispclk_required_without_ramping[i];
1711                         }
1712                 }
1713         }
1714         data->total_read_request_bandwidth = bw_int_to_fixed(0);
1715         data->total_write_request_bandwidth = bw_int_to_fixed(0);
1716         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1717                 if (data->enable[i]) {
1718                         if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1719                                 data->total_read_request_bandwidth = bw_add(data->total_read_request_bandwidth, data->request_bandwidth[i]);
1720                         }
1721                         else {
1722                                 data->total_write_request_bandwidth = bw_add(data->total_write_request_bandwidth, data->request_bandwidth[i]);
1723                         }
1724                 }
1725         }
1726         data->dispclk_required_for_total_read_request_bandwidth = bw_div(bw_mul(data->total_read_request_bandwidth, dceip->dispclk_per_request), dceip->request_efficiency);
1727         data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_with_ramping, data->dispclk_required_for_total_read_request_bandwidth);
1728         data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_without_ramping, data->dispclk_required_for_total_read_request_bandwidth);
1729         if (data->cpuc_state_change_enable == bw_def_yes) {
1730                 data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max3(data->total_dispclk_required_with_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level], data->dispclk_required_for_blackout_recovery[data->y_clk_level][data->sclk_level]);
1731                 data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max3(data->total_dispclk_required_without_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level], data->dispclk_required_for_blackout_recovery[data->y_clk_level][data->sclk_level]);
1732         }
1733         if (data->cpup_state_change_enable == bw_def_yes) {
1734                 data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_with_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level]);
1735                 data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_without_ramping_with_request_bandwidth, data->dispclk_required_for_blackout_duration[data->y_clk_level][data->sclk_level]);
1736         }
1737         if (data->nbp_state_change_enable == bw_def_yes && data->increase_voltage_to_support_mclk_switch) {
1738                 data->total_dispclk_required_with_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_with_ramping_with_request_bandwidth, data->dispclk_required_for_dram_speed_change[data->y_clk_level][data->sclk_level]);
1739                 data->total_dispclk_required_without_ramping_with_request_bandwidth = bw_max2(data->total_dispclk_required_without_ramping_with_request_bandwidth, data->dispclk_required_for_dram_speed_change[data->y_clk_level][data->sclk_level]);
1740         }
1741         if (bw_ltn(data->total_dispclk_required_with_ramping_with_request_bandwidth, vbios->high_voltage_max_dispclk)) {
1742                 data->dispclk = data->total_dispclk_required_with_ramping_with_request_bandwidth;
1743         }
1744         else if (bw_ltn(data->total_dispclk_required_without_ramping_with_request_bandwidth, vbios->high_voltage_max_dispclk)) {
1745                 data->dispclk = vbios->high_voltage_max_dispclk;
1746         }
1747         else {
1748                 data->dispclk = data->total_dispclk_required_without_ramping_with_request_bandwidth;
1749         }
1750         /* required core voltage*/
1751         /* the core voltage required is low if sclk, yclk(pclk)and dispclk are within the low limits*/
1752         /* otherwise, the core voltage required is medium if yclk (pclk) is within the low limit and sclk and dispclk are within the medium limit*/
1753         /* otherwise, the core voltage required is high if the three clocks are within the high limits*/
1754         /* otherwise, or if the mode is not supported, core voltage requirement is not applicable*/
1755         if (pipe_check == bw_def_notok) {
1756                 voltage = bw_def_na;
1757         }
1758         else if (mode_check == bw_def_notok) {
1759                 voltage = bw_def_notok;
1760         }
1761         else if (bw_equ(bw_int_to_fixed(yclk_message), vbios->low_yclk) && sclk_message == bw_def_low && bw_ltn(data->dispclk, vbios->low_voltage_max_dispclk)) {
1762                 voltage = bw_def_0_72;
1763         }
1764         else if ((bw_equ(bw_int_to_fixed(yclk_message), vbios->low_yclk) || bw_equ(bw_int_to_fixed(yclk_message), vbios->mid_yclk)) && (sclk_message == bw_def_low || sclk_message == bw_def_mid) && bw_ltn(data->dispclk, vbios->mid_voltage_max_dispclk)) {
1765                 voltage = bw_def_0_8;
1766         }
1767         else if ((bw_equ(bw_int_to_fixed(yclk_message), vbios->low_yclk) || bw_equ(bw_int_to_fixed(yclk_message), vbios->mid_yclk) || bw_equ(bw_int_to_fixed(yclk_message), vbios->high_yclk)) && (sclk_message == bw_def_low || sclk_message == bw_def_mid || sclk_message == bw_def_high) && bw_leq(data->dispclk, vbios->high_voltage_max_dispclk)) {
1768                 if ((data->nbp_state_change_enable == bw_def_no && nbp_state_change_enable_blank == bw_def_no)) {
1769                         voltage = bw_def_high_no_nbp_state_change;
1770                 }
1771                 else {
1772                         voltage = bw_def_0_9;
1773                 }
1774         }
1775         else {
1776                 voltage = bw_def_notok;
1777         }
1778         if (voltage == bw_def_0_72) {
1779                 data->max_phyclk = vbios->low_voltage_max_phyclk;
1780         }
1781         else if (voltage == bw_def_0_8) {
1782                 data->max_phyclk = vbios->mid_voltage_max_phyclk;
1783         }
1784         else {
1785                 data->max_phyclk = vbios->high_voltage_max_phyclk;
1786         }
1787         /*required blackout recovery time*/
1788         data->blackout_recovery_time = bw_int_to_fixed(0);
1789         for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
1790                 if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0)) && data->cpup_state_change_enable == bw_def_yes) {
1791                         if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) {
1792                                 data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level]));
1793                                 if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])))))) {
1794                                         data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k])))));
1795                                 }
1796                         }
1797                         else {
1798                                 data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level]));
1799                                 if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])))))) {
1800                                         data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level]), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k])))));
1801                                 }
1802                         }
1803                 }
1804         }
1805         /*sclk deep sleep*/
1806         /*during self-refresh, sclk can be reduced to dispclk divided by the minimum pixels in the data fifo entry, with 15% margin, but shoudl not be set to less than the request bandwidth.*/
1807         /*the data fifo entry is 16 pixels for the writeback, 64 bytes/bytes_per_pixel for the graphics, 16 pixels for the parallel rotation underlay,*/
1808         /*and 16 bytes/bytes_per_pixel for the orthogonal rotation underlay.*/
1809         /*in parallel mode (underlay pipe), the data read from the dmifv buffer is variable and based on the pixel depth (8bbp - 16 bytes, 16 bpp - 32 bytes, 32 bpp - 64 bytes)*/
1810         /*in orthogonal mode (underlay pipe), the data read from the dmifv buffer is fixed at 16 bytes.*/
1811         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1812                 if (data->enable[i]) {
1813                         if (surface_type[i] == bw_def_display_write_back420_luma || surface_type[i] == bw_def_display_write_back420_chroma) {
1814                                 data->pixels_per_data_fifo_entry[i] = bw_int_to_fixed(16);
1815                         }
1816                         else if (surface_type[i] == bw_def_graphics) {
1817                                 data->pixels_per_data_fifo_entry[i] = bw_div(bw_int_to_fixed(64), bw_int_to_fixed(data->bytes_per_pixel[i]));
1818                         }
1819                         else if (data->orthogonal_rotation[i] == 0) {
1820                                 data->pixels_per_data_fifo_entry[i] = bw_int_to_fixed(16);
1821                         }
1822                         else {
1823                                 data->pixels_per_data_fifo_entry[i] = bw_div(bw_int_to_fixed(16), bw_int_to_fixed(data->bytes_per_pixel[i]));
1824                         }
1825                 }
1826         }
1827         data->min_pixels_per_data_fifo_entry = bw_int_to_fixed(9999);
1828         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1829                 if (data->enable[i]) {
1830                         if (bw_mtn(data->min_pixels_per_data_fifo_entry, data->pixels_per_data_fifo_entry[i])) {
1831                                 data->min_pixels_per_data_fifo_entry = data->pixels_per_data_fifo_entry[i];
1832                         }
1833                 }
1834         }
1835         data->sclk_deep_sleep = bw_max2(bw_div(bw_mul(data->dispclk, bw_frc_to_fixed(115, 100)), data->min_pixels_per_data_fifo_entry), data->total_read_request_bandwidth);
1836         /*urgent, stutter and nb-p_state watermark*/
1837         /*the urgent watermark is the maximum of the urgent trip time plus the pixel transfer time, the urgent trip times to get data for the first pixel, and the urgent trip times to get data for the last pixel.*/
1838         /*the stutter exit watermark is the self refresh exit time plus the maximum of the data burst time plus the pixel transfer time, the data burst times to get data for the first pixel, and the data burst times to get data for the last pixel.  it does not apply to the writeback.*/
1839         /*the nb p-state change watermark is the dram speed/p-state change time plus the maximum of the data burst time plus the pixel transfer time, the data burst times to get data for the first pixel, and the data burst times to get data for the last pixel.*/
1840         /*the pixel transfer time is the maximum of the time to transfer the source pixels required for the first output pixel, and the time to transfer the pixels for the last output pixel minus the active line time.*/
1841         /*blackout_duration is added to the urgent watermark*/
1842         data->chunk_request_time = bw_int_to_fixed(0);
1843         data->cursor_request_time = bw_int_to_fixed(0);
1844         /*compute total time to request one chunk from each active display pipe*/
1845         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1846                 if (data->enable[i]) {
1847                         data->chunk_request_time = bw_add(data->chunk_request_time, (bw_div((bw_div(bw_int_to_fixed(pixels_per_chunk * data->bytes_per_pixel[i]), data->useful_bytes_per_request[i])), bw_min2(sclk[data->sclk_level], bw_div(data->dispclk, bw_int_to_fixed(2))))));
1848                 }
1849         }
1850         /*compute total time to request cursor data*/
1851         data->cursor_request_time = (bw_div(data->cursor_total_data, (bw_mul(bw_int_to_fixed(32), sclk[data->sclk_level]))));
1852         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1853                 if (data->enable[i]) {
1854                         data->line_source_pixels_transfer_time = bw_max2(bw_div(bw_div(data->src_pixels_for_first_output_pixel[i], dceip->lb_write_pixels_per_dispclk), (bw_div(data->dispclk, dceip->display_pipe_throughput_factor))), bw_sub(bw_div(bw_div(data->src_pixels_for_last_output_pixel[i], dceip->lb_write_pixels_per_dispclk), (bw_div(data->dispclk, dceip->display_pipe_throughput_factor))), data->active_time[i]));
1855                         if (surface_type[i] != bw_def_display_write_back420_luma && surface_type[i] != bw_def_display_write_back420_chroma) {
1856                                 data->urgent_watermark[i] = bw_add(bw_add(bw_add(bw_add(bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->line_source_transfer_time[i][data->y_clk_level][data->sclk_level])), vbios->blackout_duration), data->chunk_request_time), data->cursor_request_time);
1857                                 data->stutter_exit_watermark[i] = bw_add(bw_sub(vbios->stutter_self_refresh_exit_latency, data->total_dmifmc_urgent_latency), data->urgent_watermark[i]);
1858                                 data->stutter_entry_watermark[i] = bw_add(bw_sub(bw_add(vbios->stutter_self_refresh_exit_latency, vbios->stutter_self_refresh_entry_latency), data->total_dmifmc_urgent_latency), data->urgent_watermark[i]);
1859                                 /*unconditionally remove black out time from the nb p_state watermark*/
1860                                 if (data->display_pstate_change_enable[i] == 1) {
1861                                         data->nbp_state_change_watermark[i] = bw_add(bw_add(vbios->nbp_state_change_latency, data->dmif_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->dram_speed_change_line_source_transfer_time[i][data->y_clk_level][data->sclk_level]));
1862                                 }
1863                                 else {
1864                                         /*maximize the watermark to force the switch in the vb_lank region of the frame*/
1865                                         data->nbp_state_change_watermark[i] = bw_int_to_fixed(131000);
1866                                 }
1867                         }
1868                         else {
1869                                 data->urgent_watermark[i] = bw_add(bw_add(bw_add(bw_add(bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->line_source_transfer_time[i][data->y_clk_level][data->sclk_level])), vbios->blackout_duration), data->chunk_request_time), data->cursor_request_time);
1870                                 data->stutter_exit_watermark[i] = bw_int_to_fixed(0);
1871                                 data->stutter_entry_watermark[i] = bw_int_to_fixed(0);
1872                                 if (data->display_pstate_change_enable[i] == 1) {
1873                                         data->nbp_state_change_watermark[i] = bw_add(bw_add(vbios->nbp_state_change_latency, data->mcifwr_burst_time[data->y_clk_level][data->sclk_level]), bw_max2(data->line_source_pixels_transfer_time, data->dram_speed_change_line_source_transfer_time[i][data->y_clk_level][data->sclk_level]));
1874                                 }
1875                                 else {
1876                                         /*maximize the watermark to force the switch in the vb_lank region of the frame*/
1877                                         data->nbp_state_change_watermark[i] = bw_int_to_fixed(131000);
1878                                 }
1879                         }
1880                 }
1881         }
1882         /*stutter mode enable*/
1883         /*in the multi-display case the stutter exit or entry watermark cannot exceed the minimum latency hiding capabilities of the*/
1884         /*display pipe.*/
1885         data->stutter_mode_enable = data->cpuc_state_change_enable;
1886         if (data->number_of_displays > 1) {
1887                 for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1888                         if (data->enable[i]) {
1889                                 if ((bw_mtn(data->stutter_exit_watermark[i], data->minimum_latency_hiding[i]) || bw_mtn(data->stutter_entry_watermark[i], data->minimum_latency_hiding[i]))) {
1890                                         data->stutter_mode_enable = bw_def_no;
1891                                 }
1892                         }
1893                 }
1894         }
1895         /*performance metrics*/
1896         /* display read access efficiency (%)*/
1897         /* display write back access efficiency (%)*/
1898         /* stutter efficiency (%)*/
1899         /* extra underlay pitch recommended for efficiency (pixels)*/
1900         /* immediate flip time (us)*/
1901         /* latency for other clients due to urgent display read (us)*/
1902         /* latency for other clients due to urgent display write (us)*/
1903         /* average bandwidth consumed by display (no compression) (gb/s)*/
1904         /* required dram  bandwidth (gb/s)*/
1905         /* required sclk (m_hz)*/
1906         /* required rd urgent latency (us)*/
1907         /* nb p-state change margin (us)*/
1908         /*dmif and mcifwr dram access efficiency*/
1909         /*is the ratio between the ideal dram access time (which is the data buffer size in memory divided by the dram bandwidth), and the actual time which is the total page close-open time.  but it cannot exceed the dram efficiency provided by the memory subsystem*/
1910         data->dmifdram_access_efficiency = bw_min2(bw_div(bw_div(data->total_display_reads_required_dram_access_data, data->dram_bandwidth), data->dmif_total_page_close_open_time), bw_int_to_fixed(1));
1911         if (bw_mtn(data->total_display_writes_required_dram_access_data, bw_int_to_fixed(0))) {
1912                 data->mcifwrdram_access_efficiency = bw_min2(bw_div(bw_div(data->total_display_writes_required_dram_access_data, data->dram_bandwidth), data->mcifwr_total_page_close_open_time), bw_int_to_fixed(1));
1913         }
1914         else {
1915                 data->mcifwrdram_access_efficiency = bw_int_to_fixed(0);
1916         }
1917         /*stutter efficiency*/
1918         /*the stutter efficiency is the frame-average time in self-refresh divided by the frame-average stutter cycle duration.  only applies if the display write-back is not enabled.*/
1919         /*the frame-average stutter cycle used is the minimum for all pipes of the frame-average data buffer size in time, times the compression rate*/
1920         /*the frame-average time in self-refresh is the stutter cycle minus the self refresh exit latency and the burst time*/
1921         /*the stutter cycle is the dmif buffer size reduced by the excess of the stutter exit watermark over the lb size in time.*/
1922         /*the burst time is the data needed during the stutter cycle divided by the available bandwidth*/
1923         /*compute the time read all the data from the dmif buffer to the lb (dram refresh period)*/
1924         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1925                 if (data->enable[i]) {
1926                         data->stutter_refresh_duration[i] = bw_sub(bw_mul(bw_div(bw_div(bw_mul(bw_div(bw_div(data->adjusted_data_buffer_size[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_rounded_up_to_chunks[i]), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]), data->compression_rate[i]), bw_max2(bw_int_to_fixed(0), bw_sub(data->stutter_exit_watermark[i], bw_div(bw_mul((bw_sub(data->lb_partitions[i], bw_int_to_fixed(1))), data->h_total[i]), data->pixel_rate[i]))));
1927                         data->stutter_dmif_buffer_size[i] = bw_div(bw_mul(bw_mul(bw_div(bw_mul(bw_mul(data->stutter_refresh_duration[i], bw_int_to_fixed(data->bytes_per_pixel[i])), data->source_width_rounded_up_to_chunks[i]), data->h_total[i]), data->vsr[i]), data->pixel_rate[i]), data->compression_rate[i]);
1928                 }
1929         }
1930         data->min_stutter_refresh_duration = bw_int_to_fixed(9999);
1931         data->total_stutter_dmif_buffer_size = 0;
1932         data->total_bytes_requested = 0;
1933         data->min_stutter_dmif_buffer_size = 9999;
1934         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1935                 if (data->enable[i]) {
1936                         if (bw_mtn(data->min_stutter_refresh_duration, data->stutter_refresh_duration[i])) {
1937                                 data->min_stutter_refresh_duration = data->stutter_refresh_duration[i];
1938                                 data->total_bytes_requested = bw_fixed_to_int(bw_add(bw_int_to_fixed(data->total_bytes_requested), (bw_mul(bw_mul(data->source_height_rounded_up_to_chunks[i], data->source_width_rounded_up_to_chunks[i]), bw_int_to_fixed(data->bytes_per_pixel[i])))));
1939                                 data->min_stutter_dmif_buffer_size = bw_fixed_to_int(data->stutter_dmif_buffer_size[i]);
1940                         }
1941                         data->total_stutter_dmif_buffer_size = bw_fixed_to_int(bw_add(data->stutter_dmif_buffer_size[i], bw_int_to_fixed(data->total_stutter_dmif_buffer_size)));
1942                 }
1943         }
1944         data->stutter_burst_time = bw_div(bw_int_to_fixed(data->total_stutter_dmif_buffer_size), bw_mul(sclk[data->sclk_level], vbios->data_return_bus_width));
1945         data->num_stutter_bursts = data->total_bytes_requested / data->min_stutter_dmif_buffer_size;
1946         data->total_stutter_cycle_duration = bw_add(bw_add(data->min_stutter_refresh_duration, vbios->stutter_self_refresh_exit_latency), data->stutter_burst_time);
1947         data->time_in_self_refresh = data->min_stutter_refresh_duration;
1948         if (data->d1_display_write_back_dwb_enable == 1) {
1949                 data->stutter_efficiency = bw_int_to_fixed(0);
1950         }
1951         else if (bw_ltn(data->time_in_self_refresh, bw_int_to_fixed(0))) {
1952                 data->stutter_efficiency = bw_int_to_fixed(0);
1953         }
1954         else {
1955                 /*compute stutter efficiency assuming 60 hz refresh rate*/
1956                 data->stutter_efficiency = bw_max2(bw_int_to_fixed(0), bw_mul((bw_sub(bw_int_to_fixed(1), (bw_div(bw_mul((bw_add(vbios->stutter_self_refresh_exit_latency, data->stutter_burst_time)), bw_int_to_fixed(data->num_stutter_bursts)), bw_frc_to_fixed(166666667, 10000))))), bw_int_to_fixed(100)));
1957         }
1958         /*immediate flip time*/
1959         /*if scatter gather is enabled, the immediate flip takes a number of urgent memory trips equivalent to the pte requests in a row divided by the pte request limit.*/
1960         /*otherwise, it may take just one urgenr memory trip*/
1961         data->worst_number_of_trips_to_memory = bw_int_to_fixed(1);
1962         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1963                 if (data->enable[i] && data->scatter_gather_enable_for_pipe[i] == 1) {
1964                         data->number_of_trips_to_memory_for_getting_apte_row[i] = bw_ceil2(bw_div(data->scatter_gather_pte_requests_in_row[i], data->scatter_gather_pte_request_limit[i]), bw_int_to_fixed(1));
1965                         if (bw_ltn(data->worst_number_of_trips_to_memory, data->number_of_trips_to_memory_for_getting_apte_row[i])) {
1966                                 data->worst_number_of_trips_to_memory = data->number_of_trips_to_memory_for_getting_apte_row[i];
1967                         }
1968                 }
1969         }
1970         data->immediate_flip_time = bw_mul(data->worst_number_of_trips_to_memory, data->total_dmifmc_urgent_latency);
1971         /*worst latency for other clients*/
1972         /*it is the urgent latency plus the urgent burst time*/
1973         data->latency_for_non_dmif_clients = bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[data->y_clk_level][data->sclk_level]);
1974         if (data->d1_display_write_back_dwb_enable == 1) {
1975                 data->latency_for_non_mcifwr_clients = bw_add(vbios->mcifwrmc_urgent_latency, dceip->mcifwr_all_surfaces_burst_time);
1976         }
1977         else {
1978                 data->latency_for_non_mcifwr_clients = bw_int_to_fixed(0);
1979         }
1980         /*dmif mc urgent latency suppported in high sclk and yclk*/
1981         data->dmifmc_urgent_latency_supported_in_high_sclk_and_yclk = bw_div((bw_sub(data->min_read_buffer_size_in_time, data->dmif_burst_time[high][s_high])), data->total_dmifmc_urgent_trips);
1982         /*dram speed/p-state change margin*/
1983         /*in the multi-display case the nb p-state change watermark cannot exceed the average lb size plus the dmif size or the cursor dcp buffer size*/
1984         data->v_blank_nbp_state_dram_speed_change_latency_supported = bw_int_to_fixed(99999);
1985         data->nbp_state_dram_speed_change_latency_supported = bw_int_to_fixed(99999);
1986         for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
1987                 if (data->enable[i]) {
1988                         data->nbp_state_dram_speed_change_latency_supported = bw_min2(data->nbp_state_dram_speed_change_latency_supported, bw_add(bw_sub(data->maximum_latency_hiding_with_cursor[i], data->nbp_state_change_watermark[i]), vbios->nbp_state_change_latency));
1989                         data->v_blank_nbp_state_dram_speed_change_latency_supported = bw_min2(data->v_blank_nbp_state_dram_speed_change_latency_supported, bw_add(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[i], bw_sub(bw_div(data->src_height[i], data->v_scale_ratio[i]), bw_int_to_fixed(4)))), data->h_total[i]), data->pixel_rate[i]), data->nbp_state_change_watermark[i]), vbios->nbp_state_change_latency));
1990                 }
1991         }
1992         /*sclk required vs urgent latency*/
1993         for (i = 1; i <= 5; i++) {
1994                 data->display_reads_time_for_data_transfer_and_urgent_latency = bw_sub(data->min_read_buffer_size_in_time, bw_mul(data->total_dmifmc_urgent_trips, bw_int_to_fixed(i)));
1995                 if (pipe_check == bw_def_ok && (bw_mtn(data->display_reads_time_for_data_transfer_and_urgent_latency, data->dmif_total_page_close_open_time))) {
1996                         data->dmif_required_sclk_for_urgent_latency[i] = bw_div(bw_div(data->total_display_reads_required_data, data->display_reads_time_for_data_transfer_and_urgent_latency), (bw_mul(vbios->data_return_bus_width, bw_frc_to_fixed(dceip->percent_of_ideal_port_bw_received_after_urgent_latency, 100))));
1997                 }
1998                 else {
1999                         data->dmif_required_sclk_for_urgent_latency[i] = bw_int_to_fixed(bw_def_na);
2000                 }
2001         }
2002         /*output link bit per pixel supported*/
2003         for (k = 0; k <= maximum_number_of_surfaces - 1; k++) {
2004                 data->output_bpphdmi[k] = bw_def_na;
2005                 data->output_bppdp4_lane_hbr[k] = bw_def_na;
2006                 data->output_bppdp4_lane_hbr2[k] = bw_def_na;
2007                 data->output_bppdp4_lane_hbr3[k] = bw_def_na;
2008                 if (data->enable[k]) {
2009                         data->output_bpphdmi[k] = bw_fixed_to_int(bw_mul(bw_div(bw_min2(bw_int_to_fixed(600), data->max_phyclk), data->pixel_rate[k]), bw_int_to_fixed(24)));
2010                         if (bw_meq(data->max_phyclk, bw_int_to_fixed(270))) {
2011                                 data->output_bppdp4_lane_hbr[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(270), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
2012                         }
2013                         if (bw_meq(data->max_phyclk, bw_int_to_fixed(540))) {
2014                                 data->output_bppdp4_lane_hbr2[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(540), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
2015                         }
2016                         if (bw_meq(data->max_phyclk, bw_int_to_fixed(810))) {
2017                                 data->output_bppdp4_lane_hbr3[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(810), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8)));
2018                         }
2019                 }
2020         }
2021 }
2022
2023 /*******************************************************************************
2024  * Public functions
2025  ******************************************************************************/
2026 void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
2027         struct bw_calcs_vbios *bw_vbios,
2028         struct hw_asic_id asic_id)
2029 {
2030         struct bw_calcs_dceip dceip = { 0 };
2031         struct bw_calcs_vbios vbios = { 0 };
2032
2033         enum bw_calcs_version version = bw_calcs_version_from_asic_id(asic_id);
2034
2035         dceip.version = version;
2036
2037         switch (version) {
2038         case BW_CALCS_VERSION_CARRIZO:
2039                 vbios.memory_type = bw_def_gddr5;
2040                 vbios.dram_channel_width_in_bits = 64;
2041                 vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
2042                 vbios.number_of_dram_banks = 8;
2043                 vbios.high_yclk = bw_int_to_fixed(1600);
2044                 vbios.mid_yclk = bw_int_to_fixed(1600);
2045                 vbios.low_yclk = bw_frc_to_fixed(66666, 100);
2046                 vbios.low_sclk = bw_int_to_fixed(200);
2047                 vbios.mid1_sclk = bw_int_to_fixed(300);
2048                 vbios.mid2_sclk = bw_int_to_fixed(300);
2049                 vbios.mid3_sclk = bw_int_to_fixed(300);
2050                 vbios.mid4_sclk = bw_int_to_fixed(300);
2051                 vbios.mid5_sclk = bw_int_to_fixed(300);
2052                 vbios.mid6_sclk = bw_int_to_fixed(300);
2053                 vbios.high_sclk = bw_frc_to_fixed(62609, 100);
2054                 vbios.low_voltage_max_dispclk = bw_int_to_fixed(352);
2055                 vbios.mid_voltage_max_dispclk = bw_int_to_fixed(467);
2056                 vbios.high_voltage_max_dispclk = bw_int_to_fixed(643);
2057                 vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
2058                 vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
2059                 vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
2060                 vbios.data_return_bus_width = bw_int_to_fixed(32);
2061                 vbios.trc = bw_int_to_fixed(50);
2062                 vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
2063                 vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(153, 10);
2064                 vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2065                 vbios.nbp_state_change_latency = bw_frc_to_fixed(19649, 1000);
2066                 vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2067                 vbios.scatter_gather_enable = true;
2068                 vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
2069                 vbios.cursor_width = 32;
2070                 vbios.average_compression_rate = 4;
2071                 vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2072                 vbios.blackout_duration = bw_int_to_fixed(0); /* us */
2073                 vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
2074
2075                 dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2076                 dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2077                 dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2078                 dceip.large_cursor = false;
2079                 dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
2080                 dceip.dmif_pipe_en_fbc_chunk_tracker = false;
2081                 dceip.cursor_max_outstanding_group_num = 1;
2082                 dceip.lines_interleaved_into_lb = 2;
2083                 dceip.chunk_width = 256;
2084                 dceip.number_of_graphics_pipes = 3;
2085                 dceip.number_of_underlay_pipes = 1;
2086                 dceip.low_power_tiling_mode = 0;
2087                 dceip.display_write_back_supported = false;
2088                 dceip.argb_compression_support = false;
2089                 dceip.underlay_vscaler_efficiency6_bit_per_component =
2090                         bw_frc_to_fixed(35556, 10000);
2091                 dceip.underlay_vscaler_efficiency8_bit_per_component =
2092                         bw_frc_to_fixed(34286, 10000);
2093                 dceip.underlay_vscaler_efficiency10_bit_per_component =
2094                         bw_frc_to_fixed(32, 10);
2095                 dceip.underlay_vscaler_efficiency12_bit_per_component =
2096                         bw_int_to_fixed(3);
2097                 dceip.graphics_vscaler_efficiency6_bit_per_component =
2098                         bw_frc_to_fixed(35, 10);
2099                 dceip.graphics_vscaler_efficiency8_bit_per_component =
2100                         bw_frc_to_fixed(34286, 10000);
2101                 dceip.graphics_vscaler_efficiency10_bit_per_component =
2102                         bw_frc_to_fixed(32, 10);
2103                 dceip.graphics_vscaler_efficiency12_bit_per_component =
2104                         bw_int_to_fixed(3);
2105                 dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
2106                 dceip.max_dmif_buffer_allocated = 2;
2107                 dceip.graphics_dmif_size = 12288;
2108                 dceip.underlay_luma_dmif_size = 19456;
2109                 dceip.underlay_chroma_dmif_size = 23552;
2110                 dceip.pre_downscaler_enabled = true;
2111                 dceip.underlay_downscale_prefetch_enabled = true;
2112                 dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2113                 dceip.lb_size_per_component444 = bw_int_to_fixed(82176);
2114                 dceip.graphics_lb_nodownscaling_multi_line_prefetching = false;
2115                 dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
2116                         bw_int_to_fixed(0);
2117                 dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2118                         82176);
2119                 dceip.underlay420_chroma_lb_size_per_component =
2120                         bw_int_to_fixed(164352);
2121                 dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
2122                         82176);
2123                 dceip.cursor_chunk_width = bw_int_to_fixed(64);
2124                 dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2125                 dceip.underlay_maximum_width_efficient_for_tiling =
2126                         bw_int_to_fixed(1920);
2127                 dceip.underlay_maximum_height_efficient_for_tiling =
2128                         bw_int_to_fixed(1080);
2129                 dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2130                         bw_frc_to_fixed(3, 10);
2131                 dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2132                         bw_int_to_fixed(25);
2133                 dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2134                         2);
2135                 dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
2136                         bw_int_to_fixed(128);
2137                 dceip.limit_excessive_outstanding_dmif_requests = true;
2138                 dceip.linear_mode_line_request_alternation_slice =
2139                         bw_int_to_fixed(64);
2140                 dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2141                         32;
2142                 dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
2143                 dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
2144                 dceip.request_efficiency = bw_frc_to_fixed(8, 10);
2145                 dceip.dispclk_per_request = bw_int_to_fixed(2);
2146                 dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2147                 dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2148                 dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
2149                 dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); /* todo: this is a bug*/
2150                 break;
2151         case BW_CALCS_VERSION_POLARIS10:
2152                 /* TODO: Treat VEGAM the same as P10 for now
2153                  * Need to tune the para for VEGAM if needed */
2154         case BW_CALCS_VERSION_VEGAM:
2155                 vbios.memory_type = bw_def_gddr5;
2156                 vbios.dram_channel_width_in_bits = 32;
2157                 vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
2158                 vbios.number_of_dram_banks = 8;
2159                 vbios.high_yclk = bw_int_to_fixed(6000);
2160                 vbios.mid_yclk = bw_int_to_fixed(3200);
2161                 vbios.low_yclk = bw_int_to_fixed(1000);
2162                 vbios.low_sclk = bw_int_to_fixed(300);
2163                 vbios.mid1_sclk = bw_int_to_fixed(400);
2164                 vbios.mid2_sclk = bw_int_to_fixed(500);
2165                 vbios.mid3_sclk = bw_int_to_fixed(600);
2166                 vbios.mid4_sclk = bw_int_to_fixed(700);
2167                 vbios.mid5_sclk = bw_int_to_fixed(800);
2168                 vbios.mid6_sclk = bw_int_to_fixed(974);
2169                 vbios.high_sclk = bw_int_to_fixed(1154);
2170                 vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
2171                 vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
2172                 vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);
2173                 vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
2174                 vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
2175                 vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
2176                 vbios.data_return_bus_width = bw_int_to_fixed(32);
2177                 vbios.trc = bw_int_to_fixed(48);
2178                 vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
2179                 vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
2180                 vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2181                 vbios.nbp_state_change_latency = bw_int_to_fixed(45);
2182                 vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2183                 vbios.scatter_gather_enable = true;
2184                 vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
2185                 vbios.cursor_width = 32;
2186                 vbios.average_compression_rate = 4;
2187                 vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2188                 vbios.blackout_duration = bw_int_to_fixed(0); /* us */
2189                 vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
2190
2191                 dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2192                 dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2193                 dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2194                 dceip.large_cursor = false;
2195                 dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
2196                 dceip.dmif_pipe_en_fbc_chunk_tracker = false;
2197                 dceip.cursor_max_outstanding_group_num = 1;
2198                 dceip.lines_interleaved_into_lb = 2;
2199                 dceip.chunk_width = 256;
2200                 dceip.number_of_graphics_pipes = 6;
2201                 dceip.number_of_underlay_pipes = 0;
2202                 dceip.low_power_tiling_mode = 0;
2203                 dceip.display_write_back_supported = false;
2204                 dceip.argb_compression_support = true;
2205                 dceip.underlay_vscaler_efficiency6_bit_per_component =
2206                         bw_frc_to_fixed(35556, 10000);
2207                 dceip.underlay_vscaler_efficiency8_bit_per_component =
2208                         bw_frc_to_fixed(34286, 10000);
2209                 dceip.underlay_vscaler_efficiency10_bit_per_component =
2210                         bw_frc_to_fixed(32, 10);
2211                 dceip.underlay_vscaler_efficiency12_bit_per_component =
2212                         bw_int_to_fixed(3);
2213                 dceip.graphics_vscaler_efficiency6_bit_per_component =
2214                         bw_frc_to_fixed(35, 10);
2215                 dceip.graphics_vscaler_efficiency8_bit_per_component =
2216                         bw_frc_to_fixed(34286, 10000);
2217                 dceip.graphics_vscaler_efficiency10_bit_per_component =
2218                         bw_frc_to_fixed(32, 10);
2219                 dceip.graphics_vscaler_efficiency12_bit_per_component =
2220                         bw_int_to_fixed(3);
2221                 dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
2222                 dceip.max_dmif_buffer_allocated = 4;
2223                 dceip.graphics_dmif_size = 12288;
2224                 dceip.underlay_luma_dmif_size = 19456;
2225                 dceip.underlay_chroma_dmif_size = 23552;
2226                 dceip.pre_downscaler_enabled = true;
2227                 dceip.underlay_downscale_prefetch_enabled = true;
2228                 dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2229                 dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
2230                 dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
2231                 dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
2232                         bw_int_to_fixed(1);
2233                 dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2234                         82176);
2235                 dceip.underlay420_chroma_lb_size_per_component =
2236                         bw_int_to_fixed(164352);
2237                 dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
2238                         82176);
2239                 dceip.cursor_chunk_width = bw_int_to_fixed(64);
2240                 dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2241                 dceip.underlay_maximum_width_efficient_for_tiling =
2242                         bw_int_to_fixed(1920);
2243                 dceip.underlay_maximum_height_efficient_for_tiling =
2244                         bw_int_to_fixed(1080);
2245                 dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2246                         bw_frc_to_fixed(3, 10);
2247                 dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2248                         bw_int_to_fixed(25);
2249                 dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2250                         2);
2251                 dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
2252                         bw_int_to_fixed(128);
2253                 dceip.limit_excessive_outstanding_dmif_requests = true;
2254                 dceip.linear_mode_line_request_alternation_slice =
2255                         bw_int_to_fixed(64);
2256                 dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2257                         32;
2258                 dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
2259                 dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
2260                 dceip.request_efficiency = bw_frc_to_fixed(8, 10);
2261                 dceip.dispclk_per_request = bw_int_to_fixed(2);
2262                 dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2263                 dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2264                 dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
2265                 dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2266                 break;
2267         case BW_CALCS_VERSION_POLARIS11:
2268                 vbios.memory_type = bw_def_gddr5;
2269                 vbios.dram_channel_width_in_bits = 32;
2270                 vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
2271                 vbios.number_of_dram_banks = 8;
2272                 vbios.high_yclk = bw_int_to_fixed(6000);
2273                 vbios.mid_yclk = bw_int_to_fixed(3200);
2274                 vbios.low_yclk = bw_int_to_fixed(1000);
2275                 vbios.low_sclk = bw_int_to_fixed(300);
2276                 vbios.mid1_sclk = bw_int_to_fixed(400);
2277                 vbios.mid2_sclk = bw_int_to_fixed(500);
2278                 vbios.mid3_sclk = bw_int_to_fixed(600);
2279                 vbios.mid4_sclk = bw_int_to_fixed(700);
2280                 vbios.mid5_sclk = bw_int_to_fixed(800);
2281                 vbios.mid6_sclk = bw_int_to_fixed(974);
2282                 vbios.high_sclk = bw_int_to_fixed(1154);
2283                 vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
2284                 vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
2285                 vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);
2286                 vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
2287                 vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
2288                 vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
2289                 vbios.data_return_bus_width = bw_int_to_fixed(32);
2290                 vbios.trc = bw_int_to_fixed(48);
2291                 if (vbios.number_of_dram_channels == 2) // 64-bit
2292                         vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
2293                 else
2294                         vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
2295                 vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
2296                 vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2297                 vbios.nbp_state_change_latency = bw_int_to_fixed(45);
2298                 vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2299                 vbios.scatter_gather_enable = true;
2300                 vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
2301                 vbios.cursor_width = 32;
2302                 vbios.average_compression_rate = 4;
2303                 vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2304                 vbios.blackout_duration = bw_int_to_fixed(0); /* us */
2305                 vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
2306
2307                 dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2308                 dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2309                 dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2310                 dceip.large_cursor = false;
2311                 dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
2312                 dceip.dmif_pipe_en_fbc_chunk_tracker = false;
2313                 dceip.cursor_max_outstanding_group_num = 1;
2314                 dceip.lines_interleaved_into_lb = 2;
2315                 dceip.chunk_width = 256;
2316                 dceip.number_of_graphics_pipes = 5;
2317                 dceip.number_of_underlay_pipes = 0;
2318                 dceip.low_power_tiling_mode = 0;
2319                 dceip.display_write_back_supported = false;
2320                 dceip.argb_compression_support = true;
2321                 dceip.underlay_vscaler_efficiency6_bit_per_component =
2322                         bw_frc_to_fixed(35556, 10000);
2323                 dceip.underlay_vscaler_efficiency8_bit_per_component =
2324                         bw_frc_to_fixed(34286, 10000);
2325                 dceip.underlay_vscaler_efficiency10_bit_per_component =
2326                         bw_frc_to_fixed(32, 10);
2327                 dceip.underlay_vscaler_efficiency12_bit_per_component =
2328                         bw_int_to_fixed(3);
2329                 dceip.graphics_vscaler_efficiency6_bit_per_component =
2330                         bw_frc_to_fixed(35, 10);
2331                 dceip.graphics_vscaler_efficiency8_bit_per_component =
2332                         bw_frc_to_fixed(34286, 10000);
2333                 dceip.graphics_vscaler_efficiency10_bit_per_component =
2334                         bw_frc_to_fixed(32, 10);
2335                 dceip.graphics_vscaler_efficiency12_bit_per_component =
2336                         bw_int_to_fixed(3);
2337                 dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
2338                 dceip.max_dmif_buffer_allocated = 4;
2339                 dceip.graphics_dmif_size = 12288;
2340                 dceip.underlay_luma_dmif_size = 19456;
2341                 dceip.underlay_chroma_dmif_size = 23552;
2342                 dceip.pre_downscaler_enabled = true;
2343                 dceip.underlay_downscale_prefetch_enabled = true;
2344                 dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2345                 dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
2346                 dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
2347                 dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
2348                         bw_int_to_fixed(1);
2349                 dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2350                         82176);
2351                 dceip.underlay420_chroma_lb_size_per_component =
2352                         bw_int_to_fixed(164352);
2353                 dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
2354                         82176);
2355                 dceip.cursor_chunk_width = bw_int_to_fixed(64);
2356                 dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2357                 dceip.underlay_maximum_width_efficient_for_tiling =
2358                         bw_int_to_fixed(1920);
2359                 dceip.underlay_maximum_height_efficient_for_tiling =
2360                         bw_int_to_fixed(1080);
2361                 dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2362                         bw_frc_to_fixed(3, 10);
2363                 dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2364                         bw_int_to_fixed(25);
2365                 dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2366                         2);
2367                 dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
2368                         bw_int_to_fixed(128);
2369                 dceip.limit_excessive_outstanding_dmif_requests = true;
2370                 dceip.linear_mode_line_request_alternation_slice =
2371                         bw_int_to_fixed(64);
2372                 dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2373                         32;
2374                 dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
2375                 dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
2376                 dceip.request_efficiency = bw_frc_to_fixed(8, 10);
2377                 dceip.dispclk_per_request = bw_int_to_fixed(2);
2378                 dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2379                 dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2380                 dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
2381                 dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2382                 break;
2383         case BW_CALCS_VERSION_POLARIS12:
2384                 vbios.memory_type = bw_def_gddr5;
2385                 vbios.dram_channel_width_in_bits = 32;
2386                 vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
2387                 vbios.number_of_dram_banks = 8;
2388                 vbios.high_yclk = bw_int_to_fixed(6000);
2389                 vbios.mid_yclk = bw_int_to_fixed(3200);
2390                 vbios.low_yclk = bw_int_to_fixed(1000);
2391                 vbios.low_sclk = bw_int_to_fixed(678);
2392                 vbios.mid1_sclk = bw_int_to_fixed(864);
2393                 vbios.mid2_sclk = bw_int_to_fixed(900);
2394                 vbios.mid3_sclk = bw_int_to_fixed(920);
2395                 vbios.mid4_sclk = bw_int_to_fixed(940);
2396                 vbios.mid5_sclk = bw_int_to_fixed(960);
2397                 vbios.mid6_sclk = bw_int_to_fixed(980);
2398                 vbios.high_sclk = bw_int_to_fixed(1049);
2399                 vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
2400                 vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
2401                 vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);
2402                 vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
2403                 vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
2404                 vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
2405                 vbios.data_return_bus_width = bw_int_to_fixed(32);
2406                 vbios.trc = bw_int_to_fixed(48);
2407                 if (vbios.number_of_dram_channels == 2) // 64-bit
2408                         vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
2409                 else
2410                         vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
2411                 vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
2412                 vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2413                 vbios.nbp_state_change_latency = bw_int_to_fixed(250);
2414                 vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2415                 vbios.scatter_gather_enable = false;
2416                 vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
2417                 vbios.cursor_width = 32;
2418                 vbios.average_compression_rate = 4;
2419                 vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2420                 vbios.blackout_duration = bw_int_to_fixed(0); /* us */
2421                 vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
2422
2423                 dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2424                 dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2425                 dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2426                 dceip.large_cursor = false;
2427                 dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
2428                 dceip.dmif_pipe_en_fbc_chunk_tracker = false;
2429                 dceip.cursor_max_outstanding_group_num = 1;
2430                 dceip.lines_interleaved_into_lb = 2;
2431                 dceip.chunk_width = 256;
2432                 dceip.number_of_graphics_pipes = 5;
2433                 dceip.number_of_underlay_pipes = 0;
2434                 dceip.low_power_tiling_mode = 0;
2435                 dceip.display_write_back_supported = true;
2436                 dceip.argb_compression_support = true;
2437                 dceip.underlay_vscaler_efficiency6_bit_per_component =
2438                         bw_frc_to_fixed(35556, 10000);
2439                 dceip.underlay_vscaler_efficiency8_bit_per_component =
2440                         bw_frc_to_fixed(34286, 10000);
2441                 dceip.underlay_vscaler_efficiency10_bit_per_component =
2442                         bw_frc_to_fixed(32, 10);
2443                 dceip.underlay_vscaler_efficiency12_bit_per_component =
2444                         bw_int_to_fixed(3);
2445                 dceip.graphics_vscaler_efficiency6_bit_per_component =
2446                         bw_frc_to_fixed(35, 10);
2447                 dceip.graphics_vscaler_efficiency8_bit_per_component =
2448                         bw_frc_to_fixed(34286, 10000);
2449                 dceip.graphics_vscaler_efficiency10_bit_per_component =
2450                         bw_frc_to_fixed(32, 10);
2451                 dceip.graphics_vscaler_efficiency12_bit_per_component =
2452                         bw_int_to_fixed(3);
2453                 dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
2454                 dceip.max_dmif_buffer_allocated = 4;
2455                 dceip.graphics_dmif_size = 12288;
2456                 dceip.underlay_luma_dmif_size = 19456;
2457                 dceip.underlay_chroma_dmif_size = 23552;
2458                 dceip.pre_downscaler_enabled = true;
2459                 dceip.underlay_downscale_prefetch_enabled = true;
2460                 dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2461                 dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
2462                 dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
2463                 dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
2464                         bw_int_to_fixed(1);
2465                 dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2466                         82176);
2467                 dceip.underlay420_chroma_lb_size_per_component =
2468                         bw_int_to_fixed(164352);
2469                 dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
2470                         82176);
2471                 dceip.cursor_chunk_width = bw_int_to_fixed(64);
2472                 dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2473                 dceip.underlay_maximum_width_efficient_for_tiling =
2474                         bw_int_to_fixed(1920);
2475                 dceip.underlay_maximum_height_efficient_for_tiling =
2476                         bw_int_to_fixed(1080);
2477                 dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2478                         bw_frc_to_fixed(3, 10);
2479                 dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2480                         bw_int_to_fixed(25);
2481                 dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2482                         2);
2483                 dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
2484                         bw_int_to_fixed(128);
2485                 dceip.limit_excessive_outstanding_dmif_requests = true;
2486                 dceip.linear_mode_line_request_alternation_slice =
2487                         bw_int_to_fixed(64);
2488                 dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2489                         32;
2490                 dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
2491                 dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
2492                 dceip.request_efficiency = bw_frc_to_fixed(8, 10);
2493                 dceip.dispclk_per_request = bw_int_to_fixed(2);
2494                 dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2495                 dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2496                 dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
2497                 dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2498                 break;
2499         case BW_CALCS_VERSION_STONEY:
2500                 vbios.memory_type = bw_def_gddr5;
2501                 vbios.dram_channel_width_in_bits = 64;
2502                 vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
2503                 vbios.number_of_dram_banks = 8;
2504                 vbios.high_yclk = bw_int_to_fixed(1866);
2505                 vbios.mid_yclk = bw_int_to_fixed(1866);
2506                 vbios.low_yclk = bw_int_to_fixed(1333);
2507                 vbios.low_sclk = bw_int_to_fixed(200);
2508                 vbios.mid1_sclk = bw_int_to_fixed(600);
2509                 vbios.mid2_sclk = bw_int_to_fixed(600);
2510                 vbios.mid3_sclk = bw_int_to_fixed(600);
2511                 vbios.mid4_sclk = bw_int_to_fixed(600);
2512                 vbios.mid5_sclk = bw_int_to_fixed(600);
2513                 vbios.mid6_sclk = bw_int_to_fixed(600);
2514                 vbios.high_sclk = bw_int_to_fixed(800);
2515                 vbios.low_voltage_max_dispclk = bw_int_to_fixed(352);
2516                 vbios.mid_voltage_max_dispclk = bw_int_to_fixed(467);
2517                 vbios.high_voltage_max_dispclk = bw_int_to_fixed(643);
2518                 vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
2519                 vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
2520                 vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
2521                 vbios.data_return_bus_width = bw_int_to_fixed(32);
2522                 vbios.trc = bw_int_to_fixed(50);
2523                 vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
2524                 vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(158, 10);
2525                 vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
2526                 vbios.nbp_state_change_latency = bw_frc_to_fixed(2008, 100);
2527                 vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2528                 vbios.scatter_gather_enable = true;
2529                 vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
2530                 vbios.cursor_width = 32;
2531                 vbios.average_compression_rate = 4;
2532                 vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
2533                 vbios.blackout_duration = bw_int_to_fixed(0); /* us */
2534                 vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
2535
2536                 dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2537                 dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2538                 dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2539                 dceip.large_cursor = false;
2540                 dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
2541                 dceip.dmif_pipe_en_fbc_chunk_tracker = false;
2542                 dceip.cursor_max_outstanding_group_num = 1;
2543                 dceip.lines_interleaved_into_lb = 2;
2544                 dceip.chunk_width = 256;
2545                 dceip.number_of_graphics_pipes = 2;
2546                 dceip.number_of_underlay_pipes = 1;
2547                 dceip.low_power_tiling_mode = 0;
2548                 dceip.display_write_back_supported = false;
2549                 dceip.argb_compression_support = true;
2550                 dceip.underlay_vscaler_efficiency6_bit_per_component =
2551                         bw_frc_to_fixed(35556, 10000);
2552                 dceip.underlay_vscaler_efficiency8_bit_per_component =
2553                         bw_frc_to_fixed(34286, 10000);
2554                 dceip.underlay_vscaler_efficiency10_bit_per_component =
2555                         bw_frc_to_fixed(32, 10);
2556                 dceip.underlay_vscaler_efficiency12_bit_per_component =
2557                         bw_int_to_fixed(3);
2558                 dceip.graphics_vscaler_efficiency6_bit_per_component =
2559                         bw_frc_to_fixed(35, 10);
2560                 dceip.graphics_vscaler_efficiency8_bit_per_component =
2561                         bw_frc_to_fixed(34286, 10000);
2562                 dceip.graphics_vscaler_efficiency10_bit_per_component =
2563                         bw_frc_to_fixed(32, 10);
2564                 dceip.graphics_vscaler_efficiency12_bit_per_component =
2565                         bw_int_to_fixed(3);
2566                 dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
2567                 dceip.max_dmif_buffer_allocated = 2;
2568                 dceip.graphics_dmif_size = 12288;
2569                 dceip.underlay_luma_dmif_size = 19456;
2570                 dceip.underlay_chroma_dmif_size = 23552;
2571                 dceip.pre_downscaler_enabled = true;
2572                 dceip.underlay_downscale_prefetch_enabled = true;
2573                 dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2574                 dceip.lb_size_per_component444 = bw_int_to_fixed(82176);
2575                 dceip.graphics_lb_nodownscaling_multi_line_prefetching = false;
2576                 dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
2577                         bw_int_to_fixed(0);
2578                 dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2579                         82176);
2580                 dceip.underlay420_chroma_lb_size_per_component =
2581                         bw_int_to_fixed(164352);
2582                 dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
2583                         82176);
2584                 dceip.cursor_chunk_width = bw_int_to_fixed(64);
2585                 dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2586                 dceip.underlay_maximum_width_efficient_for_tiling =
2587                         bw_int_to_fixed(1920);
2588                 dceip.underlay_maximum_height_efficient_for_tiling =
2589                         bw_int_to_fixed(1080);
2590                 dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2591                         bw_frc_to_fixed(3, 10);
2592                 dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2593                         bw_int_to_fixed(25);
2594                 dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2595                         2);
2596                 dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
2597                         bw_int_to_fixed(128);
2598                 dceip.limit_excessive_outstanding_dmif_requests = true;
2599                 dceip.linear_mode_line_request_alternation_slice =
2600                         bw_int_to_fixed(64);
2601                 dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2602                         32;
2603                 dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
2604                 dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
2605                 dceip.request_efficiency = bw_frc_to_fixed(8, 10);
2606                 dceip.dispclk_per_request = bw_int_to_fixed(2);
2607                 dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2608                 dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2609                 dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
2610                 dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2611                 break;
2612         case BW_CALCS_VERSION_VEGA10:
2613                 vbios.memory_type = bw_def_hbm;
2614                 vbios.dram_channel_width_in_bits = 128;
2615                 vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
2616                 vbios.number_of_dram_banks = 16;
2617                 vbios.high_yclk = bw_int_to_fixed(2400);
2618                 vbios.mid_yclk = bw_int_to_fixed(1700);
2619                 vbios.low_yclk = bw_int_to_fixed(1000);
2620                 vbios.low_sclk = bw_int_to_fixed(300);
2621                 vbios.mid1_sclk = bw_int_to_fixed(350);
2622                 vbios.mid2_sclk = bw_int_to_fixed(400);
2623                 vbios.mid3_sclk = bw_int_to_fixed(500);
2624                 vbios.mid4_sclk = bw_int_to_fixed(600);
2625                 vbios.mid5_sclk = bw_int_to_fixed(700);
2626                 vbios.mid6_sclk = bw_int_to_fixed(760);
2627                 vbios.high_sclk = bw_int_to_fixed(776);
2628                 vbios.low_voltage_max_dispclk = bw_int_to_fixed(460);
2629                 vbios.mid_voltage_max_dispclk = bw_int_to_fixed(670);
2630                 vbios.high_voltage_max_dispclk = bw_int_to_fixed(1133);
2631                 vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
2632                 vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
2633                 vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
2634                 vbios.data_return_bus_width = bw_int_to_fixed(32);
2635                 vbios.trc = bw_int_to_fixed(48);
2636                 vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
2637                 vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(75, 10);
2638                 vbios.stutter_self_refresh_entry_latency = bw_frc_to_fixed(19, 10);
2639                 vbios.nbp_state_change_latency = bw_int_to_fixed(39);
2640                 vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
2641                 vbios.scatter_gather_enable = false;
2642                 vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
2643                 vbios.cursor_width = 32;
2644                 vbios.average_compression_rate = 4;
2645                 vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 8;
2646                 vbios.blackout_duration = bw_int_to_fixed(0); /* us */
2647                 vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
2648
2649                 dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
2650                 dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
2651                 dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
2652                 dceip.large_cursor = false;
2653                 dceip.dmif_request_buffer_size = bw_int_to_fixed(2304);
2654                 dceip.dmif_pipe_en_fbc_chunk_tracker = true;
2655                 dceip.cursor_max_outstanding_group_num = 1;
2656                 dceip.lines_interleaved_into_lb = 2;
2657                 dceip.chunk_width = 256;
2658                 dceip.number_of_graphics_pipes = 6;
2659                 dceip.number_of_underlay_pipes = 0;
2660                 dceip.low_power_tiling_mode = 0;
2661                 dceip.display_write_back_supported = true;
2662                 dceip.argb_compression_support = true;
2663                 dceip.underlay_vscaler_efficiency6_bit_per_component =
2664                         bw_frc_to_fixed(35556, 10000);
2665                 dceip.underlay_vscaler_efficiency8_bit_per_component =
2666                         bw_frc_to_fixed(34286, 10000);
2667                 dceip.underlay_vscaler_efficiency10_bit_per_component =
2668                         bw_frc_to_fixed(32, 10);
2669                 dceip.underlay_vscaler_efficiency12_bit_per_component =
2670                         bw_int_to_fixed(3);
2671                 dceip.graphics_vscaler_efficiency6_bit_per_component =
2672                         bw_frc_to_fixed(35, 10);
2673                 dceip.graphics_vscaler_efficiency8_bit_per_component =
2674                         bw_frc_to_fixed(34286, 10000);
2675                 dceip.graphics_vscaler_efficiency10_bit_per_component =
2676                         bw_frc_to_fixed(32, 10);
2677                 dceip.graphics_vscaler_efficiency12_bit_per_component =
2678                         bw_int_to_fixed(3);
2679                 dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
2680                 dceip.max_dmif_buffer_allocated = 4;
2681                 dceip.graphics_dmif_size = 24576;
2682                 dceip.underlay_luma_dmif_size = 19456;
2683                 dceip.underlay_chroma_dmif_size = 23552;
2684                 dceip.pre_downscaler_enabled = true;
2685                 dceip.underlay_downscale_prefetch_enabled = false;
2686                 dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
2687                 dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
2688                 dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
2689                 dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
2690                         bw_int_to_fixed(1);
2691                 dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
2692                         82176);
2693                 dceip.underlay420_chroma_lb_size_per_component =
2694                         bw_int_to_fixed(164352);
2695                 dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
2696                         82176);
2697                 dceip.cursor_chunk_width = bw_int_to_fixed(64);
2698                 dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
2699                 dceip.underlay_maximum_width_efficient_for_tiling =
2700                         bw_int_to_fixed(1920);
2701                 dceip.underlay_maximum_height_efficient_for_tiling =
2702                         bw_int_to_fixed(1080);
2703                 dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
2704                         bw_frc_to_fixed(3, 10);
2705                 dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
2706                         bw_int_to_fixed(25);
2707                 dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2708                         2);
2709                 dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
2710                         bw_int_to_fixed(128);
2711                 dceip.limit_excessive_outstanding_dmif_requests = true;
2712                 dceip.linear_mode_line_request_alternation_slice =
2713                         bw_int_to_fixed(64);
2714                 dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
2715                         32;
2716                 dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
2717                 dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
2718                 dceip.request_efficiency = bw_frc_to_fixed(8, 10);
2719                 dceip.dispclk_per_request = bw_int_to_fixed(2);
2720                 dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
2721                 dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
2722                 dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
2723                 dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
2724                 break;
2725         default:
2726                 break;
2727         }
2728         *bw_dceip = dceip;
2729         *bw_vbios = vbios;
2730
2731 }
2732
2733 /**
2734  * Compare calculated (required) clocks against the clocks available at
2735  * maximum voltage (max Performance Level).
2736  */
2737 static bool is_display_configuration_supported(
2738         const struct bw_calcs_vbios *vbios,
2739         const struct dce_bw_output *calcs_output)
2740 {
2741         uint32_t int_max_clk;
2742
2743         int_max_clk = bw_fixed_to_int(vbios->high_voltage_max_dispclk);
2744         int_max_clk *= 1000; /* MHz to kHz */
2745         if (calcs_output->dispclk_khz > int_max_clk)
2746                 return false;
2747
2748         int_max_clk = bw_fixed_to_int(vbios->high_sclk);
2749         int_max_clk *= 1000; /* MHz to kHz */
2750         if (calcs_output->sclk_khz > int_max_clk)
2751                 return false;
2752
2753         return true;
2754 }
2755
2756 static void populate_initial_data(
2757         const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data)
2758 {
2759         int i, j;
2760         int num_displays = 0;
2761
2762         data->underlay_surface_type = bw_def_420;
2763         data->panning_and_bezel_adjustment = bw_def_none;
2764         data->graphics_lb_bpc = 10;
2765         data->underlay_lb_bpc = 8;
2766         data->underlay_tiling_mode = bw_def_tiled;
2767         data->graphics_tiling_mode = bw_def_tiled;
2768         data->underlay_micro_tile_mode = bw_def_display_micro_tiling;
2769         data->graphics_micro_tile_mode = bw_def_display_micro_tiling;
2770         data->increase_voltage_to_support_mclk_switch = true;
2771
2772         /* Pipes with underlay first */
2773         for (i = 0; i < pipe_count; i++) {
2774                 if (!pipe[i].stream || !pipe[i].bottom_pipe)
2775                         continue;
2776
2777                 ASSERT(pipe[i].plane_state);
2778
2779                 if (num_displays == 0) {
2780                         if (!pipe[i].plane_state->visible)
2781                                 data->d0_underlay_mode = bw_def_underlay_only;
2782                         else
2783                                 data->d0_underlay_mode = bw_def_blend;
2784                 } else {
2785                         if (!pipe[i].plane_state->visible)
2786                                 data->d1_underlay_mode = bw_def_underlay_only;
2787                         else
2788                                 data->d1_underlay_mode = bw_def_blend;
2789                 }
2790
2791                 data->fbc_en[num_displays + 4] = false;
2792                 data->lpt_en[num_displays + 4] = false;
2793                 data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
2794                 data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
2795                 data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000);
2796                 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
2797                 data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
2798                 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);
2799                 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);
2800                 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);
2801                 data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);
2802                 data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);
2803                 switch (pipe[i].plane_state->rotation) {
2804                 case ROTATION_ANGLE_0:
2805                         data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
2806                         break;
2807                 case ROTATION_ANGLE_90:
2808                         data->rotation_angle[num_displays + 4] = bw_int_to_fixed(90);
2809                         break;
2810                 case ROTATION_ANGLE_180:
2811                         data->rotation_angle[num_displays + 4] = bw_int_to_fixed(180);
2812                         break;
2813                 case ROTATION_ANGLE_270:
2814                         data->rotation_angle[num_displays + 4] = bw_int_to_fixed(270);
2815                         break;
2816                 default:
2817                         break;
2818                 }
2819                 switch (pipe[i].plane_state->format) {
2820                 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2821                 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2822                 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2823                         data->bytes_per_pixel[num_displays + 4] = 2;
2824                         break;
2825                 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2826                 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2827                 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2828                 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2829                 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2830                 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2831                 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2832                         data->bytes_per_pixel[num_displays + 4] = 4;
2833                         break;
2834                 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2835                 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2836                         data->bytes_per_pixel[num_displays + 4] = 8;
2837                         break;
2838                 default:
2839                         data->bytes_per_pixel[num_displays + 4] = 4;
2840                         break;
2841                 }
2842                 data->interlace_mode[num_displays + 4] = false;
2843                 data->stereo_mode[num_displays + 4] = bw_def_mono;
2844
2845
2846                 for (j = 0; j < 2; j++) {
2847                         data->fbc_en[num_displays * 2 + j] = false;
2848                         data->lpt_en[num_displays * 2 + j] = false;
2849
2850                         data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height);
2851                         data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width);
2852                         data->pitch_in_pixels[num_displays * 2 + j] = bw_int_to_fixed(
2853                                         pipe[i].bottom_pipe->plane_state->plane_size.grph.surface_pitch);
2854                         data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps);
2855                         data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps);
2856                         data->h_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed(
2857                                         pipe[i].bottom_pipe->plane_res.scl_data.ratios.horz.value);
2858                         data->v_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed(
2859                                         pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value);
2860                         switch (pipe[i].bottom_pipe->plane_state->rotation) {
2861                         case ROTATION_ANGLE_0:
2862                                 data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(0);
2863                                 break;
2864                         case ROTATION_ANGLE_90:
2865                                 data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(90);
2866                                 break;
2867                         case ROTATION_ANGLE_180:
2868                                 data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(180);
2869                                 break;
2870                         case ROTATION_ANGLE_270:
2871                                 data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(270);
2872                                 break;
2873                         default:
2874                                 break;
2875                         }
2876                         data->stereo_mode[num_displays * 2 + j] = bw_def_mono;
2877                 }
2878
2879                 num_displays++;
2880         }
2881
2882         /* Pipes without underlay after */
2883         for (i = 0; i < pipe_count; i++) {
2884                 if (!pipe[i].stream || pipe[i].bottom_pipe)
2885                         continue;
2886
2887
2888                 data->fbc_en[num_displays + 4] = false;
2889                 data->lpt_en[num_displays + 4] = false;
2890                 data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
2891                 data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
2892                 data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000);
2893                 if (pipe[i].plane_state) {
2894                         data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
2895                         data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
2896                         data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);
2897                         data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);
2898                         data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);
2899                         data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);
2900                         data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);
2901                         switch (pipe[i].plane_state->rotation) {
2902                         case ROTATION_ANGLE_0:
2903                                 data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
2904                                 break;
2905                         case ROTATION_ANGLE_90:
2906                                 data->rotation_angle[num_displays + 4] = bw_int_to_fixed(90);
2907                                 break;
2908                         case ROTATION_ANGLE_180:
2909                                 data->rotation_angle[num_displays + 4] = bw_int_to_fixed(180);
2910                                 break;
2911                         case ROTATION_ANGLE_270:
2912                                 data->rotation_angle[num_displays + 4] = bw_int_to_fixed(270);
2913                                 break;
2914                         default:
2915                                 break;
2916                         }
2917                         switch (pipe[i].plane_state->format) {
2918                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2919                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2920                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2921                         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2922                                 data->bytes_per_pixel[num_displays + 4] = 2;
2923                                 break;
2924                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
2925                         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
2926                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
2927                         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
2928                         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
2929                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2930                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2931                                 data->bytes_per_pixel[num_displays + 4] = 4;
2932                                 break;
2933                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2934                         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2935                                 data->bytes_per_pixel[num_displays + 4] = 8;
2936                                 break;
2937                         default:
2938                                 data->bytes_per_pixel[num_displays + 4] = 4;
2939                                 break;
2940                         }
2941                 } else if (pipe[i].stream->dst.width != 0 &&
2942                                         pipe[i].stream->dst.height != 0 &&
2943                                         pipe[i].stream->src.width != 0 &&
2944                                         pipe[i].stream->src.height != 0) {
2945                         data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.width);
2946                         data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
2947                         data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.height);
2948                         data->h_taps[num_displays + 4] = pipe[i].stream->src.width == pipe[i].stream->dst.width ? bw_int_to_fixed(1) : bw_int_to_fixed(2);
2949                         data->v_taps[num_displays + 4] = pipe[i].stream->src.height == pipe[i].stream->dst.height ? bw_int_to_fixed(1) : bw_int_to_fixed(2);
2950                         data->h_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.width, pipe[i].stream->dst.width);
2951                         data->v_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.height, pipe[i].stream->dst.height);
2952                         data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
2953                         data->bytes_per_pixel[num_displays + 4] = 4;
2954                 } else {
2955                         data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);
2956                         data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
2957                         data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_addressable);
2958                         data->h_taps[num_displays + 4] = bw_int_to_fixed(1);
2959                         data->v_taps[num_displays + 4] = bw_int_to_fixed(1);
2960                         data->h_scale_ratio[num_displays + 4] = bw_int_to_fixed(1);
2961                         data->v_scale_ratio[num_displays + 4] = bw_int_to_fixed(1);
2962                         data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
2963                         data->bytes_per_pixel[num_displays + 4] = 4;
2964                 }
2965
2966                 data->interlace_mode[num_displays + 4] = false;
2967                 data->stereo_mode[num_displays + 4] = bw_def_mono;
2968                 num_displays++;
2969         }
2970
2971         data->number_of_displays = num_displays;
2972 }
2973
2974 /**
2975  * Return:
2976  *      true -  Display(s) configuration supported.
2977  *              In this case 'calcs_output' contains data for HW programming
2978  *      false - Display(s) configuration not supported (not enough bandwidth).
2979  */
2980
2981 bool bw_calcs(struct dc_context *ctx,
2982         const struct bw_calcs_dceip *dceip,
2983         const struct bw_calcs_vbios *vbios,
2984         const struct pipe_ctx pipe[],
2985         int pipe_count,
2986         struct dce_bw_output *calcs_output)
2987 {
2988         struct bw_calcs_data *data = kzalloc(sizeof(struct bw_calcs_data),
2989                                              GFP_KERNEL);
2990         if (!data)
2991                 return false;
2992
2993         populate_initial_data(pipe, pipe_count, data);
2994
2995         /*TODO: this should be taken out calcs output and assigned during timing sync for pplib use*/
2996         calcs_output->all_displays_in_sync = false;
2997
2998         if (data->number_of_displays != 0) {
2999                 uint8_t yclk_lvl, sclk_lvl;
3000                 struct bw_fixed high_sclk = vbios->high_sclk;
3001                 struct bw_fixed mid1_sclk = vbios->mid1_sclk;
3002                 struct bw_fixed mid2_sclk = vbios->mid2_sclk;
3003                 struct bw_fixed mid3_sclk = vbios->mid3_sclk;
3004                 struct bw_fixed mid4_sclk = vbios->mid4_sclk;
3005                 struct bw_fixed mid5_sclk = vbios->mid5_sclk;
3006                 struct bw_fixed mid6_sclk = vbios->mid6_sclk;
3007                 struct bw_fixed low_sclk = vbios->low_sclk;
3008                 struct bw_fixed high_yclk = vbios->high_yclk;
3009                 struct bw_fixed mid_yclk = vbios->mid_yclk;
3010                 struct bw_fixed low_yclk = vbios->low_yclk;
3011
3012                 if (ctx->dc->debug.bandwidth_calcs_trace) {
3013                         print_bw_calcs_dceip(ctx, dceip);
3014                         print_bw_calcs_vbios(ctx, vbios);
3015                         print_bw_calcs_data(ctx, data);
3016                 }
3017                 calculate_bandwidth(dceip, vbios, data);
3018
3019                 yclk_lvl = data->y_clk_level;
3020                 sclk_lvl = data->sclk_level;
3021
3022                 calcs_output->nbp_state_change_enable =
3023                         data->nbp_state_change_enable;
3024                 calcs_output->cpuc_state_change_enable =
3025                                 data->cpuc_state_change_enable;
3026                 calcs_output->cpup_state_change_enable =
3027                                 data->cpup_state_change_enable;
3028                 calcs_output->stutter_mode_enable =
3029                                 data->stutter_mode_enable;
3030                 calcs_output->dispclk_khz =
3031                         bw_fixed_to_int(bw_mul(data->dispclk,
3032                                         bw_int_to_fixed(1000)));
3033                 calcs_output->blackout_recovery_time_us =
3034                         bw_fixed_to_int(data->blackout_recovery_time);
3035                 calcs_output->sclk_khz =
3036                         bw_fixed_to_int(bw_mul(data->required_sclk,
3037                                         bw_int_to_fixed(1000)));
3038                 calcs_output->sclk_deep_sleep_khz =
3039                         bw_fixed_to_int(bw_mul(data->sclk_deep_sleep,
3040                                         bw_int_to_fixed(1000)));
3041                 if (yclk_lvl == 0)
3042                         calcs_output->yclk_khz = bw_fixed_to_int(
3043                                 bw_mul(low_yclk, bw_int_to_fixed(1000)));
3044                 else if (yclk_lvl == 1)
3045                         calcs_output->yclk_khz = bw_fixed_to_int(
3046                                 bw_mul(mid_yclk, bw_int_to_fixed(1000)));
3047                 else
3048                         calcs_output->yclk_khz = bw_fixed_to_int(
3049                                 bw_mul(high_yclk, bw_int_to_fixed(1000)));
3050
3051                 /* units: nanosecond, 16bit storage. */
3052
3053                 calcs_output->nbp_state_change_wm_ns[0].a_mark =
3054                         bw_fixed_to_int(bw_mul(data->
3055                                 nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
3056                 calcs_output->nbp_state_change_wm_ns[1].a_mark =
3057                         bw_fixed_to_int(bw_mul(data->
3058                                 nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
3059                 calcs_output->nbp_state_change_wm_ns[2].a_mark =
3060                         bw_fixed_to_int(bw_mul(data->
3061                                 nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
3062
3063                 if (ctx->dc->caps.max_slave_planes) {
3064                         calcs_output->nbp_state_change_wm_ns[3].a_mark =
3065                                 bw_fixed_to_int(bw_mul(data->
3066                                         nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
3067                         calcs_output->nbp_state_change_wm_ns[4].a_mark =
3068                                 bw_fixed_to_int(bw_mul(data->
3069                                                         nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
3070                 } else {
3071                         calcs_output->nbp_state_change_wm_ns[3].a_mark =
3072                                 bw_fixed_to_int(bw_mul(data->
3073                                         nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
3074                         calcs_output->nbp_state_change_wm_ns[4].a_mark =
3075                                 bw_fixed_to_int(bw_mul(data->
3076                                         nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
3077                 }
3078                 calcs_output->nbp_state_change_wm_ns[5].a_mark =
3079                         bw_fixed_to_int(bw_mul(data->
3080                                 nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
3081
3082
3083
3084                 calcs_output->stutter_exit_wm_ns[0].a_mark =
3085                         bw_fixed_to_int(bw_mul(data->
3086                                 stutter_exit_watermark[4], bw_int_to_fixed(1000)));
3087                 calcs_output->stutter_exit_wm_ns[1].a_mark =
3088                         bw_fixed_to_int(bw_mul(data->
3089                                 stutter_exit_watermark[5], bw_int_to_fixed(1000)));
3090                 calcs_output->stutter_exit_wm_ns[2].a_mark =
3091                         bw_fixed_to_int(bw_mul(data->
3092                                 stutter_exit_watermark[6], bw_int_to_fixed(1000)));
3093                 if (ctx->dc->caps.max_slave_planes) {
3094                         calcs_output->stutter_exit_wm_ns[3].a_mark =
3095                                 bw_fixed_to_int(bw_mul(data->
3096                                         stutter_exit_watermark[0], bw_int_to_fixed(1000)));
3097                         calcs_output->stutter_exit_wm_ns[4].a_mark =
3098                                 bw_fixed_to_int(bw_mul(data->
3099                                         stutter_exit_watermark[1], bw_int_to_fixed(1000)));
3100                 } else {
3101                         calcs_output->stutter_exit_wm_ns[3].a_mark =
3102                                 bw_fixed_to_int(bw_mul(data->
3103                                         stutter_exit_watermark[7], bw_int_to_fixed(1000)));
3104                         calcs_output->stutter_exit_wm_ns[4].a_mark =
3105                                 bw_fixed_to_int(bw_mul(data->
3106                                         stutter_exit_watermark[8], bw_int_to_fixed(1000)));
3107                 }
3108                 calcs_output->stutter_exit_wm_ns[5].a_mark =
3109                         bw_fixed_to_int(bw_mul(data->
3110                                 stutter_exit_watermark[9], bw_int_to_fixed(1000)));
3111
3112                 calcs_output->stutter_entry_wm_ns[0].a_mark =
3113                         bw_fixed_to_int(bw_mul(data->
3114                                 stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3115                 calcs_output->stutter_entry_wm_ns[1].a_mark =
3116                         bw_fixed_to_int(bw_mul(data->
3117                                 stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3118                 calcs_output->stutter_entry_wm_ns[2].a_mark =
3119                         bw_fixed_to_int(bw_mul(data->
3120                                 stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3121                 if (ctx->dc->caps.max_slave_planes) {
3122                         calcs_output->stutter_entry_wm_ns[3].a_mark =
3123                                 bw_fixed_to_int(bw_mul(data->
3124                                         stutter_entry_watermark[0], bw_int_to_fixed(1000)));
3125                         calcs_output->stutter_entry_wm_ns[4].a_mark =
3126                                 bw_fixed_to_int(bw_mul(data->
3127                                         stutter_entry_watermark[1], bw_int_to_fixed(1000)));
3128                 } else {
3129                         calcs_output->stutter_entry_wm_ns[3].a_mark =
3130                                 bw_fixed_to_int(bw_mul(data->
3131                                         stutter_entry_watermark[7], bw_int_to_fixed(1000)));
3132                         calcs_output->stutter_entry_wm_ns[4].a_mark =
3133                                 bw_fixed_to_int(bw_mul(data->
3134                                         stutter_entry_watermark[8], bw_int_to_fixed(1000)));
3135                 }
3136                 calcs_output->stutter_entry_wm_ns[5].a_mark =
3137                         bw_fixed_to_int(bw_mul(data->
3138                                 stutter_entry_watermark[9], bw_int_to_fixed(1000)));
3139
3140                 calcs_output->urgent_wm_ns[0].a_mark =
3141                         bw_fixed_to_int(bw_mul(data->
3142                                 urgent_watermark[4], bw_int_to_fixed(1000)));
3143                 calcs_output->urgent_wm_ns[1].a_mark =
3144                         bw_fixed_to_int(bw_mul(data->
3145                                 urgent_watermark[5], bw_int_to_fixed(1000)));
3146                 calcs_output->urgent_wm_ns[2].a_mark =
3147                         bw_fixed_to_int(bw_mul(data->
3148                                 urgent_watermark[6], bw_int_to_fixed(1000)));
3149                 if (ctx->dc->caps.max_slave_planes) {
3150                         calcs_output->urgent_wm_ns[3].a_mark =
3151                                 bw_fixed_to_int(bw_mul(data->
3152                                         urgent_watermark[0], bw_int_to_fixed(1000)));
3153                         calcs_output->urgent_wm_ns[4].a_mark =
3154                                 bw_fixed_to_int(bw_mul(data->
3155                                         urgent_watermark[1], bw_int_to_fixed(1000)));
3156                 } else {
3157                         calcs_output->urgent_wm_ns[3].a_mark =
3158                                 bw_fixed_to_int(bw_mul(data->
3159                                         urgent_watermark[7], bw_int_to_fixed(1000)));
3160                         calcs_output->urgent_wm_ns[4].a_mark =
3161                                 bw_fixed_to_int(bw_mul(data->
3162                                         urgent_watermark[8], bw_int_to_fixed(1000)));
3163                 }
3164                 calcs_output->urgent_wm_ns[5].a_mark =
3165                         bw_fixed_to_int(bw_mul(data->
3166                                 urgent_watermark[9], bw_int_to_fixed(1000)));
3167
3168                 if (dceip->version != BW_CALCS_VERSION_CARRIZO) {
3169                         ((struct bw_calcs_vbios *)vbios)->low_sclk = mid3_sclk;
3170                         ((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid3_sclk;
3171                         ((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid3_sclk;
3172                         calculate_bandwidth(dceip, vbios, data);
3173
3174                         calcs_output->nbp_state_change_wm_ns[0].b_mark =
3175                                 bw_fixed_to_int(bw_mul(data->
3176                                         nbp_state_change_watermark[4],bw_int_to_fixed(1000)));
3177                         calcs_output->nbp_state_change_wm_ns[1].b_mark =
3178                                 bw_fixed_to_int(bw_mul(data->
3179                                         nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
3180                         calcs_output->nbp_state_change_wm_ns[2].b_mark =
3181                                 bw_fixed_to_int(bw_mul(data->
3182                                         nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
3183
3184                         if (ctx->dc->caps.max_slave_planes) {
3185                                 calcs_output->nbp_state_change_wm_ns[3].b_mark =
3186                                         bw_fixed_to_int(bw_mul(data->
3187                                                 nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
3188                                 calcs_output->nbp_state_change_wm_ns[4].b_mark =
3189                                         bw_fixed_to_int(bw_mul(data->
3190                                                 nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
3191                         } else {
3192                                 calcs_output->nbp_state_change_wm_ns[3].b_mark =
3193                                         bw_fixed_to_int(bw_mul(data->
3194                                                 nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
3195                                 calcs_output->nbp_state_change_wm_ns[4].b_mark =
3196                                         bw_fixed_to_int(bw_mul(data->
3197                                                 nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
3198                         }
3199                         calcs_output->nbp_state_change_wm_ns[5].b_mark =
3200                                 bw_fixed_to_int(bw_mul(data->
3201                                         nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
3202
3203
3204
3205                         calcs_output->stutter_exit_wm_ns[0].b_mark =
3206                                 bw_fixed_to_int(bw_mul(data->
3207                                         stutter_exit_watermark[4], bw_int_to_fixed(1000)));
3208                         calcs_output->stutter_exit_wm_ns[1].b_mark =
3209                                 bw_fixed_to_int(bw_mul(data->
3210                                         stutter_exit_watermark[5], bw_int_to_fixed(1000)));
3211                         calcs_output->stutter_exit_wm_ns[2].b_mark =
3212                                 bw_fixed_to_int(bw_mul(data->
3213                                         stutter_exit_watermark[6], bw_int_to_fixed(1000)));
3214                         if (ctx->dc->caps.max_slave_planes) {
3215                                 calcs_output->stutter_exit_wm_ns[3].b_mark =
3216                                         bw_fixed_to_int(bw_mul(data->
3217                                                 stutter_exit_watermark[0], bw_int_to_fixed(1000)));
3218                                 calcs_output->stutter_exit_wm_ns[4].b_mark =
3219                                         bw_fixed_to_int(bw_mul(data->
3220                                                 stutter_exit_watermark[1], bw_int_to_fixed(1000)));
3221                         } else {
3222                                 calcs_output->stutter_exit_wm_ns[3].b_mark =
3223                                         bw_fixed_to_int(bw_mul(data->
3224                                                 stutter_exit_watermark[7], bw_int_to_fixed(1000)));
3225                                 calcs_output->stutter_exit_wm_ns[4].b_mark =
3226                                         bw_fixed_to_int(bw_mul(data->
3227                                                 stutter_exit_watermark[8], bw_int_to_fixed(1000)));
3228                         }
3229                         calcs_output->stutter_exit_wm_ns[5].b_mark =
3230                                 bw_fixed_to_int(bw_mul(data->
3231                                         stutter_exit_watermark[9], bw_int_to_fixed(1000)));
3232
3233                 calcs_output->stutter_entry_wm_ns[0].b_mark =
3234                         bw_fixed_to_int(bw_mul(data->
3235                                 stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3236                 calcs_output->stutter_entry_wm_ns[1].b_mark =
3237                         bw_fixed_to_int(bw_mul(data->
3238                                 stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3239                 calcs_output->stutter_entry_wm_ns[2].b_mark =
3240                         bw_fixed_to_int(bw_mul(data->
3241                                 stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3242                 if (ctx->dc->caps.max_slave_planes) {
3243                         calcs_output->stutter_entry_wm_ns[3].b_mark =
3244                                 bw_fixed_to_int(bw_mul(data->
3245                                         stutter_entry_watermark[0], bw_int_to_fixed(1000)));
3246                         calcs_output->stutter_entry_wm_ns[4].b_mark =
3247                                 bw_fixed_to_int(bw_mul(data->
3248                                         stutter_entry_watermark[1], bw_int_to_fixed(1000)));
3249                 } else {
3250                         calcs_output->stutter_entry_wm_ns[3].b_mark =
3251                                 bw_fixed_to_int(bw_mul(data->
3252                                         stutter_entry_watermark[7], bw_int_to_fixed(1000)));
3253                         calcs_output->stutter_entry_wm_ns[4].b_mark =
3254                                 bw_fixed_to_int(bw_mul(data->
3255                                         stutter_entry_watermark[8], bw_int_to_fixed(1000)));
3256                 }
3257                 calcs_output->stutter_entry_wm_ns[5].b_mark =
3258                         bw_fixed_to_int(bw_mul(data->
3259                                 stutter_entry_watermark[9], bw_int_to_fixed(1000)));
3260
3261                         calcs_output->urgent_wm_ns[0].b_mark =
3262                                 bw_fixed_to_int(bw_mul(data->
3263                                         urgent_watermark[4], bw_int_to_fixed(1000)));
3264                         calcs_output->urgent_wm_ns[1].b_mark =
3265                                 bw_fixed_to_int(bw_mul(data->
3266                                         urgent_watermark[5], bw_int_to_fixed(1000)));
3267                         calcs_output->urgent_wm_ns[2].b_mark =
3268                                 bw_fixed_to_int(bw_mul(data->
3269                                         urgent_watermark[6], bw_int_to_fixed(1000)));
3270                         if (ctx->dc->caps.max_slave_planes) {
3271                                 calcs_output->urgent_wm_ns[3].b_mark =
3272                                         bw_fixed_to_int(bw_mul(data->
3273                                                 urgent_watermark[0], bw_int_to_fixed(1000)));
3274                                 calcs_output->urgent_wm_ns[4].b_mark =
3275                                         bw_fixed_to_int(bw_mul(data->
3276                                                 urgent_watermark[1], bw_int_to_fixed(1000)));
3277                         } else {
3278                                 calcs_output->urgent_wm_ns[3].b_mark =
3279                                         bw_fixed_to_int(bw_mul(data->
3280                                                 urgent_watermark[7], bw_int_to_fixed(1000)));
3281                                 calcs_output->urgent_wm_ns[4].b_mark =
3282                                         bw_fixed_to_int(bw_mul(data->
3283                                                 urgent_watermark[8], bw_int_to_fixed(1000)));
3284                         }
3285                         calcs_output->urgent_wm_ns[5].b_mark =
3286                                 bw_fixed_to_int(bw_mul(data->
3287                                         urgent_watermark[9], bw_int_to_fixed(1000)));
3288
3289                         ((struct bw_calcs_vbios *)vbios)->low_sclk = low_sclk;
3290                         ((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid1_sclk;
3291                         ((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid2_sclk;
3292                         ((struct bw_calcs_vbios *)vbios)->low_yclk = mid_yclk;
3293                         calculate_bandwidth(dceip, vbios, data);
3294
3295                         calcs_output->nbp_state_change_wm_ns[0].c_mark =
3296                                 bw_fixed_to_int(bw_mul(data->
3297                                         nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
3298                         calcs_output->nbp_state_change_wm_ns[1].c_mark =
3299                                 bw_fixed_to_int(bw_mul(data->
3300                                         nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
3301                         calcs_output->nbp_state_change_wm_ns[2].c_mark =
3302                                 bw_fixed_to_int(bw_mul(data->
3303                                         nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
3304                         if (ctx->dc->caps.max_slave_planes) {
3305                                 calcs_output->nbp_state_change_wm_ns[3].c_mark =
3306                                         bw_fixed_to_int(bw_mul(data->
3307                                                 nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
3308                                 calcs_output->nbp_state_change_wm_ns[4].c_mark =
3309                                         bw_fixed_to_int(bw_mul(data->
3310                                                 nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
3311                         } else {
3312                                 calcs_output->nbp_state_change_wm_ns[3].c_mark =
3313                                         bw_fixed_to_int(bw_mul(data->
3314                                                 nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
3315                                 calcs_output->nbp_state_change_wm_ns[4].c_mark =
3316                                         bw_fixed_to_int(bw_mul(data->
3317                                                 nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
3318                         }
3319                         calcs_output->nbp_state_change_wm_ns[5].c_mark =
3320                                 bw_fixed_to_int(bw_mul(data->
3321                                         nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
3322
3323
3324                         calcs_output->stutter_exit_wm_ns[0].c_mark =
3325                                 bw_fixed_to_int(bw_mul(data->
3326                                         stutter_exit_watermark[4], bw_int_to_fixed(1000)));
3327                         calcs_output->stutter_exit_wm_ns[1].c_mark =
3328                                 bw_fixed_to_int(bw_mul(data->
3329                                         stutter_exit_watermark[5], bw_int_to_fixed(1000)));
3330                         calcs_output->stutter_exit_wm_ns[2].c_mark =
3331                                 bw_fixed_to_int(bw_mul(data->
3332                                         stutter_exit_watermark[6], bw_int_to_fixed(1000)));
3333                         if (ctx->dc->caps.max_slave_planes) {
3334                                 calcs_output->stutter_exit_wm_ns[3].c_mark =
3335                                         bw_fixed_to_int(bw_mul(data->
3336                                                 stutter_exit_watermark[0], bw_int_to_fixed(1000)));
3337                                 calcs_output->stutter_exit_wm_ns[4].c_mark =
3338                                         bw_fixed_to_int(bw_mul(data->
3339                                                 stutter_exit_watermark[1], bw_int_to_fixed(1000)));
3340                         } else {
3341                                 calcs_output->stutter_exit_wm_ns[3].c_mark =
3342                                         bw_fixed_to_int(bw_mul(data->
3343                                                 stutter_exit_watermark[7], bw_int_to_fixed(1000)));
3344                                 calcs_output->stutter_exit_wm_ns[4].c_mark =
3345                                         bw_fixed_to_int(bw_mul(data->
3346                                                 stutter_exit_watermark[8], bw_int_to_fixed(1000)));
3347                         }
3348                         calcs_output->stutter_exit_wm_ns[5].c_mark =
3349                                 bw_fixed_to_int(bw_mul(data->
3350                                         stutter_exit_watermark[9], bw_int_to_fixed(1000)));
3351
3352                 calcs_output->stutter_entry_wm_ns[0].c_mark =
3353                         bw_fixed_to_int(bw_mul(data->
3354                                 stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3355                 calcs_output->stutter_entry_wm_ns[1].c_mark =
3356                         bw_fixed_to_int(bw_mul(data->
3357                                 stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3358                 calcs_output->stutter_entry_wm_ns[2].c_mark =
3359                         bw_fixed_to_int(bw_mul(data->
3360                                 stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3361                 if (ctx->dc->caps.max_slave_planes) {
3362                         calcs_output->stutter_entry_wm_ns[3].c_mark =
3363                                 bw_fixed_to_int(bw_mul(data->
3364                                         stutter_entry_watermark[0], bw_int_to_fixed(1000)));
3365                         calcs_output->stutter_entry_wm_ns[4].c_mark =
3366                                 bw_fixed_to_int(bw_mul(data->
3367                                         stutter_entry_watermark[1], bw_int_to_fixed(1000)));
3368                 } else {
3369                         calcs_output->stutter_entry_wm_ns[3].c_mark =
3370                                 bw_fixed_to_int(bw_mul(data->
3371                                         stutter_entry_watermark[7], bw_int_to_fixed(1000)));
3372                         calcs_output->stutter_entry_wm_ns[4].c_mark =
3373                                 bw_fixed_to_int(bw_mul(data->
3374                                         stutter_entry_watermark[8], bw_int_to_fixed(1000)));
3375                 }
3376                 calcs_output->stutter_entry_wm_ns[5].c_mark =
3377                         bw_fixed_to_int(bw_mul(data->
3378                                 stutter_entry_watermark[9], bw_int_to_fixed(1000)));
3379
3380                         calcs_output->urgent_wm_ns[0].c_mark =
3381                                 bw_fixed_to_int(bw_mul(data->
3382                                         urgent_watermark[4], bw_int_to_fixed(1000)));
3383                         calcs_output->urgent_wm_ns[1].c_mark =
3384                                 bw_fixed_to_int(bw_mul(data->
3385                                         urgent_watermark[5], bw_int_to_fixed(1000)));
3386                         calcs_output->urgent_wm_ns[2].c_mark =
3387                                 bw_fixed_to_int(bw_mul(data->
3388                                         urgent_watermark[6], bw_int_to_fixed(1000)));
3389                         if (ctx->dc->caps.max_slave_planes) {
3390                                 calcs_output->urgent_wm_ns[3].c_mark =
3391                                         bw_fixed_to_int(bw_mul(data->
3392                                                 urgent_watermark[0], bw_int_to_fixed(1000)));
3393                                 calcs_output->urgent_wm_ns[4].c_mark =
3394                                         bw_fixed_to_int(bw_mul(data->
3395                                                 urgent_watermark[1], bw_int_to_fixed(1000)));
3396                         } else {
3397                                 calcs_output->urgent_wm_ns[3].c_mark =
3398                                         bw_fixed_to_int(bw_mul(data->
3399                                                 urgent_watermark[7], bw_int_to_fixed(1000)));
3400                                 calcs_output->urgent_wm_ns[4].c_mark =
3401                                         bw_fixed_to_int(bw_mul(data->
3402                                                 urgent_watermark[8], bw_int_to_fixed(1000)));
3403                         }
3404                         calcs_output->urgent_wm_ns[5].c_mark =
3405                                 bw_fixed_to_int(bw_mul(data->
3406                                         urgent_watermark[9], bw_int_to_fixed(1000)));
3407                 }
3408
3409                 if (dceip->version == BW_CALCS_VERSION_CARRIZO) {
3410                         ((struct bw_calcs_vbios *)vbios)->low_yclk = high_yclk;
3411                         ((struct bw_calcs_vbios *)vbios)->mid_yclk = high_yclk;
3412                         ((struct bw_calcs_vbios *)vbios)->low_sclk = high_sclk;
3413                         ((struct bw_calcs_vbios *)vbios)->mid1_sclk = high_sclk;
3414                         ((struct bw_calcs_vbios *)vbios)->mid2_sclk = high_sclk;
3415                         ((struct bw_calcs_vbios *)vbios)->mid3_sclk = high_sclk;
3416                         ((struct bw_calcs_vbios *)vbios)->mid4_sclk = high_sclk;
3417                         ((struct bw_calcs_vbios *)vbios)->mid5_sclk = high_sclk;
3418                         ((struct bw_calcs_vbios *)vbios)->mid6_sclk = high_sclk;
3419                 } else {
3420                         ((struct bw_calcs_vbios *)vbios)->low_yclk = mid_yclk;
3421                         ((struct bw_calcs_vbios *)vbios)->low_sclk = mid3_sclk;
3422                         ((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid3_sclk;
3423                         ((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid3_sclk;
3424                 }
3425
3426                 calculate_bandwidth(dceip, vbios, data);
3427
3428                 calcs_output->nbp_state_change_wm_ns[0].d_mark =
3429                         bw_fixed_to_int(bw_mul(data->
3430                                 nbp_state_change_watermark[4], bw_int_to_fixed(1000)));
3431                 calcs_output->nbp_state_change_wm_ns[1].d_mark =
3432                         bw_fixed_to_int(bw_mul(data->
3433                                 nbp_state_change_watermark[5], bw_int_to_fixed(1000)));
3434                 calcs_output->nbp_state_change_wm_ns[2].d_mark =
3435                         bw_fixed_to_int(bw_mul(data->
3436                                 nbp_state_change_watermark[6], bw_int_to_fixed(1000)));
3437                 if (ctx->dc->caps.max_slave_planes) {
3438                         calcs_output->nbp_state_change_wm_ns[3].d_mark =
3439                                 bw_fixed_to_int(bw_mul(data->
3440                                         nbp_state_change_watermark[0], bw_int_to_fixed(1000)));
3441                         calcs_output->nbp_state_change_wm_ns[4].d_mark =
3442                                 bw_fixed_to_int(bw_mul(data->
3443                                         nbp_state_change_watermark[1], bw_int_to_fixed(1000)));
3444                 } else {
3445                         calcs_output->nbp_state_change_wm_ns[3].d_mark =
3446                                 bw_fixed_to_int(bw_mul(data->
3447                                         nbp_state_change_watermark[7], bw_int_to_fixed(1000)));
3448                         calcs_output->nbp_state_change_wm_ns[4].d_mark =
3449                                 bw_fixed_to_int(bw_mul(data->
3450                                         nbp_state_change_watermark[8], bw_int_to_fixed(1000)));
3451                 }
3452                 calcs_output->nbp_state_change_wm_ns[5].d_mark =
3453                         bw_fixed_to_int(bw_mul(data->
3454                                 nbp_state_change_watermark[9], bw_int_to_fixed(1000)));
3455
3456                 calcs_output->stutter_exit_wm_ns[0].d_mark =
3457                         bw_fixed_to_int(bw_mul(data->
3458                                 stutter_exit_watermark[4], bw_int_to_fixed(1000)));
3459                 calcs_output->stutter_exit_wm_ns[1].d_mark =
3460                         bw_fixed_to_int(bw_mul(data->
3461                                 stutter_exit_watermark[5], bw_int_to_fixed(1000)));
3462                 calcs_output->stutter_exit_wm_ns[2].d_mark =
3463                         bw_fixed_to_int(bw_mul(data->
3464                                 stutter_exit_watermark[6], bw_int_to_fixed(1000)));
3465                 if (ctx->dc->caps.max_slave_planes) {
3466                         calcs_output->stutter_exit_wm_ns[3].d_mark =
3467                                 bw_fixed_to_int(bw_mul(data->
3468                                         stutter_exit_watermark[0], bw_int_to_fixed(1000)));
3469                         calcs_output->stutter_exit_wm_ns[4].d_mark =
3470                                 bw_fixed_to_int(bw_mul(data->
3471                                         stutter_exit_watermark[1], bw_int_to_fixed(1000)));
3472                 } else {
3473                         calcs_output->stutter_exit_wm_ns[3].d_mark =
3474                                 bw_fixed_to_int(bw_mul(data->
3475                                         stutter_exit_watermark[7], bw_int_to_fixed(1000)));
3476                         calcs_output->stutter_exit_wm_ns[4].d_mark =
3477                                 bw_fixed_to_int(bw_mul(data->
3478                                         stutter_exit_watermark[8], bw_int_to_fixed(1000)));
3479                 }
3480                 calcs_output->stutter_exit_wm_ns[5].d_mark =
3481                         bw_fixed_to_int(bw_mul(data->
3482                                 stutter_exit_watermark[9], bw_int_to_fixed(1000)));
3483
3484                 calcs_output->stutter_entry_wm_ns[0].d_mark =
3485                         bw_fixed_to_int(bw_mul(data->
3486                                 stutter_entry_watermark[4], bw_int_to_fixed(1000)));
3487                 calcs_output->stutter_entry_wm_ns[1].d_mark =
3488                         bw_fixed_to_int(bw_mul(data->
3489                                 stutter_entry_watermark[5], bw_int_to_fixed(1000)));
3490                 calcs_output->stutter_entry_wm_ns[2].d_mark =
3491                         bw_fixed_to_int(bw_mul(data->
3492                                 stutter_entry_watermark[6], bw_int_to_fixed(1000)));
3493                 if (ctx->dc->caps.max_slave_planes) {
3494                         calcs_output->stutter_entry_wm_ns[3].d_mark =
3495                                 bw_fixed_to_int(bw_mul(data->
3496                                         stutter_entry_watermark[0], bw_int_to_fixed(1000)));
3497                         calcs_output->stutter_entry_wm_ns[4].d_mark =
3498                                 bw_fixed_to_int(bw_mul(data->
3499                                         stutter_entry_watermark[1], bw_int_to_fixed(1000)));
3500                 } else {
3501                         calcs_output->stutter_entry_wm_ns[3].d_mark =
3502                                 bw_fixed_to_int(bw_mul(data->
3503                                         stutter_entry_watermark[7], bw_int_to_fixed(1000)));
3504                         calcs_output->stutter_entry_wm_ns[4].d_mark =
3505                                 bw_fixed_to_int(bw_mul(data->
3506                                         stutter_entry_watermark[8], bw_int_to_fixed(1000)));
3507                 }
3508                 calcs_output->stutter_entry_wm_ns[5].d_mark =
3509                         bw_fixed_to_int(bw_mul(data->
3510                                 stutter_entry_watermark[9], bw_int_to_fixed(1000)));
3511
3512                 calcs_output->urgent_wm_ns[0].d_mark =
3513                         bw_fixed_to_int(bw_mul(data->
3514                                 urgent_watermark[4], bw_int_to_fixed(1000)));
3515                 calcs_output->urgent_wm_ns[1].d_mark =
3516                         bw_fixed_to_int(bw_mul(data->
3517                                 urgent_watermark[5], bw_int_to_fixed(1000)));
3518                 calcs_output->urgent_wm_ns[2].d_mark =
3519                         bw_fixed_to_int(bw_mul(data->
3520                                 urgent_watermark[6], bw_int_to_fixed(1000)));
3521                 if (ctx->dc->caps.max_slave_planes) {
3522                         calcs_output->urgent_wm_ns[3].d_mark =
3523                                 bw_fixed_to_int(bw_mul(data->
3524                                         urgent_watermark[0], bw_int_to_fixed(1000)));
3525                         calcs_output->urgent_wm_ns[4].d_mark =
3526                                 bw_fixed_to_int(bw_mul(data->
3527                                         urgent_watermark[1], bw_int_to_fixed(1000)));
3528                 } else {
3529                         calcs_output->urgent_wm_ns[3].d_mark =
3530                                 bw_fixed_to_int(bw_mul(data->
3531                                         urgent_watermark[7], bw_int_to_fixed(1000)));
3532                         calcs_output->urgent_wm_ns[4].d_mark =
3533                                 bw_fixed_to_int(bw_mul(data->
3534                                         urgent_watermark[8], bw_int_to_fixed(1000)));
3535                 }
3536                 calcs_output->urgent_wm_ns[5].d_mark =
3537                         bw_fixed_to_int(bw_mul(data->
3538                                 urgent_watermark[9], bw_int_to_fixed(1000)));
3539
3540                 ((struct bw_calcs_vbios *)vbios)->low_yclk = low_yclk;
3541                 ((struct bw_calcs_vbios *)vbios)->mid_yclk = mid_yclk;
3542                 ((struct bw_calcs_vbios *)vbios)->low_sclk = low_sclk;
3543                 ((struct bw_calcs_vbios *)vbios)->mid1_sclk = mid1_sclk;
3544                 ((struct bw_calcs_vbios *)vbios)->mid2_sclk = mid2_sclk;
3545                 ((struct bw_calcs_vbios *)vbios)->mid3_sclk = mid3_sclk;
3546                 ((struct bw_calcs_vbios *)vbios)->mid4_sclk = mid4_sclk;
3547                 ((struct bw_calcs_vbios *)vbios)->mid5_sclk = mid5_sclk;
3548                 ((struct bw_calcs_vbios *)vbios)->mid6_sclk = mid6_sclk;
3549                 ((struct bw_calcs_vbios *)vbios)->high_sclk = high_sclk;
3550         } else {
3551                 calcs_output->nbp_state_change_enable = true;
3552                 calcs_output->cpuc_state_change_enable = true;
3553                 calcs_output->cpup_state_change_enable = true;
3554                 calcs_output->stutter_mode_enable = true;
3555                 calcs_output->dispclk_khz = 0;
3556                 calcs_output->sclk_khz = 0;
3557         }
3558
3559         kfree(data);
3560
3561         return is_display_configuration_supported(vbios, calcs_output);
3562 }