2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
28 #include "dm_services_types.h"
32 #include "amdgpu_dm.h"
33 #include "amdgpu_dm_irq.h"
35 /******************************************************************************
36 * Private declarations.
37 *****************************************************************************/
39 struct handler_common_data {
40 struct list_head list;
41 interrupt_handler handler;
44 /* DM which this handler belongs to */
45 struct amdgpu_display_manager *dm;
48 struct amdgpu_dm_irq_handler_data {
49 struct handler_common_data hcd;
50 /* DAL irq source which registered for this interrupt. */
51 enum dc_irq_source irq_source;
54 #define DM_IRQ_TABLE_LOCK(adev, flags) \
55 spin_lock_irqsave(&adev->dm.irq_handler_list_table_lock, flags)
57 #define DM_IRQ_TABLE_UNLOCK(adev, flags) \
58 spin_unlock_irqrestore(&adev->dm.irq_handler_list_table_lock, flags)
60 /******************************************************************************
62 *****************************************************************************/
64 static void init_handler_common_data(struct handler_common_data *hcd,
67 struct amdgpu_display_manager *dm)
70 hcd->handler_arg = args;
75 * dm_irq_work_func - Handle an IRQ outside of the interrupt handler proper.
79 static void dm_irq_work_func(struct work_struct *work)
81 struct list_head *entry;
82 struct irq_list_head *irq_list_head =
83 container_of(work, struct irq_list_head, work);
84 struct list_head *handler_list = &irq_list_head->head;
85 struct amdgpu_dm_irq_handler_data *handler_data;
87 list_for_each(entry, handler_list) {
91 struct amdgpu_dm_irq_handler_data,
94 DRM_DEBUG_KMS("DM_IRQ: work_func: for dal_src=%d\n",
95 handler_data->irq_source);
97 DRM_DEBUG_KMS("DM_IRQ: schedule_work: for dal_src=%d\n",
98 handler_data->irq_source);
100 handler_data->hcd.handler(handler_data->hcd.handler_arg);
103 /* Call a DAL subcomponent which registered for interrupt notification
104 * at INTERRUPT_LOW_IRQ_CONTEXT.
105 * (The most common use is HPD interrupt) */
109 * Remove a handler and return a pointer to hander list from which the
110 * handler was removed.
112 static struct list_head *remove_irq_handler(struct amdgpu_device *adev,
114 const struct dc_interrupt_params *int_params)
116 struct list_head *hnd_list;
117 struct list_head *entry, *tmp;
118 struct amdgpu_dm_irq_handler_data *handler;
119 unsigned long irq_table_flags;
120 bool handler_removed = false;
121 enum dc_irq_source irq_source;
123 DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
125 irq_source = int_params->irq_source;
127 switch (int_params->int_context) {
128 case INTERRUPT_HIGH_IRQ_CONTEXT:
129 hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
131 case INTERRUPT_LOW_IRQ_CONTEXT:
133 hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head;
137 list_for_each_safe(entry, tmp, hnd_list) {
139 handler = list_entry(entry, struct amdgpu_dm_irq_handler_data,
143 /* Found our handler. Remove it from the list. */
144 list_del(&handler->hcd.list);
145 handler_removed = true;
150 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
152 if (handler_removed == false) {
153 /* Not necessarily an error - caller may not
154 * know the context. */
161 "DM_IRQ: removed irq handler: %p for: dal_src=%d, irq context=%d\n",
162 ih, int_params->irq_source, int_params->int_context);
168 validate_irq_registration_params(struct dc_interrupt_params *int_params,
171 if (NULL == int_params || NULL == ih) {
172 DRM_ERROR("DM_IRQ: invalid input!\n");
176 if (int_params->int_context >= INTERRUPT_CONTEXT_NUMBER) {
177 DRM_ERROR("DM_IRQ: invalid context: %d!\n",
178 int_params->int_context);
182 if (!DAL_VALID_IRQ_SRC_NUM(int_params->irq_source)) {
183 DRM_ERROR("DM_IRQ: invalid irq_source: %d!\n",
184 int_params->irq_source);
191 static bool validate_irq_unregistration_params(enum dc_irq_source irq_source,
192 irq_handler_idx handler_idx)
194 if (DAL_INVALID_IRQ_HANDLER_IDX == handler_idx) {
195 DRM_ERROR("DM_IRQ: invalid handler_idx==NULL!\n");
199 if (!DAL_VALID_IRQ_SRC_NUM(irq_source)) {
200 DRM_ERROR("DM_IRQ: invalid irq_source:%d!\n", irq_source);
206 /******************************************************************************
209 * Note: caller is responsible for input validation.
210 *****************************************************************************/
212 void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
213 struct dc_interrupt_params *int_params,
217 struct list_head *hnd_list;
218 struct amdgpu_dm_irq_handler_data *handler_data;
219 unsigned long irq_table_flags;
220 enum dc_irq_source irq_source;
222 if (false == validate_irq_registration_params(int_params, ih))
223 return DAL_INVALID_IRQ_HANDLER_IDX;
225 handler_data = kzalloc(sizeof(*handler_data), GFP_KERNEL);
227 DRM_ERROR("DM_IRQ: failed to allocate irq handler!\n");
228 return DAL_INVALID_IRQ_HANDLER_IDX;
231 memset(handler_data, 0, sizeof(*handler_data));
233 init_handler_common_data(&handler_data->hcd, ih, handler_args,
236 irq_source = int_params->irq_source;
238 handler_data->irq_source = irq_source;
240 /* Lock the list, add the handler. */
241 DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
243 switch (int_params->int_context) {
244 case INTERRUPT_HIGH_IRQ_CONTEXT:
245 hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
247 case INTERRUPT_LOW_IRQ_CONTEXT:
249 hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source].head;
253 list_add_tail(&handler_data->hcd.list, hnd_list);
255 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
257 /* This pointer will be stored by code which requested interrupt
259 * The same pointer will be needed in order to unregister the
263 "DM_IRQ: added irq handler: %p for: dal_src=%d, irq context=%d\n",
266 int_params->int_context);
271 void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
272 enum dc_irq_source irq_source,
275 struct list_head *handler_list;
276 struct dc_interrupt_params int_params;
279 if (false == validate_irq_unregistration_params(irq_source, ih))
282 memset(&int_params, 0, sizeof(int_params));
284 int_params.irq_source = irq_source;
286 for (i = 0; i < INTERRUPT_CONTEXT_NUMBER; i++) {
288 int_params.int_context = i;
290 handler_list = remove_irq_handler(adev, ih, &int_params);
292 if (handler_list != NULL)
296 if (handler_list == NULL) {
297 /* If we got here, it means we searched all irq contexts
298 * for this irq source, but the handler was not found. */
300 "DM_IRQ: failed to find irq handler:%p for irq_source:%d!\n",
305 int amdgpu_dm_irq_init(struct amdgpu_device *adev)
308 struct irq_list_head *lh;
310 DRM_DEBUG_KMS("DM_IRQ\n");
312 spin_lock_init(&adev->dm.irq_handler_list_table_lock);
314 for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
315 /* low context handler list init */
316 lh = &adev->dm.irq_handler_list_low_tab[src];
317 INIT_LIST_HEAD(&lh->head);
318 INIT_WORK(&lh->work, dm_irq_work_func);
320 /* high context handler init */
321 INIT_LIST_HEAD(&adev->dm.irq_handler_list_high_tab[src]);
327 /* DM IRQ and timer resource release */
328 void amdgpu_dm_irq_fini(struct amdgpu_device *adev)
331 struct irq_list_head *lh;
332 unsigned long irq_table_flags;
333 DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n");
334 for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
335 DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
336 /* The handler was removed from the table,
337 * it means it is safe to flush all the 'work'
338 * (because no code can schedule a new one). */
339 lh = &adev->dm.irq_handler_list_low_tab[src];
340 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
341 flush_work(&lh->work);
345 int amdgpu_dm_irq_suspend(struct amdgpu_device *adev)
348 struct list_head *hnd_list_h;
349 struct list_head *hnd_list_l;
350 unsigned long irq_table_flags;
352 DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
354 DRM_DEBUG_KMS("DM_IRQ: suspend\n");
357 * Disable HW interrupt for HPD and HPDRX only since FLIP and VBLANK
358 * will be disabled from manage_dm_interrupts on disable CRTC.
360 for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
361 hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
362 hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
363 if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
364 dc_interrupt_set(adev->dm.dc, src, false);
366 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
367 flush_work(&adev->dm.irq_handler_list_low_tab[src].work);
369 DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
372 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
376 int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev)
379 struct list_head *hnd_list_h, *hnd_list_l;
380 unsigned long irq_table_flags;
382 DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
384 DRM_DEBUG_KMS("DM_IRQ: early resume\n");
386 /* re-enable short pulse interrupts HW interrupt */
387 for (src = DC_IRQ_SOURCE_HPD1RX; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
388 hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
389 hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
390 if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
391 dc_interrupt_set(adev->dm.dc, src, true);
394 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
399 int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev)
402 struct list_head *hnd_list_h, *hnd_list_l;
403 unsigned long irq_table_flags;
405 DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
407 DRM_DEBUG_KMS("DM_IRQ: resume\n");
410 * Renable HW interrupt for HPD and only since FLIP and VBLANK
411 * will be enabled from manage_dm_interrupts on enable CRTC.
413 for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6; src++) {
414 hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head;
415 hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
416 if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
417 dc_interrupt_set(adev->dm.dc, src, true);
420 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
425 * amdgpu_dm_irq_schedule_work - schedule all work items registered for the
428 static void amdgpu_dm_irq_schedule_work(struct amdgpu_device *adev,
429 enum dc_irq_source irq_source)
431 unsigned long irq_table_flags;
432 struct work_struct *work = NULL;
434 DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
436 if (!list_empty(&adev->dm.irq_handler_list_low_tab[irq_source].head))
437 work = &adev->dm.irq_handler_list_low_tab[irq_source].work;
439 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
442 if (!schedule_work(work))
443 DRM_INFO("amdgpu_dm_irq_schedule_work FAILED src %d\n",
449 /** amdgpu_dm_irq_immediate_work
450 * Callback high irq work immediately, don't send to work queue
452 static void amdgpu_dm_irq_immediate_work(struct amdgpu_device *adev,
453 enum dc_irq_source irq_source)
455 struct amdgpu_dm_irq_handler_data *handler_data;
456 struct list_head *entry;
457 unsigned long irq_table_flags;
459 DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
463 &adev->dm.irq_handler_list_high_tab[irq_source]) {
468 struct amdgpu_dm_irq_handler_data,
471 /* Call a subcomponent which registered for immediate
472 * interrupt notification */
473 handler_data->hcd.handler(handler_data->hcd.handler_arg);
476 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
480 * amdgpu_dm_irq_handler
482 * Generic IRQ handler, calls all registered high irq work immediately, and
483 * schedules work for low irq
485 static int amdgpu_dm_irq_handler(struct amdgpu_device *adev,
486 struct amdgpu_irq_src *source,
487 struct amdgpu_iv_entry *entry)
490 enum dc_irq_source src =
491 dc_interrupt_to_irq_source(
496 dc_interrupt_ack(adev->dm.dc, src);
498 /* Call high irq work immediately */
499 amdgpu_dm_irq_immediate_work(adev, src);
500 /*Schedule low_irq work */
501 amdgpu_dm_irq_schedule_work(adev, src);
506 static enum dc_irq_source amdgpu_dm_hpd_to_dal_irq_source(unsigned type)
510 return DC_IRQ_SOURCE_HPD1;
512 return DC_IRQ_SOURCE_HPD2;
514 return DC_IRQ_SOURCE_HPD3;
516 return DC_IRQ_SOURCE_HPD4;
518 return DC_IRQ_SOURCE_HPD5;
520 return DC_IRQ_SOURCE_HPD6;
522 return DC_IRQ_SOURCE_INVALID;
526 static int amdgpu_dm_set_hpd_irq_state(struct amdgpu_device *adev,
527 struct amdgpu_irq_src *source,
529 enum amdgpu_interrupt_state state)
531 enum dc_irq_source src = amdgpu_dm_hpd_to_dal_irq_source(type);
532 bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
534 dc_interrupt_set(adev->dm.dc, src, st);
538 static inline int dm_irq_state(struct amdgpu_device *adev,
539 struct amdgpu_irq_src *source,
541 enum amdgpu_interrupt_state state,
542 const enum irq_type dal_irq_type,
546 enum dc_irq_source irq_source;
548 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];
552 "%s: crtc is NULL at id :%d\n",
558 if (acrtc->otg_inst == -1)
561 irq_source = dal_irq_type + acrtc->otg_inst;
563 st = (state == AMDGPU_IRQ_STATE_ENABLE);
565 dc_interrupt_set(adev->dm.dc, irq_source, st);
569 static int amdgpu_dm_set_pflip_irq_state(struct amdgpu_device *adev,
570 struct amdgpu_irq_src *source,
572 enum amdgpu_interrupt_state state)
583 static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev,
584 struct amdgpu_irq_src *source,
586 enum amdgpu_interrupt_state state)
597 static const struct amdgpu_irq_src_funcs dm_crtc_irq_funcs = {
598 .set = amdgpu_dm_set_crtc_irq_state,
599 .process = amdgpu_dm_irq_handler,
602 static const struct amdgpu_irq_src_funcs dm_pageflip_irq_funcs = {
603 .set = amdgpu_dm_set_pflip_irq_state,
604 .process = amdgpu_dm_irq_handler,
607 static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = {
608 .set = amdgpu_dm_set_hpd_irq_state,
609 .process = amdgpu_dm_irq_handler,
612 void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
615 adev->crtc_irq.num_types = adev->mode_info.num_crtc;
616 adev->crtc_irq.funcs = &dm_crtc_irq_funcs;
618 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
619 adev->pageflip_irq.funcs = &dm_pageflip_irq_funcs;
621 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
622 adev->hpd_irq.funcs = &dm_hpd_irq_funcs;
626 * amdgpu_dm_hpd_init - hpd setup callback.
628 * @adev: amdgpu_device pointer
630 * Setup the hpd pins used by the card (evergreen+).
631 * Enable the pin, set the polarity, and enable the hpd interrupts.
633 void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
635 struct drm_device *dev = adev->ddev;
636 struct drm_connector *connector;
638 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
639 struct amdgpu_dm_connector *amdgpu_dm_connector =
640 to_amdgpu_dm_connector(connector);
642 const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
644 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
645 dc_interrupt_set(adev->dm.dc,
646 dc_link->irq_source_hpd,
650 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
651 dc_interrupt_set(adev->dm.dc,
652 dc_link->irq_source_hpd_rx,
659 * amdgpu_dm_hpd_fini - hpd tear down callback.
661 * @adev: amdgpu_device pointer
663 * Tear down the hpd pins used by the card (evergreen+).
664 * Disable the hpd interrupts.
666 void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)
668 struct drm_device *dev = adev->ddev;
669 struct drm_connector *connector;
671 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
672 struct amdgpu_dm_connector *amdgpu_dm_connector =
673 to_amdgpu_dm_connector(connector);
674 const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
676 dc_interrupt_set(adev->dm.dc, dc_link->irq_source_hpd, false);
678 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
679 dc_interrupt_set(adev->dm.dc,
680 dc_link->irq_source_hpd_rx,