2 * Copyright 2015 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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26 #ifndef __AMDGPU_DM_H__
27 #define __AMDGPU_DM_H__
30 #include <drm/drm_atomic.h>
33 * This file contains the definition for amdgpu_display_manager
34 * and its API for amdgpu driver's use.
35 * This component provides all the display related functionality
36 * and this is the only component that calls DAL API.
37 * The API contained here intended for amdgpu driver use.
38 * The API that is called directly from KMS framework is located
39 * in amdgpu_dm_kms.h file
42 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31
44 #include "include/amdgpu_dal_power_if.h"
45 #include "amdgpu_dm_irq.h"
48 #include "irq_types.h"
49 #include "signal_types.h"
51 /* Forward declarations */
54 struct amdgpu_dm_irq_handler_data;
57 struct amdgpu_dm_prev_state {
58 struct drm_framebuffer *fb;
61 struct drm_display_mode mode;
64 struct common_irq_params {
65 struct amdgpu_device *adev;
66 enum dc_irq_source irq_src;
69 struct irq_list_head {
70 struct list_head head;
71 /* In case this interrupt needs post-processing, 'work' will be queued*/
72 struct work_struct work;
75 struct dm_comressor_info {
77 struct amdgpu_bo *bo_ptr;
82 struct amdgpu_display_manager {
85 struct cgs_device *cgs_device;
87 struct amdgpu_device *adev; /*AMD base driver*/
88 struct drm_device *ddev; /*DRM base driver*/
89 u16 display_indexes_num;
91 struct amdgpu_dm_prev_state prev_state;
94 * 'irq_source_handler_table' holds a list of handlers
95 * per (DAL) IRQ source.
97 * Each IRQ source may need to be handled at different contexts.
98 * By 'context' we mean, for example:
99 * - The ISR context, which is the direct interrupt handler.
100 * - The 'deferred' context - this is the post-processing of the
101 * interrupt, but at a lower priority.
103 * Note that handlers are called in the same order as they were
106 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
107 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
109 struct common_irq_params
110 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
112 struct common_irq_params
113 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
115 /* this spin lock synchronizes access to 'irq_handler_list_table' */
116 spinlock_t irq_handler_list_table_lock;
118 struct backlight_device *backlight_dev;
120 const struct dc_link *backlight_link;
122 struct work_struct mst_hotplug_work;
124 struct mod_freesync *freesync_module;
127 * Caches device atomic state for suspend/resume
129 struct drm_atomic_state *cached_state;
131 struct dm_comressor_info compressor;
134 struct amdgpu_dm_connector {
136 struct drm_connector base;
137 uint32_t connector_id;
139 /* we need to mind the EDID between detect
140 and get modes due to analog/digital/tvencoder */
143 /* shared with amdgpu */
144 struct amdgpu_hpd hpd;
146 /* number of modes generated from EDID at 'dc_sink' */
149 /* The 'old' sink - before an HPD.
150 * The 'current' sink is in dc_link->sink. */
151 struct dc_sink *dc_sink;
152 struct dc_link *dc_link;
153 struct dc_sink *dc_em_sink;
156 struct drm_dp_mst_topology_mgr mst_mgr;
157 struct amdgpu_dm_dp_aux dm_dp_aux;
158 struct drm_dp_mst_port *port;
159 struct amdgpu_dm_connector *mst_port;
160 struct amdgpu_encoder *mst_encoder;
162 /* TODO see if we can merge with ddc_bus or make a dm_connector */
163 struct amdgpu_i2c_adapter *i2c;
165 /* Monitor range limits */
171 struct mod_freesync_caps caps;
173 struct mutex hpd_lock;
178 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
180 extern const struct amdgpu_ip_block_version dm_ip_block;
182 struct amdgpu_framebuffer;
183 struct amdgpu_display_manager;
184 struct dc_validation_set;
185 struct dc_plane_state;
187 struct dm_plane_state {
188 struct drm_plane_state base;
189 struct dc_plane_state *dc_state;
192 struct dm_crtc_state {
193 struct drm_crtc_state base;
194 struct dc_stream_state *stream;
200 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
202 struct dm_atomic_state {
203 struct drm_atomic_state base;
205 struct dc_state *context;
208 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
210 struct dm_connector_state {
211 struct drm_connector_state base;
213 enum amdgpu_rmx_type scaling;
214 uint8_t underscan_vborder;
215 uint8_t underscan_hborder;
217 bool underscan_enable;
218 struct mod_freesync_user_enable user_enable;
219 bool freesync_capable;
222 #define to_dm_connector_state(x)\
223 container_of((x), struct dm_connector_state, base)
225 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
226 struct drm_connector_state *
227 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
228 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
229 struct drm_connector_state *state,
230 struct drm_property *property,
233 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
234 const struct drm_connector_state *state,
235 struct drm_property *property,
238 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
240 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
241 struct amdgpu_dm_connector *aconnector,
243 struct dc_link *link,
246 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
247 struct drm_display_mode *mode);
249 void dm_restore_drm_connector_state(struct drm_device *dev,
250 struct drm_connector *connector);
252 void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
256 amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector);
258 /* amdgpu_dm_crc.c */
259 #ifdef CONFIG_DEBUG_FS
260 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name,
262 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
264 #define amdgpu_dm_crtc_set_crc_source NULL
265 #define amdgpu_dm_crtc_handle_crc_irq(x)
268 #define MAX_COLOR_LUT_ENTRIES 4096
269 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
270 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
272 void amdgpu_dm_init_color_mod(void);
273 int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state,
274 struct dc_plane_state *dc_plane_state);
275 void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc);
276 int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc);
278 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
280 #endif /* __AMDGPU_DM_H__ */