2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef KFD_PM4_HEADERS_H_
25 #define KFD_PM4_HEADERS_H_
27 #ifndef PM4_MES_HEADER_DEFINED
28 #define PM4_MES_HEADER_DEFINED
29 union PM4_MES_TYPE_3_HEADER {
31 uint32_t reserved1:8; /* < reserved */
32 uint32_t opcode:8; /* < IT opcode */
33 uint32_t count:14; /* < number of DWORDs - 1
34 * in the information body.
36 uint32_t type:2; /* < packet identifier.
37 * It should be 3 for type 3 packets
42 #endif /* PM4_MES_HEADER_DEFINED */
44 /* --------------------MES_SET_RESOURCES-------------------- */
46 #ifndef PM4_MES_SET_RESOURCES_DEFINED
47 #define PM4_MES_SET_RESOURCES_DEFINED
48 enum set_resources_queue_type_enum {
49 queue_type__mes_set_resources__kernel_interface_queue_kiq = 0,
50 queue_type__mes_set_resources__hsa_interface_queue_hiq = 1,
51 queue_type__mes_set_resources__hsa_debug_interface_queue = 4
54 struct pm4_set_resources {
56 union PM4_MES_TYPE_3_HEADER header; /* header */
62 uint32_t vmid_mask:16;
63 uint32_t unmap_latency:8;
65 enum set_resources_queue_type_enum queue_type:3;
70 uint32_t queue_mask_lo;
71 uint32_t queue_mask_hi;
78 uint32_t reserved2:16;
85 uint32_t gds_heap_base:6;
87 uint32_t gds_heap_size:6;
88 uint32_t reserved4:15;
96 /*--------------------MES_RUN_LIST-------------------- */
98 #ifndef PM4_MES_RUN_LIST_DEFINED
99 #define PM4_MES_RUN_LIST_DEFINED
103 union PM4_MES_TYPE_3_HEADER header; /* header */
109 uint32_t reserved1:2;
110 uint32_t ib_base_lo:30;
117 uint32_t ib_base_hi:16;
118 uint32_t reserved2:16;
127 uint32_t offload_polling:1;
128 uint32_t reserved3:1;
130 uint32_t reserved4:8;
138 /*--------------------MES_MAP_PROCESS-------------------- */
140 #ifndef PM4_MES_MAP_PROCESS_DEFINED
141 #define PM4_MES_MAP_PROCESS_DEFINED
143 struct pm4_map_process {
145 union PM4_MES_TYPE_3_HEADER header; /* header */
152 uint32_t reserved1:8;
153 uint32_t diq_enable:1;
154 uint32_t process_quantum:7;
161 uint32_t page_table_base:28;
162 uint32_t reserved3:4;
167 uint32_t sh_mem_bases;
168 uint32_t sh_mem_ape1_base;
169 uint32_t sh_mem_ape1_limit;
170 uint32_t sh_mem_config;
171 uint32_t gds_addr_lo;
172 uint32_t gds_addr_hi;
177 uint32_t reserved4:2;
179 uint32_t reserved5:4;
181 uint32_t num_queues:10;
189 /*--------------------MES_MAP_QUEUES--------------------*/
191 #ifndef PM4_MES_MAP_QUEUES_DEFINED
192 #define PM4_MES_MAP_QUEUES_DEFINED
193 enum map_queues_queue_sel_enum {
194 queue_sel__mes_map_queues__map_to_specified_queue_slots = 0,
195 queue_sel__mes_map_queues__map_to_hws_determined_queue_slots = 1,
196 queue_sel__mes_map_queues__enable_process_queues = 2
199 enum map_queues_vidmem_enum {
200 vidmem__mes_map_queues__uses_no_video_memory = 0,
201 vidmem__mes_map_queues__uses_video_memory = 1
204 enum map_queues_alloc_format_enum {
205 alloc_format__mes_map_queues__one_per_pipe = 0,
206 alloc_format__mes_map_queues__all_on_one_pipe = 1
209 enum map_queues_engine_sel_enum {
210 engine_sel__mes_map_queues__compute = 0,
211 engine_sel__mes_map_queues__sdma0 = 2,
212 engine_sel__mes_map_queues__sdma1 = 3
215 struct pm4_map_queues {
217 union PM4_MES_TYPE_3_HEADER header; /* header */
223 uint32_t reserved1:4;
224 enum map_queues_queue_sel_enum queue_sel:2;
225 uint32_t reserved2:2;
227 uint32_t reserved3:4;
228 enum map_queues_vidmem_enum vidmem:2;
229 uint32_t reserved4:6;
230 enum map_queues_alloc_format_enum alloc_format:2;
231 enum map_queues_engine_sel_enum engine_sel:3;
232 uint32_t num_queues:3;
240 uint32_t is_static:1;
241 uint32_t reserved5:1;
242 uint32_t doorbell_offset:21;
243 uint32_t reserved6:3;
249 uint32_t mqd_addr_lo;
250 uint32_t mqd_addr_hi;
251 uint32_t wptr_addr_lo;
252 uint32_t wptr_addr_hi;
254 } mes_map_queues_ordinals[1]; /* 1..N of these ordinal groups */
259 /*--------------------MES_QUERY_STATUS--------------------*/
261 #ifndef PM4_MES_QUERY_STATUS_DEFINED
262 #define PM4_MES_QUERY_STATUS_DEFINED
263 enum query_status_interrupt_sel_enum {
264 interrupt_sel__mes_query_status__completion_status = 0,
265 interrupt_sel__mes_query_status__process_status = 1,
266 interrupt_sel__mes_query_status__queue_status = 2
269 enum query_status_command_enum {
270 command__mes_query_status__interrupt_only = 0,
271 command__mes_query_status__fence_only_immediate = 1,
272 command__mes_query_status__fence_only_after_write_ack = 2,
273 command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3
276 enum query_status_engine_sel_enum {
277 engine_sel__mes_query_status__compute = 0,
278 engine_sel__mes_query_status__sdma0_queue = 2,
279 engine_sel__mes_query_status__sdma1_queue = 3
282 struct pm4_query_status {
284 union PM4_MES_TYPE_3_HEADER header; /* header */
290 uint32_t context_id:28;
291 enum query_status_interrupt_sel_enum interrupt_sel:2;
292 enum query_status_command_enum command:2;
300 uint32_t reserved1:16;
303 uint32_t reserved2:2;
304 uint32_t doorbell_offset:21;
305 uint32_t reserved3:3;
306 enum query_status_engine_sel_enum engine_sel:3;
307 uint32_t reserved4:3;
319 /*--------------------MES_UNMAP_QUEUES--------------------*/
321 #ifndef PM4_MES_UNMAP_QUEUES_DEFINED
322 #define PM4_MES_UNMAP_QUEUES_DEFINED
323 enum unmap_queues_action_enum {
324 action__mes_unmap_queues__preempt_queues = 0,
325 action__mes_unmap_queues__reset_queues = 1,
326 action__mes_unmap_queues__disable_process_queues = 2
329 enum unmap_queues_queue_sel_enum {
330 queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0,
331 queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1,
332 queue_sel__mes_unmap_queues__perform_request_on_all_active_queues = 2,
333 queue_sel__mes_unmap_queues__perform_request_on_dynamic_queues_only = 3
336 enum unmap_queues_engine_sel_enum {
337 engine_sel__mes_unmap_queues__compute = 0,
338 engine_sel__mes_unmap_queues__sdma0 = 2,
339 engine_sel__mes_unmap_queues__sdma1 = 3
342 struct pm4_unmap_queues {
344 union PM4_MES_TYPE_3_HEADER header; /* header */
350 enum unmap_queues_action_enum action:2;
351 uint32_t reserved1:2;
352 enum unmap_queues_queue_sel_enum queue_sel:2;
353 uint32_t reserved2:20;
354 enum unmap_queues_engine_sel_enum engine_sel:3;
355 uint32_t num_queues:3;
363 uint32_t reserved3:16;
366 uint32_t reserved4:2;
367 uint32_t doorbell_offset0:21;
368 uint32_t reserved5:9;
375 uint32_t reserved6:2;
376 uint32_t doorbell_offset1:21;
377 uint32_t reserved7:9;
384 uint32_t reserved8:2;
385 uint32_t doorbell_offset2:21;
386 uint32_t reserved9:9;
393 uint32_t reserved10:2;
394 uint32_t doorbell_offset3:21;
395 uint32_t reserved11:9;
404 CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014
407 #endif /* KFD_PM4_HEADERS_H_ */