2 * Copyright 2016-2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/printk.h>
25 #include <linux/slab.h>
26 #include <linux/uaccess.h>
28 #include "kfd_mqd_manager.h"
29 #include "v9_structs.h"
30 #include "gc/gc_9_0_offset.h"
31 #include "gc/gc_9_0_sh_mask.h"
32 #include "sdma0/sdma0_4_0_sh_mask.h"
34 static inline struct v9_mqd *get_mqd(void *mqd)
36 return (struct v9_mqd *)mqd;
39 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
41 return (struct v9_sdma_mqd *)mqd;
44 static void update_cu_mask(struct mqd_manager *mm, void *mqd,
45 struct queue_properties *q)
48 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
50 if (q->cu_mask_count == 0)
53 mqd_symmetrically_map_cu_mask(mm,
54 q->cu_mask, q->cu_mask_count, se_mask);
57 m->compute_static_thread_mgmt_se0 = se_mask[0];
58 m->compute_static_thread_mgmt_se1 = se_mask[1];
59 m->compute_static_thread_mgmt_se2 = se_mask[2];
60 m->compute_static_thread_mgmt_se3 = se_mask[3];
62 pr_debug("update cu mask to %#x %#x %#x %#x\n",
63 m->compute_static_thread_mgmt_se0,
64 m->compute_static_thread_mgmt_se1,
65 m->compute_static_thread_mgmt_se2,
66 m->compute_static_thread_mgmt_se3);
69 static int init_mqd(struct mqd_manager *mm, void **mqd,
70 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
71 struct queue_properties *q)
76 struct kfd_dev *kfd = mm->dev;
79 /* From V9, for CWSR, the control stack is located on the next page
80 * boundary after the mqd, we will use the gtt allocation function
81 * instead of sub-allocation function.
83 if (kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) {
84 *mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
87 retval = kfd->kfd2kgd->init_gtt_mem_allocation(kfd->kgd,
88 ALIGN(q->ctl_stack_size, PAGE_SIZE) +
89 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE),
90 &((*mqd_mem_obj)->gtt_mem),
91 &((*mqd_mem_obj)->gpu_addr),
92 (void *)&((*mqd_mem_obj)->cpu_ptr), true);
94 retval = kfd_gtt_sa_allocate(mm->dev, sizeof(struct v9_mqd),
101 m = (struct v9_mqd *) (*mqd_mem_obj)->cpu_ptr;
102 addr = (*mqd_mem_obj)->gpu_addr;
104 memset(m, 0, sizeof(struct v9_mqd));
106 m->header = 0xC0310800;
107 m->compute_pipelinestat_enable = 1;
108 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
109 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
110 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
111 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
113 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
114 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
116 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
118 m->cp_mqd_base_addr_lo = lower_32_bits(addr);
119 m->cp_mqd_base_addr_hi = upper_32_bits(addr);
121 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
122 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
123 10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
125 m->cp_hqd_pipe_priority = 1;
126 m->cp_hqd_queue_priority = 15;
128 if (q->format == KFD_QUEUE_FORMAT_AQL) {
129 m->cp_hqd_aql_control =
130 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
134 m->compute_pgm_rsrc2 |=
135 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT);
138 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) {
139 m->cp_hqd_persistent_state |=
140 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
141 m->cp_hqd_ctx_save_base_addr_lo =
142 lower_32_bits(q->ctx_save_restore_area_address);
143 m->cp_hqd_ctx_save_base_addr_hi =
144 upper_32_bits(q->ctx_save_restore_area_address);
145 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
146 m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
147 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
148 m->cp_hqd_wg_state_offset = q->ctl_stack_size;
154 retval = mm->update_mqd(mm, m, q);
159 static int load_mqd(struct mqd_manager *mm, void *mqd,
160 uint32_t pipe_id, uint32_t queue_id,
161 struct queue_properties *p, struct mm_struct *mms)
163 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
164 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
166 return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
167 (uint32_t __user *)p->write_ptr,
171 static int update_mqd(struct mqd_manager *mm, void *mqd,
172 struct queue_properties *q)
178 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
179 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
180 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
182 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
183 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
185 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
186 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
187 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
188 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
190 m->cp_hqd_pq_doorbell_control =
192 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
193 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
194 m->cp_hqd_pq_doorbell_control);
196 m->cp_hqd_ib_control =
197 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT |
198 1 << CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT;
201 * HW does not clamp this field correctly. Maximum EOP queue size
202 * is constrained by per-SE EOP done signal count, which is 8-bit.
203 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
204 * more than (EOP entry count - 1) so a queue size of 0x800 dwords
205 * is safe, giving a maximum field value of 0xA.
207 m->cp_hqd_eop_control = min(0xA,
208 order_base_2(q->eop_ring_buffer_size / 4) - 1);
209 m->cp_hqd_eop_base_addr_lo =
210 lower_32_bits(q->eop_ring_buffer_address >> 8);
211 m->cp_hqd_eop_base_addr_hi =
212 upper_32_bits(q->eop_ring_buffer_address >> 8);
214 m->cp_hqd_iq_timer = 0;
216 m->cp_hqd_vmid = q->vmid;
218 if (q->format == KFD_QUEUE_FORMAT_AQL) {
219 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
220 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT |
221 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT |
222 1 << CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT;
223 m->cp_hqd_pq_doorbell_control |= 1 <<
224 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT;
226 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address)
227 m->cp_hqd_ctx_save_control = 0;
229 update_cu_mask(mm, mqd, q);
231 q->is_active = (q->queue_size > 0 &&
232 q->queue_address != 0 &&
233 q->queue_percent > 0 &&
240 static int destroy_mqd(struct mqd_manager *mm, void *mqd,
241 enum kfd_preempt_type type,
242 unsigned int timeout, uint32_t pipe_id,
245 return mm->dev->kfd2kgd->hqd_destroy
246 (mm->dev->kgd, mqd, type, timeout,
250 static void uninit_mqd(struct mqd_manager *mm, void *mqd,
251 struct kfd_mem_obj *mqd_mem_obj)
253 struct kfd_dev *kfd = mm->dev;
255 if (mqd_mem_obj->gtt_mem) {
256 kfd->kfd2kgd->free_gtt_mem(kfd->kgd, mqd_mem_obj->gtt_mem);
259 kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
263 static bool is_occupied(struct mqd_manager *mm, void *mqd,
264 uint64_t queue_address, uint32_t pipe_id,
267 return mm->dev->kfd2kgd->hqd_is_occupied(
268 mm->dev->kgd, queue_address,
272 static int init_mqd_hiq(struct mqd_manager *mm, void **mqd,
273 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
274 struct queue_properties *q)
277 int retval = init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
284 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
285 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
290 static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
291 struct queue_properties *q)
294 int retval = update_mqd(mm, mqd, q);
299 /* TODO: what's the point? update_mqd already does this. */
301 m->cp_hqd_vmid = q->vmid;
305 static int init_mqd_sdma(struct mqd_manager *mm, void **mqd,
306 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
307 struct queue_properties *q)
310 struct v9_sdma_mqd *m;
313 retval = kfd_gtt_sa_allocate(mm->dev,
314 sizeof(struct v9_sdma_mqd),
320 m = (struct v9_sdma_mqd *) (*mqd_mem_obj)->cpu_ptr;
322 memset(m, 0, sizeof(struct v9_sdma_mqd));
326 *gart_addr = (*mqd_mem_obj)->gpu_addr;
328 retval = mm->update_mqd(mm, m, q);
333 static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd,
334 struct kfd_mem_obj *mqd_mem_obj)
336 kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
339 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
340 uint32_t pipe_id, uint32_t queue_id,
341 struct queue_properties *p, struct mm_struct *mms)
343 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
344 (uint32_t __user *)p->write_ptr,
348 #define SDMA_RLC_DUMMY_DEFAULT 0xf
350 static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
351 struct queue_properties *q)
353 struct v9_sdma_mqd *m;
355 m = get_sdma_mqd(mqd);
356 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
357 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
358 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
359 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
360 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
362 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
363 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
364 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
365 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
366 m->sdmax_rlcx_doorbell_offset =
367 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
369 m->sdma_engine_id = q->sdma_engine_id;
370 m->sdma_queue_id = q->sdma_queue_id;
371 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT;
373 q->is_active = (q->queue_size > 0 &&
374 q->queue_address != 0 &&
375 q->queue_percent > 0 &&
382 * * preempt type here is ignored because there is only one way
383 * * to preempt sdma queue
385 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
386 enum kfd_preempt_type type,
387 unsigned int timeout, uint32_t pipe_id,
390 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout);
393 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd,
394 uint64_t queue_address, uint32_t pipe_id,
397 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd);
400 #if defined(CONFIG_DEBUG_FS)
402 static int debugfs_show_mqd(struct seq_file *m, void *data)
404 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
405 data, sizeof(struct v9_mqd), false);
409 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
411 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
412 data, sizeof(struct v9_sdma_mqd), false);
418 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
421 struct mqd_manager *mqd;
423 if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
426 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
433 case KFD_MQD_TYPE_CP:
434 case KFD_MQD_TYPE_COMPUTE:
435 mqd->init_mqd = init_mqd;
436 mqd->uninit_mqd = uninit_mqd;
437 mqd->load_mqd = load_mqd;
438 mqd->update_mqd = update_mqd;
439 mqd->destroy_mqd = destroy_mqd;
440 mqd->is_occupied = is_occupied;
441 #if defined(CONFIG_DEBUG_FS)
442 mqd->debugfs_show_mqd = debugfs_show_mqd;
445 case KFD_MQD_TYPE_HIQ:
446 mqd->init_mqd = init_mqd_hiq;
447 mqd->uninit_mqd = uninit_mqd;
448 mqd->load_mqd = load_mqd;
449 mqd->update_mqd = update_mqd_hiq;
450 mqd->destroy_mqd = destroy_mqd;
451 mqd->is_occupied = is_occupied;
452 #if defined(CONFIG_DEBUG_FS)
453 mqd->debugfs_show_mqd = debugfs_show_mqd;
456 case KFD_MQD_TYPE_SDMA:
457 mqd->init_mqd = init_mqd_sdma;
458 mqd->uninit_mqd = uninit_mqd_sdma;
459 mqd->load_mqd = load_mqd_sdma;
460 mqd->update_mqd = update_mqd_sdma;
461 mqd->destroy_mqd = destroy_mqd_sdma;
462 mqd->is_occupied = is_occupied_sdma;
463 #if defined(CONFIG_DEBUG_FS)
464 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;