2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/slab.h>
26 #include "amdgpu_atombios.h"
27 #include "amdgpu_ih.h"
28 #include "amdgpu_uvd.h"
29 #include "amdgpu_vce.h"
30 #include "amdgpu_ucode.h"
34 #include "gmc/gmc_8_1_d.h"
35 #include "gmc/gmc_8_1_sh_mask.h"
37 #include "oss/oss_3_0_d.h"
38 #include "oss/oss_3_0_sh_mask.h"
40 #include "bif/bif_5_0_d.h"
41 #include "bif/bif_5_0_sh_mask.h"
43 #include "gca/gfx_8_0_d.h"
44 #include "gca/gfx_8_0_sh_mask.h"
46 #include "smu/smu_7_1_1_d.h"
47 #include "smu/smu_7_1_1_sh_mask.h"
49 #include "uvd/uvd_5_0_d.h"
50 #include "uvd/uvd_5_0_sh_mask.h"
52 #include "vce/vce_3_0_d.h"
53 #include "vce/vce_3_0_sh_mask.h"
55 #include "dce/dce_10_0_d.h"
56 #include "dce/dce_10_0_sh_mask.h"
64 #include "sdma_v2_4.h"
65 #include "sdma_v3_0.h"
66 #include "dce_v10_0.h"
67 #include "dce_v11_0.h"
68 #include "iceland_ih.h"
74 #include "amdgpu_powerplay.h"
75 #if defined(CONFIG_DRM_AMD_ACP)
76 #include "amdgpu_acp.h"
78 #include "dce_virtual.h"
82 * Indirect registers accessor
84 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
89 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
90 WREG32(mmPCIE_INDEX, reg);
91 (void)RREG32(mmPCIE_INDEX);
92 r = RREG32(mmPCIE_DATA);
93 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
97 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
101 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
102 WREG32(mmPCIE_INDEX, reg);
103 (void)RREG32(mmPCIE_INDEX);
104 WREG32(mmPCIE_DATA, v);
105 (void)RREG32(mmPCIE_DATA);
106 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
109 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
114 spin_lock_irqsave(&adev->smc_idx_lock, flags);
115 WREG32(mmSMC_IND_INDEX_11, (reg));
116 r = RREG32(mmSMC_IND_DATA_11);
117 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
121 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
125 spin_lock_irqsave(&adev->smc_idx_lock, flags);
126 WREG32(mmSMC_IND_INDEX_11, (reg));
127 WREG32(mmSMC_IND_DATA_11, (v));
128 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
132 #define mmMP0PUB_IND_INDEX 0x180
133 #define mmMP0PUB_IND_DATA 0x181
135 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
140 spin_lock_irqsave(&adev->smc_idx_lock, flags);
141 WREG32(mmMP0PUB_IND_INDEX, (reg));
142 r = RREG32(mmMP0PUB_IND_DATA);
143 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
147 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
151 spin_lock_irqsave(&adev->smc_idx_lock, flags);
152 WREG32(mmMP0PUB_IND_INDEX, (reg));
153 WREG32(mmMP0PUB_IND_DATA, (v));
154 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
157 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
162 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
163 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
164 r = RREG32(mmUVD_CTX_DATA);
165 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
169 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
173 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
174 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
175 WREG32(mmUVD_CTX_DATA, (v));
176 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
179 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
184 spin_lock_irqsave(&adev->didt_idx_lock, flags);
185 WREG32(mmDIDT_IND_INDEX, (reg));
186 r = RREG32(mmDIDT_IND_DATA);
187 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
191 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
195 spin_lock_irqsave(&adev->didt_idx_lock, flags);
196 WREG32(mmDIDT_IND_INDEX, (reg));
197 WREG32(mmDIDT_IND_DATA, (v));
198 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
201 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
206 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
207 WREG32(mmGC_CAC_IND_INDEX, (reg));
208 r = RREG32(mmGC_CAC_IND_DATA);
209 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
213 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
217 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
218 WREG32(mmGC_CAC_IND_INDEX, (reg));
219 WREG32(mmGC_CAC_IND_DATA, (v));
220 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
224 static const u32 tonga_mgcg_cgcg_init[] =
226 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
227 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
228 mmPCIE_DATA, 0x000f0000, 0x00000000,
229 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
230 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
231 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
232 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
235 static const u32 fiji_mgcg_cgcg_init[] =
237 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
238 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
239 mmPCIE_DATA, 0x000f0000, 0x00000000,
240 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
241 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
242 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
243 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
246 static const u32 iceland_mgcg_cgcg_init[] =
248 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
249 mmPCIE_DATA, 0x000f0000, 0x00000000,
250 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
251 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
252 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
255 static const u32 cz_mgcg_cgcg_init[] =
257 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
258 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
259 mmPCIE_DATA, 0x000f0000, 0x00000000,
260 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
261 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
264 static const u32 stoney_mgcg_cgcg_init[] =
266 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
267 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
268 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
271 static void vi_init_golden_registers(struct amdgpu_device *adev)
273 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
274 mutex_lock(&adev->grbm_idx_mutex);
276 if (amdgpu_sriov_vf(adev)) {
277 xgpu_vi_init_golden_registers(adev);
278 mutex_unlock(&adev->grbm_idx_mutex);
282 switch (adev->asic_type) {
284 amdgpu_program_register_sequence(adev,
285 iceland_mgcg_cgcg_init,
286 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
289 amdgpu_program_register_sequence(adev,
291 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
294 amdgpu_program_register_sequence(adev,
295 tonga_mgcg_cgcg_init,
296 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
299 amdgpu_program_register_sequence(adev,
301 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
304 amdgpu_program_register_sequence(adev,
305 stoney_mgcg_cgcg_init,
306 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
314 mutex_unlock(&adev->grbm_idx_mutex);
318 * vi_get_xclk - get the xclk
320 * @adev: amdgpu_device pointer
322 * Returns the reference clock used by the gfx engine
325 static u32 vi_get_xclk(struct amdgpu_device *adev)
327 u32 reference_clock = adev->clock.spll.reference_freq;
330 if (adev->flags & AMD_IS_APU)
331 return reference_clock;
333 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
334 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
337 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
338 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
339 return reference_clock / 4;
341 return reference_clock;
345 * vi_srbm_select - select specific register instances
347 * @adev: amdgpu_device pointer
348 * @me: selected ME (micro engine)
353 * Switches the currently active registers instances. Some
354 * registers are instanced per VMID, others are instanced per
355 * me/pipe/queue combination.
357 void vi_srbm_select(struct amdgpu_device *adev,
358 u32 me, u32 pipe, u32 queue, u32 vmid)
360 u32 srbm_gfx_cntl = 0;
361 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
362 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
363 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
364 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
365 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
368 static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
373 static bool vi_read_disabled_bios(struct amdgpu_device *adev)
376 u32 d1vga_control = 0;
377 u32 d2vga_control = 0;
378 u32 vga_render_control = 0;
382 bus_cntl = RREG32(mmBUS_CNTL);
383 if (adev->mode_info.num_crtc) {
384 d1vga_control = RREG32(mmD1VGA_CONTROL);
385 d2vga_control = RREG32(mmD2VGA_CONTROL);
386 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
388 rom_cntl = RREG32_SMC(ixROM_CNTL);
391 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
392 if (adev->mode_info.num_crtc) {
393 /* Disable VGA mode */
394 WREG32(mmD1VGA_CONTROL,
395 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
396 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
397 WREG32(mmD2VGA_CONTROL,
398 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
399 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
400 WREG32(mmVGA_RENDER_CONTROL,
401 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
403 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
405 r = amdgpu_read_bios(adev);
408 WREG32(mmBUS_CNTL, bus_cntl);
409 if (adev->mode_info.num_crtc) {
410 WREG32(mmD1VGA_CONTROL, d1vga_control);
411 WREG32(mmD2VGA_CONTROL, d2vga_control);
412 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
414 WREG32_SMC(ixROM_CNTL, rom_cntl);
418 static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
419 u8 *bios, u32 length_bytes)
427 if (length_bytes == 0)
429 /* APU vbios image is part of sbios image */
430 if (adev->flags & AMD_IS_APU)
433 dw_ptr = (u32 *)bios;
434 length_dw = ALIGN(length_bytes, 4) / 4;
435 /* take the smc lock since we are using the smc index */
436 spin_lock_irqsave(&adev->smc_idx_lock, flags);
437 /* set rom index to 0 */
438 WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);
439 WREG32(mmSMC_IND_DATA_11, 0);
440 /* set index to data for continous read */
441 WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);
442 for (i = 0; i < length_dw; i++)
443 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);
444 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
449 static void vi_detect_hw_virtualization(struct amdgpu_device *adev)
453 if (adev->asic_type == CHIP_TONGA ||
454 adev->asic_type == CHIP_FIJI) {
455 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
456 /* bit0: 0 means pf and 1 means vf */
457 /* bit31: 0 means disable IOV and 1 means enable */
459 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
461 if (reg & 0x80000000)
462 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
466 if (is_virtual_machine()) /* passthrough mode exclus sr-iov mode */
467 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
471 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
481 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
482 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
484 {mmCP_STALLED_STAT1},
485 {mmCP_STALLED_STAT2},
486 {mmCP_STALLED_STAT3},
487 {mmCP_CPF_BUSY_STAT},
488 {mmCP_CPF_STALLED_STAT1},
490 {mmCP_CPC_BUSY_STAT},
491 {mmCP_CPC_STALLED_STAT1},
527 {mmGB_MACROTILE_MODE0},
528 {mmGB_MACROTILE_MODE1},
529 {mmGB_MACROTILE_MODE2},
530 {mmGB_MACROTILE_MODE3},
531 {mmGB_MACROTILE_MODE4},
532 {mmGB_MACROTILE_MODE5},
533 {mmGB_MACROTILE_MODE6},
534 {mmGB_MACROTILE_MODE7},
535 {mmGB_MACROTILE_MODE8},
536 {mmGB_MACROTILE_MODE9},
537 {mmGB_MACROTILE_MODE10},
538 {mmGB_MACROTILE_MODE11},
539 {mmGB_MACROTILE_MODE12},
540 {mmGB_MACROTILE_MODE13},
541 {mmGB_MACROTILE_MODE14},
542 {mmGB_MACROTILE_MODE15},
543 {mmCC_RB_BACKEND_DISABLE, true},
544 {mmGC_USER_RB_BACKEND_DISABLE, true},
545 {mmGB_BACKEND_MAP, false},
546 {mmPA_SC_RASTER_CONFIG, true},
547 {mmPA_SC_RASTER_CONFIG_1, true},
550 static uint32_t vi_get_register_value(struct amdgpu_device *adev,
551 bool indexed, u32 se_num,
552 u32 sh_num, u32 reg_offset)
556 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
557 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
559 switch (reg_offset) {
560 case mmCC_RB_BACKEND_DISABLE:
561 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
562 case mmGC_USER_RB_BACKEND_DISABLE:
563 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
564 case mmPA_SC_RASTER_CONFIG:
565 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
566 case mmPA_SC_RASTER_CONFIG_1:
567 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
570 mutex_lock(&adev->grbm_idx_mutex);
571 if (se_num != 0xffffffff || sh_num != 0xffffffff)
572 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
574 val = RREG32(reg_offset);
576 if (se_num != 0xffffffff || sh_num != 0xffffffff)
577 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
578 mutex_unlock(&adev->grbm_idx_mutex);
583 switch (reg_offset) {
584 case mmGB_ADDR_CONFIG:
585 return adev->gfx.config.gb_addr_config;
586 case mmMC_ARB_RAMCFG:
587 return adev->gfx.config.mc_arb_ramcfg;
588 case mmGB_TILE_MODE0:
589 case mmGB_TILE_MODE1:
590 case mmGB_TILE_MODE2:
591 case mmGB_TILE_MODE3:
592 case mmGB_TILE_MODE4:
593 case mmGB_TILE_MODE5:
594 case mmGB_TILE_MODE6:
595 case mmGB_TILE_MODE7:
596 case mmGB_TILE_MODE8:
597 case mmGB_TILE_MODE9:
598 case mmGB_TILE_MODE10:
599 case mmGB_TILE_MODE11:
600 case mmGB_TILE_MODE12:
601 case mmGB_TILE_MODE13:
602 case mmGB_TILE_MODE14:
603 case mmGB_TILE_MODE15:
604 case mmGB_TILE_MODE16:
605 case mmGB_TILE_MODE17:
606 case mmGB_TILE_MODE18:
607 case mmGB_TILE_MODE19:
608 case mmGB_TILE_MODE20:
609 case mmGB_TILE_MODE21:
610 case mmGB_TILE_MODE22:
611 case mmGB_TILE_MODE23:
612 case mmGB_TILE_MODE24:
613 case mmGB_TILE_MODE25:
614 case mmGB_TILE_MODE26:
615 case mmGB_TILE_MODE27:
616 case mmGB_TILE_MODE28:
617 case mmGB_TILE_MODE29:
618 case mmGB_TILE_MODE30:
619 case mmGB_TILE_MODE31:
620 idx = (reg_offset - mmGB_TILE_MODE0);
621 return adev->gfx.config.tile_mode_array[idx];
622 case mmGB_MACROTILE_MODE0:
623 case mmGB_MACROTILE_MODE1:
624 case mmGB_MACROTILE_MODE2:
625 case mmGB_MACROTILE_MODE3:
626 case mmGB_MACROTILE_MODE4:
627 case mmGB_MACROTILE_MODE5:
628 case mmGB_MACROTILE_MODE6:
629 case mmGB_MACROTILE_MODE7:
630 case mmGB_MACROTILE_MODE8:
631 case mmGB_MACROTILE_MODE9:
632 case mmGB_MACROTILE_MODE10:
633 case mmGB_MACROTILE_MODE11:
634 case mmGB_MACROTILE_MODE12:
635 case mmGB_MACROTILE_MODE13:
636 case mmGB_MACROTILE_MODE14:
637 case mmGB_MACROTILE_MODE15:
638 idx = (reg_offset - mmGB_MACROTILE_MODE0);
639 return adev->gfx.config.macrotile_mode_array[idx];
641 return RREG32(reg_offset);
646 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
647 u32 sh_num, u32 reg_offset, u32 *value)
652 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
653 bool indexed = vi_allowed_read_registers[i].grbm_indexed;
655 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
658 *value = vi_get_register_value(adev, indexed, se_num, sh_num,
665 static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
669 dev_info(adev->dev, "GPU pci config reset\n");
672 pci_clear_master(adev->pdev);
674 amdgpu_pci_config_reset(adev);
678 /* wait for asic to come out of reset */
679 for (i = 0; i < adev->usec_timeout; i++) {
680 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
682 pci_set_master(adev->pdev);
683 adev->has_hw_reset = true;
692 * vi_asic_reset - soft reset GPU
694 * @adev: amdgpu_device pointer
696 * Look up which blocks are hung and attempt
698 * Returns 0 for success.
700 static int vi_asic_reset(struct amdgpu_device *adev)
704 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
706 r = vi_gpu_pci_config_reset(adev);
708 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
713 static u32 vi_get_config_memsize(struct amdgpu_device *adev)
715 return RREG32(mmCONFIG_MEMSIZE);
718 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
719 u32 cntl_reg, u32 status_reg)
722 struct atom_clock_dividers dividers;
725 r = amdgpu_atombios_get_clock_dividers(adev,
726 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
727 clock, false, ÷rs);
731 tmp = RREG32_SMC(cntl_reg);
733 if (adev->flags & AMD_IS_APU)
734 tmp &= ~CG_DCLK_CNTL__DCLK_DIVIDER_MASK;
736 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
737 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
738 tmp |= dividers.post_divider;
739 WREG32_SMC(cntl_reg, tmp);
741 for (i = 0; i < 100; i++) {
742 tmp = RREG32_SMC(status_reg);
743 if (adev->flags & AMD_IS_APU) {
747 if (tmp & CG_DCLK_STATUS__DCLK_STATUS_MASK)
757 #define ixGNB_CLK1_DFS_CNTL 0xD82200F0
758 #define ixGNB_CLK1_STATUS 0xD822010C
759 #define ixGNB_CLK2_DFS_CNTL 0xD8220110
760 #define ixGNB_CLK2_STATUS 0xD822012C
761 #define ixGNB_CLK3_DFS_CNTL 0xD8220130
762 #define ixGNB_CLK3_STATUS 0xD822014C
764 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
768 if (adev->flags & AMD_IS_APU) {
769 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
773 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
777 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
781 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
789 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
792 struct atom_clock_dividers dividers;
799 if (adev->flags & AMD_IS_APU) {
800 reg_ctrl = ixGNB_CLK3_DFS_CNTL;
801 reg_status = ixGNB_CLK3_STATUS;
802 status_mask = 0x00010000;
803 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
805 reg_ctrl = ixCG_ECLK_CNTL;
806 reg_status = ixCG_ECLK_STATUS;
807 status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK;
808 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK;
811 r = amdgpu_atombios_get_clock_dividers(adev,
812 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
813 ecclk, false, ÷rs);
817 for (i = 0; i < 100; i++) {
818 if (RREG32_SMC(reg_status) & status_mask)
826 tmp = RREG32_SMC(reg_ctrl);
828 tmp |= dividers.post_divider;
829 WREG32_SMC(reg_ctrl, tmp);
831 for (i = 0; i < 100; i++) {
832 if (RREG32_SMC(reg_status) & status_mask)
843 static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
845 if (pci_is_root_bus(adev->pdev->bus))
848 if (amdgpu_pcie_gen2 == 0)
851 if (adev->flags & AMD_IS_APU)
854 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
855 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
861 static void vi_program_aspm(struct amdgpu_device *adev)
864 if (amdgpu_aspm == 0)
870 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
875 /* not necessary on CZ */
876 if (adev->flags & AMD_IS_APU)
879 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
881 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
883 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
885 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
888 #define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
889 #define ATI_REV_ID_FUSE_MACRO__SHIFT 9
890 #define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
892 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
894 if (adev->flags & AMD_IS_APU)
895 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
896 >> ATI_REV_ID_FUSE_MACRO__SHIFT;
898 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
899 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
902 static const struct amdgpu_asic_funcs vi_asic_funcs =
904 .read_disabled_bios = &vi_read_disabled_bios,
905 .read_bios_from_rom = &vi_read_bios_from_rom,
906 .read_register = &vi_read_register,
907 .reset = &vi_asic_reset,
908 .set_vga_state = &vi_vga_set_state,
909 .get_xclk = &vi_get_xclk,
910 .set_uvd_clocks = &vi_set_uvd_clocks,
911 .set_vce_clocks = &vi_set_vce_clocks,
912 .get_config_memsize = &vi_get_config_memsize,
915 #define CZ_REV_BRISTOL(rev) \
916 ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6))
918 static int vi_common_early_init(void *handle)
920 bool smc_enabled = false;
921 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
923 if (adev->flags & AMD_IS_APU) {
924 adev->smc_rreg = &cz_smc_rreg;
925 adev->smc_wreg = &cz_smc_wreg;
927 adev->smc_rreg = &vi_smc_rreg;
928 adev->smc_wreg = &vi_smc_wreg;
930 adev->pcie_rreg = &vi_pcie_rreg;
931 adev->pcie_wreg = &vi_pcie_wreg;
932 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
933 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
934 adev->didt_rreg = &vi_didt_rreg;
935 adev->didt_wreg = &vi_didt_wreg;
936 adev->gc_cac_rreg = &vi_gc_cac_rreg;
937 adev->gc_cac_wreg = &vi_gc_cac_wreg;
939 adev->asic_funcs = &vi_asic_funcs;
941 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
942 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
945 adev->rev_id = vi_get_rev_id(adev);
946 adev->external_rev_id = 0xFF;
947 switch (adev->asic_type) {
951 adev->external_rev_id = 0x1;
954 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
955 AMD_CG_SUPPORT_GFX_MGLS |
956 AMD_CG_SUPPORT_GFX_RLC_LS |
957 AMD_CG_SUPPORT_GFX_CP_LS |
958 AMD_CG_SUPPORT_GFX_CGTS |
959 AMD_CG_SUPPORT_GFX_CGTS_LS |
960 AMD_CG_SUPPORT_GFX_CGCG |
961 AMD_CG_SUPPORT_GFX_CGLS |
962 AMD_CG_SUPPORT_SDMA_MGCG |
963 AMD_CG_SUPPORT_SDMA_LS |
964 AMD_CG_SUPPORT_BIF_LS |
965 AMD_CG_SUPPORT_HDP_MGCG |
966 AMD_CG_SUPPORT_HDP_LS |
967 AMD_CG_SUPPORT_ROM_MGCG |
968 AMD_CG_SUPPORT_MC_MGCG |
969 AMD_CG_SUPPORT_MC_LS |
970 AMD_CG_SUPPORT_UVD_MGCG;
972 adev->external_rev_id = adev->rev_id + 0x3c;
975 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
976 AMD_CG_SUPPORT_GFX_CGCG |
977 AMD_CG_SUPPORT_GFX_CGLS |
978 AMD_CG_SUPPORT_SDMA_MGCG |
979 AMD_CG_SUPPORT_SDMA_LS |
980 AMD_CG_SUPPORT_BIF_LS |
981 AMD_CG_SUPPORT_HDP_MGCG |
982 AMD_CG_SUPPORT_HDP_LS |
983 AMD_CG_SUPPORT_ROM_MGCG |
984 AMD_CG_SUPPORT_MC_MGCG |
985 AMD_CG_SUPPORT_MC_LS |
986 AMD_CG_SUPPORT_DRM_LS |
987 AMD_CG_SUPPORT_UVD_MGCG;
989 adev->external_rev_id = adev->rev_id + 0x14;
992 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
993 AMD_CG_SUPPORT_GFX_RLC_LS |
994 AMD_CG_SUPPORT_GFX_CP_LS |
995 AMD_CG_SUPPORT_GFX_CGCG |
996 AMD_CG_SUPPORT_GFX_CGLS |
997 AMD_CG_SUPPORT_GFX_3D_CGCG |
998 AMD_CG_SUPPORT_GFX_3D_CGLS |
999 AMD_CG_SUPPORT_SDMA_MGCG |
1000 AMD_CG_SUPPORT_SDMA_LS |
1001 AMD_CG_SUPPORT_BIF_MGCG |
1002 AMD_CG_SUPPORT_BIF_LS |
1003 AMD_CG_SUPPORT_HDP_MGCG |
1004 AMD_CG_SUPPORT_HDP_LS |
1005 AMD_CG_SUPPORT_ROM_MGCG |
1006 AMD_CG_SUPPORT_MC_MGCG |
1007 AMD_CG_SUPPORT_MC_LS |
1008 AMD_CG_SUPPORT_DRM_LS |
1009 AMD_CG_SUPPORT_UVD_MGCG |
1010 AMD_CG_SUPPORT_VCE_MGCG;
1012 adev->external_rev_id = adev->rev_id + 0x5A;
1014 case CHIP_POLARIS10:
1015 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1016 AMD_CG_SUPPORT_GFX_RLC_LS |
1017 AMD_CG_SUPPORT_GFX_CP_LS |
1018 AMD_CG_SUPPORT_GFX_CGCG |
1019 AMD_CG_SUPPORT_GFX_CGLS |
1020 AMD_CG_SUPPORT_GFX_3D_CGCG |
1021 AMD_CG_SUPPORT_GFX_3D_CGLS |
1022 AMD_CG_SUPPORT_SDMA_MGCG |
1023 AMD_CG_SUPPORT_SDMA_LS |
1024 AMD_CG_SUPPORT_BIF_MGCG |
1025 AMD_CG_SUPPORT_BIF_LS |
1026 AMD_CG_SUPPORT_HDP_MGCG |
1027 AMD_CG_SUPPORT_HDP_LS |
1028 AMD_CG_SUPPORT_ROM_MGCG |
1029 AMD_CG_SUPPORT_MC_MGCG |
1030 AMD_CG_SUPPORT_MC_LS |
1031 AMD_CG_SUPPORT_DRM_LS |
1032 AMD_CG_SUPPORT_UVD_MGCG |
1033 AMD_CG_SUPPORT_VCE_MGCG;
1035 adev->external_rev_id = adev->rev_id + 0x50;
1037 case CHIP_POLARIS12:
1038 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1039 AMD_CG_SUPPORT_GFX_RLC_LS |
1040 AMD_CG_SUPPORT_GFX_CP_LS |
1041 AMD_CG_SUPPORT_GFX_CGCG |
1042 AMD_CG_SUPPORT_GFX_CGLS |
1043 AMD_CG_SUPPORT_GFX_3D_CGCG |
1044 AMD_CG_SUPPORT_GFX_3D_CGLS |
1045 AMD_CG_SUPPORT_SDMA_MGCG |
1046 AMD_CG_SUPPORT_SDMA_LS |
1047 AMD_CG_SUPPORT_BIF_MGCG |
1048 AMD_CG_SUPPORT_BIF_LS |
1049 AMD_CG_SUPPORT_HDP_MGCG |
1050 AMD_CG_SUPPORT_HDP_LS |
1051 AMD_CG_SUPPORT_ROM_MGCG |
1052 AMD_CG_SUPPORT_MC_MGCG |
1053 AMD_CG_SUPPORT_MC_LS |
1054 AMD_CG_SUPPORT_DRM_LS |
1055 AMD_CG_SUPPORT_UVD_MGCG |
1056 AMD_CG_SUPPORT_VCE_MGCG;
1058 adev->external_rev_id = adev->rev_id + 0x64;
1061 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1062 AMD_CG_SUPPORT_GFX_MGCG |
1063 AMD_CG_SUPPORT_GFX_MGLS |
1064 AMD_CG_SUPPORT_GFX_RLC_LS |
1065 AMD_CG_SUPPORT_GFX_CP_LS |
1066 AMD_CG_SUPPORT_GFX_CGTS |
1067 AMD_CG_SUPPORT_GFX_CGTS_LS |
1068 AMD_CG_SUPPORT_GFX_CGCG |
1069 AMD_CG_SUPPORT_GFX_CGLS |
1070 AMD_CG_SUPPORT_BIF_LS |
1071 AMD_CG_SUPPORT_HDP_MGCG |
1072 AMD_CG_SUPPORT_HDP_LS |
1073 AMD_CG_SUPPORT_SDMA_MGCG |
1074 AMD_CG_SUPPORT_SDMA_LS |
1075 AMD_CG_SUPPORT_VCE_MGCG;
1076 /* rev0 hardware requires workarounds to support PG */
1078 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) {
1079 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG |
1080 AMD_PG_SUPPORT_GFX_PIPELINE |
1082 AMD_PG_SUPPORT_UVD |
1085 adev->external_rev_id = adev->rev_id + 0x1;
1088 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1089 AMD_CG_SUPPORT_GFX_MGCG |
1090 AMD_CG_SUPPORT_GFX_MGLS |
1091 AMD_CG_SUPPORT_GFX_RLC_LS |
1092 AMD_CG_SUPPORT_GFX_CP_LS |
1093 AMD_CG_SUPPORT_GFX_CGTS |
1094 AMD_CG_SUPPORT_GFX_CGTS_LS |
1095 AMD_CG_SUPPORT_GFX_CGCG |
1096 AMD_CG_SUPPORT_GFX_CGLS |
1097 AMD_CG_SUPPORT_BIF_LS |
1098 AMD_CG_SUPPORT_HDP_MGCG |
1099 AMD_CG_SUPPORT_HDP_LS |
1100 AMD_CG_SUPPORT_SDMA_MGCG |
1101 AMD_CG_SUPPORT_SDMA_LS |
1102 AMD_CG_SUPPORT_VCE_MGCG;
1103 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1104 AMD_PG_SUPPORT_GFX_SMG |
1105 AMD_PG_SUPPORT_GFX_PIPELINE |
1107 AMD_PG_SUPPORT_UVD |
1109 adev->external_rev_id = adev->rev_id + 0x61;
1112 /* FIXME: not supported yet */
1116 if (amdgpu_sriov_vf(adev)) {
1117 amdgpu_virt_init_setting(adev);
1118 xgpu_vi_mailbox_set_irq_funcs(adev);
1121 /* vi use smc load by default */
1122 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
1124 amdgpu_get_pcie_info(adev);
1129 static int vi_common_late_init(void *handle)
1131 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1133 if (amdgpu_sriov_vf(adev))
1134 xgpu_vi_mailbox_get_irq(adev);
1139 static int vi_common_sw_init(void *handle)
1141 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1143 if (amdgpu_sriov_vf(adev))
1144 xgpu_vi_mailbox_add_irq_id(adev);
1149 static int vi_common_sw_fini(void *handle)
1154 static int vi_common_hw_init(void *handle)
1156 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1158 /* move the golden regs per IP block */
1159 vi_init_golden_registers(adev);
1160 /* enable pcie gen2/3 link */
1161 vi_pcie_gen3_enable(adev);
1163 vi_program_aspm(adev);
1164 /* enable the doorbell aperture */
1165 vi_enable_doorbell_aperture(adev, true);
1170 static int vi_common_hw_fini(void *handle)
1172 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1174 /* enable the doorbell aperture */
1175 vi_enable_doorbell_aperture(adev, false);
1177 if (amdgpu_sriov_vf(adev))
1178 xgpu_vi_mailbox_put_irq(adev);
1183 static int vi_common_suspend(void *handle)
1185 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1187 return vi_common_hw_fini(adev);
1190 static int vi_common_resume(void *handle)
1192 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1194 return vi_common_hw_init(adev);
1197 static bool vi_common_is_idle(void *handle)
1202 static int vi_common_wait_for_idle(void *handle)
1207 static int vi_common_soft_reset(void *handle)
1212 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1215 uint32_t temp, data;
1217 temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1219 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
1220 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1221 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1222 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1224 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1225 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1226 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1229 WREG32_PCIE(ixPCIE_CNTL2, data);
1232 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1235 uint32_t temp, data;
1237 temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1239 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1240 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1242 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1245 WREG32(mmHDP_HOST_PATH_CNTL, data);
1248 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1251 uint32_t temp, data;
1253 temp = data = RREG32(mmHDP_MEM_POWER_LS);
1255 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1256 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1258 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1261 WREG32(mmHDP_MEM_POWER_LS, data);
1264 static void vi_update_drm_light_sleep(struct amdgpu_device *adev,
1267 uint32_t temp, data;
1269 temp = data = RREG32(0x157a);
1271 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1277 WREG32(0x157a, data);
1281 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1284 uint32_t temp, data;
1286 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1288 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1289 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1290 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1292 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1293 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1296 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1299 static int vi_common_set_clockgating_state_by_smu(void *handle,
1300 enum amd_clockgating_state state)
1302 uint32_t msg_id, pp_state = 0;
1303 uint32_t pp_support_state = 0;
1304 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1305 void *pp_handle = adev->powerplay.pp_handle;
1307 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1308 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
1309 pp_support_state = AMD_CG_SUPPORT_MC_LS;
1310 pp_state = PP_STATE_LS;
1312 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
1313 pp_support_state |= AMD_CG_SUPPORT_MC_MGCG;
1314 pp_state |= PP_STATE_CG;
1316 if (state == AMD_CG_STATE_UNGATE)
1318 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1322 amd_set_clockgating_by_smu(pp_handle, msg_id);
1325 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1326 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
1327 pp_support_state = AMD_CG_SUPPORT_SDMA_LS;
1328 pp_state = PP_STATE_LS;
1330 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
1331 pp_support_state |= AMD_CG_SUPPORT_SDMA_MGCG;
1332 pp_state |= PP_STATE_CG;
1334 if (state == AMD_CG_STATE_UNGATE)
1336 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1340 amd_set_clockgating_by_smu(pp_handle, msg_id);
1343 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1344 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
1345 pp_support_state = AMD_CG_SUPPORT_HDP_LS;
1346 pp_state = PP_STATE_LS;
1348 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
1349 pp_support_state |= AMD_CG_SUPPORT_HDP_MGCG;
1350 pp_state |= PP_STATE_CG;
1352 if (state == AMD_CG_STATE_UNGATE)
1354 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1358 amd_set_clockgating_by_smu(pp_handle, msg_id);
1362 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
1363 if (state == AMD_CG_STATE_UNGATE)
1366 pp_state = PP_STATE_LS;
1368 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1370 PP_STATE_SUPPORT_LS,
1372 amd_set_clockgating_by_smu(pp_handle, msg_id);
1374 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
1375 if (state == AMD_CG_STATE_UNGATE)
1378 pp_state = PP_STATE_CG;
1380 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1382 PP_STATE_SUPPORT_CG,
1384 amd_set_clockgating_by_smu(pp_handle, msg_id);
1387 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
1389 if (state == AMD_CG_STATE_UNGATE)
1392 pp_state = PP_STATE_LS;
1394 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1396 PP_STATE_SUPPORT_LS,
1398 amd_set_clockgating_by_smu(pp_handle, msg_id);
1401 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
1403 if (state == AMD_CG_STATE_UNGATE)
1406 pp_state = PP_STATE_CG;
1408 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1410 PP_STATE_SUPPORT_CG,
1412 amd_set_clockgating_by_smu(pp_handle, msg_id);
1417 static int vi_common_set_clockgating_state(void *handle,
1418 enum amd_clockgating_state state)
1420 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1422 if (amdgpu_sriov_vf(adev))
1425 switch (adev->asic_type) {
1427 vi_update_bif_medium_grain_light_sleep(adev,
1428 state == AMD_CG_STATE_GATE);
1429 vi_update_hdp_medium_grain_clock_gating(adev,
1430 state == AMD_CG_STATE_GATE);
1431 vi_update_hdp_light_sleep(adev,
1432 state == AMD_CG_STATE_GATE);
1433 vi_update_rom_medium_grain_clock_gating(adev,
1434 state == AMD_CG_STATE_GATE);
1438 vi_update_bif_medium_grain_light_sleep(adev,
1439 state == AMD_CG_STATE_GATE);
1440 vi_update_hdp_medium_grain_clock_gating(adev,
1441 state == AMD_CG_STATE_GATE);
1442 vi_update_hdp_light_sleep(adev,
1443 state == AMD_CG_STATE_GATE);
1444 vi_update_drm_light_sleep(adev,
1445 state == AMD_CG_STATE_GATE);
1448 case CHIP_POLARIS10:
1449 case CHIP_POLARIS11:
1450 case CHIP_POLARIS12:
1451 vi_common_set_clockgating_state_by_smu(adev, state);
1458 static int vi_common_set_powergating_state(void *handle,
1459 enum amd_powergating_state state)
1464 static void vi_common_get_clockgating_state(void *handle, u32 *flags)
1466 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1469 if (amdgpu_sriov_vf(adev))
1472 /* AMD_CG_SUPPORT_BIF_LS */
1473 data = RREG32_PCIE(ixPCIE_CNTL2);
1474 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
1475 *flags |= AMD_CG_SUPPORT_BIF_LS;
1477 /* AMD_CG_SUPPORT_HDP_LS */
1478 data = RREG32(mmHDP_MEM_POWER_LS);
1479 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1480 *flags |= AMD_CG_SUPPORT_HDP_LS;
1482 /* AMD_CG_SUPPORT_HDP_MGCG */
1483 data = RREG32(mmHDP_HOST_PATH_CNTL);
1484 if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK))
1485 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
1487 /* AMD_CG_SUPPORT_ROM_MGCG */
1488 data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1489 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1490 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1493 static const struct amd_ip_funcs vi_common_ip_funcs = {
1494 .name = "vi_common",
1495 .early_init = vi_common_early_init,
1496 .late_init = vi_common_late_init,
1497 .sw_init = vi_common_sw_init,
1498 .sw_fini = vi_common_sw_fini,
1499 .hw_init = vi_common_hw_init,
1500 .hw_fini = vi_common_hw_fini,
1501 .suspend = vi_common_suspend,
1502 .resume = vi_common_resume,
1503 .is_idle = vi_common_is_idle,
1504 .wait_for_idle = vi_common_wait_for_idle,
1505 .soft_reset = vi_common_soft_reset,
1506 .set_clockgating_state = vi_common_set_clockgating_state,
1507 .set_powergating_state = vi_common_set_powergating_state,
1508 .get_clockgating_state = vi_common_get_clockgating_state,
1511 static const struct amdgpu_ip_block_version vi_common_ip_block =
1513 .type = AMD_IP_BLOCK_TYPE_COMMON,
1517 .funcs = &vi_common_ip_funcs,
1520 int vi_set_ip_blocks(struct amdgpu_device *adev)
1522 /* in early init stage, vbios code won't work */
1523 vi_detect_hw_virtualization(adev);
1525 if (amdgpu_sriov_vf(adev))
1526 adev->virt.ops = &xgpu_vi_virt_ops;
1528 switch (adev->asic_type) {
1530 /* topaz has no DCE, UVD, VCE */
1531 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1532 amdgpu_ip_block_add(adev, &gmc_v7_4_ip_block);
1533 amdgpu_ip_block_add(adev, &iceland_ih_ip_block);
1534 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1535 if (adev->enable_virtual_display)
1536 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1537 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1538 amdgpu_ip_block_add(adev, &sdma_v2_4_ip_block);
1541 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1542 amdgpu_ip_block_add(adev, &gmc_v8_5_ip_block);
1543 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1544 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1545 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1546 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1548 amdgpu_ip_block_add(adev, &dce_v10_1_ip_block);
1549 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1550 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1551 if (!amdgpu_sriov_vf(adev)) {
1552 amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block);
1553 amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
1557 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1558 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1559 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1560 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1561 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1562 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1564 amdgpu_ip_block_add(adev, &dce_v10_0_ip_block);
1565 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1566 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1567 if (!amdgpu_sriov_vf(adev)) {
1568 amdgpu_ip_block_add(adev, &uvd_v5_0_ip_block);
1569 amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
1572 case CHIP_POLARIS11:
1573 case CHIP_POLARIS10:
1574 case CHIP_POLARIS12:
1575 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1576 amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block);
1577 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1578 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1579 if (adev->enable_virtual_display)
1580 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1582 amdgpu_ip_block_add(adev, &dce_v11_2_ip_block);
1583 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1584 amdgpu_ip_block_add(adev, &sdma_v3_1_ip_block);
1585 amdgpu_ip_block_add(adev, &uvd_v6_3_ip_block);
1586 amdgpu_ip_block_add(adev, &vce_v3_4_ip_block);
1589 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1590 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1591 amdgpu_ip_block_add(adev, &cz_ih_ip_block);
1592 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1593 if (adev->enable_virtual_display)
1594 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1596 amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
1597 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1598 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1599 amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block);
1600 amdgpu_ip_block_add(adev, &vce_v3_1_ip_block);
1601 #if defined(CONFIG_DRM_AMD_ACP)
1602 amdgpu_ip_block_add(adev, &acp_ip_block);
1606 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1607 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1608 amdgpu_ip_block_add(adev, &cz_ih_ip_block);
1609 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1610 if (adev->enable_virtual_display)
1611 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1613 amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
1614 amdgpu_ip_block_add(adev, &gfx_v8_1_ip_block);
1615 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1616 amdgpu_ip_block_add(adev, &uvd_v6_2_ip_block);
1617 amdgpu_ip_block_add(adev, &vce_v3_4_ip_block);
1618 #if defined(CONFIG_DRM_AMD_ACP)
1619 amdgpu_ip_block_add(adev, &acp_ip_block);
1623 /* FIXME: not supported yet */