2 * Copyright 2014 Advanced Micro Devices, Inc.
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_ih.h"
28 #include "oss/oss_3_0_d.h"
29 #include "oss/oss_3_0_sh_mask.h"
31 #include "bif/bif_5_1_d.h"
32 #include "bif/bif_5_1_sh_mask.h"
36 * Starting with r6xx, interrupts are handled via a ring buffer.
37 * Ring buffers are areas of GPU accessible memory that the GPU
38 * writes interrupt vectors into and the host reads vectors out of.
39 * There is a rptr (read pointer) that determines where the
40 * host is currently reading, and a wptr (write pointer)
41 * which determines where the GPU has written. When the
42 * pointers are equal, the ring is idle. When the GPU
43 * writes vectors to the ring buffer, it increments the
44 * wptr. When there is an interrupt, the host then starts
45 * fetching commands and processing them until the pointers are
46 * equal again at which point it updates the rptr.
49 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev);
52 * tonga_ih_enable_interrupts - Enable the interrupt ring buffer
54 * @adev: amdgpu_device pointer
56 * Enable the interrupt ring buffer (VI).
58 static void tonga_ih_enable_interrupts(struct amdgpu_device *adev)
60 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
62 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
63 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
64 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
65 adev->irq.ih.enabled = true;
69 * tonga_ih_disable_interrupts - Disable the interrupt ring buffer
71 * @adev: amdgpu_device pointer
73 * Disable the interrupt ring buffer (VI).
75 static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)
77 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
79 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
80 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
81 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
82 /* set rptr, wptr to 0 */
83 WREG32(mmIH_RB_RPTR, 0);
84 WREG32(mmIH_RB_WPTR, 0);
85 adev->irq.ih.enabled = false;
86 adev->irq.ih.rptr = 0;
90 * tonga_ih_irq_init - init and enable the interrupt ring
92 * @adev: amdgpu_device pointer
94 * Allocate a ring buffer for the interrupt controller,
95 * enable the RLC, disable interrupts, enable the IH
96 * ring buffer and enable it (VI).
97 * Called at device load and reume.
98 * Returns 0 for success, errors for failure.
100 static int tonga_ih_irq_init(struct amdgpu_device *adev)
103 u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
107 tonga_ih_disable_interrupts(adev);
109 /* setup interrupt control */
110 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
111 interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
112 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
113 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
115 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
116 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
117 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
118 WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
120 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
121 if (adev->irq.ih.use_bus_addr)
122 WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);
124 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
126 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
127 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
128 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
129 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
133 if (adev->irq.msi_enabled)
134 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
136 WREG32(mmIH_RB_CNTL, ih_rb_cntl);
138 /* set the writeback address whether it's enabled or not */
139 if (adev->irq.ih.use_bus_addr)
140 wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);
142 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
143 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
144 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
146 /* set rptr, wptr to 0 */
147 WREG32(mmIH_RB_RPTR, 0);
148 WREG32(mmIH_RB_WPTR, 0);
150 ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);
151 if (adev->irq.ih.use_doorbell) {
152 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
153 OFFSET, adev->irq.ih.doorbell_index);
154 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
157 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
160 WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
162 pci_set_master(adev->pdev);
164 /* enable interrupts */
165 tonga_ih_enable_interrupts(adev);
171 * tonga_ih_irq_disable - disable interrupts
173 * @adev: amdgpu_device pointer
175 * Disable interrupts on the hw (VI).
177 static void tonga_ih_irq_disable(struct amdgpu_device *adev)
179 tonga_ih_disable_interrupts(adev);
181 /* Wait and acknowledge irq */
186 * tonga_ih_get_wptr - get the IH ring buffer wptr
188 * @adev: amdgpu_device pointer
190 * Get the IH ring buffer wptr from either the register
191 * or the writeback memory buffer (VI). Also check for
192 * ring buffer overflow and deal with it.
193 * Used by cz_irq_process(VI).
194 * Returns the value of the wptr.
196 static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
200 if (adev->irq.ih.use_bus_addr)
201 wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
203 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
205 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
206 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
207 /* When a ring buffer overflow happen start parsing interrupt
208 * from the last not overwritten vector (wptr + 16). Hopefully
209 * this should allow us to catchup.
211 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
212 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
213 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
214 tmp = RREG32(mmIH_RB_CNTL);
215 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
216 WREG32(mmIH_RB_CNTL, tmp);
218 return (wptr & adev->irq.ih.ptr_mask);
222 * tonga_ih_decode_iv - decode an interrupt vector
224 * @adev: amdgpu_device pointer
226 * Decodes the interrupt vector at the current rptr
227 * position and also advance the position.
229 static void tonga_ih_decode_iv(struct amdgpu_device *adev,
230 struct amdgpu_iv_entry *entry)
232 /* wptr/rptr are in bytes! */
233 u32 ring_index = adev->irq.ih.rptr >> 2;
236 dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
237 dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
238 dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
239 dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
241 entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
242 entry->src_id = dw[0] & 0xff;
243 entry->src_data[0] = dw[1] & 0xfffffff;
244 entry->ring_id = dw[2] & 0xff;
245 entry->vm_id = (dw[2] >> 8) & 0xff;
246 entry->pas_id = (dw[2] >> 16) & 0xffff;
248 /* wptr/rptr are in bytes! */
249 adev->irq.ih.rptr += 16;
253 * tonga_ih_set_rptr - set the IH ring buffer rptr
255 * @adev: amdgpu_device pointer
257 * Set the IH ring buffer rptr.
259 static void tonga_ih_set_rptr(struct amdgpu_device *adev)
261 if (adev->irq.ih.use_doorbell) {
262 /* XXX check if swapping is necessary on BE */
263 if (adev->irq.ih.use_bus_addr)
264 adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
266 adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
267 WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
269 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
273 static int tonga_ih_early_init(void *handle)
275 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
278 ret = amdgpu_irq_add_domain(adev);
282 tonga_ih_set_interrupt_funcs(adev);
287 static int tonga_ih_sw_init(void *handle)
290 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
292 r = amdgpu_ih_ring_init(adev, 64 * 1024, true);
296 adev->irq.ih.use_doorbell = true;
297 adev->irq.ih.doorbell_index = AMDGPU_DOORBELL_IH;
299 r = amdgpu_irq_init(adev);
304 static int tonga_ih_sw_fini(void *handle)
306 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
308 amdgpu_irq_fini(adev);
309 amdgpu_ih_ring_fini(adev);
310 amdgpu_irq_remove_domain(adev);
315 static int tonga_ih_hw_init(void *handle)
318 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
320 r = tonga_ih_irq_init(adev);
327 static int tonga_ih_hw_fini(void *handle)
329 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
331 tonga_ih_irq_disable(adev);
336 static int tonga_ih_suspend(void *handle)
338 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
340 return tonga_ih_hw_fini(adev);
343 static int tonga_ih_resume(void *handle)
345 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
347 return tonga_ih_hw_init(adev);
350 static bool tonga_ih_is_idle(void *handle)
352 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
353 u32 tmp = RREG32(mmSRBM_STATUS);
355 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
361 static int tonga_ih_wait_for_idle(void *handle)
365 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
367 for (i = 0; i < adev->usec_timeout; i++) {
369 tmp = RREG32(mmSRBM_STATUS);
370 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
377 static bool tonga_ih_check_soft_reset(void *handle)
379 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
380 u32 srbm_soft_reset = 0;
381 u32 tmp = RREG32(mmSRBM_STATUS);
383 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
384 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
387 if (srbm_soft_reset) {
388 adev->irq.srbm_soft_reset = srbm_soft_reset;
391 adev->irq.srbm_soft_reset = 0;
396 static int tonga_ih_pre_soft_reset(void *handle)
398 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
400 if (!adev->irq.srbm_soft_reset)
403 return tonga_ih_hw_fini(adev);
406 static int tonga_ih_post_soft_reset(void *handle)
408 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
410 if (!adev->irq.srbm_soft_reset)
413 return tonga_ih_hw_init(adev);
416 static int tonga_ih_soft_reset(void *handle)
418 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
421 if (!adev->irq.srbm_soft_reset)
423 srbm_soft_reset = adev->irq.srbm_soft_reset;
425 if (srbm_soft_reset) {
428 tmp = RREG32(mmSRBM_SOFT_RESET);
429 tmp |= srbm_soft_reset;
430 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
431 WREG32(mmSRBM_SOFT_RESET, tmp);
432 tmp = RREG32(mmSRBM_SOFT_RESET);
436 tmp &= ~srbm_soft_reset;
437 WREG32(mmSRBM_SOFT_RESET, tmp);
438 tmp = RREG32(mmSRBM_SOFT_RESET);
440 /* Wait a little for things to settle down */
447 static int tonga_ih_set_clockgating_state(void *handle,
448 enum amd_clockgating_state state)
453 static int tonga_ih_set_powergating_state(void *handle,
454 enum amd_powergating_state state)
459 static const struct amd_ip_funcs tonga_ih_ip_funcs = {
461 .early_init = tonga_ih_early_init,
463 .sw_init = tonga_ih_sw_init,
464 .sw_fini = tonga_ih_sw_fini,
465 .hw_init = tonga_ih_hw_init,
466 .hw_fini = tonga_ih_hw_fini,
467 .suspend = tonga_ih_suspend,
468 .resume = tonga_ih_resume,
469 .is_idle = tonga_ih_is_idle,
470 .wait_for_idle = tonga_ih_wait_for_idle,
471 .check_soft_reset = tonga_ih_check_soft_reset,
472 .pre_soft_reset = tonga_ih_pre_soft_reset,
473 .soft_reset = tonga_ih_soft_reset,
474 .post_soft_reset = tonga_ih_post_soft_reset,
475 .set_clockgating_state = tonga_ih_set_clockgating_state,
476 .set_powergating_state = tonga_ih_set_powergating_state,
479 static const struct amdgpu_ih_funcs tonga_ih_funcs = {
480 .get_wptr = tonga_ih_get_wptr,
481 .decode_iv = tonga_ih_decode_iv,
482 .set_rptr = tonga_ih_set_rptr
485 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)
487 if (adev->irq.ih_funcs == NULL)
488 adev->irq.ih_funcs = &tonga_ih_funcs;
491 const struct amdgpu_ip_block_version tonga_ih_ip_block =
493 .type = AMD_IP_BLOCK_TYPE_IH,
497 .funcs = &tonga_ih_ip_funcs,