drivers/gpu/drm/amd/amdgpu/soc15d.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef SOC15_H
  24 #define SOC15_H
  25
  26 #define GFX9_NUM_GFX_RINGS     1
  27 #define GFX9_NUM_COMPUTE_RINGS 8
  28
  29 /*
  30  * PM4
  31  */
  32 #define PACKET_TYPE0    0
  33 #define PACKET_TYPE1    1
  34 #define PACKET_TYPE2    2
  35 #define PACKET_TYPE3    3
  36
  37 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
  38 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
  39 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
  40 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
  41 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) |                         \
  42                          ((reg) & 0xFFFF) |                     \
  43                          ((n) & 0x3FFF) << 16)
  44 #define CP_PACKET2                      0x80000000
  45 #define         PACKET2_PAD_SHIFT               0
  46 #define         PACKET2_PAD_MASK                (0x3fffffff << 0)
  47
  48 #define PACKET2(v)      (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
  49
  50 #define PACKET3(op, n)  ((PACKET_TYPE3 << 30) |                         \
  51                          (((op) & 0xFF) << 8) |                         \
  52                          ((n) & 0x3FFF) << 16)
  53
  54 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
  55
  56 /* Packet 3 types */
  57 #define PACKET3_NOP                                     0x10
  58 #define PACKET3_SET_BASE                                0x11
  59 #define         PACKET3_BASE_INDEX(x)                  ((x) << 0)
  60 #define                 CE_PARTITION_BASE               3
  61 #define PACKET3_CLEAR_STATE                             0x12
  62 #define PACKET3_INDEX_BUFFER_SIZE                       0x13
  63 #define PACKET3_DISPATCH_DIRECT                         0x15
  64 #define PACKET3_DISPATCH_INDIRECT                       0x16
  65 #define PACKET3_ATOMIC_GDS                              0x1D
  66 #define PACKET3_ATOMIC_MEM                              0x1E
  67 #define PACKET3_OCCLUSION_QUERY                         0x1F
  68 #define PACKET3_SET_PREDICATION                         0x20
  69 #define PACKET3_REG_RMW                                 0x21
  70 #define PACKET3_COND_EXEC                               0x22
  71 #define PACKET3_PRED_EXEC                               0x23
  72 #define PACKET3_DRAW_INDIRECT                           0x24
  73 #define PACKET3_DRAW_INDEX_INDIRECT                     0x25
  74 #define PACKET3_INDEX_BASE                              0x26
  75 #define PACKET3_DRAW_INDEX_2                            0x27
  76 #define PACKET3_CONTEXT_CONTROL                         0x28
  77 #define PACKET3_INDEX_TYPE                              0x2A
  78 #define PACKET3_DRAW_INDIRECT_MULTI                     0x2C
  79 #define PACKET3_DRAW_INDEX_AUTO                         0x2D
  80 #define PACKET3_NUM_INSTANCES                           0x2F
  81 #define PACKET3_DRAW_INDEX_MULTI_AUTO                   0x30
  82 #define PACKET3_INDIRECT_BUFFER_CONST                   0x33
  83 #define PACKET3_STRMOUT_BUFFER_UPDATE                   0x34
  84 #define PACKET3_DRAW_INDEX_OFFSET_2                     0x35
  85 #define PACKET3_DRAW_PREAMBLE                           0x36
  86 #define PACKET3_WRITE_DATA                              0x37
  87 #define         WRITE_DATA_DST_SEL(x)                   ((x) << 8)
  88                 /* 0 - register
  89                  * 1 - memory (sync - via GRBM)
  90                  * 2 - gl2
  91                  * 3 - gds
  92                  * 4 - reserved
  93                  * 5 - memory (async - direct)
  94                  */
  95 #define         WR_ONE_ADDR                             (1 << 16)
  96 #define         WR_CONFIRM                              (1 << 20)
  97 #define         WRITE_DATA_CACHE_POLICY(x)              ((x) << 25)
  98                 /* 0 - LRU
  99                  * 1 - Stream
 100                  */
 101 #define         WRITE_DATA_ENGINE_SEL(x)                ((x) << 30)
 102                 /* 0 - me
 103                  * 1 - pfp
 104                  * 2 - ce
 105                  */
 106 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI               0x38
 107 #define PACKET3_MEM_SEMAPHORE                           0x39
 108 #              define PACKET3_SEM_USE_MAILBOX       (0x1 << 16)
 109 #              define PACKET3_SEM_SEL_SIGNAL_TYPE   (0x1 << 20) /* 0 = increment, 1 = write 1 */
 110 #              define PACKET3_SEM_SEL_SIGNAL        (0x6 << 29)
 111 #              define PACKET3_SEM_SEL_WAIT          (0x7 << 29)
 112 #define PACKET3_WAIT_REG_MEM                            0x3C
 113 #define         WAIT_REG_MEM_FUNCTION(x)                ((x) << 0)
 114                 /* 0 - always
 115                  * 1 - <
 116                  * 2 - <=
 117                  * 3 - ==
 118                  * 4 - !=
 119                  * 5 - >=
 120                  * 6 - >
 121                  */
 122 #define         WAIT_REG_MEM_MEM_SPACE(x)               ((x) << 4)
 123                 /* 0 - reg
 124                  * 1 - mem
 125                  */
 126 #define         WAIT_REG_MEM_OPERATION(x)               ((x) << 6)
 127                 /* 0 - wait_reg_mem
 128                  * 1 - wr_wait_wr_reg
 129                  */
 130 #define         WAIT_REG_MEM_ENGINE(x)                  ((x) << 8)
 131                 /* 0 - me
 132                  * 1 - pfp
 133                  */
 134 #define PACKET3_INDIRECT_BUFFER                         0x3F
 135 #define         INDIRECT_BUFFER_VALID                   (1 << 23)
 136 #define         INDIRECT_BUFFER_CACHE_POLICY(x)         ((x) << 28)
 137                 /* 0 - LRU
 138                  * 1 - Stream
 139                  * 2 - Bypass
 140                  */
 141 #define     INDIRECT_BUFFER_PRE_ENB(x)           ((x) << 21)
 142 #define PACKET3_COPY_DATA                               0x40
 143 #define PACKET3_PFP_SYNC_ME                             0x42
 144 #define PACKET3_COND_WRITE                              0x45
 145 #define PACKET3_EVENT_WRITE                             0x46
 146 #define         EVENT_TYPE(x)                           ((x) << 0)
 147 #define         EVENT_INDEX(x)                          ((x) << 8)
 148                 /* 0 - any non-TS event
 149                  * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
 150                  * 2 - SAMPLE_PIPELINESTAT
 151                  * 3 - SAMPLE_STREAMOUTSTAT*
 152                  * 4 - *S_PARTIAL_FLUSH
 153                  */
 154 #define PACKET3_RELEASE_MEM                             0x49
 155 #define         EVENT_TYPE(x)                           ((x) << 0)
 156 #define         EVENT_INDEX(x)                          ((x) << 8)
 157 #define         EOP_TCL1_VOL_ACTION_EN                  (1 << 12)
 158 #define         EOP_TC_VOL_ACTION_EN                    (1 << 13) /* L2 */
 159 #define         EOP_TC_WB_ACTION_EN                     (1 << 15) /* L2 */
 160 #define         EOP_TCL1_ACTION_EN                      (1 << 16)
 161 #define         EOP_TC_ACTION_EN                        (1 << 17) /* L2 */
 162 #define         EOP_TC_MD_ACTION_EN                     (1 << 21) /* L2 metadata */
 163
 164 #define         DATA_SEL(x)                             ((x) << 29)
 165                 /* 0 - discard
 166                  * 1 - send low 32bit data
 167                  * 2 - send 64bit data
 168                  * 3 - send 64bit GPU counter value
 169                  * 4 - send 64bit sys counter value
 170                  */
 171 #define         INT_SEL(x)                              ((x) << 24)
 172                 /* 0 - none
 173                  * 1 - interrupt only (DATA_SEL = 0)
 174                  * 2 - interrupt when data write is confirmed
 175                  */
 176 #define         DST_SEL(x)                              ((x) << 16)
 177                 /* 0 - MC
 178                  * 1 - TC/L2
 179                  */
 180
 181
 182
 183 #define PACKET3_PREAMBLE_CNTL                           0x4A
 184 #              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
 185 #              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
 186 #define PACKET3_DMA_DATA                                0x50
 187 /* 1. header
 188  * 2. CONTROL
 189  * 3. SRC_ADDR_LO or DATA [31:0]
 190  * 4. SRC_ADDR_HI [31:0]
 191  * 5. DST_ADDR_LO [31:0]
 192  * 6. DST_ADDR_HI [7:0]
 193  * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
 194  */
 195 /* CONTROL */
 196 #              define PACKET3_DMA_DATA_ENGINE(x)     ((x) << 0)
 197                 /* 0 - ME
 198                  * 1 - PFP
 199                  */
 200 #              define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
 201                 /* 0 - LRU
 202                  * 1 - Stream
 203                  */
 204 #              define PACKET3_DMA_DATA_DST_SEL(x)  ((x) << 20)
 205                 /* 0 - DST_ADDR using DAS
 206                  * 1 - GDS
 207                  * 3 - DST_ADDR using L2
 208                  */
 209 #              define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
 210                 /* 0 - LRU
 211                  * 1 - Stream
 212                  */
 213 #              define PACKET3_DMA_DATA_SRC_SEL(x)  ((x) << 29)
 214                 /* 0 - SRC_ADDR using SAS
 215                  * 1 - GDS
 216                  * 2 - DATA
 217                  * 3 - SRC_ADDR using L2
 218                  */
 219 #              define PACKET3_DMA_DATA_CP_SYNC     (1 << 31)
 220 /* COMMAND */
 221 #              define PACKET3_DMA_DATA_CMD_SAS     (1 << 26)
 222                 /* 0 - memory
 223                  * 1 - register
 224                  */
 225 #              define PACKET3_DMA_DATA_CMD_DAS     (1 << 27)
 226                 /* 0 - memory
 227                  * 1 - register
 228                  */
 229 #              define PACKET3_DMA_DATA_CMD_SAIC    (1 << 28)
 230 #              define PACKET3_DMA_DATA_CMD_DAIC    (1 << 29)
 231 #              define PACKET3_DMA_DATA_CMD_RAW_WAIT  (1 << 30)
 232 #define PACKET3_AQUIRE_MEM                              0x58
 233 #define PACKET3_REWIND                                  0x59
 234 #define PACKET3_LOAD_UCONFIG_REG                        0x5E
 235 #define PACKET3_LOAD_SH_REG                             0x5F
 236 #define PACKET3_LOAD_CONFIG_REG                         0x60
 237 #define PACKET3_LOAD_CONTEXT_REG                        0x61
 238 #define PACKET3_SET_CONFIG_REG                          0x68
 239 #define         PACKET3_SET_CONFIG_REG_START                    0x00002000
 240 #define         PACKET3_SET_CONFIG_REG_END                      0x00002c00
 241 #define PACKET3_SET_CONTEXT_REG                         0x69
 242 #define         PACKET3_SET_CONTEXT_REG_START                   0x0000a000
 243 #define         PACKET3_SET_CONTEXT_REG_END                     0x0000a400
 244 #define PACKET3_SET_CONTEXT_REG_INDIRECT                0x73
 245 #define PACKET3_SET_SH_REG                              0x76
 246 #define         PACKET3_SET_SH_REG_START                        0x00002c00
 247 #define         PACKET3_SET_SH_REG_END                          0x00003000
 248 #define PACKET3_SET_SH_REG_OFFSET                       0x77
 249 #define PACKET3_SET_QUEUE_REG                           0x78
 250 #define PACKET3_SET_UCONFIG_REG                         0x79
 251 #define         PACKET3_SET_UCONFIG_REG_START                   0x0000c000
 252 #define         PACKET3_SET_UCONFIG_REG_END                     0x0000c400
 253 #define         PACKET3_SET_UCONFIG_REG_INDEX_TYPE              (2 << 28)
 254 #define PACKET3_SCRATCH_RAM_WRITE                       0x7D
 255 #define PACKET3_SCRATCH_RAM_READ                        0x7E
 256 #define PACKET3_LOAD_CONST_RAM                          0x80
 257 #define PACKET3_WRITE_CONST_RAM                         0x81
 258 #define PACKET3_DUMP_CONST_RAM                          0x83
 259 #define PACKET3_INCREMENT_CE_COUNTER                    0x84
 260 #define PACKET3_INCREMENT_DE_COUNTER                    0x85
 261 #define PACKET3_WAIT_ON_CE_COUNTER                      0x86
 262 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF                 0x88
 263 #define PACKET3_SWITCH_BUFFER                           0x8B
 264 #define PACKET3_FRAME_CONTROL                           0x90
 265 #                       define FRAME_CMD(x) ((x) << 28)
 266                         /*
 267                          * x=0: tmz_begin
 268                          * x=1: tmz_end
 269                          */
 270
 271 #define PACKET3_SET_RESOURCES                           0xA0
 272 /* 1. header
 273  * 2. CONTROL
 274  * 3. QUEUE_MASK_LO [31:0]
 275  * 4. QUEUE_MASK_HI [31:0]
 276  * 5. GWS_MASK_LO [31:0]
 277  * 6. GWS_MASK_HI [31:0]
 278  * 7. OAC_MASK [15:0]
 279  * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0]
 280  */
 281 #              define PACKET3_SET_RESOURCES_VMID_MASK(x)     ((x) << 0)
 282 #              define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16)
 283 #              define PACKET3_SET_RESOURCES_QUEUE_TYPE(x)    ((x) << 29)
 284 #define PACKET3_MAP_QUEUES                              0xA2
 285 /* 1. header
 286  * 2. CONTROL
 287  * 3. CONTROL2
 288  * 4. MQD_ADDR_LO [31:0]
 289  * 5. MQD_ADDR_HI [31:0]
 290  * 6. WPTR_ADDR_LO [31:0]
 291  * 7. WPTR_ADDR_HI [31:0]
 292  */
 293 /* CONTROL */
 294 #              define PACKET3_MAP_QUEUES_QUEUE_SEL(x)       ((x) << 4)
 295 #              define PACKET3_MAP_QUEUES_VMID(x)            ((x) << 8)
 296 #              define PACKET3_MAP_QUEUES_QUEUE(x)           ((x) << 13)
 297 #              define PACKET3_MAP_QUEUES_PIPE(x)            ((x) << 16)
 298 #              define PACKET3_MAP_QUEUES_ME(x)              ((x) << 18)
 299 #              define PACKET3_MAP_QUEUES_QUEUE_TYPE(x)      ((x) << 21)
 300 #              define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x)    ((x) << 24)
 301 #              define PACKET3_MAP_QUEUES_ENGINE_SEL(x)      ((x) << 26)
 302 #              define PACKET3_MAP_QUEUES_NUM_QUEUES(x)      ((x) << 29)
 303 /* CONTROL2 */
 304 #              define PACKET3_MAP_QUEUES_CHECK_DISABLE(x)   ((x) << 1)
 305 #              define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2)
 306 #define PACKET3_UNMAP_QUEUES                            0xA3
 307 /* 1. header
 308  * 2. CONTROL
 309  * 3. CONTROL2
 310  * 4. CONTROL3
 311  * 5. CONTROL4
 312  * 6. CONTROL5
 313  */
 314 /* CONTROL */
 315 #              define PACKET3_UNMAP_QUEUES_ACTION(x)           ((x) << 0)
 316                 /* 0 - PREEMPT_QUEUES
 317                  * 1 - RESET_QUEUES
 318                  * 2 - DISABLE_PROCESS_QUEUES
 319                  * 3 - PREEMPT_QUEUES_NO_UNMAP
 320                  */
 321 #              define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x)        ((x) << 4)
 322 #              define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x)       ((x) << 26)
 323 #              define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x)       ((x) << 29)
 324 /* CONTROL2a */
 325 #              define PACKET3_UNMAP_QUEUES_PASID(x)            ((x) << 0)
 326 /* CONTROL2b */
 327 #              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2)
 328 /* CONTROL3a */
 329 #              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2)
 330 /* CONTROL3b */
 331 #              define PACKET3_UNMAP_QUEUES_RB_WPTR(x)          ((x) << 0)
 332 /* CONTROL4 */
 333 #              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2)
 334 /* CONTROL5 */
 335 #              define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2)
 336 #define PACKET3_QUERY_STATUS                            0xA4
 337 /* 1. header
 338  * 2. CONTROL
 339  * 3. CONTROL2
 340  * 4. ADDR_LO [31:0]
 341  * 5. ADDR_HI [31:0]
 342  * 6. DATA_LO [31:0]
 343  * 7. DATA_HI [31:0]
 344  */
 345 /* CONTROL */
 346 #              define PACKET3_QUERY_STATUS_CONTEXT_ID(x)       ((x) << 0)
 347 #              define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x)    ((x) << 28)
 348 #              define PACKET3_QUERY_STATUS_COMMAND(x)          ((x) << 30)
 349 /* CONTROL2a */
 350 #              define PACKET3_QUERY_STATUS_PASID(x)            ((x) << 0)
 351 /* CONTROL2b */
 352 #              define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x)  ((x) << 2)
 353 #              define PACKET3_QUERY_STATUS_ENG_SEL(x)          ((x) << 25)
 354
 355
 356 #define VCE_CMD_NO_OP           0x00000000
 357 #define VCE_CMD_END             0x00000001
 358 #define VCE_CMD_IB              0x00000002
 359 #define VCE_CMD_FENCE           0x00000003
 360 #define VCE_CMD_TRAP            0x00000004
 361 #define VCE_CMD_IB_AUTO         0x00000005
 362 #define VCE_CMD_SEMAPHORE       0x00000006
 363
 364 #define VCE_CMD_IB_VM           0x00000102
 365 #define VCE_CMD_WAIT_GE         0x00000106
 366 #define VCE_CMD_UPDATE_PTB      0x00000107
 367 #define VCE_CMD_FLUSH_TLB       0x00000108
 368 #define VCE_CMD_REG_WRITE       0x00000109
 369 #define VCE_CMD_REG_WAIT        0x0000010a
 370
 371 #define HEVC_ENC_CMD_NO_OP              0x00000000
 372 #define HEVC_ENC_CMD_END                0x00000001
 373 #define HEVC_ENC_CMD_FENCE              0x00000003
 374 #define HEVC_ENC_CMD_TRAP               0x00000004
 375 #define HEVC_ENC_CMD_IB_VM              0x00000102
 376 #define HEVC_ENC_CMD_REG_WRITE          0x00000109
 377 #define HEVC_ENC_CMD_REG_WAIT           0x0000010a
 378
 379 #endif