2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "amdgpu_pm.h"
27 #include "amdgpu_dpm.h"
28 #include "amdgpu_atombios.h"
34 #include "../include/pptable.h"
35 #include <linux/math64.h>
36 #include <linux/seq_file.h>
37 #include <linux/firmware.h>
39 #define MC_CG_ARB_FREQ_F0 0x0a
40 #define MC_CG_ARB_FREQ_F1 0x0b
41 #define MC_CG_ARB_FREQ_F2 0x0c
42 #define MC_CG_ARB_FREQ_F3 0x0d
44 #define SMC_RAM_END 0x20000
46 #define SCLK_MIN_DEEPSLEEP_FREQ 1350
49 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
50 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
51 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
52 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
53 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
54 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
55 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
57 #define BIOS_SCRATCH_4 0x5cd
62 struct _ATOM_POWERPLAY_INFO info;
63 struct _ATOM_POWERPLAY_INFO_V2 info_2;
64 struct _ATOM_POWERPLAY_INFO_V3 info_3;
65 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
66 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
67 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
68 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
69 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
73 struct _ATOM_PPLIB_FANTABLE fan;
74 struct _ATOM_PPLIB_FANTABLE2 fan2;
75 struct _ATOM_PPLIB_FANTABLE3 fan3;
78 union pplib_clock_info {
79 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
80 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
81 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
82 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
83 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
86 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
105 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
124 static const struct si_cac_config_reg cac_weights_tahiti[] =
126 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
127 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
128 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
129 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
130 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
131 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
132 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
133 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
134 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
135 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
136 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
137 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
138 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
139 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
140 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
141 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
142 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
143 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
144 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
145 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
146 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
147 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
148 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
149 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
150 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
151 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
152 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
153 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
154 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
155 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
156 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
157 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
158 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
159 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
160 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
161 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
162 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
163 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
164 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
165 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
166 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
167 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
168 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
169 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
170 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
171 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
172 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
173 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
174 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
175 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
176 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
177 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
178 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
179 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
180 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
181 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
182 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
183 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
184 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
185 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
189 static const struct si_cac_config_reg lcac_tahiti[] =
191 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
192 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
193 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
194 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
195 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
196 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
197 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
198 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
199 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
200 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
201 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
202 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
203 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
204 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
205 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
206 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
207 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
208 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
209 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
210 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
211 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
212 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
213 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
214 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
215 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
216 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
217 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
218 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
219 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
220 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
221 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
222 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
223 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
224 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
225 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
226 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
227 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
228 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
229 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
230 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
231 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
232 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
233 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
234 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
235 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
236 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
237 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
238 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
239 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
240 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
241 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
242 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
243 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
244 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
245 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
246 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
247 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
248 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
249 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
250 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
251 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
252 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
253 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
254 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
255 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
256 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
257 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
258 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
259 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
260 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
261 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
262 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
263 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
264 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
265 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
266 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
267 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
268 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
269 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
270 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
271 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
272 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
273 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
274 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
275 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
276 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
281 static const struct si_cac_config_reg cac_override_tahiti[] =
286 static const struct si_powertune_data powertune_data_tahiti =
317 static const struct si_dte_data dte_data_tahiti =
319 { 1159409, 0, 0, 0, 0 },
328 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
329 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
330 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
336 static const struct si_dte_data dte_data_tahiti_le =
338 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
339 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
347 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
348 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
349 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
355 static const struct si_dte_data dte_data_tahiti_pro =
357 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
358 { 0x0, 0x0, 0x0, 0x0, 0x0 },
366 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
367 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
368 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
373 static const struct si_dte_data dte_data_new_zealand =
375 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
376 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
384 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
385 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
386 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
391 static const struct si_dte_data dte_data_aruba_pro =
393 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
394 { 0x0, 0x0, 0x0, 0x0, 0x0 },
402 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
403 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
404 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
409 static const struct si_dte_data dte_data_malta =
411 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
412 { 0x0, 0x0, 0x0, 0x0, 0x0 },
420 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
421 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
422 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
427 static const struct si_cac_config_reg cac_weights_pitcairn[] =
429 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
430 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
431 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
432 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
433 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
434 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
435 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
436 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
437 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
438 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
439 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
440 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
441 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
442 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
443 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
444 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
445 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
446 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
447 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
448 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
449 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
450 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
451 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
452 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
453 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
454 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
455 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
456 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
457 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
458 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
459 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
460 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
461 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
462 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
463 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
464 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
465 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
466 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
467 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
468 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
469 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
470 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
471 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
472 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
473 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
474 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
475 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
476 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
477 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
478 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
479 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
480 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
481 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
482 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
483 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
484 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
485 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
486 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
487 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
488 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
492 static const struct si_cac_config_reg lcac_pitcairn[] =
494 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
495 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
496 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
497 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
498 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
499 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
500 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
501 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
502 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
503 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
504 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
505 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
506 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
507 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
508 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
509 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
510 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
511 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
512 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
513 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
514 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
515 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
516 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
517 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
518 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
519 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
520 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
521 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
522 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
523 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
524 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
525 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
526 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
527 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
528 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
529 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
530 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
531 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
532 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
533 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
534 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
535 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
536 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
537 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
538 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
539 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
540 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
541 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
542 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
543 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
544 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
545 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
546 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
547 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
548 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
549 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
550 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
551 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
552 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
553 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
554 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
555 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
556 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
557 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
558 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
559 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
560 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
561 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
562 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
563 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
564 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
565 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
566 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
567 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
568 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
569 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
570 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
571 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
572 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
573 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
574 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
575 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
576 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
577 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
578 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
579 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
583 static const struct si_cac_config_reg cac_override_pitcairn[] =
588 static const struct si_powertune_data powertune_data_pitcairn =
619 static const struct si_dte_data dte_data_pitcairn =
630 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
631 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
632 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
637 static const struct si_dte_data dte_data_curacao_xt =
639 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
640 { 0x0, 0x0, 0x0, 0x0, 0x0 },
648 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
649 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
650 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
655 static const struct si_dte_data dte_data_curacao_pro =
657 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
658 { 0x0, 0x0, 0x0, 0x0, 0x0 },
666 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
667 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
668 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
673 static const struct si_dte_data dte_data_neptune_xt =
675 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
676 { 0x0, 0x0, 0x0, 0x0, 0x0 },
684 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
685 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
686 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
691 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
693 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
694 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
695 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
696 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
697 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
698 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
699 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
700 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
701 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
702 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
703 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
704 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
705 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
706 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
707 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
708 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
709 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
710 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
711 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
712 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
713 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
714 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
715 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
716 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
717 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
718 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
719 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
720 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
721 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
722 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
723 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
724 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
725 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
726 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
727 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
728 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
729 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
730 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
731 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
732 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
733 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
734 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
735 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
736 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
737 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
738 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
739 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
740 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
741 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
742 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
743 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
744 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
745 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
746 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
747 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
748 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
749 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
750 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
751 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
752 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
756 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
758 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
759 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
760 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
761 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
762 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
763 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
764 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
765 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
766 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
767 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
768 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
769 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
770 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
771 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
772 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
773 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
774 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
775 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
776 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
777 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
778 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
779 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
780 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
781 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
782 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
783 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
784 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
785 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
786 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
787 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
788 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
789 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
790 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
791 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
792 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
793 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
794 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
795 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
796 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
797 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
798 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
799 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
800 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
801 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
802 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
803 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
804 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
805 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
806 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
807 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
808 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
809 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
810 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
811 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
812 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
813 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
814 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
815 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
816 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
817 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
821 static const struct si_cac_config_reg cac_weights_heathrow[] =
823 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
824 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
825 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
826 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
827 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
828 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
829 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
830 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
831 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
832 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
833 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
834 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
835 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
836 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
837 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
838 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
839 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
840 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
841 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
842 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
843 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
844 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
845 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
846 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
847 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
848 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
849 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
850 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
851 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
852 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
853 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
854 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
855 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
856 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
857 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
858 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
859 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
860 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
861 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
862 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
863 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
864 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
865 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
866 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
867 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
868 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
869 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
870 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
871 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
872 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
873 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
874 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
875 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
876 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
877 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
878 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
879 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
880 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
881 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
882 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
886 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
888 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
889 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
890 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
891 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
892 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
893 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
894 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
895 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
896 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
897 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
898 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
899 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
900 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
901 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
902 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
903 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
904 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
905 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
906 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
907 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
908 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
909 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
910 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
911 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
912 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
913 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
914 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
915 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
916 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
917 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
918 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
919 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
920 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
921 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
922 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
923 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
924 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
925 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
926 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
927 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
928 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
929 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
930 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
931 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
932 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
933 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
934 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
935 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
936 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
937 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
938 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
939 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
940 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
941 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
942 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
943 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
944 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
945 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
946 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
947 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
951 static const struct si_cac_config_reg cac_weights_cape_verde[] =
953 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
954 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
955 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
956 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
957 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
958 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
959 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
960 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
961 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
962 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
963 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
964 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
965 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
966 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
967 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
968 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
969 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
970 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
971 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
972 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
973 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
974 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
975 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
976 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
977 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
978 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
979 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
980 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
981 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
982 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
983 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
984 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
985 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
986 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
987 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
988 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
989 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
990 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
991 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
992 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
993 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
994 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
995 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
996 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
997 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
998 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
999 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1000 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1001 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1002 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1003 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1004 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1005 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1006 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1007 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1008 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1009 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1010 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1011 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1012 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1016 static const struct si_cac_config_reg lcac_cape_verde[] =
1018 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1019 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1020 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1021 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1022 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1023 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1024 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1025 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1026 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1027 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1028 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1029 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1030 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1031 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1032 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1033 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1034 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1035 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1036 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1037 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1038 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1039 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1040 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1041 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1042 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1043 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1045 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1047 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1049 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1051 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1053 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1059 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1061 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1063 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1065 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1067 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1069 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1071 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1075 static const struct si_cac_config_reg cac_override_cape_verde[] =
1080 static const struct si_powertune_data powertune_data_cape_verde =
1082 ((1 << 16) | 0x6993),
1111 static const struct si_dte_data dte_data_cape_verde =
1122 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1123 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1124 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1129 static const struct si_dte_data dte_data_venus_xtx =
1131 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1132 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1140 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1141 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1142 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1147 static const struct si_dte_data dte_data_venus_xt =
1149 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1150 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1158 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1159 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1160 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1165 static const struct si_dte_data dte_data_venus_pro =
1167 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1168 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1176 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1177 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1178 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1183 static const struct si_cac_config_reg cac_weights_oland[] =
1185 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1186 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1187 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1188 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1189 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1190 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1191 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1192 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1193 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1194 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1195 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1196 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1197 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1198 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1199 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1200 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1201 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1202 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1203 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1204 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1205 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1206 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1207 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1208 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1209 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1210 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1211 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1212 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1213 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1214 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1215 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1216 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1217 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1218 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1219 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1220 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1221 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1222 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1223 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1224 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1225 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1226 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1227 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1228 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1229 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1230 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1231 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1232 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1233 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1234 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1235 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1236 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1239 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1241 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1242 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1243 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1244 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1248 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1250 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1251 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1252 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1253 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1254 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1255 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1256 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1257 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1258 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1259 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1260 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1261 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1262 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1263 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1264 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1265 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1266 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1267 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1268 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1269 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1270 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1271 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1272 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1273 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1274 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1275 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1276 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1277 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1278 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1279 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1280 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1281 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1282 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1283 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1284 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1285 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1286 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1287 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1288 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1289 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1290 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1291 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1292 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1293 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1294 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1295 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1296 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1297 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1298 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1299 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1300 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1301 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1302 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1304 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1305 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1306 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1307 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1308 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1309 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1313 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1315 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1316 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1317 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1318 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1319 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1320 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1321 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1322 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1323 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1324 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1325 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1326 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1327 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1328 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1329 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1330 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1331 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1332 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1333 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1334 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1335 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1336 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1337 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1338 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1339 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1340 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1341 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1342 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1343 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1344 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1345 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1346 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1347 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1348 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1349 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1350 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1351 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1352 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1353 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1354 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1355 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1356 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1357 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1358 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1359 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1360 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1361 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1362 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1363 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1364 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1365 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1366 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1367 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1370 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1371 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1372 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1373 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1374 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1378 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1380 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1381 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1382 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1383 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1384 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1385 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1386 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1387 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1388 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1389 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1390 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1391 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1392 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1393 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1394 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1395 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1396 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1397 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1398 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1399 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1400 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1401 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1402 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1403 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1404 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1405 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1406 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1407 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1408 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1409 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1410 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1411 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1412 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1413 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1414 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1415 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1416 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1417 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1418 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1419 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1420 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1421 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1422 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1423 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1424 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1425 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1426 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1427 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1428 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1429 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1430 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1431 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1432 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1433 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1434 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1435 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1436 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1437 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1438 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1439 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1443 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1445 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1446 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1447 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1448 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1449 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1450 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1451 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1452 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1453 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1454 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1455 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1456 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1457 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1458 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1459 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1460 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1461 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1462 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1463 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1464 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1465 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1466 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1467 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1468 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1469 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1470 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1471 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1472 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1473 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1474 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1475 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1476 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1477 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1478 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1479 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1480 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1481 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1482 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1483 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1484 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1485 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1486 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1487 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1488 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1489 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1490 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1491 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1492 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1493 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1494 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1495 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1496 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1497 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1498 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1499 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1500 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1501 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1502 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1503 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1504 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1508 static const struct si_cac_config_reg lcac_oland[] =
1510 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1511 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1513 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1515 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1516 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1517 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1518 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1519 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1520 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1521 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1522 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1523 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1524 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1525 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1526 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1527 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1528 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1529 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1530 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1531 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1532 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1533 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1534 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1535 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1537 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1539 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1541 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1543 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1545 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1547 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1549 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1555 static const struct si_cac_config_reg lcac_mars_pro[] =
1557 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1558 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1559 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1560 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1561 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1562 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1563 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1564 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1565 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1566 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1567 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1568 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1569 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1570 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1571 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1572 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1573 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1574 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1575 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1576 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1577 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1578 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1579 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1580 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1581 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1582 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1584 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1586 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1588 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1590 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1592 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1594 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1596 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1602 static const struct si_cac_config_reg cac_override_oland[] =
1607 static const struct si_powertune_data powertune_data_oland =
1609 ((1 << 16) | 0x6993),
1638 static const struct si_powertune_data powertune_data_mars_pro =
1640 ((1 << 16) | 0x6993),
1669 static const struct si_dte_data dte_data_oland =
1680 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1681 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1682 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1687 static const struct si_dte_data dte_data_mars_pro =
1689 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1690 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1698 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1699 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1700 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1705 static const struct si_dte_data dte_data_sun_xt =
1707 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1708 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1716 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1717 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1718 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1724 static const struct si_cac_config_reg cac_weights_hainan[] =
1726 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1727 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1728 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1729 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1730 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1731 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1732 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1733 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1734 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1735 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1736 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1737 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1738 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1739 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1740 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1741 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1742 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1743 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1744 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1745 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1746 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1747 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1748 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1749 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1750 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1751 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1752 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1753 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1754 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1755 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1756 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1757 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1758 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1759 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1760 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1761 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1762 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1763 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1764 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1765 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1766 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1767 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1768 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1769 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1770 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1771 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1772 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1773 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1774 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1775 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1776 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1777 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1778 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1779 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1780 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1781 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1782 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1783 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1784 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1785 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1789 static const struct si_powertune_data powertune_data_hainan =
1791 ((1 << 16) | 0x6993),
1820 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1821 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1822 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1823 static struct si_ps *si_get_ps(struct amdgpu_ps *rps);
1825 static int si_populate_voltage_value(struct amdgpu_device *adev,
1826 const struct atom_voltage_table *table,
1827 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1828 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1829 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1831 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1832 u16 reg_offset, u32 value);
1833 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1834 struct rv7xx_pl *pl,
1835 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1836 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1838 SISLANDS_SMC_SCLK_VALUE *sclk);
1840 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1841 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1842 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
1843 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1845 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1847 struct si_power_info *pi = adev->pm.dpm.priv;
1851 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1852 u16 v, s32 t, u32 ileakage, u32 *leakage)
1854 s64 kt, kv, leakage_w, i_leakage, vddc;
1855 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1858 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1859 vddc = div64_s64(drm_int2fixp(v), 1000);
1860 temperature = div64_s64(drm_int2fixp(t), 1000);
1862 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1863 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1864 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1865 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1866 t_ref = drm_int2fixp(coeff->t_ref);
1868 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1869 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1870 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1871 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1873 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1875 *leakage = drm_fixp2int(leakage_w * 1000);
1878 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1879 const struct ni_leakage_coeffients *coeff,
1885 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1888 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1889 const u32 fixed_kt, u16 v,
1890 u32 ileakage, u32 *leakage)
1892 s64 kt, kv, leakage_w, i_leakage, vddc;
1894 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1895 vddc = div64_s64(drm_int2fixp(v), 1000);
1897 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1898 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1899 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1901 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1903 *leakage = drm_fixp2int(leakage_w * 1000);
1906 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1907 const struct ni_leakage_coeffients *coeff,
1913 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1917 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1918 struct si_dte_data *dte_data)
1920 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1921 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1922 u32 k = dte_data->k;
1923 u32 t_max = dte_data->max_t;
1924 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1925 u32 t_0 = dte_data->t0;
1928 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1929 dte_data->tdep_count = 3;
1931 for (i = 0; i < k; i++) {
1933 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1934 (p_limit2 * (u32)100);
1937 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1939 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1940 dte_data->tdep_r[i] = dte_data->r[4];
1943 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1947 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1949 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1954 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1956 struct ni_power_info *pi = adev->pm.dpm.priv;
1961 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1963 struct si_ps *ps = aps->ps_priv;
1968 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1970 struct ni_power_info *ni_pi = ni_get_pi(adev);
1971 struct si_power_info *si_pi = si_get_pi(adev);
1972 bool update_dte_from_pl2 = false;
1974 if (adev->asic_type == CHIP_TAHITI) {
1975 si_pi->cac_weights = cac_weights_tahiti;
1976 si_pi->lcac_config = lcac_tahiti;
1977 si_pi->cac_override = cac_override_tahiti;
1978 si_pi->powertune_data = &powertune_data_tahiti;
1979 si_pi->dte_data = dte_data_tahiti;
1981 switch (adev->pdev->device) {
1983 si_pi->dte_data.enable_dte_by_default = true;
1986 si_pi->dte_data = dte_data_new_zealand;
1992 si_pi->dte_data = dte_data_aruba_pro;
1993 update_dte_from_pl2 = true;
1996 si_pi->dte_data = dte_data_malta;
1997 update_dte_from_pl2 = true;
2000 si_pi->dte_data = dte_data_tahiti_pro;
2001 update_dte_from_pl2 = true;
2004 if (si_pi->dte_data.enable_dte_by_default == true)
2005 DRM_ERROR("DTE is not enabled!\n");
2008 } else if (adev->asic_type == CHIP_PITCAIRN) {
2009 si_pi->cac_weights = cac_weights_pitcairn;
2010 si_pi->lcac_config = lcac_pitcairn;
2011 si_pi->cac_override = cac_override_pitcairn;
2012 si_pi->powertune_data = &powertune_data_pitcairn;
2014 switch (adev->pdev->device) {
2017 si_pi->dte_data = dte_data_curacao_xt;
2018 update_dte_from_pl2 = true;
2022 si_pi->dte_data = dte_data_curacao_pro;
2023 update_dte_from_pl2 = true;
2027 si_pi->dte_data = dte_data_neptune_xt;
2028 update_dte_from_pl2 = true;
2031 si_pi->dte_data = dte_data_pitcairn;
2034 } else if (adev->asic_type == CHIP_VERDE) {
2035 si_pi->lcac_config = lcac_cape_verde;
2036 si_pi->cac_override = cac_override_cape_verde;
2037 si_pi->powertune_data = &powertune_data_cape_verde;
2039 switch (adev->pdev->device) {
2044 si_pi->cac_weights = cac_weights_cape_verde_pro;
2045 si_pi->dte_data = dte_data_cape_verde;
2048 si_pi->cac_weights = cac_weights_cape_verde_pro;
2049 si_pi->dte_data = dte_data_sun_xt;
2050 update_dte_from_pl2 = true;
2054 si_pi->cac_weights = cac_weights_heathrow;
2055 si_pi->dte_data = dte_data_cape_verde;
2059 si_pi->cac_weights = cac_weights_chelsea_xt;
2060 si_pi->dte_data = dte_data_cape_verde;
2063 si_pi->cac_weights = cac_weights_chelsea_pro;
2064 si_pi->dte_data = dte_data_cape_verde;
2067 si_pi->cac_weights = cac_weights_heathrow;
2068 si_pi->dte_data = dte_data_venus_xtx;
2071 si_pi->cac_weights = cac_weights_heathrow;
2072 si_pi->dte_data = dte_data_venus_xt;
2078 si_pi->cac_weights = cac_weights_chelsea_pro;
2079 si_pi->dte_data = dte_data_venus_pro;
2082 si_pi->cac_weights = cac_weights_cape_verde;
2083 si_pi->dte_data = dte_data_cape_verde;
2086 } else if (adev->asic_type == CHIP_OLAND) {
2087 si_pi->lcac_config = lcac_mars_pro;
2088 si_pi->cac_override = cac_override_oland;
2089 si_pi->powertune_data = &powertune_data_mars_pro;
2090 si_pi->dte_data = dte_data_mars_pro;
2092 switch (adev->pdev->device) {
2097 si_pi->cac_weights = cac_weights_mars_pro;
2098 update_dte_from_pl2 = true;
2104 si_pi->cac_weights = cac_weights_mars_xt;
2105 update_dte_from_pl2 = true;
2110 si_pi->cac_weights = cac_weights_oland_pro;
2111 update_dte_from_pl2 = true;
2114 si_pi->cac_weights = cac_weights_oland_xt;
2115 update_dte_from_pl2 = true;
2118 si_pi->cac_weights = cac_weights_oland;
2119 si_pi->lcac_config = lcac_oland;
2120 si_pi->cac_override = cac_override_oland;
2121 si_pi->powertune_data = &powertune_data_oland;
2122 si_pi->dte_data = dte_data_oland;
2125 } else if (adev->asic_type == CHIP_HAINAN) {
2126 si_pi->cac_weights = cac_weights_hainan;
2127 si_pi->lcac_config = lcac_oland;
2128 si_pi->cac_override = cac_override_oland;
2129 si_pi->powertune_data = &powertune_data_hainan;
2130 si_pi->dte_data = dte_data_sun_xt;
2131 update_dte_from_pl2 = true;
2133 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2137 ni_pi->enable_power_containment = false;
2138 ni_pi->enable_cac = false;
2139 ni_pi->enable_sq_ramping = false;
2140 si_pi->enable_dte = false;
2142 if (si_pi->powertune_data->enable_powertune_by_default) {
2143 ni_pi->enable_power_containment = true;
2144 ni_pi->enable_cac = true;
2145 if (si_pi->dte_data.enable_dte_by_default) {
2146 si_pi->enable_dte = true;
2147 if (update_dte_from_pl2)
2148 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2151 ni_pi->enable_sq_ramping = true;
2154 ni_pi->driver_calculate_cac_leakage = true;
2155 ni_pi->cac_configuration_required = true;
2157 if (ni_pi->cac_configuration_required) {
2158 ni_pi->support_cac_long_term_average = true;
2159 si_pi->dyn_powertune_data.l2_lta_window_size =
2160 si_pi->powertune_data->l2_lta_window_size_default;
2161 si_pi->dyn_powertune_data.lts_truncate =
2162 si_pi->powertune_data->lts_truncate_default;
2164 ni_pi->support_cac_long_term_average = false;
2165 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2166 si_pi->dyn_powertune_data.lts_truncate = 0;
2169 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2172 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2177 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2182 u32 cac_window_size;
2184 xclk = amdgpu_asic_get_xclk(adev);
2189 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2190 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2192 wintime = (cac_window_size * 100) / xclk;
2197 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2199 return power_in_watts;
2202 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2203 bool adjust_polarity,
2206 u32 *near_tdp_limit)
2208 u32 adjustment_delta, max_tdp_limit;
2210 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2213 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2215 if (adjust_polarity) {
2216 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2217 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2219 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2220 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit;
2221 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2222 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2224 *near_tdp_limit = 0;
2227 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2229 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2235 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2236 struct amdgpu_ps *amdgpu_state)
2238 struct ni_power_info *ni_pi = ni_get_pi(adev);
2239 struct si_power_info *si_pi = si_get_pi(adev);
2241 if (ni_pi->enable_power_containment) {
2242 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2243 PP_SIslands_PAPMParameters *papm_parm;
2244 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2245 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2250 if (scaling_factor == 0)
2253 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2255 ret = si_calculate_adjusted_tdp_limits(adev,
2257 adev->pm.dpm.tdp_adjustment,
2263 smc_table->dpm2Params.TDPLimit =
2264 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2265 smc_table->dpm2Params.NearTDPLimit =
2266 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2267 smc_table->dpm2Params.SafePowerLimit =
2268 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2270 ret = amdgpu_si_copy_bytes_to_smc(adev,
2271 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2272 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2273 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2279 if (si_pi->enable_ppm) {
2280 papm_parm = &si_pi->papm_parm;
2281 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2282 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2283 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2284 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2285 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2286 papm_parm->PlatformPowerLimit = 0xffffffff;
2287 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2289 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2291 sizeof(PP_SIslands_PAPMParameters),
2300 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2301 struct amdgpu_ps *amdgpu_state)
2303 struct ni_power_info *ni_pi = ni_get_pi(adev);
2304 struct si_power_info *si_pi = si_get_pi(adev);
2306 if (ni_pi->enable_power_containment) {
2307 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2308 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2311 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2313 smc_table->dpm2Params.NearTDPLimit =
2314 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2315 smc_table->dpm2Params.SafePowerLimit =
2316 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2318 ret = amdgpu_si_copy_bytes_to_smc(adev,
2319 (si_pi->state_table_start +
2320 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2321 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2322 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2332 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2333 const u16 prev_std_vddc,
2334 const u16 curr_std_vddc)
2336 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2337 u64 prev_vddc = (u64)prev_std_vddc;
2338 u64 curr_vddc = (u64)curr_std_vddc;
2339 u64 pwr_efficiency_ratio, n, d;
2341 if ((prev_vddc == 0) || (curr_vddc == 0))
2344 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2345 d = prev_vddc * prev_vddc;
2346 pwr_efficiency_ratio = div64_u64(n, d);
2348 if (pwr_efficiency_ratio > (u64)0xFFFF)
2351 return (u16)pwr_efficiency_ratio;
2354 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2355 struct amdgpu_ps *amdgpu_state)
2357 struct si_power_info *si_pi = si_get_pi(adev);
2359 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2360 amdgpu_state->vclk && amdgpu_state->dclk)
2366 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2368 struct evergreen_power_info *pi = adev->pm.dpm.priv;
2373 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2374 struct amdgpu_ps *amdgpu_state,
2375 SISLANDS_SMC_SWSTATE *smc_state)
2377 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2378 struct ni_power_info *ni_pi = ni_get_pi(adev);
2379 struct si_ps *state = si_get_ps(amdgpu_state);
2380 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2387 u16 pwr_efficiency_ratio;
2389 bool disable_uvd_power_tune;
2392 if (ni_pi->enable_power_containment == false)
2395 if (state->performance_level_count == 0)
2398 if (smc_state->levelCount != state->performance_level_count)
2401 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2403 smc_state->levels[0].dpm2.MaxPS = 0;
2404 smc_state->levels[0].dpm2.NearTDPDec = 0;
2405 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2406 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2407 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2409 for (i = 1; i < state->performance_level_count; i++) {
2410 prev_sclk = state->performance_levels[i-1].sclk;
2411 max_sclk = state->performance_levels[i].sclk;
2413 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2415 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2417 if (prev_sclk > max_sclk)
2420 if ((max_ps_percent == 0) ||
2421 (prev_sclk == max_sclk) ||
2422 disable_uvd_power_tune)
2423 min_sclk = max_sclk;
2425 min_sclk = prev_sclk;
2427 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2429 if (min_sclk < state->performance_levels[0].sclk)
2430 min_sclk = state->performance_levels[0].sclk;
2435 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2436 state->performance_levels[i-1].vddc, &vddc);
2440 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2444 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2445 state->performance_levels[i].vddc, &vddc);
2449 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2453 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2454 prev_std_vddc, curr_std_vddc);
2456 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2457 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2458 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2459 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2460 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2466 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2467 struct amdgpu_ps *amdgpu_state,
2468 SISLANDS_SMC_SWSTATE *smc_state)
2470 struct ni_power_info *ni_pi = ni_get_pi(adev);
2471 struct si_ps *state = si_get_ps(amdgpu_state);
2472 u32 sq_power_throttle, sq_power_throttle2;
2473 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2476 if (state->performance_level_count == 0)
2479 if (smc_state->levelCount != state->performance_level_count)
2482 if (adev->pm.dpm.sq_ramping_threshold == 0)
2485 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2486 enable_sq_ramping = false;
2488 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2489 enable_sq_ramping = false;
2491 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2492 enable_sq_ramping = false;
2494 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2495 enable_sq_ramping = false;
2497 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2498 enable_sq_ramping = false;
2500 for (i = 0; i < state->performance_level_count; i++) {
2501 sq_power_throttle = 0;
2502 sq_power_throttle2 = 0;
2504 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2505 enable_sq_ramping) {
2506 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2507 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2508 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2509 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2510 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2512 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2513 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2516 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2517 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2523 static int si_enable_power_containment(struct amdgpu_device *adev,
2524 struct amdgpu_ps *amdgpu_new_state,
2527 struct ni_power_info *ni_pi = ni_get_pi(adev);
2528 PPSMC_Result smc_result;
2531 if (ni_pi->enable_power_containment) {
2533 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2534 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2535 if (smc_result != PPSMC_Result_OK) {
2537 ni_pi->pc_enabled = false;
2539 ni_pi->pc_enabled = true;
2543 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2544 if (smc_result != PPSMC_Result_OK)
2546 ni_pi->pc_enabled = false;
2553 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2555 struct si_power_info *si_pi = si_get_pi(adev);
2557 struct si_dte_data *dte_data = &si_pi->dte_data;
2558 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2563 if (dte_data == NULL)
2564 si_pi->enable_dte = false;
2566 if (si_pi->enable_dte == false)
2569 if (dte_data->k <= 0)
2572 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2573 if (dte_tables == NULL) {
2574 si_pi->enable_dte = false;
2578 table_size = dte_data->k;
2580 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2581 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2583 tdep_count = dte_data->tdep_count;
2584 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2585 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2587 dte_tables->K = cpu_to_be32(table_size);
2588 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2589 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2590 dte_tables->WindowSize = dte_data->window_size;
2591 dte_tables->temp_select = dte_data->temp_select;
2592 dte_tables->DTE_mode = dte_data->dte_mode;
2593 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2598 for (i = 0; i < table_size; i++) {
2599 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2600 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2603 dte_tables->Tdep_count = tdep_count;
2605 for (i = 0; i < (u32)tdep_count; i++) {
2606 dte_tables->T_limits[i] = dte_data->t_limits[i];
2607 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2608 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2611 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2613 sizeof(Smc_SIslands_DTE_Configuration),
2620 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2623 struct si_power_info *si_pi = si_get_pi(adev);
2624 struct amdgpu_cac_leakage_table *table =
2625 &adev->pm.dpm.dyn_state.cac_leakage_table;
2635 for (i = 0; i < table->count; i++) {
2636 if (table->entries[i].vddc > *max)
2637 *max = table->entries[i].vddc;
2638 if (table->entries[i].vddc < *min)
2639 *min = table->entries[i].vddc;
2642 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2645 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2647 if (v0_loadline > 0xFFFFUL)
2650 *min = (u16)v0_loadline;
2652 if ((*min > *max) || (*max == 0) || (*min == 0))
2658 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2660 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2661 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2664 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2665 PP_SIslands_CacConfig *cac_tables,
2666 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2669 struct si_power_info *si_pi = si_get_pi(adev);
2677 scaling_factor = si_get_smc_power_scaling_factor(adev);
2679 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2680 t = (1000 * (i * t_step + t0));
2682 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2683 voltage = vddc_max - (vddc_step * j);
2685 si_calculate_leakage_for_v_and_t(adev,
2686 &si_pi->powertune_data->leakage_coefficients,
2689 si_pi->dyn_powertune_data.cac_leakage,
2692 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2694 if (smc_leakage > 0xFFFF)
2695 smc_leakage = 0xFFFF;
2697 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2698 cpu_to_be16((u16)smc_leakage);
2704 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2705 PP_SIslands_CacConfig *cac_tables,
2706 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2708 struct si_power_info *si_pi = si_get_pi(adev);
2715 scaling_factor = si_get_smc_power_scaling_factor(adev);
2717 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2718 voltage = vddc_max - (vddc_step * j);
2720 si_calculate_leakage_for_v(adev,
2721 &si_pi->powertune_data->leakage_coefficients,
2722 si_pi->powertune_data->fixed_kt,
2724 si_pi->dyn_powertune_data.cac_leakage,
2727 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2729 if (smc_leakage > 0xFFFF)
2730 smc_leakage = 0xFFFF;
2732 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2733 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2734 cpu_to_be16((u16)smc_leakage);
2739 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2741 struct ni_power_info *ni_pi = ni_get_pi(adev);
2742 struct si_power_info *si_pi = si_get_pi(adev);
2743 PP_SIslands_CacConfig *cac_tables = NULL;
2744 u16 vddc_max, vddc_min, vddc_step;
2746 u32 load_line_slope, reg;
2748 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2750 if (ni_pi->enable_cac == false)
2753 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2757 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2758 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2759 WREG32(CG_CAC_CTRL, reg);
2761 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2762 si_pi->dyn_powertune_data.dc_pwr_value =
2763 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2764 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2765 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2767 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2769 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2773 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2774 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2778 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2779 ret = si_init_dte_leakage_table(adev, cac_tables,
2780 vddc_max, vddc_min, vddc_step,
2783 ret = si_init_simplified_leakage_table(adev, cac_tables,
2784 vddc_max, vddc_min, vddc_step);
2788 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2790 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2791 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2792 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2793 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2794 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2795 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2796 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2797 cac_tables->calculation_repeats = cpu_to_be32(2);
2798 cac_tables->dc_cac = cpu_to_be32(0);
2799 cac_tables->log2_PG_LKG_SCALE = 12;
2800 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2801 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2802 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2804 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2806 sizeof(PP_SIslands_CacConfig),
2812 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2816 ni_pi->enable_cac = false;
2817 ni_pi->enable_power_containment = false;
2825 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2826 const struct si_cac_config_reg *cac_config_regs)
2828 const struct si_cac_config_reg *config_regs = cac_config_regs;
2829 u32 data = 0, offset;
2834 while (config_regs->offset != 0xFFFFFFFF) {
2835 switch (config_regs->type) {
2836 case SISLANDS_CACCONFIG_CGIND:
2837 offset = SMC_CG_IND_START + config_regs->offset;
2838 if (offset < SMC_CG_IND_END)
2839 data = RREG32_SMC(offset);
2842 data = RREG32(config_regs->offset);
2846 data &= ~config_regs->mask;
2847 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2849 switch (config_regs->type) {
2850 case SISLANDS_CACCONFIG_CGIND:
2851 offset = SMC_CG_IND_START + config_regs->offset;
2852 if (offset < SMC_CG_IND_END)
2853 WREG32_SMC(offset, data);
2856 WREG32(config_regs->offset, data);
2864 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2866 struct ni_power_info *ni_pi = ni_get_pi(adev);
2867 struct si_power_info *si_pi = si_get_pi(adev);
2870 if ((ni_pi->enable_cac == false) ||
2871 (ni_pi->cac_configuration_required == false))
2874 ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2877 ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2880 ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2887 static int si_enable_smc_cac(struct amdgpu_device *adev,
2888 struct amdgpu_ps *amdgpu_new_state,
2891 struct ni_power_info *ni_pi = ni_get_pi(adev);
2892 struct si_power_info *si_pi = si_get_pi(adev);
2893 PPSMC_Result smc_result;
2896 if (ni_pi->enable_cac) {
2898 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2899 if (ni_pi->support_cac_long_term_average) {
2900 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2901 if (smc_result != PPSMC_Result_OK)
2902 ni_pi->support_cac_long_term_average = false;
2905 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2906 if (smc_result != PPSMC_Result_OK) {
2908 ni_pi->cac_enabled = false;
2910 ni_pi->cac_enabled = true;
2913 if (si_pi->enable_dte) {
2914 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2915 if (smc_result != PPSMC_Result_OK)
2919 } else if (ni_pi->cac_enabled) {
2920 if (si_pi->enable_dte)
2921 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2923 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2925 ni_pi->cac_enabled = false;
2927 if (ni_pi->support_cac_long_term_average)
2928 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2934 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2936 struct ni_power_info *ni_pi = ni_get_pi(adev);
2937 struct si_power_info *si_pi = si_get_pi(adev);
2938 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2939 SISLANDS_SMC_SCLK_VALUE sclk_params;
2947 if (si_pi->spll_table_start == 0)
2950 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2951 if (spll_table == NULL)
2954 for (i = 0; i < 256; i++) {
2955 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2958 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2959 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2960 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2961 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2963 fb_div &= ~0x00001FFF;
2967 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2969 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2971 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2973 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2979 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2980 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2981 spll_table->freq[i] = cpu_to_be32(tmp);
2983 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2984 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2985 spll_table->ss[i] = cpu_to_be32(tmp);
2992 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
2994 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2998 ni_pi->enable_power_containment = false;
3005 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3008 u16 highest_leakage = 0;
3009 struct si_power_info *si_pi = si_get_pi(adev);
3012 for (i = 0; i < si_pi->leakage_voltage.count; i++){
3013 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3014 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3017 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3018 return highest_leakage;
3023 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3024 u32 evclk, u32 ecclk, u16 *voltage)
3028 struct amdgpu_vce_clock_voltage_dependency_table *table =
3029 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3031 if (((evclk == 0) && (ecclk == 0)) ||
3032 (table && (table->count == 0))) {
3037 for (i = 0; i < table->count; i++) {
3038 if ((evclk <= table->entries[i].evclk) &&
3039 (ecclk <= table->entries[i].ecclk)) {
3040 *voltage = table->entries[i].v;
3046 /* if no match return the highest voltage */
3048 *voltage = table->entries[table->count - 1].v;
3050 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3055 static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
3058 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3059 /* we never hit the non-gddr5 limit so disable it */
3060 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3062 if (vblank_time < switch_limit)
3069 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3070 u32 arb_freq_src, u32 arb_freq_dest)
3072 u32 mc_arb_dram_timing;
3073 u32 mc_arb_dram_timing2;
3077 switch (arb_freq_src) {
3078 case MC_CG_ARB_FREQ_F0:
3079 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
3080 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3081 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3083 case MC_CG_ARB_FREQ_F1:
3084 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
3085 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3086 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3088 case MC_CG_ARB_FREQ_F2:
3089 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
3090 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3091 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3093 case MC_CG_ARB_FREQ_F3:
3094 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
3095 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3096 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3102 switch (arb_freq_dest) {
3103 case MC_CG_ARB_FREQ_F0:
3104 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3105 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3106 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3108 case MC_CG_ARB_FREQ_F1:
3109 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3110 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3111 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3113 case MC_CG_ARB_FREQ_F2:
3114 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3115 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3116 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3118 case MC_CG_ARB_FREQ_F3:
3119 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3120 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3121 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3127 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3128 WREG32(MC_CG_CONFIG, mc_cg_config);
3129 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3134 static void ni_update_current_ps(struct amdgpu_device *adev,
3135 struct amdgpu_ps *rps)
3137 struct si_ps *new_ps = si_get_ps(rps);
3138 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3139 struct ni_power_info *ni_pi = ni_get_pi(adev);
3141 eg_pi->current_rps = *rps;
3142 ni_pi->current_ps = *new_ps;
3143 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3144 adev->pm.dpm.current_ps = &eg_pi->current_rps;
3147 static void ni_update_requested_ps(struct amdgpu_device *adev,
3148 struct amdgpu_ps *rps)
3150 struct si_ps *new_ps = si_get_ps(rps);
3151 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3152 struct ni_power_info *ni_pi = ni_get_pi(adev);
3154 eg_pi->requested_rps = *rps;
3155 ni_pi->requested_ps = *new_ps;
3156 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3157 adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3160 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3161 struct amdgpu_ps *new_ps,
3162 struct amdgpu_ps *old_ps)
3164 struct si_ps *new_state = si_get_ps(new_ps);
3165 struct si_ps *current_state = si_get_ps(old_ps);
3167 if ((new_ps->vclk == old_ps->vclk) &&
3168 (new_ps->dclk == old_ps->dclk))
3171 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3172 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3175 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3178 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3179 struct amdgpu_ps *new_ps,
3180 struct amdgpu_ps *old_ps)
3182 struct si_ps *new_state = si_get_ps(new_ps);
3183 struct si_ps *current_state = si_get_ps(old_ps);
3185 if ((new_ps->vclk == old_ps->vclk) &&
3186 (new_ps->dclk == old_ps->dclk))
3189 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3190 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3193 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3196 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3200 for (i = 0; i < table->count; i++)
3201 if (voltage <= table->entries[i].value)
3202 return table->entries[i].value;
3204 return table->entries[table->count - 1].value;
3207 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3208 u32 max_clock, u32 requested_clock)
3212 if ((clocks == NULL) || (clocks->count == 0))
3213 return (requested_clock < max_clock) ? requested_clock : max_clock;
3215 for (i = 0; i < clocks->count; i++) {
3216 if (clocks->values[i] >= requested_clock)
3217 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3220 return (clocks->values[clocks->count - 1] < max_clock) ?
3221 clocks->values[clocks->count - 1] : max_clock;
3224 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3225 u32 max_mclk, u32 requested_mclk)
3227 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3228 max_mclk, requested_mclk);
3231 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3232 u32 max_sclk, u32 requested_sclk)
3234 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3235 max_sclk, requested_sclk);
3238 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3243 if ((table == NULL) || (table->count == 0)) {
3248 for (i = 0; i < table->count; i++) {
3249 if (clock < table->entries[i].clk)
3250 clock = table->entries[i].clk;
3255 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3256 u32 clock, u16 max_voltage, u16 *voltage)
3260 if ((table == NULL) || (table->count == 0))
3263 for (i= 0; i < table->count; i++) {
3264 if (clock <= table->entries[i].clk) {
3265 if (*voltage < table->entries[i].v)
3266 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3267 table->entries[i].v : max_voltage);
3272 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3275 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3276 const struct amdgpu_clock_and_voltage_limits *max_limits,
3277 struct rv7xx_pl *pl)
3280 if ((pl->mclk == 0) || (pl->sclk == 0))
3283 if (pl->mclk == pl->sclk)
3286 if (pl->mclk > pl->sclk) {
3287 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3288 pl->sclk = btc_get_valid_sclk(adev,
3291 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3292 adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3294 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3295 pl->mclk = btc_get_valid_mclk(adev,
3298 adev->pm.dpm.dyn_state.sclk_mclk_delta);
3302 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3303 u16 max_vddc, u16 max_vddci,
3304 u16 *vddc, u16 *vddci)
3306 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3309 if ((0 == *vddc) || (0 == *vddci))
3312 if (*vddc > *vddci) {
3313 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3314 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3315 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3316 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3319 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3320 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3321 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3322 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3327 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3334 i_c = (i * r_c) / 100;
3343 *p = i_c / (1 << (2 * (*u)));
3346 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3351 if ((fl == 0) || (fh == 0) || (fl > fh))
3354 k = (100 * fh) / fl;
3355 t1 = (t * (k - 100));
3356 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3358 ah = ((a * t) + 5000) / 10000;
3367 static bool r600_is_uvd_state(u32 class, u32 class2)
3369 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3371 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3373 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3375 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3377 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3382 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3384 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3387 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3389 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3392 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3395 pi->max_vddc = vddc;
3398 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3400 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3401 struct amdgpu_atom_ss ss;
3403 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3404 ASIC_INTERNAL_ENGINE_SS, 0);
3405 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3406 ASIC_INTERNAL_MEMORY_SS, 0);
3408 if (pi->sclk_ss || pi->mclk_ss)
3409 pi->dynamic_ss = true;
3411 pi->dynamic_ss = false;
3415 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3416 struct amdgpu_ps *rps)
3418 struct si_ps *ps = si_get_ps(rps);
3419 struct amdgpu_clock_and_voltage_limits *max_limits;
3420 bool disable_mclk_switching = false;
3421 bool disable_sclk_switching = false;
3423 u16 vddc, vddci, min_vce_voltage = 0;
3424 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3425 u32 max_sclk = 0, max_mclk = 0;
3428 if (adev->asic_type == CHIP_HAINAN) {
3429 if ((adev->pdev->revision == 0x81) ||
3430 (adev->pdev->revision == 0x83) ||
3431 (adev->pdev->revision == 0xC3) ||
3432 (adev->pdev->device == 0x6664) ||
3433 (adev->pdev->device == 0x6665) ||
3434 (adev->pdev->device == 0x6667)) {
3437 if ((adev->pdev->revision == 0xC3) ||
3438 (adev->pdev->device == 0x6665)) {
3442 } else if (adev->asic_type == CHIP_OLAND) {
3443 if ((adev->pdev->revision == 0xC7) ||
3444 (adev->pdev->revision == 0x80) ||
3445 (adev->pdev->revision == 0x81) ||
3446 (adev->pdev->revision == 0x83) ||
3447 (adev->pdev->revision == 0x87) ||
3448 (adev->pdev->device == 0x6604) ||
3449 (adev->pdev->device == 0x6605)) {
3454 if (rps->vce_active) {
3455 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3456 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3457 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3464 if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3465 si_dpm_vblank_too_short(adev))
3466 disable_mclk_switching = true;
3468 if (rps->vclk || rps->dclk) {
3469 disable_mclk_switching = true;
3470 disable_sclk_switching = true;
3473 if (adev->pm.dpm.ac_power)
3474 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3476 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3478 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3479 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3480 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3482 if (adev->pm.dpm.ac_power == false) {
3483 for (i = 0; i < ps->performance_level_count; i++) {
3484 if (ps->performance_levels[i].mclk > max_limits->mclk)
3485 ps->performance_levels[i].mclk = max_limits->mclk;
3486 if (ps->performance_levels[i].sclk > max_limits->sclk)
3487 ps->performance_levels[i].sclk = max_limits->sclk;
3488 if (ps->performance_levels[i].vddc > max_limits->vddc)
3489 ps->performance_levels[i].vddc = max_limits->vddc;
3490 if (ps->performance_levels[i].vddci > max_limits->vddci)
3491 ps->performance_levels[i].vddci = max_limits->vddci;
3495 /* limit clocks to max supported clocks based on voltage dependency tables */
3496 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3498 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3500 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3503 for (i = 0; i < ps->performance_level_count; i++) {
3504 if (max_sclk_vddc) {
3505 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3506 ps->performance_levels[i].sclk = max_sclk_vddc;
3508 if (max_mclk_vddci) {
3509 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3510 ps->performance_levels[i].mclk = max_mclk_vddci;
3512 if (max_mclk_vddc) {
3513 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3514 ps->performance_levels[i].mclk = max_mclk_vddc;
3517 if (ps->performance_levels[i].mclk > max_mclk)
3518 ps->performance_levels[i].mclk = max_mclk;
3521 if (ps->performance_levels[i].sclk > max_sclk)
3522 ps->performance_levels[i].sclk = max_sclk;
3526 /* XXX validate the min clocks required for display */
3528 if (disable_mclk_switching) {
3529 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3530 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3532 mclk = ps->performance_levels[0].mclk;
3533 vddci = ps->performance_levels[0].vddci;
3536 if (disable_sclk_switching) {
3537 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3538 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3540 sclk = ps->performance_levels[0].sclk;
3541 vddc = ps->performance_levels[0].vddc;
3544 if (rps->vce_active) {
3545 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3546 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3547 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3548 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3551 /* adjusted low state */
3552 ps->performance_levels[0].sclk = sclk;
3553 ps->performance_levels[0].mclk = mclk;
3554 ps->performance_levels[0].vddc = vddc;
3555 ps->performance_levels[0].vddci = vddci;
3557 if (disable_sclk_switching) {
3558 sclk = ps->performance_levels[0].sclk;
3559 for (i = 1; i < ps->performance_level_count; i++) {
3560 if (sclk < ps->performance_levels[i].sclk)
3561 sclk = ps->performance_levels[i].sclk;
3563 for (i = 0; i < ps->performance_level_count; i++) {
3564 ps->performance_levels[i].sclk = sclk;
3565 ps->performance_levels[i].vddc = vddc;
3568 for (i = 1; i < ps->performance_level_count; i++) {
3569 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3570 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3571 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3572 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3576 if (disable_mclk_switching) {
3577 mclk = ps->performance_levels[0].mclk;
3578 for (i = 1; i < ps->performance_level_count; i++) {
3579 if (mclk < ps->performance_levels[i].mclk)
3580 mclk = ps->performance_levels[i].mclk;
3582 for (i = 0; i < ps->performance_level_count; i++) {
3583 ps->performance_levels[i].mclk = mclk;
3584 ps->performance_levels[i].vddci = vddci;
3587 for (i = 1; i < ps->performance_level_count; i++) {
3588 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3589 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3590 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3591 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3595 for (i = 0; i < ps->performance_level_count; i++)
3596 btc_adjust_clock_combinations(adev, max_limits,
3597 &ps->performance_levels[i]);
3599 for (i = 0; i < ps->performance_level_count; i++) {
3600 if (ps->performance_levels[i].vddc < min_vce_voltage)
3601 ps->performance_levels[i].vddc = min_vce_voltage;
3602 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3603 ps->performance_levels[i].sclk,
3604 max_limits->vddc, &ps->performance_levels[i].vddc);
3605 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3606 ps->performance_levels[i].mclk,
3607 max_limits->vddci, &ps->performance_levels[i].vddci);
3608 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3609 ps->performance_levels[i].mclk,
3610 max_limits->vddc, &ps->performance_levels[i].vddc);
3611 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3612 adev->clock.current_dispclk,
3613 max_limits->vddc, &ps->performance_levels[i].vddc);
3616 for (i = 0; i < ps->performance_level_count; i++) {
3617 btc_apply_voltage_delta_rules(adev,
3618 max_limits->vddc, max_limits->vddci,
3619 &ps->performance_levels[i].vddc,
3620 &ps->performance_levels[i].vddci);
3623 ps->dc_compatible = true;
3624 for (i = 0; i < ps->performance_level_count; i++) {
3625 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3626 ps->dc_compatible = false;
3631 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3632 u16 reg_offset, u32 *value)
3634 struct si_power_info *si_pi = si_get_pi(adev);
3636 return amdgpu_si_read_smc_sram_dword(adev,
3637 si_pi->soft_regs_start + reg_offset, value,
3642 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3643 u16 reg_offset, u32 value)
3645 struct si_power_info *si_pi = si_get_pi(adev);
3647 return amdgpu_si_write_smc_sram_dword(adev,
3648 si_pi->soft_regs_start + reg_offset,
3649 value, si_pi->sram_end);
3652 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3655 u32 tmp, width, row, column, bank, density;
3656 bool is_memory_gddr5, is_special;
3658 tmp = RREG32(MC_SEQ_MISC0);
3659 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3660 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3661 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3663 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3664 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3666 tmp = RREG32(MC_ARB_RAMCFG);
3667 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3668 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3669 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3671 density = (1 << (row + column - 20 + bank)) * width;
3673 if ((adev->pdev->device == 0x6819) &&
3674 is_memory_gddr5 && is_special && (density == 0x400))
3680 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3682 struct si_power_info *si_pi = si_get_pi(adev);
3683 u16 vddc, count = 0;
3686 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3687 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3689 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3690 si_pi->leakage_voltage.entries[count].voltage = vddc;
3691 si_pi->leakage_voltage.entries[count].leakage_index =
3692 SISLANDS_LEAKAGE_INDEX0 + i;
3696 si_pi->leakage_voltage.count = count;
3699 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3700 u32 index, u16 *leakage_voltage)
3702 struct si_power_info *si_pi = si_get_pi(adev);
3705 if (leakage_voltage == NULL)
3708 if ((index & 0xff00) != 0xff00)
3711 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3714 if (index < SISLANDS_LEAKAGE_INDEX0)
3717 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3718 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3719 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3726 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3728 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3729 bool want_thermal_protection;
3730 enum amdgpu_dpm_event_src dpm_event_src;
3735 want_thermal_protection = false;
3737 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3738 want_thermal_protection = true;
3739 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3741 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3742 want_thermal_protection = true;
3743 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3745 case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3746 (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3747 want_thermal_protection = true;
3748 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3752 if (want_thermal_protection) {
3753 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3754 if (pi->thermal_protection)
3755 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3757 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3761 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3762 enum amdgpu_dpm_auto_throttle_src source,
3765 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3768 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3769 pi->active_auto_throttle_sources |= 1 << source;
3770 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3773 if (pi->active_auto_throttle_sources & (1 << source)) {
3774 pi->active_auto_throttle_sources &= ~(1 << source);
3775 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3780 static void si_start_dpm(struct amdgpu_device *adev)
3782 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3785 static void si_stop_dpm(struct amdgpu_device *adev)
3787 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3790 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3793 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3795 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3800 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3805 if (thermal_level == 0) {
3806 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3807 if (ret == PPSMC_Result_OK)
3815 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3817 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3822 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3825 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3832 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3833 PPSMC_Msg msg, u32 parameter)
3835 WREG32(SMC_SCRATCH0, parameter);
3836 return amdgpu_si_send_msg_to_smc(adev, msg);
3839 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3841 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3844 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3848 static int si_dpm_force_performance_level(struct amdgpu_device *adev,
3849 enum amd_dpm_forced_level level)
3851 struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3852 struct si_ps *ps = si_get_ps(rps);
3853 u32 levels = ps->performance_level_count;
3855 if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
3856 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3859 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3861 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
3862 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3865 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3867 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
3868 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3871 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3875 adev->pm.dpm.forced_level = level;
3881 static int si_set_boot_state(struct amdgpu_device *adev)
3883 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3888 static int si_set_sw_state(struct amdgpu_device *adev)
3890 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3894 static int si_halt_smc(struct amdgpu_device *adev)
3896 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3899 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3903 static int si_resume_smc(struct amdgpu_device *adev)
3905 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3908 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3912 static void si_dpm_start_smc(struct amdgpu_device *adev)
3914 amdgpu_si_program_jump_on_start(adev);
3915 amdgpu_si_start_smc(adev);
3916 amdgpu_si_smc_clock(adev, true);
3919 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3921 amdgpu_si_reset_smc(adev);
3922 amdgpu_si_smc_clock(adev, false);
3925 static int si_process_firmware_header(struct amdgpu_device *adev)
3927 struct si_power_info *si_pi = si_get_pi(adev);
3931 ret = amdgpu_si_read_smc_sram_dword(adev,
3932 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3933 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3934 &tmp, si_pi->sram_end);
3938 si_pi->state_table_start = tmp;
3940 ret = amdgpu_si_read_smc_sram_dword(adev,
3941 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3942 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3943 &tmp, si_pi->sram_end);
3947 si_pi->soft_regs_start = tmp;
3949 ret = amdgpu_si_read_smc_sram_dword(adev,
3950 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3951 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3952 &tmp, si_pi->sram_end);
3956 si_pi->mc_reg_table_start = tmp;
3958 ret = amdgpu_si_read_smc_sram_dword(adev,
3959 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3960 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3961 &tmp, si_pi->sram_end);
3965 si_pi->fan_table_start = tmp;
3967 ret = amdgpu_si_read_smc_sram_dword(adev,
3968 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3969 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3970 &tmp, si_pi->sram_end);
3974 si_pi->arb_table_start = tmp;
3976 ret = amdgpu_si_read_smc_sram_dword(adev,
3977 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3978 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3979 &tmp, si_pi->sram_end);
3983 si_pi->cac_table_start = tmp;
3985 ret = amdgpu_si_read_smc_sram_dword(adev,
3986 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3987 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3988 &tmp, si_pi->sram_end);
3992 si_pi->dte_table_start = tmp;
3994 ret = amdgpu_si_read_smc_sram_dword(adev,
3995 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3996 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3997 &tmp, si_pi->sram_end);
4001 si_pi->spll_table_start = tmp;
4003 ret = amdgpu_si_read_smc_sram_dword(adev,
4004 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4005 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4006 &tmp, si_pi->sram_end);
4010 si_pi->papm_cfg_table_start = tmp;
4015 static void si_read_clock_registers(struct amdgpu_device *adev)
4017 struct si_power_info *si_pi = si_get_pi(adev);
4019 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4020 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4021 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4022 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4023 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4024 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4025 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4026 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4027 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4028 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4029 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4030 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4031 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4032 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4033 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4036 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4040 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4042 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4045 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4047 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4051 static int si_enter_ulp_state(struct amdgpu_device *adev)
4053 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4060 static int si_exit_ulp_state(struct amdgpu_device *adev)
4064 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4068 for (i = 0; i < adev->usec_timeout; i++) {
4069 if (RREG32(SMC_RESP_0) == 1)
4078 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4081 PPSMC_Msg msg = has_display ?
4082 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4084 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4088 static void si_program_response_times(struct amdgpu_device *adev)
4090 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4091 u32 vddc_dly, acpi_dly, vbi_dly;
4092 u32 reference_clock;
4094 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4096 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4097 backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
4099 if (voltage_response_time == 0)
4100 voltage_response_time = 1000;
4102 acpi_delay_time = 15000;
4103 vbi_time_out = 100000;
4105 reference_clock = amdgpu_asic_get_xclk(adev);
4107 vddc_dly = (voltage_response_time * reference_clock) / 100;
4108 acpi_dly = (acpi_delay_time * reference_clock) / 100;
4109 vbi_dly = (vbi_time_out * reference_clock) / 100;
4111 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
4112 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
4113 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4114 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4117 static void si_program_ds_registers(struct amdgpu_device *adev)
4119 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4122 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4123 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4128 if (eg_pi->sclk_deep_sleep) {
4129 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4130 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4131 ~AUTOSCALE_ON_SS_CLEAR);
4135 static void si_program_display_gap(struct amdgpu_device *adev)
4140 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4141 if (adev->pm.dpm.new_active_crtc_count > 0)
4142 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4144 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4146 if (adev->pm.dpm.new_active_crtc_count > 1)
4147 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4149 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4151 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4153 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4154 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4156 if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4157 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4158 /* find the first active crtc */
4159 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4160 if (adev->pm.dpm.new_active_crtcs & (1 << i))
4163 if (i == adev->mode_info.num_crtc)
4168 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4169 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4170 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4173 /* Setting this to false forces the performance state to low if the crtcs are disabled.
4174 * This can be a problem on PowerXpress systems or if you want to use the card
4175 * for offscreen rendering or compute if there are no crtcs enabled.
4177 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4180 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4182 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4186 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4188 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4189 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4193 static void si_setup_bsp(struct amdgpu_device *adev)
4195 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4196 u32 xclk = amdgpu_asic_get_xclk(adev);
4198 r600_calculate_u_and_p(pi->asi,
4204 r600_calculate_u_and_p(pi->pasi,
4211 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4212 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4214 WREG32(CG_BSP, pi->dsp);
4217 static void si_program_git(struct amdgpu_device *adev)
4219 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4222 static void si_program_tp(struct amdgpu_device *adev)
4225 enum r600_td td = R600_TD_DFLT;
4227 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4228 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4230 if (td == R600_TD_AUTO)
4231 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4233 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4235 if (td == R600_TD_UP)
4236 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4238 if (td == R600_TD_DOWN)
4239 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4242 static void si_program_tpp(struct amdgpu_device *adev)
4244 WREG32(CG_TPC, R600_TPC_DFLT);
4247 static void si_program_sstp(struct amdgpu_device *adev)
4249 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4252 static void si_enable_display_gap(struct amdgpu_device *adev)
4254 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4256 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4257 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4258 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4260 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4261 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4262 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4263 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4266 static void si_program_vc(struct amdgpu_device *adev)
4268 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4270 WREG32(CG_FTV, pi->vrc);
4273 static void si_clear_vc(struct amdgpu_device *adev)
4278 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4282 if (memory_clock < 10000)
4284 else if (memory_clock >= 80000)
4285 mc_para_index = 0x0f;
4287 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4288 return mc_para_index;
4291 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4296 if (memory_clock < 12500)
4297 mc_para_index = 0x00;
4298 else if (memory_clock > 47500)
4299 mc_para_index = 0x0f;
4301 mc_para_index = (u8)((memory_clock - 10000) / 2500);
4303 if (memory_clock < 65000)
4304 mc_para_index = 0x00;
4305 else if (memory_clock > 135000)
4306 mc_para_index = 0x0f;
4308 mc_para_index = (u8)((memory_clock - 60000) / 5000);
4310 return mc_para_index;
4313 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4315 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4316 bool strobe_mode = false;
4319 if (mclk <= pi->mclk_strobe_mode_threshold)
4322 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4323 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4325 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4328 result |= SISLANDS_SMC_STROBE_ENABLE;
4333 static int si_upload_firmware(struct amdgpu_device *adev)
4335 struct si_power_info *si_pi = si_get_pi(adev);
4337 amdgpu_si_reset_smc(adev);
4338 amdgpu_si_smc_clock(adev, false);
4340 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4343 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4344 const struct atom_voltage_table *table,
4345 const struct amdgpu_phase_shedding_limits_table *limits)
4347 u32 data, num_bits, num_levels;
4349 if ((table == NULL) || (limits == NULL))
4352 data = table->mask_low;
4354 num_bits = hweight32(data);
4359 num_levels = (1 << num_bits);
4361 if (table->count != num_levels)
4364 if (limits->count != (num_levels - 1))
4370 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4371 u32 max_voltage_steps,
4372 struct atom_voltage_table *voltage_table)
4374 unsigned int i, diff;
4376 if (voltage_table->count <= max_voltage_steps)
4379 diff = voltage_table->count - max_voltage_steps;
4381 for (i= 0; i < max_voltage_steps; i++)
4382 voltage_table->entries[i] = voltage_table->entries[i + diff];
4384 voltage_table->count = max_voltage_steps;
4387 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4388 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4389 struct atom_voltage_table *voltage_table)
4393 if (voltage_dependency_table == NULL)
4396 voltage_table->mask_low = 0;
4397 voltage_table->phase_delay = 0;
4399 voltage_table->count = voltage_dependency_table->count;
4400 for (i = 0; i < voltage_table->count; i++) {
4401 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4402 voltage_table->entries[i].smio_low = 0;
4408 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4410 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4411 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4412 struct si_power_info *si_pi = si_get_pi(adev);
4415 if (pi->voltage_control) {
4416 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4417 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4421 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4422 si_trim_voltage_table_to_fit_state_table(adev,
4423 SISLANDS_MAX_NO_VREG_STEPS,
4424 &eg_pi->vddc_voltage_table);
4425 } else if (si_pi->voltage_control_svi2) {
4426 ret = si_get_svi2_voltage_table(adev,
4427 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4428 &eg_pi->vddc_voltage_table);
4435 if (eg_pi->vddci_control) {
4436 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4437 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4441 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4442 si_trim_voltage_table_to_fit_state_table(adev,
4443 SISLANDS_MAX_NO_VREG_STEPS,
4444 &eg_pi->vddci_voltage_table);
4446 if (si_pi->vddci_control_svi2) {
4447 ret = si_get_svi2_voltage_table(adev,
4448 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4449 &eg_pi->vddci_voltage_table);
4454 if (pi->mvdd_control) {
4455 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4456 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4459 pi->mvdd_control = false;
4463 if (si_pi->mvdd_voltage_table.count == 0) {
4464 pi->mvdd_control = false;
4468 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4469 si_trim_voltage_table_to_fit_state_table(adev,
4470 SISLANDS_MAX_NO_VREG_STEPS,
4471 &si_pi->mvdd_voltage_table);
4474 if (si_pi->vddc_phase_shed_control) {
4475 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4476 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4478 si_pi->vddc_phase_shed_control = false;
4480 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4481 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4482 si_pi->vddc_phase_shed_control = false;
4488 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4489 const struct atom_voltage_table *voltage_table,
4490 SISLANDS_SMC_STATETABLE *table)
4494 for (i = 0; i < voltage_table->count; i++)
4495 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4498 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4499 SISLANDS_SMC_STATETABLE *table)
4501 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4502 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4503 struct si_power_info *si_pi = si_get_pi(adev);
4506 if (si_pi->voltage_control_svi2) {
4507 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4508 si_pi->svc_gpio_id);
4509 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4510 si_pi->svd_gpio_id);
4511 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4514 if (eg_pi->vddc_voltage_table.count) {
4515 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4516 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4517 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4519 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4520 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4521 table->maxVDDCIndexInPPTable = i;
4527 if (eg_pi->vddci_voltage_table.count) {
4528 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4530 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4531 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4535 if (si_pi->mvdd_voltage_table.count) {
4536 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4538 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4539 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4542 if (si_pi->vddc_phase_shed_control) {
4543 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4544 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4545 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4547 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4548 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4550 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4551 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4553 si_pi->vddc_phase_shed_control = false;
4561 static int si_populate_voltage_value(struct amdgpu_device *adev,
4562 const struct atom_voltage_table *table,
4563 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4567 for (i = 0; i < table->count; i++) {
4568 if (value <= table->entries[i].value) {
4569 voltage->index = (u8)i;
4570 voltage->value = cpu_to_be16(table->entries[i].value);
4575 if (i >= table->count)
4581 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4582 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4584 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4585 struct si_power_info *si_pi = si_get_pi(adev);
4587 if (pi->mvdd_control) {
4588 if (mclk <= pi->mvdd_split_frequency)
4591 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4593 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4598 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4599 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4603 bool voltage_found = false;
4604 *std_voltage = be16_to_cpu(voltage->value);
4606 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4607 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4608 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4611 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4612 if (be16_to_cpu(voltage->value) ==
4613 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4614 voltage_found = true;
4615 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4617 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4620 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4625 if (!voltage_found) {
4626 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4627 if (be16_to_cpu(voltage->value) <=
4628 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4629 voltage_found = true;
4630 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4632 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4635 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4641 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4642 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4649 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4650 u16 value, u8 index,
4651 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4653 voltage->index = index;
4654 voltage->value = cpu_to_be16(value);
4659 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4660 const struct amdgpu_phase_shedding_limits_table *limits,
4661 u16 voltage, u32 sclk, u32 mclk,
4662 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4666 for (i = 0; i < limits->count; i++) {
4667 if ((voltage <= limits->entries[i].voltage) &&
4668 (sclk <= limits->entries[i].sclk) &&
4669 (mclk <= limits->entries[i].mclk))
4673 smc_voltage->phase_settings = (u8)i;
4678 static int si_init_arb_table_index(struct amdgpu_device *adev)
4680 struct si_power_info *si_pi = si_get_pi(adev);
4684 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4685 &tmp, si_pi->sram_end);
4690 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4692 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4693 tmp, si_pi->sram_end);
4696 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4698 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4701 static int si_reset_to_default(struct amdgpu_device *adev)
4703 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4707 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4709 struct si_power_info *si_pi = si_get_pi(adev);
4713 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4714 &tmp, si_pi->sram_end);
4718 tmp = (tmp >> 24) & 0xff;
4720 if (tmp == MC_CG_ARB_FREQ_F0)
4723 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4726 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4730 u32 dram_refresh_rate;
4731 u32 mc_arb_rfsh_rate;
4732 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4737 dram_rows = 1 << (tmp + 10);
4739 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4740 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4742 return mc_arb_rfsh_rate;
4745 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4746 struct rv7xx_pl *pl,
4747 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4753 arb_regs->mc_arb_rfsh_rate =
4754 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4756 amdgpu_atombios_set_engine_dram_timings(adev,
4760 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4761 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4762 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4764 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4765 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4766 arb_regs->mc_arb_burst_time = (u8)burst_time;
4771 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4772 struct amdgpu_ps *amdgpu_state,
4773 unsigned int first_arb_set)
4775 struct si_power_info *si_pi = si_get_pi(adev);
4776 struct si_ps *state = si_get_ps(amdgpu_state);
4777 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4780 for (i = 0; i < state->performance_level_count; i++) {
4781 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4784 ret = amdgpu_si_copy_bytes_to_smc(adev,
4785 si_pi->arb_table_start +
4786 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4787 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4789 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4798 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4799 struct amdgpu_ps *amdgpu_new_state)
4801 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4802 SISLANDS_DRIVER_STATE_ARB_INDEX);
4805 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4806 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4808 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4809 struct si_power_info *si_pi = si_get_pi(adev);
4811 if (pi->mvdd_control)
4812 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4813 si_pi->mvdd_bootup_value, voltage);
4818 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4819 struct amdgpu_ps *amdgpu_initial_state,
4820 SISLANDS_SMC_STATETABLE *table)
4822 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4823 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4824 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4825 struct si_power_info *si_pi = si_get_pi(adev);
4829 table->initialState.levels[0].mclk.vDLL_CNTL =
4830 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4831 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4832 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4833 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4834 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4835 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4836 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4837 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4838 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4839 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4840 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4841 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4842 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4843 table->initialState.levels[0].mclk.vMPLL_SS =
4844 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4845 table->initialState.levels[0].mclk.vMPLL_SS2 =
4846 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4848 table->initialState.levels[0].mclk.mclk_value =
4849 cpu_to_be32(initial_state->performance_levels[0].mclk);
4851 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4852 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4853 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4854 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4855 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4856 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4857 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4858 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4859 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4860 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4861 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4862 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4864 table->initialState.levels[0].sclk.sclk_value =
4865 cpu_to_be32(initial_state->performance_levels[0].sclk);
4867 table->initialState.levels[0].arbRefreshState =
4868 SISLANDS_INITIAL_STATE_ARB_INDEX;
4870 table->initialState.levels[0].ACIndex = 0;
4872 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4873 initial_state->performance_levels[0].vddc,
4874 &table->initialState.levels[0].vddc);
4879 ret = si_get_std_voltage_value(adev,
4880 &table->initialState.levels[0].vddc,
4883 si_populate_std_voltage_value(adev, std_vddc,
4884 table->initialState.levels[0].vddc.index,
4885 &table->initialState.levels[0].std_vddc);
4888 if (eg_pi->vddci_control)
4889 si_populate_voltage_value(adev,
4890 &eg_pi->vddci_voltage_table,
4891 initial_state->performance_levels[0].vddci,
4892 &table->initialState.levels[0].vddci);
4894 if (si_pi->vddc_phase_shed_control)
4895 si_populate_phase_shedding_value(adev,
4896 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4897 initial_state->performance_levels[0].vddc,
4898 initial_state->performance_levels[0].sclk,
4899 initial_state->performance_levels[0].mclk,
4900 &table->initialState.levels[0].vddc);
4902 si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4904 reg = CG_R(0xffff) | CG_L(0);
4905 table->initialState.levels[0].aT = cpu_to_be32(reg);
4906 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4907 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4909 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4910 table->initialState.levels[0].strobeMode =
4911 si_get_strobe_mode_settings(adev,
4912 initial_state->performance_levels[0].mclk);
4914 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4915 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4917 table->initialState.levels[0].mcFlags = 0;
4920 table->initialState.levelCount = 1;
4922 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4924 table->initialState.levels[0].dpm2.MaxPS = 0;
4925 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4926 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4927 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4928 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4930 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4931 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4933 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4934 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4939 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
4940 SISLANDS_SMC_STATETABLE *table)
4942 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4943 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4944 struct si_power_info *si_pi = si_get_pi(adev);
4945 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4946 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4947 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4948 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4949 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4950 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4951 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4952 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4953 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4954 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4955 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4959 table->ACPIState = table->initialState;
4961 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4963 if (pi->acpi_vddc) {
4964 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4965 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4969 ret = si_get_std_voltage_value(adev,
4970 &table->ACPIState.levels[0].vddc, &std_vddc);
4972 si_populate_std_voltage_value(adev, std_vddc,
4973 table->ACPIState.levels[0].vddc.index,
4974 &table->ACPIState.levels[0].std_vddc);
4976 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4978 if (si_pi->vddc_phase_shed_control) {
4979 si_populate_phase_shedding_value(adev,
4980 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4984 &table->ACPIState.levels[0].vddc);
4987 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4988 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4992 ret = si_get_std_voltage_value(adev,
4993 &table->ACPIState.levels[0].vddc, &std_vddc);
4996 si_populate_std_voltage_value(adev, std_vddc,
4997 table->ACPIState.levels[0].vddc.index,
4998 &table->ACPIState.levels[0].std_vddc);
5000 table->ACPIState.levels[0].gen2PCIE =
5001 (u8)amdgpu_get_pcie_gen_support(adev,
5002 si_pi->sys_pcie_mask,
5003 si_pi->boot_pcie_gen,
5006 if (si_pi->vddc_phase_shed_control)
5007 si_populate_phase_shedding_value(adev,
5008 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5009 pi->min_vddc_in_table,
5012 &table->ACPIState.levels[0].vddc);
5015 if (pi->acpi_vddc) {
5016 if (eg_pi->acpi_vddci)
5017 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5019 &table->ACPIState.levels[0].vddci);
5022 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5023 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5025 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5027 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5028 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5030 table->ACPIState.levels[0].mclk.vDLL_CNTL =
5031 cpu_to_be32(dll_cntl);
5032 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5033 cpu_to_be32(mclk_pwrmgt_cntl);
5034 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5035 cpu_to_be32(mpll_ad_func_cntl);
5036 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5037 cpu_to_be32(mpll_dq_func_cntl);
5038 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5039 cpu_to_be32(mpll_func_cntl);
5040 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5041 cpu_to_be32(mpll_func_cntl_1);
5042 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5043 cpu_to_be32(mpll_func_cntl_2);
5044 table->ACPIState.levels[0].mclk.vMPLL_SS =
5045 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5046 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5047 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5049 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5050 cpu_to_be32(spll_func_cntl);
5051 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5052 cpu_to_be32(spll_func_cntl_2);
5053 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5054 cpu_to_be32(spll_func_cntl_3);
5055 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5056 cpu_to_be32(spll_func_cntl_4);
5058 table->ACPIState.levels[0].mclk.mclk_value = 0;
5059 table->ACPIState.levels[0].sclk.sclk_value = 0;
5061 si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5063 if (eg_pi->dynamic_ac_timing)
5064 table->ACPIState.levels[0].ACIndex = 0;
5066 table->ACPIState.levels[0].dpm2.MaxPS = 0;
5067 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5068 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5069 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5070 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5072 reg = MIN_POWER_MASK | MAX_POWER_MASK;
5073 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5075 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5076 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5081 static int si_populate_ulv_state(struct amdgpu_device *adev,
5082 SISLANDS_SMC_SWSTATE *state)
5084 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5085 struct si_power_info *si_pi = si_get_pi(adev);
5086 struct si_ulv_param *ulv = &si_pi->ulv;
5087 u32 sclk_in_sr = 1350; /* ??? */
5090 ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5093 if (eg_pi->sclk_deep_sleep) {
5094 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5095 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5097 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5099 if (ulv->one_pcie_lane_in_ulv)
5100 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5101 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5102 state->levels[0].ACIndex = 1;
5103 state->levels[0].std_vddc = state->levels[0].vddc;
5104 state->levelCount = 1;
5106 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5112 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5114 struct si_power_info *si_pi = si_get_pi(adev);
5115 struct si_ulv_param *ulv = &si_pi->ulv;
5116 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5119 ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5124 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5125 ulv->volt_change_delay);
5127 ret = amdgpu_si_copy_bytes_to_smc(adev,
5128 si_pi->arb_table_start +
5129 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5130 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5132 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5138 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5140 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5142 pi->mvdd_split_frequency = 30000;
5145 static int si_init_smc_table(struct amdgpu_device *adev)
5147 struct si_power_info *si_pi = si_get_pi(adev);
5148 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5149 const struct si_ulv_param *ulv = &si_pi->ulv;
5150 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
5155 si_populate_smc_voltage_tables(adev, table);
5157 switch (adev->pm.int_thermal_type) {
5158 case THERMAL_TYPE_SI:
5159 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5160 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5162 case THERMAL_TYPE_NONE:
5163 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5166 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5170 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5171 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5173 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5174 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5175 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5178 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5179 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5181 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5182 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5184 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5185 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5187 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5188 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5189 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5190 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5194 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5198 ret = si_populate_smc_acpi_state(adev, table);
5202 table->driverState = table->initialState;
5204 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5205 SISLANDS_INITIAL_STATE_ARB_INDEX);
5209 if (ulv->supported && ulv->pl.vddc) {
5210 ret = si_populate_ulv_state(adev, &table->ULVState);
5214 ret = si_program_ulv_memory_timing_parameters(adev);
5218 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5219 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5221 lane_width = amdgpu_get_pcie_lanes(adev);
5222 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5224 table->ULVState = table->initialState;
5227 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5228 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5232 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5234 SISLANDS_SMC_SCLK_VALUE *sclk)
5236 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5237 struct si_power_info *si_pi = si_get_pi(adev);
5238 struct atom_clock_dividers dividers;
5239 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5240 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5241 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5242 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5243 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5244 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5246 u32 reference_clock = adev->clock.spll.reference_freq;
5247 u32 reference_divider;
5251 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5252 engine_clock, false, ÷rs);
5256 reference_divider = 1 + dividers.ref_div;
5258 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5259 do_div(tmp, reference_clock);
5262 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5263 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5264 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5266 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5267 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5269 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5270 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5271 spll_func_cntl_3 |= SPLL_DITHEN;
5274 struct amdgpu_atom_ss ss;
5275 u32 vco_freq = engine_clock * dividers.post_div;
5277 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5278 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5279 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5280 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5282 cg_spll_spread_spectrum &= ~CLK_S_MASK;
5283 cg_spll_spread_spectrum |= CLK_S(clk_s);
5284 cg_spll_spread_spectrum |= SSEN;
5286 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5287 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5291 sclk->sclk_value = engine_clock;
5292 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5293 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5294 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5295 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5296 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5297 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5302 static int si_populate_sclk_value(struct amdgpu_device *adev,
5304 SISLANDS_SMC_SCLK_VALUE *sclk)
5306 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5309 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5311 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5312 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5313 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5314 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5315 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5316 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5317 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5323 static int si_populate_mclk_value(struct amdgpu_device *adev,
5326 SISLANDS_SMC_MCLK_VALUE *mclk,
5330 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5331 struct si_power_info *si_pi = si_get_pi(adev);
5332 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5333 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5334 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5335 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5336 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5337 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5338 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5339 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5340 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5341 struct atom_mpll_param mpll_param;
5344 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5348 mpll_func_cntl &= ~BWCTRL_MASK;
5349 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5351 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5352 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5353 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5355 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5356 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5358 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5359 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5360 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5361 YCLK_POST_DIV(mpll_param.post_div);
5365 struct amdgpu_atom_ss ss;
5368 u32 reference_clock = adev->clock.mpll.reference_freq;
5370 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5371 freq_nom = memory_clock * 4;
5373 freq_nom = memory_clock * 2;
5375 tmp = freq_nom / reference_clock;
5377 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5378 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5379 u32 clks = reference_clock * 5 / ss.rate;
5380 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5382 mpll_ss1 &= ~CLKV_MASK;
5383 mpll_ss1 |= CLKV(clkv);
5385 mpll_ss2 &= ~CLKS_MASK;
5386 mpll_ss2 |= CLKS(clks);
5390 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5391 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5394 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5396 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5398 mclk->mclk_value = cpu_to_be32(memory_clock);
5399 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5400 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5401 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5402 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5403 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5404 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5405 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5406 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5407 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5412 static void si_populate_smc_sp(struct amdgpu_device *adev,
5413 struct amdgpu_ps *amdgpu_state,
5414 SISLANDS_SMC_SWSTATE *smc_state)
5416 struct si_ps *ps = si_get_ps(amdgpu_state);
5417 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5420 for (i = 0; i < ps->performance_level_count - 1; i++)
5421 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5423 smc_state->levels[ps->performance_level_count - 1].bSP =
5424 cpu_to_be32(pi->psp);
5427 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5428 struct rv7xx_pl *pl,
5429 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5431 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5432 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5433 struct si_power_info *si_pi = si_get_pi(adev);
5437 bool gmc_pg = false;
5439 if (eg_pi->pcie_performance_request &&
5440 (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5441 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5443 level->gen2PCIE = (u8)pl->pcie_gen;
5445 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5451 if (pi->mclk_stutter_mode_threshold &&
5452 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5453 !eg_pi->uvd_enabled &&
5454 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5455 (adev->pm.dpm.new_active_crtc_count <= 2)) {
5456 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5459 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5462 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5463 if (pl->mclk > pi->mclk_edc_enable_threshold)
5464 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5466 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5467 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5469 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5471 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5472 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5473 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5474 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5476 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5478 dll_state_on = false;
5481 level->strobeMode = si_get_strobe_mode_settings(adev,
5484 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5487 ret = si_populate_mclk_value(adev,
5491 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5495 ret = si_populate_voltage_value(adev,
5496 &eg_pi->vddc_voltage_table,
5497 pl->vddc, &level->vddc);
5502 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5506 ret = si_populate_std_voltage_value(adev, std_vddc,
5507 level->vddc.index, &level->std_vddc);
5511 if (eg_pi->vddci_control) {
5512 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5513 pl->vddci, &level->vddci);
5518 if (si_pi->vddc_phase_shed_control) {
5519 ret = si_populate_phase_shedding_value(adev,
5520 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5529 level->MaxPoweredUpCU = si_pi->max_cu;
5531 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5536 static int si_populate_smc_t(struct amdgpu_device *adev,
5537 struct amdgpu_ps *amdgpu_state,
5538 SISLANDS_SMC_SWSTATE *smc_state)
5540 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5541 struct si_ps *state = si_get_ps(amdgpu_state);
5547 if (state->performance_level_count >= 9)
5550 if (state->performance_level_count < 2) {
5551 a_t = CG_R(0xffff) | CG_L(0);
5552 smc_state->levels[0].aT = cpu_to_be32(a_t);
5556 smc_state->levels[0].aT = cpu_to_be32(0);
5558 for (i = 0; i <= state->performance_level_count - 2; i++) {
5559 ret = r600_calculate_at(
5560 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5562 state->performance_levels[i + 1].sclk,
5563 state->performance_levels[i].sclk,
5568 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5569 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5572 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5573 a_t |= CG_R(t_l * pi->bsp / 20000);
5574 smc_state->levels[i].aT = cpu_to_be32(a_t);
5576 high_bsp = (i == state->performance_level_count - 2) ?
5578 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5579 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5585 static int si_disable_ulv(struct amdgpu_device *adev)
5587 struct si_power_info *si_pi = si_get_pi(adev);
5588 struct si_ulv_param *ulv = &si_pi->ulv;
5591 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5597 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5598 struct amdgpu_ps *amdgpu_state)
5600 const struct si_power_info *si_pi = si_get_pi(adev);
5601 const struct si_ulv_param *ulv = &si_pi->ulv;
5602 const struct si_ps *state = si_get_ps(amdgpu_state);
5605 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5608 /* XXX validate against display requirements! */
5610 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5611 if (adev->clock.current_dispclk <=
5612 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5614 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5619 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5625 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5626 struct amdgpu_ps *amdgpu_new_state)
5628 const struct si_power_info *si_pi = si_get_pi(adev);
5629 const struct si_ulv_param *ulv = &si_pi->ulv;
5631 if (ulv->supported) {
5632 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5633 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5639 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5640 struct amdgpu_ps *amdgpu_state,
5641 SISLANDS_SMC_SWSTATE *smc_state)
5643 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5644 struct ni_power_info *ni_pi = ni_get_pi(adev);
5645 struct si_power_info *si_pi = si_get_pi(adev);
5646 struct si_ps *state = si_get_ps(amdgpu_state);
5649 u32 sclk_in_sr = 1350; /* ??? */
5651 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5654 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5656 if (amdgpu_state->vclk && amdgpu_state->dclk) {
5657 eg_pi->uvd_enabled = true;
5658 if (eg_pi->smu_uvd_hs)
5659 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5661 eg_pi->uvd_enabled = false;
5664 if (state->dc_compatible)
5665 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5667 smc_state->levelCount = 0;
5668 for (i = 0; i < state->performance_level_count; i++) {
5669 if (eg_pi->sclk_deep_sleep) {
5670 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5671 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5672 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5674 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5678 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5679 &smc_state->levels[i]);
5680 smc_state->levels[i].arbRefreshState =
5681 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5686 if (ni_pi->enable_power_containment)
5687 smc_state->levels[i].displayWatermark =
5688 (state->performance_levels[i].sclk < threshold) ?
5689 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5691 smc_state->levels[i].displayWatermark = (i < 2) ?
5692 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5694 if (eg_pi->dynamic_ac_timing)
5695 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5697 smc_state->levels[i].ACIndex = 0;
5699 smc_state->levelCount++;
5702 si_write_smc_soft_register(adev,
5703 SI_SMC_SOFT_REGISTER_watermark_threshold,
5706 si_populate_smc_sp(adev, amdgpu_state, smc_state);
5708 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5710 ni_pi->enable_power_containment = false;
5712 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5714 ni_pi->enable_sq_ramping = false;
5716 return si_populate_smc_t(adev, amdgpu_state, smc_state);
5719 static int si_upload_sw_state(struct amdgpu_device *adev,
5720 struct amdgpu_ps *amdgpu_new_state)
5722 struct si_power_info *si_pi = si_get_pi(adev);
5723 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
5725 u32 address = si_pi->state_table_start +
5726 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5727 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5728 ((new_state->performance_level_count - 1) *
5729 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5730 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5732 memset(smc_state, 0, state_size);
5734 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5738 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5739 state_size, si_pi->sram_end);
5742 static int si_upload_ulv_state(struct amdgpu_device *adev)
5744 struct si_power_info *si_pi = si_get_pi(adev);
5745 struct si_ulv_param *ulv = &si_pi->ulv;
5748 if (ulv->supported && ulv->pl.vddc) {
5749 u32 address = si_pi->state_table_start +
5750 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5751 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5752 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5754 memset(smc_state, 0, state_size);
5756 ret = si_populate_ulv_state(adev, smc_state);
5758 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5759 state_size, si_pi->sram_end);
5765 static int si_upload_smc_data(struct amdgpu_device *adev)
5767 struct amdgpu_crtc *amdgpu_crtc = NULL;
5770 if (adev->pm.dpm.new_active_crtc_count == 0)
5773 for (i = 0; i < adev->mode_info.num_crtc; i++) {
5774 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5775 amdgpu_crtc = adev->mode_info.crtcs[i];
5780 if (amdgpu_crtc == NULL)
5783 if (amdgpu_crtc->line_time <= 0)
5786 if (si_write_smc_soft_register(adev,
5787 SI_SMC_SOFT_REGISTER_crtc_index,
5788 amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5791 if (si_write_smc_soft_register(adev,
5792 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5793 amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5796 if (si_write_smc_soft_register(adev,
5797 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5798 amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5804 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5805 struct si_mc_reg_table *table)
5810 for (i = 0, j = table->last; i < table->last; i++) {
5811 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5813 switch (table->mc_reg_address[i].s1) {
5815 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5816 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5817 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5818 for (k = 0; k < table->num_entries; k++)
5819 table->mc_reg_table_entry[k].mc_data[j] =
5820 ((temp_reg & 0xffff0000)) |
5821 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5823 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5826 temp_reg = RREG32(MC_PMG_CMD_MRS);
5827 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5828 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5829 for (k = 0; k < table->num_entries; k++) {
5830 table->mc_reg_table_entry[k].mc_data[j] =
5831 (temp_reg & 0xffff0000) |
5832 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5833 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5834 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5837 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5840 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5841 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5842 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5843 for (k = 0; k < table->num_entries; k++)
5844 table->mc_reg_table_entry[k].mc_data[j] =
5845 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5847 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5851 case MC_SEQ_RESERVE_M:
5852 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5853 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5854 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5855 for(k = 0; k < table->num_entries; k++)
5856 table->mc_reg_table_entry[k].mc_data[j] =
5857 (temp_reg & 0xffff0000) |
5858 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5860 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5873 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5877 case MC_SEQ_RAS_TIMING:
5878 *out_reg = MC_SEQ_RAS_TIMING_LP;
5880 case MC_SEQ_CAS_TIMING:
5881 *out_reg = MC_SEQ_CAS_TIMING_LP;
5883 case MC_SEQ_MISC_TIMING:
5884 *out_reg = MC_SEQ_MISC_TIMING_LP;
5886 case MC_SEQ_MISC_TIMING2:
5887 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5889 case MC_SEQ_RD_CTL_D0:
5890 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5892 case MC_SEQ_RD_CTL_D1:
5893 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5895 case MC_SEQ_WR_CTL_D0:
5896 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5898 case MC_SEQ_WR_CTL_D1:
5899 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5901 case MC_PMG_CMD_EMRS:
5902 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5904 case MC_PMG_CMD_MRS:
5905 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5907 case MC_PMG_CMD_MRS1:
5908 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5910 case MC_SEQ_PMG_TIMING:
5911 *out_reg = MC_SEQ_PMG_TIMING_LP;
5913 case MC_PMG_CMD_MRS2:
5914 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5916 case MC_SEQ_WR_CTL_2:
5917 *out_reg = MC_SEQ_WR_CTL_2_LP;
5927 static void si_set_valid_flag(struct si_mc_reg_table *table)
5931 for (i = 0; i < table->last; i++) {
5932 for (j = 1; j < table->num_entries; j++) {
5933 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5934 table->valid_flag |= 1 << i;
5941 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5946 for (i = 0; i < table->last; i++)
5947 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5948 address : table->mc_reg_address[i].s1;
5952 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5953 struct si_mc_reg_table *si_table)
5957 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5959 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5962 for (i = 0; i < table->last; i++)
5963 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5964 si_table->last = table->last;
5966 for (i = 0; i < table->num_entries; i++) {
5967 si_table->mc_reg_table_entry[i].mclk_max =
5968 table->mc_reg_table_entry[i].mclk_max;
5969 for (j = 0; j < table->last; j++) {
5970 si_table->mc_reg_table_entry[i].mc_data[j] =
5971 table->mc_reg_table_entry[i].mc_data[j];
5974 si_table->num_entries = table->num_entries;
5979 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
5981 struct si_power_info *si_pi = si_get_pi(adev);
5982 struct atom_mc_reg_table *table;
5983 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5984 u8 module_index = rv770_get_memory_module_index(adev);
5987 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5991 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5992 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5993 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5994 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5995 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5996 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5997 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5998 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5999 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6000 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6001 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6002 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6003 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6004 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6006 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6010 ret = si_copy_vbios_mc_reg_table(table, si_table);
6014 si_set_s0_mc_reg_index(si_table);
6016 ret = si_set_mc_special_registers(adev, si_table);
6020 si_set_valid_flag(si_table);
6029 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6030 SMC_SIslands_MCRegisters *mc_reg_table)
6032 struct si_power_info *si_pi = si_get_pi(adev);
6035 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6036 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6037 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6039 mc_reg_table->address[i].s0 =
6040 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6041 mc_reg_table->address[i].s1 =
6042 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6046 mc_reg_table->last = (u8)i;
6049 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6050 SMC_SIslands_MCRegisterSet *data,
6051 u32 num_entries, u32 valid_flag)
6055 for(i = 0, j = 0; j < num_entries; j++) {
6056 if (valid_flag & (1 << j)) {
6057 data->value[i] = cpu_to_be32(entry->mc_data[j]);
6063 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6064 struct rv7xx_pl *pl,
6065 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6067 struct si_power_info *si_pi = si_get_pi(adev);
6070 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6071 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6075 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6078 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6079 mc_reg_table_data, si_pi->mc_reg_table.last,
6080 si_pi->mc_reg_table.valid_flag);
6083 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6084 struct amdgpu_ps *amdgpu_state,
6085 SMC_SIslands_MCRegisters *mc_reg_table)
6087 struct si_ps *state = si_get_ps(amdgpu_state);
6090 for (i = 0; i < state->performance_level_count; i++) {
6091 si_convert_mc_reg_table_entry_to_smc(adev,
6092 &state->performance_levels[i],
6093 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6097 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6098 struct amdgpu_ps *amdgpu_boot_state)
6100 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6101 struct si_power_info *si_pi = si_get_pi(adev);
6102 struct si_ulv_param *ulv = &si_pi->ulv;
6103 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6105 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6107 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6109 si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6111 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6112 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6114 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6115 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6116 si_pi->mc_reg_table.last,
6117 si_pi->mc_reg_table.valid_flag);
6119 if (ulv->supported && ulv->pl.vddc != 0)
6120 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6121 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6123 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6124 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6125 si_pi->mc_reg_table.last,
6126 si_pi->mc_reg_table.valid_flag);
6128 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6130 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6131 (u8 *)smc_mc_reg_table,
6132 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6135 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6136 struct amdgpu_ps *amdgpu_new_state)
6138 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6139 struct si_power_info *si_pi = si_get_pi(adev);
6140 u32 address = si_pi->mc_reg_table_start +
6141 offsetof(SMC_SIslands_MCRegisters,
6142 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6143 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6145 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6147 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6149 return amdgpu_si_copy_bytes_to_smc(adev, address,
6150 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6151 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6155 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6158 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6160 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
6163 static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6164 struct amdgpu_ps *amdgpu_state)
6166 struct si_ps *state = si_get_ps(amdgpu_state);
6168 u16 pcie_speed, max_speed = 0;
6170 for (i = 0; i < state->performance_level_count; i++) {
6171 pcie_speed = state->performance_levels[i].pcie_gen;
6172 if (max_speed < pcie_speed)
6173 max_speed = pcie_speed;
6178 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6182 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6183 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6185 return (u16)speed_cntl;
6188 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6189 struct amdgpu_ps *amdgpu_new_state,
6190 struct amdgpu_ps *amdgpu_current_state)
6192 struct si_power_info *si_pi = si_get_pi(adev);
6193 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6194 enum amdgpu_pcie_gen current_link_speed;
6196 if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6197 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6199 current_link_speed = si_pi->force_pcie_gen;
6201 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6202 si_pi->pspp_notify_required = false;
6203 if (target_link_speed > current_link_speed) {
6204 switch (target_link_speed) {
6205 #if defined(CONFIG_ACPI)
6206 case AMDGPU_PCIE_GEN3:
6207 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6209 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6210 if (current_link_speed == AMDGPU_PCIE_GEN2)
6212 case AMDGPU_PCIE_GEN2:
6213 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6217 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6221 if (target_link_speed < current_link_speed)
6222 si_pi->pspp_notify_required = true;
6226 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6227 struct amdgpu_ps *amdgpu_new_state,
6228 struct amdgpu_ps *amdgpu_current_state)
6230 struct si_power_info *si_pi = si_get_pi(adev);
6231 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6234 if (si_pi->pspp_notify_required) {
6235 if (target_link_speed == AMDGPU_PCIE_GEN3)
6236 request = PCIE_PERF_REQ_PECI_GEN3;
6237 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6238 request = PCIE_PERF_REQ_PECI_GEN2;
6240 request = PCIE_PERF_REQ_PECI_GEN1;
6242 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6243 (si_get_current_pcie_speed(adev) > 0))
6246 #if defined(CONFIG_ACPI)
6247 amdgpu_acpi_pcie_performance_request(adev, request, false);
6253 static int si_ds_request(struct amdgpu_device *adev,
6254 bool ds_status_on, u32 count_write)
6256 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6258 if (eg_pi->sclk_deep_sleep) {
6260 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6264 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6265 PPSMC_Result_OK) ? 0 : -EINVAL;
6271 static void si_set_max_cu_value(struct amdgpu_device *adev)
6273 struct si_power_info *si_pi = si_get_pi(adev);
6275 if (adev->asic_type == CHIP_VERDE) {
6276 switch (adev->pdev->device) {
6312 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6313 struct amdgpu_clock_voltage_dependency_table *table)
6317 u16 leakage_voltage;
6320 for (i = 0; i < table->count; i++) {
6321 switch (si_get_leakage_voltage_from_leakage_index(adev,
6322 table->entries[i].v,
6323 &leakage_voltage)) {
6325 table->entries[i].v = leakage_voltage;
6335 for (j = (table->count - 2); j >= 0; j--) {
6336 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6337 table->entries[j].v : table->entries[j + 1].v;
6343 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6347 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6348 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6350 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6351 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6352 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6354 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6355 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6356 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6358 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6362 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6363 struct amdgpu_ps *amdgpu_new_state,
6364 struct amdgpu_ps *amdgpu_current_state)
6367 u32 new_lane_width =
6368 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6369 u32 current_lane_width =
6370 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6372 if (new_lane_width != current_lane_width) {
6373 amdgpu_set_pcie_lanes(adev, new_lane_width);
6374 lane_width = amdgpu_get_pcie_lanes(adev);
6375 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6379 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6381 si_read_clock_registers(adev);
6382 si_enable_acpi_power_management(adev);
6385 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6388 u32 thermal_int = RREG32(CG_THERMAL_INT);
6391 PPSMC_Result result;
6393 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6394 WREG32(CG_THERMAL_INT, thermal_int);
6395 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6396 if (result != PPSMC_Result_OK) {
6397 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6401 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6402 WREG32(CG_THERMAL_INT, thermal_int);
6408 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6409 int min_temp, int max_temp)
6411 int low_temp = 0 * 1000;
6412 int high_temp = 255 * 1000;
6414 if (low_temp < min_temp)
6415 low_temp = min_temp;
6416 if (high_temp > max_temp)
6417 high_temp = max_temp;
6418 if (high_temp < low_temp) {
6419 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6423 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6424 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6425 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6427 adev->pm.dpm.thermal.min_temp = low_temp;
6428 adev->pm.dpm.thermal.max_temp = high_temp;
6433 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6435 struct si_power_info *si_pi = si_get_pi(adev);
6438 if (si_pi->fan_ctrl_is_in_default_mode) {
6439 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6440 si_pi->fan_ctrl_default_mode = tmp;
6441 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6443 si_pi->fan_ctrl_is_in_default_mode = false;
6446 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6448 WREG32(CG_FDO_CTRL2, tmp);
6450 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6451 tmp |= FDO_PWM_MODE(mode);
6452 WREG32(CG_FDO_CTRL2, tmp);
6455 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6457 struct si_power_info *si_pi = si_get_pi(adev);
6458 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6460 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6461 u16 fdo_min, slope1, slope2;
6462 u32 reference_clock, tmp;
6466 if (!si_pi->fan_table_start) {
6467 adev->pm.dpm.fan.ucode_fan_control = false;
6471 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6474 adev->pm.dpm.fan.ucode_fan_control = false;
6478 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6479 do_div(tmp64, 10000);
6480 fdo_min = (u16)tmp64;
6482 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6483 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6485 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6486 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6488 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6489 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6491 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6492 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6493 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6494 fan_table.slope1 = cpu_to_be16(slope1);
6495 fan_table.slope2 = cpu_to_be16(slope2);
6496 fan_table.fdo_min = cpu_to_be16(fdo_min);
6497 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6498 fan_table.hys_up = cpu_to_be16(1);
6499 fan_table.hys_slope = cpu_to_be16(1);
6500 fan_table.temp_resp_lim = cpu_to_be16(5);
6501 reference_clock = amdgpu_asic_get_xclk(adev);
6503 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6504 reference_clock) / 1600);
6505 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6507 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6508 fan_table.temp_src = (uint8_t)tmp;
6510 ret = amdgpu_si_copy_bytes_to_smc(adev,
6511 si_pi->fan_table_start,
6517 DRM_ERROR("Failed to load fan table to the SMC.");
6518 adev->pm.dpm.fan.ucode_fan_control = false;
6524 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6526 struct si_power_info *si_pi = si_get_pi(adev);
6529 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6530 if (ret == PPSMC_Result_OK) {
6531 si_pi->fan_is_controlled_by_smc = true;
6538 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6540 struct si_power_info *si_pi = si_get_pi(adev);
6543 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6545 if (ret == PPSMC_Result_OK) {
6546 si_pi->fan_is_controlled_by_smc = false;
6553 static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
6559 if (adev->pm.no_fan)
6562 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6563 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6568 tmp64 = (u64)duty * 100;
6569 do_div(tmp64, duty100);
6570 *speed = (u32)tmp64;
6578 static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
6581 struct si_power_info *si_pi = si_get_pi(adev);
6586 if (adev->pm.no_fan)
6589 if (si_pi->fan_is_controlled_by_smc)
6595 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6600 tmp64 = (u64)speed * duty100;
6604 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6605 tmp |= FDO_STATIC_DUTY(duty);
6606 WREG32(CG_FDO_CTRL0, tmp);
6611 static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
6614 /* stop auto-manage */
6615 if (adev->pm.dpm.fan.ucode_fan_control)
6616 si_fan_ctrl_stop_smc_fan_control(adev);
6617 si_fan_ctrl_set_static_mode(adev, mode);
6619 /* restart auto-manage */
6620 if (adev->pm.dpm.fan.ucode_fan_control)
6621 si_thermal_start_smc_fan_control(adev);
6623 si_fan_ctrl_set_default_mode(adev);
6627 static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
6629 struct si_power_info *si_pi = si_get_pi(adev);
6632 if (si_pi->fan_is_controlled_by_smc)
6635 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6636 return (tmp >> FDO_PWM_MODE_SHIFT);
6640 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6644 u32 xclk = amdgpu_asic_get_xclk(adev);
6646 if (adev->pm.no_fan)
6649 if (adev->pm.fan_pulses_per_revolution == 0)
6652 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6653 if (tach_period == 0)
6656 *speed = 60 * xclk * 10000 / tach_period;
6661 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6664 u32 tach_period, tmp;
6665 u32 xclk = amdgpu_asic_get_xclk(adev);
6667 if (adev->pm.no_fan)
6670 if (adev->pm.fan_pulses_per_revolution == 0)
6673 if ((speed < adev->pm.fan_min_rpm) ||
6674 (speed > adev->pm.fan_max_rpm))
6677 if (adev->pm.dpm.fan.ucode_fan_control)
6678 si_fan_ctrl_stop_smc_fan_control(adev);
6680 tach_period = 60 * xclk * 10000 / (8 * speed);
6681 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6682 tmp |= TARGET_PERIOD(tach_period);
6683 WREG32(CG_TACH_CTRL, tmp);
6685 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6691 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6693 struct si_power_info *si_pi = si_get_pi(adev);
6696 if (!si_pi->fan_ctrl_is_in_default_mode) {
6697 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6698 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6699 WREG32(CG_FDO_CTRL2, tmp);
6701 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6702 tmp |= TMIN(si_pi->t_min);
6703 WREG32(CG_FDO_CTRL2, tmp);
6704 si_pi->fan_ctrl_is_in_default_mode = true;
6708 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6710 if (adev->pm.dpm.fan.ucode_fan_control) {
6711 si_fan_ctrl_start_smc_fan_control(adev);
6712 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6716 static void si_thermal_initialize(struct amdgpu_device *adev)
6720 if (adev->pm.fan_pulses_per_revolution) {
6721 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6722 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6723 WREG32(CG_TACH_CTRL, tmp);
6726 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6727 tmp |= TACH_PWM_RESP_RATE(0x28);
6728 WREG32(CG_FDO_CTRL2, tmp);
6731 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6735 si_thermal_initialize(adev);
6736 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6739 ret = si_thermal_enable_alert(adev, true);
6742 if (adev->pm.dpm.fan.ucode_fan_control) {
6743 ret = si_halt_smc(adev);
6746 ret = si_thermal_setup_fan_table(adev);
6749 ret = si_resume_smc(adev);
6752 si_thermal_start_smc_fan_control(adev);
6758 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6760 if (!adev->pm.no_fan) {
6761 si_fan_ctrl_set_default_mode(adev);
6762 si_fan_ctrl_stop_smc_fan_control(adev);
6766 static int si_dpm_enable(struct amdgpu_device *adev)
6768 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6769 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6770 struct si_power_info *si_pi = si_get_pi(adev);
6771 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6774 if (amdgpu_si_is_smc_running(adev))
6776 if (pi->voltage_control || si_pi->voltage_control_svi2)
6777 si_enable_voltage_control(adev, true);
6778 if (pi->mvdd_control)
6779 si_get_mvdd_configuration(adev);
6780 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6781 ret = si_construct_voltage_tables(adev);
6783 DRM_ERROR("si_construct_voltage_tables failed\n");
6787 if (eg_pi->dynamic_ac_timing) {
6788 ret = si_initialize_mc_reg_table(adev);
6790 eg_pi->dynamic_ac_timing = false;
6793 si_enable_spread_spectrum(adev, true);
6794 if (pi->thermal_protection)
6795 si_enable_thermal_protection(adev, true);
6797 si_program_git(adev);
6798 si_program_tp(adev);
6799 si_program_tpp(adev);
6800 si_program_sstp(adev);
6801 si_enable_display_gap(adev);
6802 si_program_vc(adev);
6803 ret = si_upload_firmware(adev);
6805 DRM_ERROR("si_upload_firmware failed\n");
6808 ret = si_process_firmware_header(adev);
6810 DRM_ERROR("si_process_firmware_header failed\n");
6813 ret = si_initial_switch_from_arb_f0_to_f1(adev);
6815 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6818 ret = si_init_smc_table(adev);
6820 DRM_ERROR("si_init_smc_table failed\n");
6823 ret = si_init_smc_spll_table(adev);
6825 DRM_ERROR("si_init_smc_spll_table failed\n");
6828 ret = si_init_arb_table_index(adev);
6830 DRM_ERROR("si_init_arb_table_index failed\n");
6833 if (eg_pi->dynamic_ac_timing) {
6834 ret = si_populate_mc_reg_table(adev, boot_ps);
6836 DRM_ERROR("si_populate_mc_reg_table failed\n");
6840 ret = si_initialize_smc_cac_tables(adev);
6842 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6845 ret = si_initialize_hardware_cac_manager(adev);
6847 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6850 ret = si_initialize_smc_dte_tables(adev);
6852 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6855 ret = si_populate_smc_tdp_limits(adev, boot_ps);
6857 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6860 ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6862 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6865 si_program_response_times(adev);
6866 si_program_ds_registers(adev);
6867 si_dpm_start_smc(adev);
6868 ret = si_notify_smc_display_change(adev, false);
6870 DRM_ERROR("si_notify_smc_display_change failed\n");
6873 si_enable_sclk_control(adev, true);
6876 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6877 si_thermal_start_thermal_controller(adev);
6882 static int si_set_temperature_range(struct amdgpu_device *adev)
6886 ret = si_thermal_enable_alert(adev, false);
6889 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6892 ret = si_thermal_enable_alert(adev, true);
6899 static void si_dpm_disable(struct amdgpu_device *adev)
6901 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6902 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6904 if (!amdgpu_si_is_smc_running(adev))
6906 si_thermal_stop_thermal_controller(adev);
6907 si_disable_ulv(adev);
6909 if (pi->thermal_protection)
6910 si_enable_thermal_protection(adev, false);
6911 si_enable_power_containment(adev, boot_ps, false);
6912 si_enable_smc_cac(adev, boot_ps, false);
6913 si_enable_spread_spectrum(adev, false);
6914 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6916 si_reset_to_default(adev);
6917 si_dpm_stop_smc(adev);
6918 si_force_switch_to_arb_f0(adev);
6920 ni_update_current_ps(adev, boot_ps);
6923 static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
6925 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6926 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6927 struct amdgpu_ps *new_ps = &requested_ps;
6929 ni_update_requested_ps(adev, new_ps);
6930 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
6935 static int si_power_control_set_level(struct amdgpu_device *adev)
6937 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6940 ret = si_restrict_performance_levels_before_switch(adev);
6943 ret = si_halt_smc(adev);
6946 ret = si_populate_smc_tdp_limits(adev, new_ps);
6949 ret = si_populate_smc_tdp_limits_2(adev, new_ps);
6952 ret = si_resume_smc(adev);
6955 ret = si_set_sw_state(adev);
6961 static int si_dpm_set_power_state(struct amdgpu_device *adev)
6963 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6964 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
6965 struct amdgpu_ps *old_ps = &eg_pi->current_rps;
6968 ret = si_disable_ulv(adev);
6970 DRM_ERROR("si_disable_ulv failed\n");
6973 ret = si_restrict_performance_levels_before_switch(adev);
6975 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6978 if (eg_pi->pcie_performance_request)
6979 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
6980 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
6981 ret = si_enable_power_containment(adev, new_ps, false);
6983 DRM_ERROR("si_enable_power_containment failed\n");
6986 ret = si_enable_smc_cac(adev, new_ps, false);
6988 DRM_ERROR("si_enable_smc_cac failed\n");
6991 ret = si_halt_smc(adev);
6993 DRM_ERROR("si_halt_smc failed\n");
6996 ret = si_upload_sw_state(adev, new_ps);
6998 DRM_ERROR("si_upload_sw_state failed\n");
7001 ret = si_upload_smc_data(adev);
7003 DRM_ERROR("si_upload_smc_data failed\n");
7006 ret = si_upload_ulv_state(adev);
7008 DRM_ERROR("si_upload_ulv_state failed\n");
7011 if (eg_pi->dynamic_ac_timing) {
7012 ret = si_upload_mc_reg_table(adev, new_ps);
7014 DRM_ERROR("si_upload_mc_reg_table failed\n");
7018 ret = si_program_memory_timing_parameters(adev, new_ps);
7020 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7023 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7025 ret = si_resume_smc(adev);
7027 DRM_ERROR("si_resume_smc failed\n");
7030 ret = si_set_sw_state(adev);
7032 DRM_ERROR("si_set_sw_state failed\n");
7035 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7036 if (eg_pi->pcie_performance_request)
7037 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7038 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7040 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7043 ret = si_enable_smc_cac(adev, new_ps, true);
7045 DRM_ERROR("si_enable_smc_cac failed\n");
7048 ret = si_enable_power_containment(adev, new_ps, true);
7050 DRM_ERROR("si_enable_power_containment failed\n");
7054 ret = si_power_control_set_level(adev);
7056 DRM_ERROR("si_power_control_set_level failed\n");
7063 static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
7065 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7066 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7068 ni_update_current_ps(adev, new_ps);
7072 void si_dpm_reset_asic(struct amdgpu_device *adev)
7074 si_restrict_performance_levels_before_switch(adev);
7075 si_disable_ulv(adev);
7076 si_set_boot_state(adev);
7080 static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
7082 si_program_display_gap(adev);
7086 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7087 struct amdgpu_ps *rps,
7088 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7091 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7092 rps->class = le16_to_cpu(non_clock_info->usClassification);
7093 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7095 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7096 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7097 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7098 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7099 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7100 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7106 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7107 adev->pm.dpm.boot_ps = rps;
7108 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7109 adev->pm.dpm.uvd_ps = rps;
7112 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7113 struct amdgpu_ps *rps, int index,
7114 union pplib_clock_info *clock_info)
7116 struct rv7xx_power_info *pi = rv770_get_pi(adev);
7117 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7118 struct si_power_info *si_pi = si_get_pi(adev);
7119 struct si_ps *ps = si_get_ps(rps);
7120 u16 leakage_voltage;
7121 struct rv7xx_pl *pl = &ps->performance_levels[index];
7124 ps->performance_level_count = index + 1;
7126 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7127 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7128 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7129 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7131 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7132 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7133 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7134 pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
7135 si_pi->sys_pcie_mask,
7136 si_pi->boot_pcie_gen,
7137 clock_info->si.ucPCIEGen);
7139 /* patch up vddc if necessary */
7140 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7143 pl->vddc = leakage_voltage;
7145 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7146 pi->acpi_vddc = pl->vddc;
7147 eg_pi->acpi_vddci = pl->vddci;
7148 si_pi->acpi_pcie_gen = pl->pcie_gen;
7151 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7153 /* XXX disable for A0 tahiti */
7154 si_pi->ulv.supported = false;
7155 si_pi->ulv.pl = *pl;
7156 si_pi->ulv.one_pcie_lane_in_ulv = false;
7157 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7158 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7159 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7162 if (pi->min_vddc_in_table > pl->vddc)
7163 pi->min_vddc_in_table = pl->vddc;
7165 if (pi->max_vddc_in_table < pl->vddc)
7166 pi->max_vddc_in_table = pl->vddc;
7168 /* patch up boot state */
7169 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7170 u16 vddc, vddci, mvdd;
7171 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7172 pl->mclk = adev->clock.default_mclk;
7173 pl->sclk = adev->clock.default_sclk;
7176 si_pi->mvdd_bootup_value = mvdd;
7179 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7180 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7181 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7182 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7183 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7184 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7188 union pplib_power_state {
7189 struct _ATOM_PPLIB_STATE v1;
7190 struct _ATOM_PPLIB_STATE_V2 v2;
7193 static int si_parse_power_table(struct amdgpu_device *adev)
7195 struct amdgpu_mode_info *mode_info = &adev->mode_info;
7196 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7197 union pplib_power_state *power_state;
7198 int i, j, k, non_clock_array_index, clock_array_index;
7199 union pplib_clock_info *clock_info;
7200 struct _StateArray *state_array;
7201 struct _ClockInfoArray *clock_info_array;
7202 struct _NonClockInfoArray *non_clock_info_array;
7203 union power_info *power_info;
7204 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7207 u8 *power_state_offset;
7210 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7211 &frev, &crev, &data_offset))
7213 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7215 amdgpu_add_thermal_controller(adev);
7217 state_array = (struct _StateArray *)
7218 (mode_info->atom_context->bios + data_offset +
7219 le16_to_cpu(power_info->pplib.usStateArrayOffset));
7220 clock_info_array = (struct _ClockInfoArray *)
7221 (mode_info->atom_context->bios + data_offset +
7222 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7223 non_clock_info_array = (struct _NonClockInfoArray *)
7224 (mode_info->atom_context->bios + data_offset +
7225 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7227 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7228 state_array->ucNumEntries, GFP_KERNEL);
7229 if (!adev->pm.dpm.ps)
7231 power_state_offset = (u8 *)state_array->states;
7232 for (i = 0; i < state_array->ucNumEntries; i++) {
7234 power_state = (union pplib_power_state *)power_state_offset;
7235 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7236 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7237 &non_clock_info_array->nonClockInfo[non_clock_array_index];
7238 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL);
7240 kfree(adev->pm.dpm.ps);
7243 adev->pm.dpm.ps[i].ps_priv = ps;
7244 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7246 non_clock_info_array->ucEntrySize);
7248 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7249 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7250 clock_array_index = idx[j];
7251 if (clock_array_index >= clock_info_array->ucNumEntries)
7253 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7255 clock_info = (union pplib_clock_info *)
7256 ((u8 *)&clock_info_array->clockInfo[0] +
7257 (clock_array_index * clock_info_array->ucEntrySize));
7258 si_parse_pplib_clock_info(adev,
7259 &adev->pm.dpm.ps[i], k,
7263 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7265 adev->pm.dpm.num_ps = state_array->ucNumEntries;
7267 /* fill in the vce power states */
7268 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7270 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7271 clock_info = (union pplib_clock_info *)
7272 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7273 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7274 sclk |= clock_info->si.ucEngineClockHigh << 16;
7275 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7276 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7277 adev->pm.dpm.vce_states[i].sclk = sclk;
7278 adev->pm.dpm.vce_states[i].mclk = mclk;
7284 static int si_dpm_init(struct amdgpu_device *adev)
7286 struct rv7xx_power_info *pi;
7287 struct evergreen_power_info *eg_pi;
7288 struct ni_power_info *ni_pi;
7289 struct si_power_info *si_pi;
7290 struct atom_clock_dividers dividers;
7293 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7296 adev->pm.dpm.priv = si_pi;
7301 si_pi->sys_pcie_mask =
7302 (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
7303 CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
7304 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7305 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7307 si_set_max_cu_value(adev);
7309 rv770_get_max_vddc(adev);
7310 si_get_leakage_vddc(adev);
7311 si_patch_dependency_tables_based_on_leakage(adev);
7314 eg_pi->acpi_vddci = 0;
7315 pi->min_vddc_in_table = 0;
7316 pi->max_vddc_in_table = 0;
7318 ret = amdgpu_get_platform_caps(adev);
7322 ret = amdgpu_parse_extended_power_table(adev);
7326 ret = si_parse_power_table(adev);
7330 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7331 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7332 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7333 amdgpu_free_extended_power_table(adev);
7336 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7337 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7338 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7339 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7340 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7341 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7342 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7343 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7344 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7346 if (adev->pm.dpm.voltage_response_time == 0)
7347 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7348 if (adev->pm.dpm.backbias_response_time == 0)
7349 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7351 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7352 0, false, ÷rs);
7354 pi->ref_div = dividers.ref_div + 1;
7356 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7358 eg_pi->smu_uvd_hs = false;
7360 pi->mclk_strobe_mode_threshold = 40000;
7361 if (si_is_special_1gb_platform(adev))
7362 pi->mclk_stutter_mode_threshold = 0;
7364 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7365 pi->mclk_edc_enable_threshold = 40000;
7366 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7368 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7370 pi->voltage_control =
7371 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7372 VOLTAGE_OBJ_GPIO_LUT);
7373 if (!pi->voltage_control) {
7374 si_pi->voltage_control_svi2 =
7375 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7377 if (si_pi->voltage_control_svi2)
7378 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7379 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7383 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7384 VOLTAGE_OBJ_GPIO_LUT);
7386 eg_pi->vddci_control =
7387 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7388 VOLTAGE_OBJ_GPIO_LUT);
7389 if (!eg_pi->vddci_control)
7390 si_pi->vddci_control_svi2 =
7391 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7394 si_pi->vddc_phase_shed_control =
7395 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7396 VOLTAGE_OBJ_PHASE_LUT);
7398 rv770_get_engine_memory_ss(adev);
7400 pi->asi = RV770_ASI_DFLT;
7401 pi->pasi = CYPRESS_HASI_DFLT;
7402 pi->vrc = SISLANDS_VRC_DFLT;
7404 pi->gfx_clock_gating = true;
7406 eg_pi->sclk_deep_sleep = true;
7407 si_pi->sclk_deep_sleep_above_low = false;
7409 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7410 pi->thermal_protection = true;
7412 pi->thermal_protection = false;
7414 eg_pi->dynamic_ac_timing = true;
7416 eg_pi->light_sleep = true;
7417 #if defined(CONFIG_ACPI)
7418 eg_pi->pcie_performance_request =
7419 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7421 eg_pi->pcie_performance_request = false;
7424 si_pi->sram_end = SMC_RAM_END;
7426 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7427 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7428 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7429 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7430 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7431 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7432 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7434 si_initialize_powertune_defaults(adev);
7436 /* make sure dc limits are valid */
7437 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7438 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7439 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7440 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7442 si_pi->fan_ctrl_is_in_default_mode = true;
7447 static void si_dpm_fini(struct amdgpu_device *adev)
7451 if (adev->pm.dpm.ps)
7452 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7453 kfree(adev->pm.dpm.ps[i].ps_priv);
7454 kfree(adev->pm.dpm.ps);
7455 kfree(adev->pm.dpm.priv);
7456 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7457 amdgpu_free_extended_power_table(adev);
7460 static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
7463 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7464 struct amdgpu_ps *rps = &eg_pi->current_rps;
7465 struct si_ps *ps = si_get_ps(rps);
7466 struct rv7xx_pl *pl;
7468 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7469 CURRENT_STATE_INDEX_SHIFT;
7471 if (current_index >= ps->performance_level_count) {
7472 seq_printf(m, "invalid dpm profile %d\n", current_index);
7474 pl = &ps->performance_levels[current_index];
7475 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7476 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7477 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7481 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7482 struct amdgpu_irq_src *source,
7484 enum amdgpu_interrupt_state state)
7489 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7491 case AMDGPU_IRQ_STATE_DISABLE:
7492 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7493 cg_thermal_int |= THERM_INT_MASK_HIGH;
7494 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7496 case AMDGPU_IRQ_STATE_ENABLE:
7497 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7498 cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7499 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7506 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7508 case AMDGPU_IRQ_STATE_DISABLE:
7509 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7510 cg_thermal_int |= THERM_INT_MASK_LOW;
7511 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7513 case AMDGPU_IRQ_STATE_ENABLE:
7514 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7515 cg_thermal_int &= ~THERM_INT_MASK_LOW;
7516 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7529 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7530 struct amdgpu_irq_src *source,
7531 struct amdgpu_iv_entry *entry)
7533 bool queue_thermal = false;
7538 switch (entry->src_id) {
7539 case 230: /* thermal low to high */
7540 DRM_DEBUG("IH: thermal low to high\n");
7541 adev->pm.dpm.thermal.high_to_low = false;
7542 queue_thermal = true;
7544 case 231: /* thermal high to low */
7545 DRM_DEBUG("IH: thermal high to low\n");
7546 adev->pm.dpm.thermal.high_to_low = true;
7547 queue_thermal = true;
7554 schedule_work(&adev->pm.dpm.thermal.work);
7559 static int si_dpm_late_init(void *handle)
7562 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7567 /* init the sysfs and debugfs files late */
7568 ret = amdgpu_pm_sysfs_init(adev);
7572 ret = si_set_temperature_range(adev);
7576 si_dpm_powergate_uvd(adev, true);
7582 * si_dpm_init_microcode - load ucode images from disk
7584 * @adev: amdgpu_device pointer
7586 * Use the firmware interface to load the ucode images into
7587 * the driver (not loaded into hw).
7588 * Returns 0 on success, error on failure.
7590 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7592 const char *chip_name;
7597 switch (adev->asic_type) {
7599 chip_name = "tahiti";
7602 if ((adev->pdev->revision == 0x81) &&
7603 ((adev->pdev->device == 0x6810) ||
7604 (adev->pdev->device == 0x6811)))
7605 chip_name = "pitcairn_k";
7607 chip_name = "pitcairn";
7610 if (((adev->pdev->device == 0x6820) &&
7611 ((adev->pdev->revision == 0x81) ||
7612 (adev->pdev->revision == 0x83))) ||
7613 ((adev->pdev->device == 0x6821) &&
7614 ((adev->pdev->revision == 0x83) ||
7615 (adev->pdev->revision == 0x87))) ||
7616 ((adev->pdev->revision == 0x87) &&
7617 ((adev->pdev->device == 0x6823) ||
7618 (adev->pdev->device == 0x682b))))
7619 chip_name = "verde_k";
7621 chip_name = "verde";
7624 if (((adev->pdev->revision == 0x81) &&
7625 ((adev->pdev->device == 0x6600) ||
7626 (adev->pdev->device == 0x6604) ||
7627 (adev->pdev->device == 0x6605) ||
7628 (adev->pdev->device == 0x6610))) ||
7629 ((adev->pdev->revision == 0x83) &&
7630 (adev->pdev->device == 0x6610)))
7631 chip_name = "oland_k";
7633 chip_name = "oland";
7636 if (((adev->pdev->revision == 0x81) &&
7637 (adev->pdev->device == 0x6660)) ||
7638 ((adev->pdev->revision == 0x83) &&
7639 ((adev->pdev->device == 0x6660) ||
7640 (adev->pdev->device == 0x6663) ||
7641 (adev->pdev->device == 0x6665) ||
7642 (adev->pdev->device == 0x6667))))
7643 chip_name = "hainan_k";
7644 else if ((adev->pdev->revision == 0xc3) &&
7645 (adev->pdev->device == 0x6665))
7646 chip_name = "banks_k_2";
7648 chip_name = "hainan";
7653 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
7654 err = reject_firmware(&adev->pm.fw, fw_name, adev->dev);
7657 err = amdgpu_ucode_validate(adev->pm.fw);
7661 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7663 release_firmware(adev->pm.fw);
7670 static int si_dpm_sw_init(void *handle)
7673 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7675 ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
7679 ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
7683 /* default to balanced state */
7684 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7685 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7686 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
7687 adev->pm.default_sclk = adev->clock.default_sclk;
7688 adev->pm.default_mclk = adev->clock.default_mclk;
7689 adev->pm.current_sclk = adev->clock.default_sclk;
7690 adev->pm.current_mclk = adev->clock.default_mclk;
7691 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7693 if (amdgpu_dpm == 0)
7696 ret = si_dpm_init_microcode(adev);
7700 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7701 mutex_lock(&adev->pm.mutex);
7702 ret = si_dpm_init(adev);
7705 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7706 if (amdgpu_dpm == 1)
7707 amdgpu_pm_print_power_states(adev);
7708 mutex_unlock(&adev->pm.mutex);
7709 DRM_INFO("amdgpu: dpm initialized\n");
7715 mutex_unlock(&adev->pm.mutex);
7716 DRM_ERROR("amdgpu: dpm initialization failed\n");
7720 static int si_dpm_sw_fini(void *handle)
7722 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7724 flush_work(&adev->pm.dpm.thermal.work);
7726 mutex_lock(&adev->pm.mutex);
7727 amdgpu_pm_sysfs_fini(adev);
7729 mutex_unlock(&adev->pm.mutex);
7734 static int si_dpm_hw_init(void *handle)
7738 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7743 mutex_lock(&adev->pm.mutex);
7744 si_dpm_setup_asic(adev);
7745 ret = si_dpm_enable(adev);
7747 adev->pm.dpm_enabled = false;
7749 adev->pm.dpm_enabled = true;
7750 mutex_unlock(&adev->pm.mutex);
7751 amdgpu_pm_compute_clocks(adev);
7755 static int si_dpm_hw_fini(void *handle)
7757 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7759 if (adev->pm.dpm_enabled) {
7760 mutex_lock(&adev->pm.mutex);
7761 si_dpm_disable(adev);
7762 mutex_unlock(&adev->pm.mutex);
7768 static int si_dpm_suspend(void *handle)
7770 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7772 if (adev->pm.dpm_enabled) {
7773 mutex_lock(&adev->pm.mutex);
7775 si_dpm_disable(adev);
7776 /* reset the power state */
7777 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7778 mutex_unlock(&adev->pm.mutex);
7783 static int si_dpm_resume(void *handle)
7786 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7788 if (adev->pm.dpm_enabled) {
7789 /* asic init will reset to the boot state */
7790 mutex_lock(&adev->pm.mutex);
7791 si_dpm_setup_asic(adev);
7792 ret = si_dpm_enable(adev);
7794 adev->pm.dpm_enabled = false;
7796 adev->pm.dpm_enabled = true;
7797 mutex_unlock(&adev->pm.mutex);
7798 if (adev->pm.dpm_enabled)
7799 amdgpu_pm_compute_clocks(adev);
7804 static bool si_dpm_is_idle(void *handle)
7810 static int si_dpm_wait_for_idle(void *handle)
7816 static int si_dpm_soft_reset(void *handle)
7821 static int si_dpm_set_clockgating_state(void *handle,
7822 enum amd_clockgating_state state)
7827 static int si_dpm_set_powergating_state(void *handle,
7828 enum amd_powergating_state state)
7833 /* get temperature in millidegrees */
7834 static int si_dpm_get_temp(struct amdgpu_device *adev)
7837 int actual_temp = 0;
7839 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7845 actual_temp = temp & 0x1ff;
7847 actual_temp = (actual_temp * 1000);
7852 static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
7854 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7855 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7858 return requested_state->performance_levels[0].sclk;
7860 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7863 static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
7865 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7866 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7869 return requested_state->performance_levels[0].mclk;
7871 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7874 static void si_dpm_print_power_state(struct amdgpu_device *adev,
7875 struct amdgpu_ps *rps)
7877 struct si_ps *ps = si_get_ps(rps);
7878 struct rv7xx_pl *pl;
7881 amdgpu_dpm_print_class_info(rps->class, rps->class2);
7882 amdgpu_dpm_print_cap_info(rps->caps);
7883 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7884 for (i = 0; i < ps->performance_level_count; i++) {
7885 pl = &ps->performance_levels[i];
7886 if (adev->asic_type >= CHIP_TAHITI)
7887 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7888 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7890 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
7891 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
7893 amdgpu_dpm_print_ps_status(adev, rps);
7896 static int si_dpm_early_init(void *handle)
7899 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7901 si_dpm_set_dpm_funcs(adev);
7902 si_dpm_set_irq_funcs(adev);
7906 static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1,
7907 const struct rv7xx_pl *si_cpl2)
7909 return ((si_cpl1->mclk == si_cpl2->mclk) &&
7910 (si_cpl1->sclk == si_cpl2->sclk) &&
7911 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
7912 (si_cpl1->vddc == si_cpl2->vddc) &&
7913 (si_cpl1->vddci == si_cpl2->vddci));
7916 static int si_check_state_equal(struct amdgpu_device *adev,
7917 struct amdgpu_ps *cps,
7918 struct amdgpu_ps *rps,
7921 struct si_ps *si_cps;
7922 struct si_ps *si_rps;
7925 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
7928 si_cps = si_get_ps(cps);
7929 si_rps = si_get_ps(rps);
7931 if (si_cps == NULL) {
7932 printk("si_cps is NULL\n");
7937 if (si_cps->performance_level_count != si_rps->performance_level_count) {
7942 for (i = 0; i < si_cps->performance_level_count; i++) {
7943 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
7944 &(si_rps->performance_levels[i]))) {
7950 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
7951 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
7952 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
7957 static int si_dpm_read_sensor(struct amdgpu_device *adev, int idx,
7958 void *value, int *size)
7960 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7961 struct amdgpu_ps *rps = &eg_pi->current_rps;
7962 struct si_ps *ps = si_get_ps(rps);
7963 uint32_t sclk, mclk;
7965 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7966 CURRENT_STATE_INDEX_SHIFT;
7968 /* size must be at least 4 bytes for all sensors */
7973 case AMDGPU_PP_SENSOR_GFX_SCLK:
7974 if (pl_index < ps->performance_level_count) {
7975 sclk = ps->performance_levels[pl_index].sclk;
7976 *((uint32_t *)value) = sclk;
7981 case AMDGPU_PP_SENSOR_GFX_MCLK:
7982 if (pl_index < ps->performance_level_count) {
7983 mclk = ps->performance_levels[pl_index].mclk;
7984 *((uint32_t *)value) = mclk;
7989 case AMDGPU_PP_SENSOR_GPU_TEMP:
7990 *((uint32_t *)value) = si_dpm_get_temp(adev);
7998 const struct amd_ip_funcs si_dpm_ip_funcs = {
8000 .early_init = si_dpm_early_init,
8001 .late_init = si_dpm_late_init,
8002 .sw_init = si_dpm_sw_init,
8003 .sw_fini = si_dpm_sw_fini,
8004 .hw_init = si_dpm_hw_init,
8005 .hw_fini = si_dpm_hw_fini,
8006 .suspend = si_dpm_suspend,
8007 .resume = si_dpm_resume,
8008 .is_idle = si_dpm_is_idle,
8009 .wait_for_idle = si_dpm_wait_for_idle,
8010 .soft_reset = si_dpm_soft_reset,
8011 .set_clockgating_state = si_dpm_set_clockgating_state,
8012 .set_powergating_state = si_dpm_set_powergating_state,
8015 static const struct amdgpu_dpm_funcs si_dpm_funcs = {
8016 .get_temperature = &si_dpm_get_temp,
8017 .pre_set_power_state = &si_dpm_pre_set_power_state,
8018 .set_power_state = &si_dpm_set_power_state,
8019 .post_set_power_state = &si_dpm_post_set_power_state,
8020 .display_configuration_changed = &si_dpm_display_configuration_changed,
8021 .get_sclk = &si_dpm_get_sclk,
8022 .get_mclk = &si_dpm_get_mclk,
8023 .print_power_state = &si_dpm_print_power_state,
8024 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8025 .force_performance_level = &si_dpm_force_performance_level,
8026 .vblank_too_short = &si_dpm_vblank_too_short,
8027 .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8028 .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8029 .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
8030 .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
8031 .check_state_equal = &si_check_state_equal,
8032 .get_vce_clock_state = amdgpu_get_vce_clock_state,
8033 .read_sensor = &si_dpm_read_sensor,
8036 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
8038 if (adev->pm.funcs == NULL)
8039 adev->pm.funcs = &si_dpm_funcs;
8042 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8043 .set = si_dpm_set_interrupt_state,
8044 .process = si_dpm_process_interrupt,
8047 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8049 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8050 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;