drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29
  30 #include "vega10/soc15ip.h"
  31 #include "vega10/SDMA0/sdma0_4_0_offset.h"
  32 #include "vega10/SDMA0/sdma0_4_0_sh_mask.h"
  33 #include "vega10/SDMA1/sdma1_4_0_offset.h"
  34 #include "vega10/SDMA1/sdma1_4_0_sh_mask.h"
  35 #include "vega10/MMHUB/mmhub_1_0_offset.h"
  36 #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
  37 #include "vega10/HDP/hdp_4_0_offset.h"
  38 #include "raven1/SDMA0/sdma0_4_1_default.h"
  39
  40 #include "soc15_common.h"
  41 #include "soc15.h"
  42 #include "vega10_sdma_pkt_open.h"
  43
  44 /*(DEBLOBBED)*/
  45
  46 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
  47 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
  48
  49 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
  50 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
  51 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  52 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  53
  54 static const u32 golden_settings_sdma_4[] = {
  55         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
  56         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100,
  57         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100,
  58         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
  59         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL), 0x800f0100, 0x00000100,
  60         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  61         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0x003ff006, 0x0003c000,
  62         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0100, 0x00000100,
  63         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  64         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0100, 0x00000100,
  65         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  66         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0,
  67         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
  68         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), 0xffffffff, 0x3f000100,
  69         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_IB_CNTL), 0x800f0100, 0x00000100,
  70         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  71         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL), 0x800f0100, 0x00000100,
  72         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  73         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), 0x003ff000, 0x0003c000,
  74         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL), 0x800f0100, 0x00000100,
  75         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  76         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL), 0x800f0100, 0x00000100,
  77         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000,
  78         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_UTCL1_PAGE), 0x000003ff, 0x000003c0
  79 };
  80
  81 static const u32 golden_settings_sdma_vg10[] = {
  82         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,
  83         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002,
  84         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,
  85         SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002
  86 };
  87
  88 static const u32 golden_settings_sdma_4_1[] =
  89 {
  90         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07,
  91         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xffffffff, 0x3f000100,
  92         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0111, 0x00000100,
  93         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
  94         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0xfc3fffff, 0x40000051,
  95         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0111, 0x00000100,
  96         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
  97         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0111, 0x00000100,
  98         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000,
  99         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0
 100 };
 101
 102 static const u32 golden_settings_sdma_rv1[] =
 103 {
 104         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00000002,
 105         SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00000002
 106 };
 107
 108 static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset)
 109 {
 110         u32 base = 0;
 111
 112         switch (instance) {
 113         case 0:
 114                 base = SDMA0_BASE.instance[0].segment[0];
 115                 break;
 116         case 1:
 117                 base = SDMA1_BASE.instance[0].segment[0];
 118                 break;
 119         default:
 120                 BUG();
 121                 break;
 122         }
 123
 124         return base + internal_offset;
 125 }
 126
 127 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 128 {
 129         switch (adev->asic_type) {
 130         case CHIP_VEGA10:
 131                 amdgpu_program_register_sequence(adev,
 132                                                  golden_settings_sdma_4,
 133                                                  (const u32)ARRAY_SIZE(golden_settings_sdma_4));
 134                 amdgpu_program_register_sequence(adev,
 135                                                  golden_settings_sdma_vg10,
 136                                                  (const u32)ARRAY_SIZE(golden_settings_sdma_vg10));
 137                 break;
 138         case CHIP_RAVEN:
 139                 amdgpu_program_register_sequence(adev,
 140                                                  golden_settings_sdma_4_1,
 141                                                  (const u32)ARRAY_SIZE(golden_settings_sdma_4_1));
 142                 amdgpu_program_register_sequence(adev,
 143                                                  golden_settings_sdma_rv1,
 144                                                  (const u32)ARRAY_SIZE(golden_settings_sdma_rv1));
 145                 break;
 146         default:
 147                 break;
 148         }
 149 }
 150
 151 /**
 152  * sdma_v4_0_init_microcode - load ucode images from disk
 153  *
 154  * @adev: amdgpu_device pointer
 155  *
 156  * Use the firmware interface to load the ucode images into
 157  * the driver (not loaded into hw).
 158  * Returns 0 on success, error on failure.
 159  */
 160
 161 // emulation only, won't work on real chip
 162 // vega10 real chip need to use PSP to load firmware
 163 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 164 {
 165         const char *chip_name;
 166         char fw_name[30];
 167         int err = 0, i;
 168         struct amdgpu_firmware_info *info = NULL;
 169         const struct common_firmware_header *header = NULL;
 170         const struct sdma_firmware_header_v1_0 *hdr;
 171
 172         DRM_DEBUG("\n");
 173
 174         switch (adev->asic_type) {
 175         case CHIP_VEGA10:
 176                 chip_name = "vega10";
 177                 break;
 178         case CHIP_RAVEN:
 179                 chip_name = "raven";
 180                 break;
 181         default:
 182                 BUG();
 183         }
 184
 185         for (i = 0; i < adev->sdma.num_instances; i++) {
 186                 if (i == 0)
 187                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 188                 else
 189                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 190                 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 191                 if (err)
 192                         goto out;
 193                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 194                 if (err)
 195                         goto out;
 196                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 197                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 198                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 199                 if (adev->sdma.instance[i].feature_version >= 20)
 200                         adev->sdma.instance[i].burst_nop = true;
 201                 DRM_DEBUG("psp_load == '%s'\n",
 202                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 203
 204                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 205                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 206                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 207                         info->fw = adev->sdma.instance[i].fw;
 208                         header = (const struct common_firmware_header *)info->fw->data;
 209                         adev->firmware.fw_size +=
 210                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 211                 }
 212         }
 213 out:
 214         if (err) {
 215                 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
 216                 for (i = 0; i < adev->sdma.num_instances; i++) {
 217                         release_firmware(adev->sdma.instance[i].fw);
 218                         adev->sdma.instance[i].fw = NULL;
 219                 }
 220         }
 221         return err;
 222 }
 223
 224 /**
 225  * sdma_v4_0_ring_get_rptr - get the current read pointer
 226  *
 227  * @ring: amdgpu ring pointer
 228  *
 229  * Get the current rptr from the hardware (VEGA10+).
 230  */
 231 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
 232 {
 233         u64 *rptr;
 234
 235         /* XXX check if swapping is necessary on BE */
 236         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 237
 238         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 239         return ((*rptr) >> 2);
 240 }
 241
 242 /**
 243  * sdma_v4_0_ring_get_wptr - get the current write pointer
 244  *
 245  * @ring: amdgpu ring pointer
 246  *
 247  * Get the current wptr from the hardware (VEGA10+).
 248  */
 249 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 250 {
 251         struct amdgpu_device *adev = ring->adev;
 252         u64 *wptr = NULL;
 253         uint64_t local_wptr = 0;
 254
 255         if (ring->use_doorbell) {
 256                 /* XXX check if swapping is necessary on BE */
 257                 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]);
 258                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
 259                 *wptr = (*wptr) >> 2;
 260                 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
 261         } else {
 262                 u32 lowbit, highbit;
 263                 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 264
 265                 wptr = &local_wptr;
 266                 lowbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR)) >> 2;
 267                 highbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
 268
 269                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
 270                                 me, highbit, lowbit);
 271                 *wptr = highbit;
 272                 *wptr = (*wptr) << 32;
 273                 *wptr |= lowbit;
 274         }
 275
 276         return *wptr;
 277 }
 278
 279 /**
 280  * sdma_v4_0_ring_set_wptr - commit the write pointer
 281  *
 282  * @ring: amdgpu ring pointer
 283  *
 284  * Write the wptr back to the hardware (VEGA10+).
 285  */
 286 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 287 {
 288         struct amdgpu_device *adev = ring->adev;
 289
 290         DRM_DEBUG("Setting write pointer\n");
 291         if (ring->use_doorbell) {
 292                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 293
 294                 DRM_DEBUG("Using doorbell -- "
 295                                 "wptr_offs == 0x%08x "
 296                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 297                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 298                                 ring->wptr_offs,
 299                                 lower_32_bits(ring->wptr << 2),
 300                                 upper_32_bits(ring->wptr << 2));
 301                 /* XXX check if swapping is necessary on BE */
 302                 WRITE_ONCE(*wb, (ring->wptr << 2));
 303                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 304                                 ring->doorbell_index, ring->wptr << 2);
 305                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 306         } else {
 307                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 308
 309                 DRM_DEBUG("Not using doorbell -- "
 310                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 311                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 312                                 me,
 313                                 lower_32_bits(ring->wptr << 2),
 314                                 me,
 315                                 upper_32_bits(ring->wptr << 2));
 316                 WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
 317                 WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
 318         }
 319 }
 320
 321 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 322 {
 323         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 324         int i;
 325
 326         for (i = 0; i < count; i++)
 327                 if (sdma && sdma->burst_nop && (i == 0))
 328                         amdgpu_ring_write(ring, ring->funcs->nop |
 329                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 330                 else
 331                         amdgpu_ring_write(ring, ring->funcs->nop);
 332 }
 333
 334 /**
 335  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
 336  *
 337  * @ring: amdgpu ring pointer
 338  * @ib: IB object to schedule
 339  *
 340  * Schedule an IB in the DMA ring (VEGA10).
 341  */
 342 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
 343                                         struct amdgpu_ib *ib,
 344                                         unsigned vm_id, bool ctx_switch)
 345 {
 346         u32 vmid = vm_id & 0xf;
 347
 348         /* IB packet must end on a 8 DW boundary */
 349         sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 350
 351         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 352                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 353         /* base must be 32 byte aligned */
 354         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 355         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 356         amdgpu_ring_write(ring, ib->length_dw);
 357         amdgpu_ring_write(ring, 0);
 358         amdgpu_ring_write(ring, 0);
 359
 360 }
 361
 362 /**
 363  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 364  *
 365  * @ring: amdgpu ring pointer
 366  *
 367  * Emit an hdp flush packet on the requested DMA ring.
 368  */
 369 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 370 {
 371         u32 ref_and_mask = 0;
 372         struct nbio_hdp_flush_reg *nbio_hf_reg;
 373
 374         if (ring->adev->flags & AMD_IS_APU)
 375                 nbio_hf_reg = &nbio_v7_0_hdp_flush_reg;
 376         else
 377                 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
 378
 379         if (ring == &ring->adev->sdma.instance[0].ring)
 380                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 381         else
 382                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 383
 384         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 385                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 386                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 387         amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_done_offset << 2);
 388         amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_req_offset << 2);
 389         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 390         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 391         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 392                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 393 }
 394
 395 static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 396 {
 397         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 398                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 399         amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0));
 400         amdgpu_ring_write(ring, 1);
 401 }
 402
 403 /**
 404  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
 405  *
 406  * @ring: amdgpu ring pointer
 407  * @fence: amdgpu fence object
 408  *
 409  * Add a DMA fence packet to the ring to write
 410  * the fence seq number and DMA trap packet to generate
 411  * an interrupt if needed (VEGA10).
 412  */
 413 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 414                                       unsigned flags)
 415 {
 416         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 417         /* write the fence */
 418         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 419         /* zero in first two bits */
 420         BUG_ON(addr & 0x3);
 421         amdgpu_ring_write(ring, lower_32_bits(addr));
 422         amdgpu_ring_write(ring, upper_32_bits(addr));
 423         amdgpu_ring_write(ring, lower_32_bits(seq));
 424
 425         /* optionally write high bits as well */
 426         if (write64bit) {
 427                 addr += 4;
 428                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 429                 /* zero in first two bits */
 430                 BUG_ON(addr & 0x3);
 431                 amdgpu_ring_write(ring, lower_32_bits(addr));
 432                 amdgpu_ring_write(ring, upper_32_bits(addr));
 433                 amdgpu_ring_write(ring, upper_32_bits(seq));
 434         }
 435
 436         /* generate an interrupt */
 437         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 438         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 439 }
 440
 441
 442 /**
 443  * sdma_v4_0_gfx_stop - stop the gfx async dma engines
 444  *
 445  * @adev: amdgpu_device pointer
 446  *
 447  * Stop the gfx async dma ring buffers (VEGA10).
 448  */
 449 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
 450 {
 451         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 452         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 453         u32 rb_cntl, ib_cntl;
 454         int i;
 455
 456         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 457             (adev->mman.buffer_funcs_ring == sdma1))
 458                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 459
 460         for (i = 0; i < adev->sdma.num_instances; i++) {
 461                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL));
 462                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 463                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 464                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL));
 465                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 466                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 467         }
 468
 469         sdma0->ready = false;
 470         sdma1->ready = false;
 471 }
 472
 473 /**
 474  * sdma_v4_0_rlc_stop - stop the compute async dma engines
 475  *
 476  * @adev: amdgpu_device pointer
 477  *
 478  * Stop the compute async dma queues (VEGA10).
 479  */
 480 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
 481 {
 482         /* XXX todo */
 483 }
 484
 485 /**
 486  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 487  *
 488  * @adev: amdgpu_device pointer
 489  * @enable: enable/disable the DMA MEs context switch.
 490  *
 491  * Halt or unhalt the async dma engines context switch (VEGA10).
 492  */
 493 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 494 {
 495         u32 f32_cntl, phase_quantum = 0;
 496         int i;
 497
 498         if (amdgpu_sdma_phase_quantum) {
 499                 unsigned value = amdgpu_sdma_phase_quantum;
 500                 unsigned unit = 0;
 501
 502                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 503                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 504                         value = (value + 1) >> 1;
 505                         unit++;
 506                 }
 507                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 508                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 509                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 510                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 511                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 512                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 513                         WARN_ONCE(1,
 514                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 515                                   value << unit);
 516                 }
 517                 phase_quantum =
 518                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 519                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 520         }
 521
 522         for (i = 0; i < adev->sdma.num_instances; i++) {
 523                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL));
 524                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 525                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 526                 if (enable && amdgpu_sdma_phase_quantum) {
 527                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE0_QUANTUM),
 528                                phase_quantum);
 529                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE1_QUANTUM),
 530                                phase_quantum);
 531                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_PHASE2_QUANTUM),
 532                                phase_quantum);
 533                 }
 534                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), f32_cntl);
 535         }
 536
 537 }
 538
 539 /**
 540  * sdma_v4_0_enable - stop the async dma engines
 541  *
 542  * @adev: amdgpu_device pointer
 543  * @enable: enable/disable the DMA MEs.
 544  *
 545  * Halt or unhalt the async dma engines (VEGA10).
 546  */
 547 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
 548 {
 549         u32 f32_cntl;
 550         int i;
 551
 552         if (enable == false) {
 553                 sdma_v4_0_gfx_stop(adev);
 554                 sdma_v4_0_rlc_stop(adev);
 555         }
 556
 557         for (i = 0; i < adev->sdma.num_instances; i++) {
 558                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL));
 559                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 560                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), f32_cntl);
 561         }
 562 }
 563
 564 /**
 565  * sdma_v4_0_gfx_resume - setup and start the async dma engines
 566  *
 567  * @adev: amdgpu_device pointer
 568  *
 569  * Set up the gfx DMA ring buffers and enable them (VEGA10).
 570  * Returns 0 for success, error for failure.
 571  */
 572 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 573 {
 574         struct amdgpu_ring *ring;
 575         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 576         u32 rb_bufsz;
 577         u32 wb_offset;
 578         u32 doorbell;
 579         u32 doorbell_offset;
 580         u32 temp;
 581         u64 wptr_gpu_addr;
 582         int i, r;
 583
 584         for (i = 0; i < adev->sdma.num_instances; i++) {
 585                 ring = &adev->sdma.instance[i].ring;
 586                 wb_offset = (ring->rptr_offs * 4);
 587
 588                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 589
 590                 /* Set ring buffer size in dwords */
 591                 rb_bufsz = order_base_2(ring->ring_size / 4);
 592                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL));
 593                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 594 #ifdef __BIG_ENDIAN
 595                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 596                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 597                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 598 #endif
 599                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 600
 601                 /* Initialize the ring buffer's read and write pointers */
 602                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR), 0);
 603                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 604                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), 0);
 605                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 606
 607                 /* set the wb address whether it's enabled or not */
 608                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 609                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 610                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 611                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 612
 613                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 614
 615                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 616                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 617
 618                 ring->wptr = 0;
 619
 620                 /* before programing wptr to a less value, need set minor_ptr_update first */
 621                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 622
 623                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 624                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 625                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 626                 }
 627
 628                 doorbell = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL));
 629                 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET));
 630
 631                 if (ring->use_doorbell) {
 632                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 633                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 634                                         OFFSET, ring->doorbell_index);
 635                 } else {
 636                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 637                 }
 638                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL), doorbell);
 639                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 640                 if (adev->flags & AMD_IS_APU)
 641                         nbio_v7_0_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
 642                 else
 643                         nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index);
 644
 645                 if (amdgpu_sriov_vf(adev))
 646                         sdma_v4_0_ring_set_wptr(ring);
 647
 648                 /* set minor_ptr_update to 0 after wptr programed */
 649                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 650
 651                 /* set utc l1 enable flag always to 1 */
 652                 temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL));
 653                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 654                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), temp);
 655
 656                 if (!amdgpu_sriov_vf(adev)) {
 657                         /* unhalt engine */
 658                         temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL));
 659                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 660                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), temp);
 661                 }
 662
 663                 /* setup the wptr shadow polling */
 664                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 665                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 666                        lower_32_bits(wptr_gpu_addr));
 667                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 668                        upper_32_bits(wptr_gpu_addr));
 669                 wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 670                 if (amdgpu_sriov_vf(adev))
 671                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
 672                 else
 673                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
 674                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
 675
 676                 /* enable DMA RB */
 677                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 678                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 679
 680                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL));
 681                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 682 #ifdef __BIG_ENDIAN
 683                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 684 #endif
 685                 /* enable DMA IBs */
 686                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 687
 688                 ring->ready = true;
 689
 690                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 691                         sdma_v4_0_ctx_switch_enable(adev, true);
 692                         sdma_v4_0_enable(adev, true);
 693                 }
 694
 695                 r = amdgpu_ring_test_ring(ring);
 696                 if (r) {
 697                         ring->ready = false;
 698                         return r;
 699                 }
 700
 701                 if (adev->mman.buffer_funcs_ring == ring)
 702                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 703
 704         }
 705
 706         return 0;
 707 }
 708
 709 static void
 710 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
 711 {
 712         uint32_t def, data;
 713
 714         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
 715                 /* disable idle interrupt */
 716                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 717                 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 718
 719                 if (data != def)
 720                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 721         } else {
 722                 /* disable idle interrupt */
 723                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 724                 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 725                 if (data != def)
 726                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 727         }
 728 }
 729
 730 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
 731 {
 732         uint32_t def, data;
 733
 734         /* Enable HW based PG. */
 735         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
 736         data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
 737         if (data != def)
 738                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 739
 740         /* enable interrupt */
 741         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 742         data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 743         if (data != def)
 744                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 745
 746         /* Configure hold time to filter in-valid power on/off request. Use default right now */
 747         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
 748         data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
 749         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
 750         /* Configure switch time for hysteresis purpose. Use default right now */
 751         data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
 752         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
 753         if(data != def)
 754                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 755 }
 756
 757 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
 758 {
 759         if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
 760                 return;
 761
 762         switch (adev->asic_type) {
 763         case CHIP_RAVEN:
 764                 sdma_v4_1_init_power_gating(adev);
 765                 sdma_v4_1_update_power_gating(adev, true);
 766                 break;
 767         default:
 768                 break;
 769         }
 770 }
 771
 772 /**
 773  * sdma_v4_0_rlc_resume - setup and start the async dma engines
 774  *
 775  * @adev: amdgpu_device pointer
 776  *
 777  * Set up the compute DMA queues and enable them (VEGA10).
 778  * Returns 0 for success, error for failure.
 779  */
 780 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
 781 {
 782         sdma_v4_0_init_pg(adev);
 783
 784         return 0;
 785 }
 786
 787 /**
 788  * sdma_v4_0_load_microcode - load the sDMA ME ucode
 789  *
 790  * @adev: amdgpu_device pointer
 791  *
 792  * Loads the sDMA0/1 ucode.
 793  * Returns 0 for success, -EINVAL if the ucode is not available.
 794  */
 795 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
 796 {
 797         const struct sdma_firmware_header_v1_0 *hdr;
 798         const __le32 *fw_data;
 799         u32 fw_size;
 800         int i, j;
 801
 802         /* halt the MEs */
 803         sdma_v4_0_enable(adev, false);
 804
 805         for (i = 0; i < adev->sdma.num_instances; i++) {
 806                 if (!adev->sdma.instance[i].fw)
 807                         return -EINVAL;
 808
 809                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 810                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 811                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 812
 813                 fw_data = (const __le32 *)
 814                         (adev->sdma.instance[i].fw->data +
 815                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 816
 817                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), 0);
 818
 819                 for (j = 0; j < fw_size; j++)
 820                         WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 821
 822                 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 823         }
 824
 825         return 0;
 826 }
 827
 828 /**
 829  * sdma_v4_0_start - setup and start the async dma engines
 830  *
 831  * @adev: amdgpu_device pointer
 832  *
 833  * Set up the DMA engines and enable them (VEGA10).
 834  * Returns 0 for success, error for failure.
 835  */
 836 static int sdma_v4_0_start(struct amdgpu_device *adev)
 837 {
 838         int r = 0;
 839
 840         if (amdgpu_sriov_vf(adev)) {
 841                 sdma_v4_0_ctx_switch_enable(adev, false);
 842                 sdma_v4_0_enable(adev, false);
 843
 844                 /* set RB registers */
 845                 r = sdma_v4_0_gfx_resume(adev);
 846                 return r;
 847         }
 848
 849         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 850                 r = sdma_v4_0_load_microcode(adev);
 851                 if (r)
 852                         return r;
 853         }
 854
 855         /* unhalt the MEs */
 856         sdma_v4_0_enable(adev, true);
 857         /* enable sdma ring preemption */
 858         sdma_v4_0_ctx_switch_enable(adev, true);
 859
 860         /* start the gfx rings and rlc compute queues */
 861         r = sdma_v4_0_gfx_resume(adev);
 862         if (r)
 863                 return r;
 864         r = sdma_v4_0_rlc_resume(adev);
 865
 866         return r;
 867 }
 868
 869 /**
 870  * sdma_v4_0_ring_test_ring - simple async dma engine test
 871  *
 872  * @ring: amdgpu_ring structure holding ring information
 873  *
 874  * Test the DMA engine by writing using it to write an
 875  * value to memory. (VEGA10).
 876  * Returns 0 for success, error for failure.
 877  */
 878 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
 879 {
 880         struct amdgpu_device *adev = ring->adev;
 881         unsigned i;
 882         unsigned index;
 883         int r;
 884         u32 tmp;
 885         u64 gpu_addr;
 886
 887         r = amdgpu_wb_get(adev, &index);
 888         if (r) {
 889                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 890                 return r;
 891         }
 892
 893         gpu_addr = adev->wb.gpu_addr + (index * 4);
 894         tmp = 0xCAFEDEAD;
 895         adev->wb.wb[index] = cpu_to_le32(tmp);
 896
 897         r = amdgpu_ring_alloc(ring, 5);
 898         if (r) {
 899                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 900                 amdgpu_wb_free(adev, index);
 901                 return r;
 902         }
 903
 904         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 905                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 906         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 907         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 908         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 909         amdgpu_ring_write(ring, 0xDEADBEEF);
 910         amdgpu_ring_commit(ring);
 911
 912         for (i = 0; i < adev->usec_timeout; i++) {
 913                 tmp = le32_to_cpu(adev->wb.wb[index]);
 914                 if (tmp == 0xDEADBEEF)
 915                         break;
 916                 DRM_UDELAY(1);
 917         }
 918
 919         if (i < adev->usec_timeout) {
 920                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 921         } else {
 922                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 923                           ring->idx, tmp);
 924                 r = -EINVAL;
 925         }
 926         amdgpu_wb_free(adev, index);
 927
 928         return r;
 929 }
 930
 931 /**
 932  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
 933  *
 934  * @ring: amdgpu_ring structure holding ring information
 935  *
 936  * Test a simple IB in the DMA ring (VEGA10).
 937  * Returns 0 on success, error on failure.
 938  */
 939 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 940 {
 941         struct amdgpu_device *adev = ring->adev;
 942         struct amdgpu_ib ib;
 943         struct dma_fence *f = NULL;
 944         unsigned index;
 945         long r;
 946         u32 tmp = 0;
 947         u64 gpu_addr;
 948
 949         r = amdgpu_wb_get(adev, &index);
 950         if (r) {
 951                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 952                 return r;
 953         }
 954
 955         gpu_addr = adev->wb.gpu_addr + (index * 4);
 956         tmp = 0xCAFEDEAD;
 957         adev->wb.wb[index] = cpu_to_le32(tmp);
 958         memset(&ib, 0, sizeof(ib));
 959         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 960         if (r) {
 961                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 962                 goto err0;
 963         }
 964
 965         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 966                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 967         ib.ptr[1] = lower_32_bits(gpu_addr);
 968         ib.ptr[2] = upper_32_bits(gpu_addr);
 969         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 970         ib.ptr[4] = 0xDEADBEEF;
 971         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 972         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 973         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 974         ib.length_dw = 8;
 975
 976         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 977         if (r)
 978                 goto err1;
 979
 980         r = dma_fence_wait_timeout(f, false, timeout);
 981         if (r == 0) {
 982                 DRM_ERROR("amdgpu: IB test timed out\n");
 983                 r = -ETIMEDOUT;
 984                 goto err1;
 985         } else if (r < 0) {
 986                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 987                 goto err1;
 988         }
 989         tmp = le32_to_cpu(adev->wb.wb[index]);
 990         if (tmp == 0xDEADBEEF) {
 991                 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
 992                 r = 0;
 993         } else {
 994                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 995                 r = -EINVAL;
 996         }
 997 err1:
 998         amdgpu_ib_free(adev, &ib, NULL);
 999         dma_fence_put(f);
1000 err0:
1001         amdgpu_wb_free(adev, index);
1002         return r;
1003 }
1004
1005
1006 /**
1007  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1008  *
1009  * @ib: indirect buffer to fill with commands
1010  * @pe: addr of the page entry
1011  * @src: src addr to copy from
1012  * @count: number of page entries to update
1013  *
1014  * Update PTEs by copying them from the GART using sDMA (VEGA10).
1015  */
1016 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1017                                   uint64_t pe, uint64_t src,
1018                                   unsigned count)
1019 {
1020         unsigned bytes = count * 8;
1021
1022         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1023                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1024         ib->ptr[ib->length_dw++] = bytes - 1;
1025         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1026         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1027         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1028         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1029         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1030
1031 }
1032
1033 /**
1034  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1035  *
1036  * @ib: indirect buffer to fill with commands
1037  * @pe: addr of the page entry
1038  * @addr: dst addr to write into pe
1039  * @count: number of page entries to update
1040  * @incr: increase next addr by incr bytes
1041  * @flags: access flags
1042  *
1043  * Update PTEs by writing them manually using sDMA (VEGA10).
1044  */
1045 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1046                                    uint64_t value, unsigned count,
1047                                    uint32_t incr)
1048 {
1049         unsigned ndw = count * 2;
1050
1051         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1052                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1053         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1054         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1055         ib->ptr[ib->length_dw++] = ndw - 1;
1056         for (; ndw > 0; ndw -= 2) {
1057                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1058                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1059                 value += incr;
1060         }
1061 }
1062
1063 /**
1064  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1065  *
1066  * @ib: indirect buffer to fill with commands
1067  * @pe: addr of the page entry
1068  * @addr: dst addr to write into pe
1069  * @count: number of page entries to update
1070  * @incr: increase next addr by incr bytes
1071  * @flags: access flags
1072  *
1073  * Update the page tables using sDMA (VEGA10).
1074  */
1075 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1076                                      uint64_t pe,
1077                                      uint64_t addr, unsigned count,
1078                                      uint32_t incr, uint64_t flags)
1079 {
1080         /* for physically contiguous pages (vram) */
1081         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1082         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1083         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1084         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1085         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1086         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1087         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1088         ib->ptr[ib->length_dw++] = incr; /* increment size */
1089         ib->ptr[ib->length_dw++] = 0;
1090         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1091 }
1092
1093 /**
1094  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1095  *
1096  * @ib: indirect buffer to fill with padding
1097  *
1098  */
1099 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1100 {
1101         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1102         u32 pad_count;
1103         int i;
1104
1105         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1106         for (i = 0; i < pad_count; i++)
1107                 if (sdma && sdma->burst_nop && (i == 0))
1108                         ib->ptr[ib->length_dw++] =
1109                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1110                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1111                 else
1112                         ib->ptr[ib->length_dw++] =
1113                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1114 }
1115
1116
1117 /**
1118  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1119  *
1120  * @ring: amdgpu_ring pointer
1121  *
1122  * Make sure all previous operations are completed (CIK).
1123  */
1124 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1125 {
1126         uint32_t seq = ring->fence_drv.sync_seq;
1127         uint64_t addr = ring->fence_drv.gpu_addr;
1128
1129         /* wait for idle */
1130         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1131                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1132                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1133                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1134         amdgpu_ring_write(ring, addr & 0xfffffffc);
1135         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1136         amdgpu_ring_write(ring, seq); /* reference */
1137         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1138         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1139                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1140 }
1141
1142
1143 /**
1144  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1145  *
1146  * @ring: amdgpu_ring pointer
1147  * @vm: amdgpu_vm pointer
1148  *
1149  * Update the page table base and flush the VM TLB
1150  * using sDMA (VEGA10).
1151  */
1152 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1153                                          unsigned vm_id, uint64_t pd_addr)
1154 {
1155         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1156         uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
1157         unsigned eng = ring->vm_inv_eng;
1158
1159         pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
1160         pd_addr |= AMDGPU_PTE_VALID;
1161
1162         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1163                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1164         amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vm_id * 2);
1165         amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1166
1167         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1168                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1169         amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vm_id * 2);
1170         amdgpu_ring_write(ring, upper_32_bits(pd_addr));
1171
1172         /* flush TLB */
1173         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1174                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1175         amdgpu_ring_write(ring, hub->vm_inv_eng0_req + eng);
1176         amdgpu_ring_write(ring, req);
1177
1178         /* wait for flush */
1179         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1180                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1181                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1182         amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
1183         amdgpu_ring_write(ring, 0);
1184         amdgpu_ring_write(ring, 1 << vm_id); /* reference */
1185         amdgpu_ring_write(ring, 1 << vm_id); /* mask */
1186         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1187                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1188 }
1189
1190 static int sdma_v4_0_early_init(void *handle)
1191 {
1192         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1193
1194         if (adev->asic_type == CHIP_RAVEN)
1195                 adev->sdma.num_instances = 1;
1196         else
1197                 adev->sdma.num_instances = 2;
1198
1199         sdma_v4_0_set_ring_funcs(adev);
1200         sdma_v4_0_set_buffer_funcs(adev);
1201         sdma_v4_0_set_vm_pte_funcs(adev);
1202         sdma_v4_0_set_irq_funcs(adev);
1203
1204         return 0;
1205 }
1206
1207
1208 static int sdma_v4_0_sw_init(void *handle)
1209 {
1210         struct amdgpu_ring *ring;
1211         int r, i;
1212         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1213
1214         /* SDMA trap event */
1215         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA0, 224,
1216                               &adev->sdma.trap_irq);
1217         if (r)
1218                 return r;
1219
1220         /* SDMA trap event */
1221         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA1, 224,
1222                               &adev->sdma.trap_irq);
1223         if (r)
1224                 return r;
1225
1226         r = sdma_v4_0_init_microcode(adev);
1227         if (r) {
1228                 DRM_ERROR("Failed to load sdma firmware!\n");
1229                 return r;
1230         }
1231
1232         for (i = 0; i < adev->sdma.num_instances; i++) {
1233                 ring = &adev->sdma.instance[i].ring;
1234                 ring->ring_obj = NULL;
1235                 ring->use_doorbell = true;
1236
1237                 DRM_INFO("use_doorbell being set to: [%s]\n",
1238                                 ring->use_doorbell?"true":"false");
1239
1240                 ring->doorbell_index = (i == 0) ?
1241                         (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
1242                         : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
1243
1244                 sprintf(ring->name, "sdma%d", i);
1245                 r = amdgpu_ring_init(adev, ring, 1024,
1246                                      &adev->sdma.trap_irq,
1247                                      (i == 0) ?
1248                                      AMDGPU_SDMA_IRQ_TRAP0 :
1249                                      AMDGPU_SDMA_IRQ_TRAP1);
1250                 if (r)
1251                         return r;
1252         }
1253
1254         return r;
1255 }
1256
1257 static int sdma_v4_0_sw_fini(void *handle)
1258 {
1259         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1260         int i;
1261
1262         for (i = 0; i < adev->sdma.num_instances; i++)
1263                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1264
1265         return 0;
1266 }
1267
1268 static int sdma_v4_0_hw_init(void *handle)
1269 {
1270         int r;
1271         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1272
1273         sdma_v4_0_init_golden_registers(adev);
1274
1275         r = sdma_v4_0_start(adev);
1276
1277         return r;
1278 }
1279
1280 static int sdma_v4_0_hw_fini(void *handle)
1281 {
1282         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1283
1284         if (amdgpu_sriov_vf(adev))
1285                 return 0;
1286
1287         sdma_v4_0_ctx_switch_enable(adev, false);
1288         sdma_v4_0_enable(adev, false);
1289
1290         return 0;
1291 }
1292
1293 static int sdma_v4_0_suspend(void *handle)
1294 {
1295         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1296
1297         return sdma_v4_0_hw_fini(adev);
1298 }
1299
1300 static int sdma_v4_0_resume(void *handle)
1301 {
1302         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1303
1304         return sdma_v4_0_hw_init(adev);
1305 }
1306
1307 static bool sdma_v4_0_is_idle(void *handle)
1308 {
1309         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1310         u32 i;
1311
1312         for (i = 0; i < adev->sdma.num_instances; i++) {
1313                 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_STATUS_REG));
1314
1315                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1316                         return false;
1317         }
1318
1319         return true;
1320 }
1321
1322 static int sdma_v4_0_wait_for_idle(void *handle)
1323 {
1324         unsigned i;
1325         u32 sdma0, sdma1;
1326         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1327
1328         for (i = 0; i < adev->usec_timeout; i++) {
1329                 sdma0 = RREG32(sdma_v4_0_get_reg_offset(0, mmSDMA0_STATUS_REG));
1330                 sdma1 = RREG32(sdma_v4_0_get_reg_offset(1, mmSDMA0_STATUS_REG));
1331
1332                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1333                         return 0;
1334                 udelay(1);
1335         }
1336         return -ETIMEDOUT;
1337 }
1338
1339 static int sdma_v4_0_soft_reset(void *handle)
1340 {
1341         /* todo */
1342
1343         return 0;
1344 }
1345
1346 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1347                                         struct amdgpu_irq_src *source,
1348                                         unsigned type,
1349                                         enum amdgpu_interrupt_state state)
1350 {
1351         u32 sdma_cntl;
1352
1353         u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ?
1354                 sdma_v4_0_get_reg_offset(0, mmSDMA0_CNTL) :
1355                 sdma_v4_0_get_reg_offset(1, mmSDMA0_CNTL);
1356
1357         sdma_cntl = RREG32(reg_offset);
1358         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1359                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1360         WREG32(reg_offset, sdma_cntl);
1361
1362         return 0;
1363 }
1364
1365 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1366                                       struct amdgpu_irq_src *source,
1367                                       struct amdgpu_iv_entry *entry)
1368 {
1369         DRM_DEBUG("IH: SDMA trap\n");
1370         switch (entry->client_id) {
1371         case AMDGPU_IH_CLIENTID_SDMA0:
1372                 switch (entry->ring_id) {
1373                 case 0:
1374                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1375                         break;
1376                 case 1:
1377                         /* XXX compute */
1378                         break;
1379                 case 2:
1380                         /* XXX compute */
1381                         break;
1382                 case 3:
1383                         /* XXX page queue*/
1384                         break;
1385                 }
1386                 break;
1387         case AMDGPU_IH_CLIENTID_SDMA1:
1388                 switch (entry->ring_id) {
1389                 case 0:
1390                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1391                         break;
1392                 case 1:
1393                         /* XXX compute */
1394                         break;
1395                 case 2:
1396                         /* XXX compute */
1397                         break;
1398                 case 3:
1399                         /* XXX page queue*/
1400                         break;
1401                 }
1402                 break;
1403         }
1404         return 0;
1405 }
1406
1407 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1408                                               struct amdgpu_irq_src *source,
1409                                               struct amdgpu_iv_entry *entry)
1410 {
1411         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1412         schedule_work(&adev->reset_work);
1413         return 0;
1414 }
1415
1416
1417 static void sdma_v4_0_update_medium_grain_clock_gating(
1418                 struct amdgpu_device *adev,
1419                 bool enable)
1420 {
1421         uint32_t data, def;
1422
1423         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1424                 /* enable sdma0 clock gating */
1425                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1426                 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1427                           SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1428                           SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1429                           SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1430                           SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1431                           SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1432                           SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1433                           SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1434                 if (def != data)
1435                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1436
1437                 if (adev->asic_type == CHIP_VEGA10) {
1438                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1439                         data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1440                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1441                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1442                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1443                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1444                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1445                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1446                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1447                         if (def != data)
1448                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1449                 }
1450         } else {
1451                 /* disable sdma0 clock gating */
1452                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1453                 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1454                          SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1455                          SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1456                          SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1457                          SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1458                          SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1459                          SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1460                          SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1461
1462                 if (def != data)
1463                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1464
1465                 if (adev->asic_type == CHIP_VEGA10) {
1466                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1467                         data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1468                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1469                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1470                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1471                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1472                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1473                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1474                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1475                         if (def != data)
1476                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1477                 }
1478         }
1479 }
1480
1481
1482 static void sdma_v4_0_update_medium_grain_light_sleep(
1483                 struct amdgpu_device *adev,
1484                 bool enable)
1485 {
1486         uint32_t data, def;
1487
1488         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1489                 /* 1-not override: enable sdma0 mem light sleep */
1490                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1491                 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1492                 if (def != data)
1493                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1494
1495                 /* 1-not override: enable sdma1 mem light sleep */
1496                 if (adev->asic_type == CHIP_VEGA10) {
1497                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1498                         data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1499                         if (def != data)
1500                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1501                 }
1502         } else {
1503                 /* 0-override:disable sdma0 mem light sleep */
1504                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1505                 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1506                 if (def != data)
1507                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1508
1509                 /* 0-override:disable sdma1 mem light sleep */
1510                 if (adev->asic_type == CHIP_VEGA10) {
1511                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1512                         data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1513                         if (def != data)
1514                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1515                 }
1516         }
1517 }
1518
1519 static int sdma_v4_0_set_clockgating_state(void *handle,
1520                                           enum amd_clockgating_state state)
1521 {
1522         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1523
1524         if (amdgpu_sriov_vf(adev))
1525                 return 0;
1526
1527         switch (adev->asic_type) {
1528         case CHIP_VEGA10:
1529         case CHIP_RAVEN:
1530                 sdma_v4_0_update_medium_grain_clock_gating(adev,
1531                                 state == AMD_CG_STATE_GATE ? true : false);
1532                 sdma_v4_0_update_medium_grain_light_sleep(adev,
1533                                 state == AMD_CG_STATE_GATE ? true : false);
1534                 break;
1535         default:
1536                 break;
1537         }
1538         return 0;
1539 }
1540
1541 static int sdma_v4_0_set_powergating_state(void *handle,
1542                                           enum amd_powergating_state state)
1543 {
1544         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1545
1546         switch (adev->asic_type) {
1547         case CHIP_RAVEN:
1548                 sdma_v4_1_update_power_gating(adev,
1549                                 state == AMD_PG_STATE_GATE ? true : false);
1550                 break;
1551         default:
1552                 break;
1553         }
1554
1555         return 0;
1556 }
1557
1558 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
1559 {
1560         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1561         int data;
1562
1563         if (amdgpu_sriov_vf(adev))
1564                 *flags = 0;
1565
1566         /* AMD_CG_SUPPORT_SDMA_MGCG */
1567         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1568         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1569                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1570
1571         /* AMD_CG_SUPPORT_SDMA_LS */
1572         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1573         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1574                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1575 }
1576
1577 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
1578         .name = "sdma_v4_0",
1579         .early_init = sdma_v4_0_early_init,
1580         .late_init = NULL,
1581         .sw_init = sdma_v4_0_sw_init,
1582         .sw_fini = sdma_v4_0_sw_fini,
1583         .hw_init = sdma_v4_0_hw_init,
1584         .hw_fini = sdma_v4_0_hw_fini,
1585         .suspend = sdma_v4_0_suspend,
1586         .resume = sdma_v4_0_resume,
1587         .is_idle = sdma_v4_0_is_idle,
1588         .wait_for_idle = sdma_v4_0_wait_for_idle,
1589         .soft_reset = sdma_v4_0_soft_reset,
1590         .set_clockgating_state = sdma_v4_0_set_clockgating_state,
1591         .set_powergating_state = sdma_v4_0_set_powergating_state,
1592         .get_clockgating_state = sdma_v4_0_get_clockgating_state,
1593 };
1594
1595 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
1596         .type = AMDGPU_RING_TYPE_SDMA,
1597         .align_mask = 0xf,
1598         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1599         .support_64bit_ptrs = true,
1600         .vmhub = AMDGPU_MMHUB,
1601         .get_rptr = sdma_v4_0_ring_get_rptr,
1602         .get_wptr = sdma_v4_0_ring_get_wptr,
1603         .set_wptr = sdma_v4_0_ring_set_wptr,
1604         .emit_frame_size =
1605                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
1606                 3 + /* sdma_v4_0_ring_emit_hdp_invalidate */
1607                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
1608                 18 + /* sdma_v4_0_ring_emit_vm_flush */
1609                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
1610         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
1611         .emit_ib = sdma_v4_0_ring_emit_ib,
1612         .emit_fence = sdma_v4_0_ring_emit_fence,
1613         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
1614         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
1615         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
1616         .emit_hdp_invalidate = sdma_v4_0_ring_emit_hdp_invalidate,
1617         .test_ring = sdma_v4_0_ring_test_ring,
1618         .test_ib = sdma_v4_0_ring_test_ib,
1619         .insert_nop = sdma_v4_0_ring_insert_nop,
1620         .pad_ib = sdma_v4_0_ring_pad_ib,
1621 };
1622
1623 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
1624 {
1625         int i;
1626
1627         for (i = 0; i < adev->sdma.num_instances; i++)
1628                 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
1629 }
1630
1631 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
1632         .set = sdma_v4_0_set_trap_irq_state,
1633         .process = sdma_v4_0_process_trap_irq,
1634 };
1635
1636 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
1637         .process = sdma_v4_0_process_illegal_inst_irq,
1638 };
1639
1640 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
1641 {
1642         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1643         adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
1644         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
1645 }
1646
1647 /**
1648  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
1649  *
1650  * @ring: amdgpu_ring structure holding ring information
1651  * @src_offset: src GPU address
1652  * @dst_offset: dst GPU address
1653  * @byte_count: number of bytes to xfer
1654  *
1655  * Copy GPU buffers using the DMA engine (VEGA10).
1656  * Used by the amdgpu ttm implementation to move pages if
1657  * registered as the asic copy callback.
1658  */
1659 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
1660                                        uint64_t src_offset,
1661                                        uint64_t dst_offset,
1662                                        uint32_t byte_count)
1663 {
1664         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1665                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1666         ib->ptr[ib->length_dw++] = byte_count - 1;
1667         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1668         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1669         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1670         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1671         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1672 }
1673
1674 /**
1675  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
1676  *
1677  * @ring: amdgpu_ring structure holding ring information
1678  * @src_data: value to write to buffer
1679  * @dst_offset: dst GPU address
1680  * @byte_count: number of bytes to xfer
1681  *
1682  * Fill GPU buffers using the DMA engine (VEGA10).
1683  */
1684 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
1685                                        uint32_t src_data,
1686                                        uint64_t dst_offset,
1687                                        uint32_t byte_count)
1688 {
1689         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1690         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1691         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1692         ib->ptr[ib->length_dw++] = src_data;
1693         ib->ptr[ib->length_dw++] = byte_count - 1;
1694 }
1695
1696 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
1697         .copy_max_bytes = 0x400000,
1698         .copy_num_dw = 7,
1699         .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
1700
1701         .fill_max_bytes = 0x400000,
1702         .fill_num_dw = 5,
1703         .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
1704 };
1705
1706 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
1707 {
1708         if (adev->mman.buffer_funcs == NULL) {
1709                 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
1710                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1711         }
1712 }
1713
1714 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
1715         .copy_pte = sdma_v4_0_vm_copy_pte,
1716         .write_pte = sdma_v4_0_vm_write_pte,
1717         .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
1718 };
1719
1720 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1721 {
1722         unsigned i;
1723
1724         if (adev->vm_manager.vm_pte_funcs == NULL) {
1725                 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
1726                 for (i = 0; i < adev->sdma.num_instances; i++)
1727                         adev->vm_manager.vm_pte_rings[i] =
1728                                 &adev->sdma.instance[i].ring;
1729
1730                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1731         }
1732 }
1733
1734 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
1735         .type = AMD_IP_BLOCK_TYPE_SDMA,
1736         .major = 4,
1737         .minor = 0,
1738         .rev = 0,
1739         .funcs = &sdma_v4_0_ip_funcs,
1740 };