drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29
  30 #include "sdma0/sdma0_4_0_offset.h"
  31 #include "sdma0/sdma0_4_0_sh_mask.h"
  32 #include "sdma1/sdma1_4_0_offset.h"
  33 #include "sdma1/sdma1_4_0_sh_mask.h"
  34 #include "hdp/hdp_4_0_offset.h"
  35 #include "sdma0/sdma0_4_1_default.h"
  36
  37 #include "soc15_common.h"
  38 #include "soc15.h"
  39 #include "vega10_sdma_pkt_open.h"
  40
  41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
  42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
  43
  44 /*(DEBLOBBED)*/
  45
  46 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
  47 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
  48
  49 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
  50 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
  51 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  52 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  53
  54 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
  55         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
  56         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
  57         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
  58         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  59         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
  60         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  61         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
  62         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
  63         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  64         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
  65         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  66         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
  67         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
  68         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
  69         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
  70         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  71         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
  72         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  73         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
  74         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
  75         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  76         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
  77         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  78         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
  79         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
  80 };
  81
  82 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
  83         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
  84         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
  85         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
  86         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
  87         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
  88 };
  89
  90 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
  91         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
  92         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
  93         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
  94         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
  95         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001)
  96 };
  97
  98 static const struct soc15_reg_golden golden_settings_sdma_4_1[] =
  99 {
 100         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 101         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 102         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
 103         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 104         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
 105         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
 106         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 107         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
 108         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 109         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 110         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
 111 };
 112
 113 static const struct soc15_reg_golden golden_settings_sdma_4_2[] =
 114 {
 115         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 116         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
 117         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 118         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 119         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 120         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 121         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
 122         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 123         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
 124         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
 125         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
 126         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
 127         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
 128         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 129         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 130         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 131         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 132         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0)
 133 };
 134
 135 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
 136 {
 137         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
 138         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
 139 };
 140
 141 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
 142                 u32 instance, u32 offset)
 143 {
 144         return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) :
 145                         (adev->reg_offset[SDMA1_HWIP][0][0] + offset));
 146 }
 147
 148 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 149 {
 150         switch (adev->asic_type) {
 151         case CHIP_VEGA10:
 152                 soc15_program_register_sequence(adev,
 153                                                  golden_settings_sdma_4,
 154                                                  ARRAY_SIZE(golden_settings_sdma_4));
 155                 soc15_program_register_sequence(adev,
 156                                                  golden_settings_sdma_vg10,
 157                                                  ARRAY_SIZE(golden_settings_sdma_vg10));
 158                 break;
 159         case CHIP_VEGA12:
 160                 soc15_program_register_sequence(adev,
 161                                                 golden_settings_sdma_4,
 162                                                 ARRAY_SIZE(golden_settings_sdma_4));
 163                 soc15_program_register_sequence(adev,
 164                                                 golden_settings_sdma_vg12,
 165                                                 ARRAY_SIZE(golden_settings_sdma_vg12));
 166                 break;
 167         case CHIP_VEGA20:
 168                 soc15_program_register_sequence(adev,
 169                                                 golden_settings_sdma_4_2,
 170                                                 ARRAY_SIZE(golden_settings_sdma_4_2));
 171                 break;
 172         case CHIP_RAVEN:
 173                 soc15_program_register_sequence(adev,
 174                                                  golden_settings_sdma_4_1,
 175                                                  ARRAY_SIZE(golden_settings_sdma_4_1));
 176                 soc15_program_register_sequence(adev,
 177                                                  golden_settings_sdma_rv1,
 178                                                  ARRAY_SIZE(golden_settings_sdma_rv1));
 179                 break;
 180         default:
 181                 break;
 182         }
 183 }
 184
 185 /**
 186  * sdma_v4_0_init_microcode - load ucode images from disk
 187  *
 188  * @adev: amdgpu_device pointer
 189  *
 190  * Use the firmware interface to load the ucode images into
 191  * the driver (not loaded into hw).
 192  * Returns 0 on success, error on failure.
 193  */
 194
 195 // emulation only, won't work on real chip
 196 // vega10 real chip need to use PSP to load firmware
 197 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 198 {
 199         const char *chip_name;
 200         char fw_name[30];
 201         int err = 0, i;
 202         struct amdgpu_firmware_info *info = NULL;
 203         const struct common_firmware_header *header = NULL;
 204         const struct sdma_firmware_header_v1_0 *hdr;
 205
 206         DRM_DEBUG("\n");
 207
 208         switch (adev->asic_type) {
 209         case CHIP_VEGA10:
 210                 chip_name = "vega10";
 211                 break;
 212         case CHIP_VEGA12:
 213                 chip_name = "vega12";
 214                 break;
 215         case CHIP_VEGA20:
 216                 chip_name = "vega20";
 217                 break;
 218         case CHIP_RAVEN:
 219                 chip_name = "raven";
 220                 break;
 221         default:
 222                 BUG();
 223         }
 224
 225         for (i = 0; i < adev->sdma.num_instances; i++) {
 226                 if (i == 0)
 227                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 228                 else
 229                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 230                 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 231                 if (err)
 232                         goto out;
 233                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 234                 if (err)
 235                         goto out;
 236                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 237                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 238                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 239                 if (adev->sdma.instance[i].feature_version >= 20)
 240                         adev->sdma.instance[i].burst_nop = true;
 241                 DRM_DEBUG("psp_load == '%s'\n",
 242                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 243
 244                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 245                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 246                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 247                         info->fw = adev->sdma.instance[i].fw;
 248                         header = (const struct common_firmware_header *)info->fw->data;
 249                         adev->firmware.fw_size +=
 250                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 251                 }
 252         }
 253 out:
 254         if (err) {
 255                 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
 256                 for (i = 0; i < adev->sdma.num_instances; i++) {
 257                         release_firmware(adev->sdma.instance[i].fw);
 258                         adev->sdma.instance[i].fw = NULL;
 259                 }
 260         }
 261         return err;
 262 }
 263
 264 /**
 265  * sdma_v4_0_ring_get_rptr - get the current read pointer
 266  *
 267  * @ring: amdgpu ring pointer
 268  *
 269  * Get the current rptr from the hardware (VEGA10+).
 270  */
 271 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
 272 {
 273         u64 *rptr;
 274
 275         /* XXX check if swapping is necessary on BE */
 276         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 277
 278         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 279         return ((*rptr) >> 2);
 280 }
 281
 282 /**
 283  * sdma_v4_0_ring_get_wptr - get the current write pointer
 284  *
 285  * @ring: amdgpu ring pointer
 286  *
 287  * Get the current wptr from the hardware (VEGA10+).
 288  */
 289 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 290 {
 291         struct amdgpu_device *adev = ring->adev;
 292         u64 wptr;
 293
 294         if (ring->use_doorbell) {
 295                 /* XXX check if swapping is necessary on BE */
 296                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 297                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 298         } else {
 299                 u32 lowbit, highbit;
 300
 301                 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
 302                 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
 303
 304                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
 305                                 ring->me, highbit, lowbit);
 306                 wptr = highbit;
 307                 wptr = wptr << 32;
 308                 wptr |= lowbit;
 309         }
 310
 311         return wptr >> 2;
 312 }
 313
 314 /**
 315  * sdma_v4_0_ring_set_wptr - commit the write pointer
 316  *
 317  * @ring: amdgpu ring pointer
 318  *
 319  * Write the wptr back to the hardware (VEGA10+).
 320  */
 321 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 322 {
 323         struct amdgpu_device *adev = ring->adev;
 324
 325         DRM_DEBUG("Setting write pointer\n");
 326         if (ring->use_doorbell) {
 327                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 328
 329                 DRM_DEBUG("Using doorbell -- "
 330                                 "wptr_offs == 0x%08x "
 331                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 332                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 333                                 ring->wptr_offs,
 334                                 lower_32_bits(ring->wptr << 2),
 335                                 upper_32_bits(ring->wptr << 2));
 336                 /* XXX check if swapping is necessary on BE */
 337                 WRITE_ONCE(*wb, (ring->wptr << 2));
 338                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 339                                 ring->doorbell_index, ring->wptr << 2);
 340                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 341         } else {
 342                 DRM_DEBUG("Not using doorbell -- "
 343                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 344                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 345                                 ring->me,
 346                                 lower_32_bits(ring->wptr << 2),
 347                                 ring->me,
 348                                 upper_32_bits(ring->wptr << 2));
 349                 WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
 350                 WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
 351         }
 352 }
 353
 354 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 355 {
 356         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 357         int i;
 358
 359         for (i = 0; i < count; i++)
 360                 if (sdma && sdma->burst_nop && (i == 0))
 361                         amdgpu_ring_write(ring, ring->funcs->nop |
 362                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 363                 else
 364                         amdgpu_ring_write(ring, ring->funcs->nop);
 365 }
 366
 367 /**
 368  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
 369  *
 370  * @ring: amdgpu ring pointer
 371  * @ib: IB object to schedule
 372  *
 373  * Schedule an IB in the DMA ring (VEGA10).
 374  */
 375 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
 376                                         struct amdgpu_ib *ib,
 377                                         unsigned vmid, bool ctx_switch)
 378 {
 379         /* IB packet must end on a 8 DW boundary */
 380         sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 381
 382         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 383                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 384         /* base must be 32 byte aligned */
 385         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 386         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 387         amdgpu_ring_write(ring, ib->length_dw);
 388         amdgpu_ring_write(ring, 0);
 389         amdgpu_ring_write(ring, 0);
 390
 391 }
 392
 393 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
 394                                    int mem_space, int hdp,
 395                                    uint32_t addr0, uint32_t addr1,
 396                                    uint32_t ref, uint32_t mask,
 397                                    uint32_t inv)
 398 {
 399         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 400                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
 401                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
 402                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 403         if (mem_space) {
 404                 /* memory */
 405                 amdgpu_ring_write(ring, addr0);
 406                 amdgpu_ring_write(ring, addr1);
 407         } else {
 408                 /* registers */
 409                 amdgpu_ring_write(ring, addr0 << 2);
 410                 amdgpu_ring_write(ring, addr1 << 2);
 411         }
 412         amdgpu_ring_write(ring, ref); /* reference */
 413         amdgpu_ring_write(ring, mask); /* mask */
 414         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 415                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
 416 }
 417
 418 /**
 419  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 420  *
 421  * @ring: amdgpu ring pointer
 422  *
 423  * Emit an hdp flush packet on the requested DMA ring.
 424  */
 425 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 426 {
 427         struct amdgpu_device *adev = ring->adev;
 428         u32 ref_and_mask = 0;
 429         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
 430
 431         if (ring->me == 0)
 432                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 433         else
 434                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 435
 436         sdma_v4_0_wait_reg_mem(ring, 0, 1,
 437                                adev->nbio_funcs->get_hdp_flush_done_offset(adev),
 438                                adev->nbio_funcs->get_hdp_flush_req_offset(adev),
 439                                ref_and_mask, ref_and_mask, 10);
 440 }
 441
 442 /**
 443  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
 444  *
 445  * @ring: amdgpu ring pointer
 446  * @fence: amdgpu fence object
 447  *
 448  * Add a DMA fence packet to the ring to write
 449  * the fence seq number and DMA trap packet to generate
 450  * an interrupt if needed (VEGA10).
 451  */
 452 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 453                                       unsigned flags)
 454 {
 455         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 456         /* write the fence */
 457         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 458         /* zero in first two bits */
 459         BUG_ON(addr & 0x3);
 460         amdgpu_ring_write(ring, lower_32_bits(addr));
 461         amdgpu_ring_write(ring, upper_32_bits(addr));
 462         amdgpu_ring_write(ring, lower_32_bits(seq));
 463
 464         /* optionally write high bits as well */
 465         if (write64bit) {
 466                 addr += 4;
 467                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 468                 /* zero in first two bits */
 469                 BUG_ON(addr & 0x3);
 470                 amdgpu_ring_write(ring, lower_32_bits(addr));
 471                 amdgpu_ring_write(ring, upper_32_bits(addr));
 472                 amdgpu_ring_write(ring, upper_32_bits(seq));
 473         }
 474
 475         /* generate an interrupt */
 476         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 477         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 478 }
 479
 480
 481 /**
 482  * sdma_v4_0_gfx_stop - stop the gfx async dma engines
 483  *
 484  * @adev: amdgpu_device pointer
 485  *
 486  * Stop the gfx async dma ring buffers (VEGA10).
 487  */
 488 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
 489 {
 490         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 491         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 492         u32 rb_cntl, ib_cntl;
 493         int i;
 494
 495         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 496             (adev->mman.buffer_funcs_ring == sdma1))
 497                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 498
 499         for (i = 0; i < adev->sdma.num_instances; i++) {
 500                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 501                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 502                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 503                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 504                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 505                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 506         }
 507
 508         sdma0->ready = false;
 509         sdma1->ready = false;
 510 }
 511
 512 /**
 513  * sdma_v4_0_rlc_stop - stop the compute async dma engines
 514  *
 515  * @adev: amdgpu_device pointer
 516  *
 517  * Stop the compute async dma queues (VEGA10).
 518  */
 519 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
 520 {
 521         /* XXX todo */
 522 }
 523
 524 /**
 525  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 526  *
 527  * @adev: amdgpu_device pointer
 528  * @enable: enable/disable the DMA MEs context switch.
 529  *
 530  * Halt or unhalt the async dma engines context switch (VEGA10).
 531  */
 532 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 533 {
 534         u32 f32_cntl, phase_quantum = 0;
 535         int i;
 536
 537         if (amdgpu_sdma_phase_quantum) {
 538                 unsigned value = amdgpu_sdma_phase_quantum;
 539                 unsigned unit = 0;
 540
 541                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 542                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 543                         value = (value + 1) >> 1;
 544                         unit++;
 545                 }
 546                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 547                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 548                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 549                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 550                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 551                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 552                         WARN_ONCE(1,
 553                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 554                                   value << unit);
 555                 }
 556                 phase_quantum =
 557                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 558                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 559         }
 560
 561         for (i = 0; i < adev->sdma.num_instances; i++) {
 562                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 563                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 564                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 565                 if (enable && amdgpu_sdma_phase_quantum) {
 566                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 567                                phase_quantum);
 568                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 569                                phase_quantum);
 570                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 571                                phase_quantum);
 572                 }
 573                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 574         }
 575
 576 }
 577
 578 /**
 579  * sdma_v4_0_enable - stop the async dma engines
 580  *
 581  * @adev: amdgpu_device pointer
 582  * @enable: enable/disable the DMA MEs.
 583  *
 584  * Halt or unhalt the async dma engines (VEGA10).
 585  */
 586 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
 587 {
 588         u32 f32_cntl;
 589         int i;
 590
 591         if (enable == false) {
 592                 sdma_v4_0_gfx_stop(adev);
 593                 sdma_v4_0_rlc_stop(adev);
 594         }
 595
 596         for (i = 0; i < adev->sdma.num_instances; i++) {
 597                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 598                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 599                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 600         }
 601 }
 602
 603 /**
 604  * sdma_v4_0_gfx_resume - setup and start the async dma engines
 605  *
 606  * @adev: amdgpu_device pointer
 607  *
 608  * Set up the gfx DMA ring buffers and enable them (VEGA10).
 609  * Returns 0 for success, error for failure.
 610  */
 611 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 612 {
 613         struct amdgpu_ring *ring;
 614         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 615         u32 rb_bufsz;
 616         u32 wb_offset;
 617         u32 doorbell;
 618         u32 doorbell_offset;
 619         u32 temp;
 620         u64 wptr_gpu_addr;
 621         int i, r;
 622
 623         for (i = 0; i < adev->sdma.num_instances; i++) {
 624                 ring = &adev->sdma.instance[i].ring;
 625                 wb_offset = (ring->rptr_offs * 4);
 626
 627                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 628
 629                 /* Set ring buffer size in dwords */
 630                 rb_bufsz = order_base_2(ring->ring_size / 4);
 631                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 632                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 633 #ifdef __BIG_ENDIAN
 634                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 635                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 636                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 637 #endif
 638                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 639
 640                 /* Initialize the ring buffer's read and write pointers */
 641                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 642                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 643                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 644                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 645
 646                 /* set the wb address whether it's enabled or not */
 647                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 648                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 649                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 650                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 651
 652                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 653
 654                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 655                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 656
 657                 ring->wptr = 0;
 658
 659                 /* before programing wptr to a less value, need set minor_ptr_update first */
 660                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 661
 662                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 663                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 664                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 665                 }
 666
 667                 doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 668                 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 669
 670                 if (ring->use_doorbell) {
 671                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 672                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 673                                         OFFSET, ring->doorbell_index);
 674                 } else {
 675                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 676                 }
 677                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 678                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 679                 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 680                                                       ring->doorbell_index);
 681
 682                 if (amdgpu_sriov_vf(adev))
 683                         sdma_v4_0_ring_set_wptr(ring);
 684
 685                 /* set minor_ptr_update to 0 after wptr programed */
 686                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 687
 688                 /* set utc l1 enable flag always to 1 */
 689                 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 690                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 691                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 692
 693                 if (!amdgpu_sriov_vf(adev)) {
 694                         /* unhalt engine */
 695                         temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 696                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 697                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 698                 }
 699
 700                 /* setup the wptr shadow polling */
 701                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 702                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 703                        lower_32_bits(wptr_gpu_addr));
 704                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 705                        upper_32_bits(wptr_gpu_addr));
 706                 wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 707                 if (amdgpu_sriov_vf(adev))
 708                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
 709                 else
 710                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
 711                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
 712
 713                 /* enable DMA RB */
 714                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 715                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 716
 717                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 718                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 719 #ifdef __BIG_ENDIAN
 720                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 721 #endif
 722                 /* enable DMA IBs */
 723                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 724
 725                 ring->ready = true;
 726
 727                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 728                         sdma_v4_0_ctx_switch_enable(adev, true);
 729                         sdma_v4_0_enable(adev, true);
 730                 }
 731
 732                 r = amdgpu_ring_test_ring(ring);
 733                 if (r) {
 734                         ring->ready = false;
 735                         return r;
 736                 }
 737
 738                 if (adev->mman.buffer_funcs_ring == ring)
 739                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 740
 741         }
 742
 743         return 0;
 744 }
 745
 746 static void
 747 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
 748 {
 749         uint32_t def, data;
 750
 751         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
 752                 /* disable idle interrupt */
 753                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 754                 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 755
 756                 if (data != def)
 757                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 758         } else {
 759                 /* disable idle interrupt */
 760                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 761                 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 762                 if (data != def)
 763                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 764         }
 765 }
 766
 767 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
 768 {
 769         uint32_t def, data;
 770
 771         /* Enable HW based PG. */
 772         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
 773         data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
 774         if (data != def)
 775                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 776
 777         /* enable interrupt */
 778         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 779         data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 780         if (data != def)
 781                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 782
 783         /* Configure hold time to filter in-valid power on/off request. Use default right now */
 784         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
 785         data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
 786         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
 787         /* Configure switch time for hysteresis purpose. Use default right now */
 788         data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
 789         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
 790         if(data != def)
 791                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 792 }
 793
 794 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
 795 {
 796         if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
 797                 return;
 798
 799         switch (adev->asic_type) {
 800         case CHIP_RAVEN:
 801                 sdma_v4_1_init_power_gating(adev);
 802                 sdma_v4_1_update_power_gating(adev, true);
 803                 break;
 804         default:
 805                 break;
 806         }
 807 }
 808
 809 /**
 810  * sdma_v4_0_rlc_resume - setup and start the async dma engines
 811  *
 812  * @adev: amdgpu_device pointer
 813  *
 814  * Set up the compute DMA queues and enable them (VEGA10).
 815  * Returns 0 for success, error for failure.
 816  */
 817 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
 818 {
 819         sdma_v4_0_init_pg(adev);
 820
 821         return 0;
 822 }
 823
 824 /**
 825  * sdma_v4_0_load_microcode - load the sDMA ME ucode
 826  *
 827  * @adev: amdgpu_device pointer
 828  *
 829  * Loads the sDMA0/1 ucode.
 830  * Returns 0 for success, -EINVAL if the ucode is not available.
 831  */
 832 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
 833 {
 834         const struct sdma_firmware_header_v1_0 *hdr;
 835         const __le32 *fw_data;
 836         u32 fw_size;
 837         int i, j;
 838
 839         /* halt the MEs */
 840         sdma_v4_0_enable(adev, false);
 841
 842         for (i = 0; i < adev->sdma.num_instances; i++) {
 843                 if (!adev->sdma.instance[i].fw)
 844                         return -EINVAL;
 845
 846                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 847                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 848                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 849
 850                 fw_data = (const __le32 *)
 851                         (adev->sdma.instance[i].fw->data +
 852                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 853
 854                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 855
 856                 for (j = 0; j < fw_size; j++)
 857                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 858
 859                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 860         }
 861
 862         return 0;
 863 }
 864
 865 /**
 866  * sdma_v4_0_start - setup and start the async dma engines
 867  *
 868  * @adev: amdgpu_device pointer
 869  *
 870  * Set up the DMA engines and enable them (VEGA10).
 871  * Returns 0 for success, error for failure.
 872  */
 873 static int sdma_v4_0_start(struct amdgpu_device *adev)
 874 {
 875         int r = 0;
 876
 877         if (amdgpu_sriov_vf(adev)) {
 878                 sdma_v4_0_ctx_switch_enable(adev, false);
 879                 sdma_v4_0_enable(adev, false);
 880
 881                 /* set RB registers */
 882                 r = sdma_v4_0_gfx_resume(adev);
 883                 return r;
 884         }
 885
 886         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 887                 r = sdma_v4_0_load_microcode(adev);
 888                 if (r)
 889                         return r;
 890         }
 891
 892         /* unhalt the MEs */
 893         sdma_v4_0_enable(adev, true);
 894         /* enable sdma ring preemption */
 895         sdma_v4_0_ctx_switch_enable(adev, true);
 896
 897         /* start the gfx rings and rlc compute queues */
 898         r = sdma_v4_0_gfx_resume(adev);
 899         if (r)
 900                 return r;
 901         r = sdma_v4_0_rlc_resume(adev);
 902
 903         return r;
 904 }
 905
 906 /**
 907  * sdma_v4_0_ring_test_ring - simple async dma engine test
 908  *
 909  * @ring: amdgpu_ring structure holding ring information
 910  *
 911  * Test the DMA engine by writing using it to write an
 912  * value to memory. (VEGA10).
 913  * Returns 0 for success, error for failure.
 914  */
 915 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
 916 {
 917         struct amdgpu_device *adev = ring->adev;
 918         unsigned i;
 919         unsigned index;
 920         int r;
 921         u32 tmp;
 922         u64 gpu_addr;
 923
 924         r = amdgpu_device_wb_get(adev, &index);
 925         if (r) {
 926                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 927                 return r;
 928         }
 929
 930         gpu_addr = adev->wb.gpu_addr + (index * 4);
 931         tmp = 0xCAFEDEAD;
 932         adev->wb.wb[index] = cpu_to_le32(tmp);
 933
 934         r = amdgpu_ring_alloc(ring, 5);
 935         if (r) {
 936                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 937                 amdgpu_device_wb_free(adev, index);
 938                 return r;
 939         }
 940
 941         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 942                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 943         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 944         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 945         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 946         amdgpu_ring_write(ring, 0xDEADBEEF);
 947         amdgpu_ring_commit(ring);
 948
 949         for (i = 0; i < adev->usec_timeout; i++) {
 950                 tmp = le32_to_cpu(adev->wb.wb[index]);
 951                 if (tmp == 0xDEADBEEF)
 952                         break;
 953                 DRM_UDELAY(1);
 954         }
 955
 956         if (i < adev->usec_timeout) {
 957                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 958         } else {
 959                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 960                           ring->idx, tmp);
 961                 r = -EINVAL;
 962         }
 963         amdgpu_device_wb_free(adev, index);
 964
 965         return r;
 966 }
 967
 968 /**
 969  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
 970  *
 971  * @ring: amdgpu_ring structure holding ring information
 972  *
 973  * Test a simple IB in the DMA ring (VEGA10).
 974  * Returns 0 on success, error on failure.
 975  */
 976 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 977 {
 978         struct amdgpu_device *adev = ring->adev;
 979         struct amdgpu_ib ib;
 980         struct dma_fence *f = NULL;
 981         unsigned index;
 982         long r;
 983         u32 tmp = 0;
 984         u64 gpu_addr;
 985
 986         r = amdgpu_device_wb_get(adev, &index);
 987         if (r) {
 988                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 989                 return r;
 990         }
 991
 992         gpu_addr = adev->wb.gpu_addr + (index * 4);
 993         tmp = 0xCAFEDEAD;
 994         adev->wb.wb[index] = cpu_to_le32(tmp);
 995         memset(&ib, 0, sizeof(ib));
 996         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 997         if (r) {
 998                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 999                 goto err0;
1000         }
1001
1002         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1003                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1004         ib.ptr[1] = lower_32_bits(gpu_addr);
1005         ib.ptr[2] = upper_32_bits(gpu_addr);
1006         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1007         ib.ptr[4] = 0xDEADBEEF;
1008         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1009         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1010         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1011         ib.length_dw = 8;
1012
1013         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1014         if (r)
1015                 goto err1;
1016
1017         r = dma_fence_wait_timeout(f, false, timeout);
1018         if (r == 0) {
1019                 DRM_ERROR("amdgpu: IB test timed out\n");
1020                 r = -ETIMEDOUT;
1021                 goto err1;
1022         } else if (r < 0) {
1023                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1024                 goto err1;
1025         }
1026         tmp = le32_to_cpu(adev->wb.wb[index]);
1027         if (tmp == 0xDEADBEEF) {
1028                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
1029                 r = 0;
1030         } else {
1031                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
1032                 r = -EINVAL;
1033         }
1034 err1:
1035         amdgpu_ib_free(adev, &ib, NULL);
1036         dma_fence_put(f);
1037 err0:
1038         amdgpu_device_wb_free(adev, index);
1039         return r;
1040 }
1041
1042
1043 /**
1044  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1045  *
1046  * @ib: indirect buffer to fill with commands
1047  * @pe: addr of the page entry
1048  * @src: src addr to copy from
1049  * @count: number of page entries to update
1050  *
1051  * Update PTEs by copying them from the GART using sDMA (VEGA10).
1052  */
1053 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1054                                   uint64_t pe, uint64_t src,
1055                                   unsigned count)
1056 {
1057         unsigned bytes = count * 8;
1058
1059         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1060                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1061         ib->ptr[ib->length_dw++] = bytes - 1;
1062         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1063         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1064         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1065         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1066         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1067
1068 }
1069
1070 /**
1071  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1072  *
1073  * @ib: indirect buffer to fill with commands
1074  * @pe: addr of the page entry
1075  * @addr: dst addr to write into pe
1076  * @count: number of page entries to update
1077  * @incr: increase next addr by incr bytes
1078  * @flags: access flags
1079  *
1080  * Update PTEs by writing them manually using sDMA (VEGA10).
1081  */
1082 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1083                                    uint64_t value, unsigned count,
1084                                    uint32_t incr)
1085 {
1086         unsigned ndw = count * 2;
1087
1088         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1089                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1090         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1091         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1092         ib->ptr[ib->length_dw++] = ndw - 1;
1093         for (; ndw > 0; ndw -= 2) {
1094                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1095                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1096                 value += incr;
1097         }
1098 }
1099
1100 /**
1101  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1102  *
1103  * @ib: indirect buffer to fill with commands
1104  * @pe: addr of the page entry
1105  * @addr: dst addr to write into pe
1106  * @count: number of page entries to update
1107  * @incr: increase next addr by incr bytes
1108  * @flags: access flags
1109  *
1110  * Update the page tables using sDMA (VEGA10).
1111  */
1112 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1113                                      uint64_t pe,
1114                                      uint64_t addr, unsigned count,
1115                                      uint32_t incr, uint64_t flags)
1116 {
1117         /* for physically contiguous pages (vram) */
1118         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1119         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1120         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1121         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1122         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1123         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1124         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1125         ib->ptr[ib->length_dw++] = incr; /* increment size */
1126         ib->ptr[ib->length_dw++] = 0;
1127         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1128 }
1129
1130 /**
1131  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1132  *
1133  * @ib: indirect buffer to fill with padding
1134  *
1135  */
1136 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1137 {
1138         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1139         u32 pad_count;
1140         int i;
1141
1142         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1143         for (i = 0; i < pad_count; i++)
1144                 if (sdma && sdma->burst_nop && (i == 0))
1145                         ib->ptr[ib->length_dw++] =
1146                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1147                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1148                 else
1149                         ib->ptr[ib->length_dw++] =
1150                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1151 }
1152
1153
1154 /**
1155  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1156  *
1157  * @ring: amdgpu_ring pointer
1158  *
1159  * Make sure all previous operations are completed (CIK).
1160  */
1161 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1162 {
1163         uint32_t seq = ring->fence_drv.sync_seq;
1164         uint64_t addr = ring->fence_drv.gpu_addr;
1165
1166         /* wait for idle */
1167         sdma_v4_0_wait_reg_mem(ring, 1, 0,
1168                                addr & 0xfffffffc,
1169                                upper_32_bits(addr) & 0xffffffff,
1170                                seq, 0xffffffff, 4);
1171 }
1172
1173
1174 /**
1175  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1176  *
1177  * @ring: amdgpu_ring pointer
1178  * @vm: amdgpu_vm pointer
1179  *
1180  * Update the page table base and flush the VM TLB
1181  * using sDMA (VEGA10).
1182  */
1183 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1184                                          unsigned vmid, uint64_t pd_addr)
1185 {
1186         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1187 }
1188
1189 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1190                                      uint32_t reg, uint32_t val)
1191 {
1192         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1193                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1194         amdgpu_ring_write(ring, reg);
1195         amdgpu_ring_write(ring, val);
1196 }
1197
1198 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1199                                          uint32_t val, uint32_t mask)
1200 {
1201         sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1202 }
1203
1204 static int sdma_v4_0_early_init(void *handle)
1205 {
1206         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1207
1208         if (adev->asic_type == CHIP_RAVEN)
1209                 adev->sdma.num_instances = 1;
1210         else
1211                 adev->sdma.num_instances = 2;
1212
1213         sdma_v4_0_set_ring_funcs(adev);
1214         sdma_v4_0_set_buffer_funcs(adev);
1215         sdma_v4_0_set_vm_pte_funcs(adev);
1216         sdma_v4_0_set_irq_funcs(adev);
1217
1218         return 0;
1219 }
1220
1221
1222 static int sdma_v4_0_sw_init(void *handle)
1223 {
1224         struct amdgpu_ring *ring;
1225         int r, i;
1226         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1227
1228         /* SDMA trap event */
1229         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP,
1230                               &adev->sdma.trap_irq);
1231         if (r)
1232                 return r;
1233
1234         /* SDMA trap event */
1235         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP,
1236                               &adev->sdma.trap_irq);
1237         if (r)
1238                 return r;
1239
1240         r = sdma_v4_0_init_microcode(adev);
1241         if (r) {
1242                 DRM_ERROR("Failed to load sdma firmware!\n");
1243                 return r;
1244         }
1245
1246         for (i = 0; i < adev->sdma.num_instances; i++) {
1247                 ring = &adev->sdma.instance[i].ring;
1248                 ring->ring_obj = NULL;
1249                 ring->use_doorbell = true;
1250
1251                 DRM_INFO("use_doorbell being set to: [%s]\n",
1252                                 ring->use_doorbell?"true":"false");
1253
1254                 ring->doorbell_index = (i == 0) ?
1255                         (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
1256                         : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
1257
1258                 sprintf(ring->name, "sdma%d", i);
1259                 r = amdgpu_ring_init(adev, ring, 1024,
1260                                      &adev->sdma.trap_irq,
1261                                      (i == 0) ?
1262                                      AMDGPU_SDMA_IRQ_TRAP0 :
1263                                      AMDGPU_SDMA_IRQ_TRAP1);
1264                 if (r)
1265                         return r;
1266         }
1267
1268         return r;
1269 }
1270
1271 static int sdma_v4_0_sw_fini(void *handle)
1272 {
1273         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1274         int i;
1275
1276         for (i = 0; i < adev->sdma.num_instances; i++)
1277                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1278
1279         for (i = 0; i < adev->sdma.num_instances; i++) {
1280                 release_firmware(adev->sdma.instance[i].fw);
1281                 adev->sdma.instance[i].fw = NULL;
1282         }
1283
1284         return 0;
1285 }
1286
1287 static int sdma_v4_0_hw_init(void *handle)
1288 {
1289         int r;
1290         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1291
1292         sdma_v4_0_init_golden_registers(adev);
1293
1294         r = sdma_v4_0_start(adev);
1295
1296         return r;
1297 }
1298
1299 static int sdma_v4_0_hw_fini(void *handle)
1300 {
1301         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1302
1303         if (amdgpu_sriov_vf(adev))
1304                 return 0;
1305
1306         sdma_v4_0_ctx_switch_enable(adev, false);
1307         sdma_v4_0_enable(adev, false);
1308
1309         return 0;
1310 }
1311
1312 static int sdma_v4_0_suspend(void *handle)
1313 {
1314         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1315
1316         return sdma_v4_0_hw_fini(adev);
1317 }
1318
1319 static int sdma_v4_0_resume(void *handle)
1320 {
1321         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1322
1323         return sdma_v4_0_hw_init(adev);
1324 }
1325
1326 static bool sdma_v4_0_is_idle(void *handle)
1327 {
1328         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1329         u32 i;
1330
1331         for (i = 0; i < adev->sdma.num_instances; i++) {
1332                 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1333
1334                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1335                         return false;
1336         }
1337
1338         return true;
1339 }
1340
1341 static int sdma_v4_0_wait_for_idle(void *handle)
1342 {
1343         unsigned i;
1344         u32 sdma0, sdma1;
1345         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1346
1347         for (i = 0; i < adev->usec_timeout; i++) {
1348                 sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1349                 sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1350
1351                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1352                         return 0;
1353                 udelay(1);
1354         }
1355         return -ETIMEDOUT;
1356 }
1357
1358 static int sdma_v4_0_soft_reset(void *handle)
1359 {
1360         /* todo */
1361
1362         return 0;
1363 }
1364
1365 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1366                                         struct amdgpu_irq_src *source,
1367                                         unsigned type,
1368                                         enum amdgpu_interrupt_state state)
1369 {
1370         u32 sdma_cntl;
1371
1372         u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ?
1373                 sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1374                 sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1375
1376         sdma_cntl = RREG32(reg_offset);
1377         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1378                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1379         WREG32(reg_offset, sdma_cntl);
1380
1381         return 0;
1382 }
1383
1384 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1385                                       struct amdgpu_irq_src *source,
1386                                       struct amdgpu_iv_entry *entry)
1387 {
1388         DRM_DEBUG("IH: SDMA trap\n");
1389         switch (entry->client_id) {
1390         case SOC15_IH_CLIENTID_SDMA0:
1391                 switch (entry->ring_id) {
1392                 case 0:
1393                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1394                         break;
1395                 case 1:
1396                         /* XXX compute */
1397                         break;
1398                 case 2:
1399                         /* XXX compute */
1400                         break;
1401                 case 3:
1402                         /* XXX page queue*/
1403                         break;
1404                 }
1405                 break;
1406         case SOC15_IH_CLIENTID_SDMA1:
1407                 switch (entry->ring_id) {
1408                 case 0:
1409                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1410                         break;
1411                 case 1:
1412                         /* XXX compute */
1413                         break;
1414                 case 2:
1415                         /* XXX compute */
1416                         break;
1417                 case 3:
1418                         /* XXX page queue*/
1419                         break;
1420                 }
1421                 break;
1422         }
1423         return 0;
1424 }
1425
1426 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1427                                               struct amdgpu_irq_src *source,
1428                                               struct amdgpu_iv_entry *entry)
1429 {
1430         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1431         schedule_work(&adev->reset_work);
1432         return 0;
1433 }
1434
1435
1436 static void sdma_v4_0_update_medium_grain_clock_gating(
1437                 struct amdgpu_device *adev,
1438                 bool enable)
1439 {
1440         uint32_t data, def;
1441
1442         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1443                 /* enable sdma0 clock gating */
1444                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1445                 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1446                           SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1447                           SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1448                           SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1449                           SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1450                           SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1451                           SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1452                           SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1453                 if (def != data)
1454                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1455
1456                 if (adev->sdma.num_instances > 1) {
1457                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1458                         data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1459                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1460                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1461                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1462                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1463                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1464                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1465                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1466                         if (def != data)
1467                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1468                 }
1469         } else {
1470                 /* disable sdma0 clock gating */
1471                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1472                 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1473                          SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1474                          SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1475                          SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1476                          SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1477                          SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1478                          SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1479                          SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1480
1481                 if (def != data)
1482                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1483
1484                 if (adev->sdma.num_instances > 1) {
1485                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1486                         data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1487                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1488                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1489                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1490                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1491                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1492                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1493                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1494                         if (def != data)
1495                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1496                 }
1497         }
1498 }
1499
1500
1501 static void sdma_v4_0_update_medium_grain_light_sleep(
1502                 struct amdgpu_device *adev,
1503                 bool enable)
1504 {
1505         uint32_t data, def;
1506
1507         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1508                 /* 1-not override: enable sdma0 mem light sleep */
1509                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1510                 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1511                 if (def != data)
1512                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1513
1514                 /* 1-not override: enable sdma1 mem light sleep */
1515                 if (adev->sdma.num_instances > 1) {
1516                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1517                         data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1518                         if (def != data)
1519                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1520                 }
1521         } else {
1522                 /* 0-override:disable sdma0 mem light sleep */
1523                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1524                 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1525                 if (def != data)
1526                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1527
1528                 /* 0-override:disable sdma1 mem light sleep */
1529                 if (adev->sdma.num_instances > 1) {
1530                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1531                         data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1532                         if (def != data)
1533                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1534                 }
1535         }
1536 }
1537
1538 static int sdma_v4_0_set_clockgating_state(void *handle,
1539                                           enum amd_clockgating_state state)
1540 {
1541         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1542
1543         if (amdgpu_sriov_vf(adev))
1544                 return 0;
1545
1546         switch (adev->asic_type) {
1547         case CHIP_VEGA10:
1548         case CHIP_VEGA12:
1549         case CHIP_VEGA20:
1550         case CHIP_RAVEN:
1551                 sdma_v4_0_update_medium_grain_clock_gating(adev,
1552                                 state == AMD_CG_STATE_GATE ? true : false);
1553                 sdma_v4_0_update_medium_grain_light_sleep(adev,
1554                                 state == AMD_CG_STATE_GATE ? true : false);
1555                 break;
1556         default:
1557                 break;
1558         }
1559         return 0;
1560 }
1561
1562 static int sdma_v4_0_set_powergating_state(void *handle,
1563                                           enum amd_powergating_state state)
1564 {
1565         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1566
1567         switch (adev->asic_type) {
1568         case CHIP_RAVEN:
1569                 sdma_v4_1_update_power_gating(adev,
1570                                 state == AMD_PG_STATE_GATE ? true : false);
1571                 break;
1572         default:
1573                 break;
1574         }
1575
1576         return 0;
1577 }
1578
1579 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
1580 {
1581         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1582         int data;
1583
1584         if (amdgpu_sriov_vf(adev))
1585                 *flags = 0;
1586
1587         /* AMD_CG_SUPPORT_SDMA_MGCG */
1588         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1589         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1590                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1591
1592         /* AMD_CG_SUPPORT_SDMA_LS */
1593         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1594         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1595                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1596 }
1597
1598 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
1599         .name = "sdma_v4_0",
1600         .early_init = sdma_v4_0_early_init,
1601         .late_init = NULL,
1602         .sw_init = sdma_v4_0_sw_init,
1603         .sw_fini = sdma_v4_0_sw_fini,
1604         .hw_init = sdma_v4_0_hw_init,
1605         .hw_fini = sdma_v4_0_hw_fini,
1606         .suspend = sdma_v4_0_suspend,
1607         .resume = sdma_v4_0_resume,
1608         .is_idle = sdma_v4_0_is_idle,
1609         .wait_for_idle = sdma_v4_0_wait_for_idle,
1610         .soft_reset = sdma_v4_0_soft_reset,
1611         .set_clockgating_state = sdma_v4_0_set_clockgating_state,
1612         .set_powergating_state = sdma_v4_0_set_powergating_state,
1613         .get_clockgating_state = sdma_v4_0_get_clockgating_state,
1614 };
1615
1616 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
1617         .type = AMDGPU_RING_TYPE_SDMA,
1618         .align_mask = 0xf,
1619         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1620         .support_64bit_ptrs = true,
1621         .vmhub = AMDGPU_MMHUB,
1622         .get_rptr = sdma_v4_0_ring_get_rptr,
1623         .get_wptr = sdma_v4_0_ring_get_wptr,
1624         .set_wptr = sdma_v4_0_ring_set_wptr,
1625         .emit_frame_size =
1626                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
1627                 3 + /* hdp invalidate */
1628                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
1629                 /* sdma_v4_0_ring_emit_vm_flush */
1630                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1631                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1632                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
1633         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
1634         .emit_ib = sdma_v4_0_ring_emit_ib,
1635         .emit_fence = sdma_v4_0_ring_emit_fence,
1636         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
1637         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
1638         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
1639         .test_ring = sdma_v4_0_ring_test_ring,
1640         .test_ib = sdma_v4_0_ring_test_ib,
1641         .insert_nop = sdma_v4_0_ring_insert_nop,
1642         .pad_ib = sdma_v4_0_ring_pad_ib,
1643         .emit_wreg = sdma_v4_0_ring_emit_wreg,
1644         .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
1645         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1646 };
1647
1648 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
1649 {
1650         int i;
1651
1652         for (i = 0; i < adev->sdma.num_instances; i++) {
1653                 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
1654                 adev->sdma.instance[i].ring.me = i;
1655         }
1656 }
1657
1658 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
1659         .set = sdma_v4_0_set_trap_irq_state,
1660         .process = sdma_v4_0_process_trap_irq,
1661 };
1662
1663 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
1664         .process = sdma_v4_0_process_illegal_inst_irq,
1665 };
1666
1667 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
1668 {
1669         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1670         adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
1671         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
1672 }
1673
1674 /**
1675  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
1676  *
1677  * @ring: amdgpu_ring structure holding ring information
1678  * @src_offset: src GPU address
1679  * @dst_offset: dst GPU address
1680  * @byte_count: number of bytes to xfer
1681  *
1682  * Copy GPU buffers using the DMA engine (VEGA10/12).
1683  * Used by the amdgpu ttm implementation to move pages if
1684  * registered as the asic copy callback.
1685  */
1686 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
1687                                        uint64_t src_offset,
1688                                        uint64_t dst_offset,
1689                                        uint32_t byte_count)
1690 {
1691         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1692                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1693         ib->ptr[ib->length_dw++] = byte_count - 1;
1694         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1695         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1696         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1697         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1698         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1699 }
1700
1701 /**
1702  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
1703  *
1704  * @ring: amdgpu_ring structure holding ring information
1705  * @src_data: value to write to buffer
1706  * @dst_offset: dst GPU address
1707  * @byte_count: number of bytes to xfer
1708  *
1709  * Fill GPU buffers using the DMA engine (VEGA10/12).
1710  */
1711 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
1712                                        uint32_t src_data,
1713                                        uint64_t dst_offset,
1714                                        uint32_t byte_count)
1715 {
1716         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1717         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1718         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1719         ib->ptr[ib->length_dw++] = src_data;
1720         ib->ptr[ib->length_dw++] = byte_count - 1;
1721 }
1722
1723 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
1724         .copy_max_bytes = 0x400000,
1725         .copy_num_dw = 7,
1726         .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
1727
1728         .fill_max_bytes = 0x400000,
1729         .fill_num_dw = 5,
1730         .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
1731 };
1732
1733 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
1734 {
1735         if (adev->mman.buffer_funcs == NULL) {
1736                 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
1737                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1738         }
1739 }
1740
1741 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
1742         .copy_pte_num_dw = 7,
1743         .copy_pte = sdma_v4_0_vm_copy_pte,
1744
1745         .write_pte = sdma_v4_0_vm_write_pte,
1746         .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
1747 };
1748
1749 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1750 {
1751         unsigned i;
1752
1753         if (adev->vm_manager.vm_pte_funcs == NULL) {
1754                 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
1755                 for (i = 0; i < adev->sdma.num_instances; i++)
1756                         adev->vm_manager.vm_pte_rings[i] =
1757                                 &adev->sdma.instance[i].ring;
1758
1759                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1760         }
1761 }
1762
1763 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
1764         .type = AMD_IP_BLOCK_TYPE_SDMA,
1765         .major = 4,
1766         .minor = 0,
1767         .rev = 0,
1768         .funcs = &sdma_v4_0_ip_funcs,
1769 };