2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "oss/oss_3_0_d.h"
33 #include "oss/oss_3_0_sh_mask.h"
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "tonga_sdma_pkt_open.h"
47 #include "ivsrcid/ivsrcid_vislands30.h"
49 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
50 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
51 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
52 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
57 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
59 SDMA0_REGISTER_OFFSET,
63 static const u32 golden_settings_tonga_a11[] =
65 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
66 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
67 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
68 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
69 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
70 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
71 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
72 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
73 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
74 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
77 static const u32 tonga_mgcg_cgcg_init[] =
79 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
80 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
83 static const u32 golden_settings_fiji_a10[] =
85 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
86 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
87 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
88 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
89 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
90 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
91 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
92 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
95 static const u32 fiji_mgcg_cgcg_init[] =
97 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
98 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
101 static const u32 golden_settings_polaris11_a11[] =
103 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
104 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
105 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
106 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
107 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
108 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
109 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
110 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
111 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
112 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
115 static const u32 golden_settings_polaris10_a11[] =
117 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
118 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
119 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
120 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
121 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
122 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
123 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
124 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
125 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
126 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
129 static const u32 cz_golden_settings_a11[] =
131 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
132 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
133 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
134 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
135 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
136 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
137 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
138 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
139 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
140 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
141 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
142 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
145 static const u32 cz_mgcg_cgcg_init[] =
147 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
148 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
151 static const u32 stoney_golden_settings_a11[] =
153 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
154 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
155 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
156 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
159 static const u32 stoney_mgcg_cgcg_init[] =
161 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
166 * Starting with CIK, the GPU has new asynchronous
167 * DMA engines. These engines are used for compute
168 * and gfx. There are two DMA engines (SDMA0, SDMA1)
169 * and each one supports 1 ring buffer used for gfx
170 * and 2 queues used for compute.
172 * The programming model is very similar to the CP
173 * (ring buffer, IBs, etc.), but sDMA has it's own
174 * packet format that is different from the PM4 format
175 * used by the CP. sDMA supports copying data, writing
176 * embedded data, solid fills, and a number of other
177 * things. It also has support for tiling/detiling of
181 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
183 switch (adev->asic_type) {
185 amdgpu_device_program_register_sequence(adev,
187 ARRAY_SIZE(fiji_mgcg_cgcg_init));
188 amdgpu_device_program_register_sequence(adev,
189 golden_settings_fiji_a10,
190 ARRAY_SIZE(golden_settings_fiji_a10));
193 amdgpu_device_program_register_sequence(adev,
194 tonga_mgcg_cgcg_init,
195 ARRAY_SIZE(tonga_mgcg_cgcg_init));
196 amdgpu_device_program_register_sequence(adev,
197 golden_settings_tonga_a11,
198 ARRAY_SIZE(golden_settings_tonga_a11));
203 amdgpu_device_program_register_sequence(adev,
204 golden_settings_polaris11_a11,
205 ARRAY_SIZE(golden_settings_polaris11_a11));
208 amdgpu_device_program_register_sequence(adev,
209 golden_settings_polaris10_a11,
210 ARRAY_SIZE(golden_settings_polaris10_a11));
213 amdgpu_device_program_register_sequence(adev,
215 ARRAY_SIZE(cz_mgcg_cgcg_init));
216 amdgpu_device_program_register_sequence(adev,
217 cz_golden_settings_a11,
218 ARRAY_SIZE(cz_golden_settings_a11));
221 amdgpu_device_program_register_sequence(adev,
222 stoney_mgcg_cgcg_init,
223 ARRAY_SIZE(stoney_mgcg_cgcg_init));
224 amdgpu_device_program_register_sequence(adev,
225 stoney_golden_settings_a11,
226 ARRAY_SIZE(stoney_golden_settings_a11));
233 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
236 for (i = 0; i < adev->sdma.num_instances; i++) {
237 release_firmware(adev->sdma.instance[i].fw);
238 adev->sdma.instance[i].fw = NULL;
243 * sdma_v3_0_init_microcode - load ucode images from disk
245 * @adev: amdgpu_device pointer
247 * Use the firmware interface to load the ucode images into
248 * the driver (not loaded into hw).
249 * Returns 0 on success, error on failure.
251 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
253 const char *chip_name;
256 struct amdgpu_firmware_info *info = NULL;
257 const struct common_firmware_header *header = NULL;
258 const struct sdma_firmware_header_v1_0 *hdr;
262 switch (adev->asic_type) {
270 chip_name = "polaris10";
273 chip_name = "polaris11";
276 chip_name = "polaris12";
282 chip_name = "carrizo";
285 chip_name = "stoney";
290 for (i = 0; i < adev->sdma.num_instances; i++) {
292 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
294 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
295 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
298 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
301 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
302 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
303 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
304 if (adev->sdma.instance[i].feature_version >= 20)
305 adev->sdma.instance[i].burst_nop = true;
307 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
308 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
309 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
310 info->fw = adev->sdma.instance[i].fw;
311 header = (const struct common_firmware_header *)info->fw->data;
312 adev->firmware.fw_size +=
313 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
318 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name);
319 for (i = 0; i < adev->sdma.num_instances; i++) {
320 release_firmware(adev->sdma.instance[i].fw);
321 adev->sdma.instance[i].fw = NULL;
328 * sdma_v3_0_ring_get_rptr - get the current read pointer
330 * @ring: amdgpu ring pointer
332 * Get the current rptr from the hardware (VI+).
334 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
336 /* XXX check if swapping is necessary on BE */
337 return ring->adev->wb.wb[ring->rptr_offs] >> 2;
341 * sdma_v3_0_ring_get_wptr - get the current write pointer
343 * @ring: amdgpu ring pointer
345 * Get the current wptr from the hardware (VI+).
347 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
349 struct amdgpu_device *adev = ring->adev;
352 if (ring->use_doorbell || ring->use_pollmem) {
353 /* XXX check if swapping is necessary on BE */
354 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
356 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
363 * sdma_v3_0_ring_set_wptr - commit the write pointer
365 * @ring: amdgpu ring pointer
367 * Write the wptr back to the hardware (VI+).
369 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
371 struct amdgpu_device *adev = ring->adev;
373 if (ring->use_doorbell) {
374 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
375 /* XXX check if swapping is necessary on BE */
376 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
377 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);
378 } else if (ring->use_pollmem) {
379 u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];
381 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
383 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
387 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
389 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
392 for (i = 0; i < count; i++)
393 if (sdma && sdma->burst_nop && (i == 0))
394 amdgpu_ring_write(ring, ring->funcs->nop |
395 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
397 amdgpu_ring_write(ring, ring->funcs->nop);
401 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
403 * @ring: amdgpu ring pointer
404 * @ib: IB object to schedule
406 * Schedule an IB in the DMA ring (VI).
408 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
409 struct amdgpu_ib *ib,
410 unsigned vmid, bool ctx_switch)
412 /* IB packet must end on a 8 DW boundary */
413 sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
415 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
416 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
417 /* base must be 32 byte aligned */
418 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
419 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
420 amdgpu_ring_write(ring, ib->length_dw);
421 amdgpu_ring_write(ring, 0);
422 amdgpu_ring_write(ring, 0);
427 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
429 * @ring: amdgpu ring pointer
431 * Emit an hdp flush packet on the requested DMA ring.
433 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
435 u32 ref_and_mask = 0;
438 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
440 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
442 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
443 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
444 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
445 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
446 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
447 amdgpu_ring_write(ring, ref_and_mask); /* reference */
448 amdgpu_ring_write(ring, ref_and_mask); /* mask */
449 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
450 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
454 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
456 * @ring: amdgpu ring pointer
457 * @fence: amdgpu fence object
459 * Add a DMA fence packet to the ring to write
460 * the fence seq number and DMA trap packet to generate
461 * an interrupt if needed (VI).
463 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
466 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
467 /* write the fence */
468 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
469 amdgpu_ring_write(ring, lower_32_bits(addr));
470 amdgpu_ring_write(ring, upper_32_bits(addr));
471 amdgpu_ring_write(ring, lower_32_bits(seq));
473 /* optionally write high bits as well */
476 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
477 amdgpu_ring_write(ring, lower_32_bits(addr));
478 amdgpu_ring_write(ring, upper_32_bits(addr));
479 amdgpu_ring_write(ring, upper_32_bits(seq));
482 /* generate an interrupt */
483 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
484 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
488 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
490 * @adev: amdgpu_device pointer
492 * Stop the gfx async dma ring buffers (VI).
494 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
496 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
497 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
498 u32 rb_cntl, ib_cntl;
501 if ((adev->mman.buffer_funcs_ring == sdma0) ||
502 (adev->mman.buffer_funcs_ring == sdma1))
503 amdgpu_ttm_set_buffer_funcs_status(adev, false);
505 for (i = 0; i < adev->sdma.num_instances; i++) {
506 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
507 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
508 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
509 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
510 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
511 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
513 sdma0->ready = false;
514 sdma1->ready = false;
518 * sdma_v3_0_rlc_stop - stop the compute async dma engines
520 * @adev: amdgpu_device pointer
522 * Stop the compute async dma queues (VI).
524 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
530 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
532 * @adev: amdgpu_device pointer
533 * @enable: enable/disable the DMA MEs context switch.
535 * Halt or unhalt the async dma engines context switch (VI).
537 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
539 u32 f32_cntl, phase_quantum = 0;
542 if (amdgpu_sdma_phase_quantum) {
543 unsigned value = amdgpu_sdma_phase_quantum;
546 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
547 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
548 value = (value + 1) >> 1;
551 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
552 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
553 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
554 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
555 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
556 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
558 "clamping sdma_phase_quantum to %uK clock cycles\n",
562 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
563 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
566 for (i = 0; i < adev->sdma.num_instances; i++) {
567 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
569 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
570 AUTO_CTXSW_ENABLE, 1);
571 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
573 if (amdgpu_sdma_phase_quantum) {
574 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
576 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
580 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
581 AUTO_CTXSW_ENABLE, 0);
582 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
586 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
591 * sdma_v3_0_enable - stop the async dma engines
593 * @adev: amdgpu_device pointer
594 * @enable: enable/disable the DMA MEs.
596 * Halt or unhalt the async dma engines (VI).
598 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
604 sdma_v3_0_gfx_stop(adev);
605 sdma_v3_0_rlc_stop(adev);
608 for (i = 0; i < adev->sdma.num_instances; i++) {
609 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
611 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
613 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
614 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
619 * sdma_v3_0_gfx_resume - setup and start the async dma engines
621 * @adev: amdgpu_device pointer
623 * Set up the gfx DMA ring buffers and enable them (VI).
624 * Returns 0 for success, error for failure.
626 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
628 struct amdgpu_ring *ring;
629 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
636 for (i = 0; i < adev->sdma.num_instances; i++) {
637 ring = &adev->sdma.instance[i].ring;
638 amdgpu_ring_clear_ring(ring);
639 wb_offset = (ring->rptr_offs * 4);
641 mutex_lock(&adev->srbm_mutex);
642 for (j = 0; j < 16; j++) {
643 vi_srbm_select(adev, 0, 0, 0, j);
645 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
646 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
648 vi_srbm_select(adev, 0, 0, 0, 0);
649 mutex_unlock(&adev->srbm_mutex);
651 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
652 adev->gfx.config.gb_addr_config & 0x70);
654 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
656 /* Set ring buffer size in dwords */
657 rb_bufsz = order_base_2(ring->ring_size / 4);
658 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
659 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
661 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
662 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
663 RPTR_WRITEBACK_SWAP_ENABLE, 1);
665 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
667 /* Initialize the ring buffer's read and write pointers */
669 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
670 sdma_v3_0_ring_set_wptr(ring);
671 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
672 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
674 /* set the wb address whether it's enabled or not */
675 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
676 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
677 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
678 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
680 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
682 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
683 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
685 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
687 if (ring->use_doorbell) {
688 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
689 OFFSET, ring->doorbell_index);
690 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
692 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
694 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
696 /* setup the wptr shadow polling */
697 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
699 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
700 lower_32_bits(wptr_gpu_addr));
701 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
702 upper_32_bits(wptr_gpu_addr));
703 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
704 if (ring->use_pollmem) {
705 /*wptr polling is not enogh fast, directly clean the wptr register */
706 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
707 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
708 SDMA0_GFX_RB_WPTR_POLL_CNTL,
711 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
712 SDMA0_GFX_RB_WPTR_POLL_CNTL,
715 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
718 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
719 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
721 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
722 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
724 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
727 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
733 sdma_v3_0_enable(adev, true);
734 /* enable sdma ring preemption */
735 sdma_v3_0_ctx_switch_enable(adev, true);
737 for (i = 0; i < adev->sdma.num_instances; i++) {
738 ring = &adev->sdma.instance[i].ring;
739 r = amdgpu_ring_test_ring(ring);
745 if (adev->mman.buffer_funcs_ring == ring)
746 amdgpu_ttm_set_buffer_funcs_status(adev, true);
753 * sdma_v3_0_rlc_resume - setup and start the async dma engines
755 * @adev: amdgpu_device pointer
757 * Set up the compute DMA queues and enable them (VI).
758 * Returns 0 for success, error for failure.
760 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
767 * sdma_v3_0_load_microcode - load the sDMA ME ucode
769 * @adev: amdgpu_device pointer
771 * Loads the sDMA0/1 ucode.
772 * Returns 0 for success, -EINVAL if the ucode is not available.
774 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
776 const struct sdma_firmware_header_v1_0 *hdr;
777 const __le32 *fw_data;
782 sdma_v3_0_enable(adev, false);
784 for (i = 0; i < adev->sdma.num_instances; i++) {
785 if (!adev->sdma.instance[i].fw)
787 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
788 amdgpu_ucode_print_sdma_hdr(&hdr->header);
789 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
790 fw_data = (const __le32 *)
791 (adev->sdma.instance[i].fw->data +
792 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
793 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
794 for (j = 0; j < fw_size; j++)
795 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
796 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
803 * sdma_v3_0_start - setup and start the async dma engines
805 * @adev: amdgpu_device pointer
807 * Set up the DMA engines and enable them (VI).
808 * Returns 0 for success, error for failure.
810 static int sdma_v3_0_start(struct amdgpu_device *adev)
814 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
815 r = sdma_v3_0_load_microcode(adev);
820 /* disable sdma engine before programing it */
821 sdma_v3_0_ctx_switch_enable(adev, false);
822 sdma_v3_0_enable(adev, false);
824 /* start the gfx rings and rlc compute queues */
825 r = sdma_v3_0_gfx_resume(adev);
828 r = sdma_v3_0_rlc_resume(adev);
836 * sdma_v3_0_ring_test_ring - simple async dma engine test
838 * @ring: amdgpu_ring structure holding ring information
840 * Test the DMA engine by writing using it to write an
841 * value to memory. (VI).
842 * Returns 0 for success, error for failure.
844 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
846 struct amdgpu_device *adev = ring->adev;
853 r = amdgpu_device_wb_get(adev, &index);
855 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
859 gpu_addr = adev->wb.gpu_addr + (index * 4);
861 adev->wb.wb[index] = cpu_to_le32(tmp);
863 r = amdgpu_ring_alloc(ring, 5);
865 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
866 amdgpu_device_wb_free(adev, index);
870 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
871 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
872 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
873 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
874 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
875 amdgpu_ring_write(ring, 0xDEADBEEF);
876 amdgpu_ring_commit(ring);
878 for (i = 0; i < adev->usec_timeout; i++) {
879 tmp = le32_to_cpu(adev->wb.wb[index]);
880 if (tmp == 0xDEADBEEF)
885 if (i < adev->usec_timeout) {
886 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
888 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
892 amdgpu_device_wb_free(adev, index);
898 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
900 * @ring: amdgpu_ring structure holding ring information
902 * Test a simple IB in the DMA ring (VI).
903 * Returns 0 on success, error on failure.
905 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
907 struct amdgpu_device *adev = ring->adev;
909 struct dma_fence *f = NULL;
915 r = amdgpu_device_wb_get(adev, &index);
917 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
921 gpu_addr = adev->wb.gpu_addr + (index * 4);
923 adev->wb.wb[index] = cpu_to_le32(tmp);
924 memset(&ib, 0, sizeof(ib));
925 r = amdgpu_ib_get(adev, NULL, 256, &ib);
927 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
931 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
932 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
933 ib.ptr[1] = lower_32_bits(gpu_addr);
934 ib.ptr[2] = upper_32_bits(gpu_addr);
935 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
936 ib.ptr[4] = 0xDEADBEEF;
937 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
938 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
939 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
942 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
946 r = dma_fence_wait_timeout(f, false, timeout);
948 DRM_ERROR("amdgpu: IB test timed out\n");
952 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
955 tmp = le32_to_cpu(adev->wb.wb[index]);
956 if (tmp == 0xDEADBEEF) {
957 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
960 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
964 amdgpu_ib_free(adev, &ib, NULL);
967 amdgpu_device_wb_free(adev, index);
972 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
974 * @ib: indirect buffer to fill with commands
975 * @pe: addr of the page entry
976 * @src: src addr to copy from
977 * @count: number of page entries to update
979 * Update PTEs by copying them from the GART using sDMA (CIK).
981 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
982 uint64_t pe, uint64_t src,
985 unsigned bytes = count * 8;
987 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
988 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
989 ib->ptr[ib->length_dw++] = bytes;
990 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
991 ib->ptr[ib->length_dw++] = lower_32_bits(src);
992 ib->ptr[ib->length_dw++] = upper_32_bits(src);
993 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
994 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
998 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
1000 * @ib: indirect buffer to fill with commands
1001 * @pe: addr of the page entry
1002 * @value: dst addr to write into pe
1003 * @count: number of page entries to update
1004 * @incr: increase next addr by incr bytes
1006 * Update PTEs by writing them manually using sDMA (CIK).
1008 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1009 uint64_t value, unsigned count,
1012 unsigned ndw = count * 2;
1014 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1015 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1016 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1017 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1018 ib->ptr[ib->length_dw++] = ndw;
1019 for (; ndw > 0; ndw -= 2) {
1020 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1021 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1027 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
1029 * @ib: indirect buffer to fill with commands
1030 * @pe: addr of the page entry
1031 * @addr: dst addr to write into pe
1032 * @count: number of page entries to update
1033 * @incr: increase next addr by incr bytes
1034 * @flags: access flags
1036 * Update the page tables using sDMA (CIK).
1038 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
1039 uint64_t addr, unsigned count,
1040 uint32_t incr, uint64_t flags)
1042 /* for physically contiguous pages (vram) */
1043 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1044 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1045 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1046 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1047 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1048 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1049 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1050 ib->ptr[ib->length_dw++] = incr; /* increment size */
1051 ib->ptr[ib->length_dw++] = 0;
1052 ib->ptr[ib->length_dw++] = count; /* number of entries */
1056 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1058 * @ib: indirect buffer to fill with padding
1061 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1063 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1067 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1068 for (i = 0; i < pad_count; i++)
1069 if (sdma && sdma->burst_nop && (i == 0))
1070 ib->ptr[ib->length_dw++] =
1071 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1072 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1074 ib->ptr[ib->length_dw++] =
1075 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1079 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1081 * @ring: amdgpu_ring pointer
1083 * Make sure all previous operations are completed (CIK).
1085 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1087 uint32_t seq = ring->fence_drv.sync_seq;
1088 uint64_t addr = ring->fence_drv.gpu_addr;
1091 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1092 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1093 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1094 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1095 amdgpu_ring_write(ring, addr & 0xfffffffc);
1096 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1097 amdgpu_ring_write(ring, seq); /* reference */
1098 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1099 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1100 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1104 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1106 * @ring: amdgpu_ring pointer
1107 * @vm: amdgpu_vm pointer
1109 * Update the page table base and flush the VM TLB
1112 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1113 unsigned vmid, uint64_t pd_addr)
1115 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1117 /* wait for flush */
1118 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1119 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1120 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1121 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1122 amdgpu_ring_write(ring, 0);
1123 amdgpu_ring_write(ring, 0); /* reference */
1124 amdgpu_ring_write(ring, 0); /* mask */
1125 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1126 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1129 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring,
1130 uint32_t reg, uint32_t val)
1132 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1133 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1134 amdgpu_ring_write(ring, reg);
1135 amdgpu_ring_write(ring, val);
1138 static int sdma_v3_0_early_init(void *handle)
1140 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1142 switch (adev->asic_type) {
1144 adev->sdma.num_instances = 1;
1147 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1151 sdma_v3_0_set_ring_funcs(adev);
1152 sdma_v3_0_set_buffer_funcs(adev);
1153 sdma_v3_0_set_vm_pte_funcs(adev);
1154 sdma_v3_0_set_irq_funcs(adev);
1159 static int sdma_v3_0_sw_init(void *handle)
1161 struct amdgpu_ring *ring;
1163 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1165 /* SDMA trap event */
1166 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
1167 &adev->sdma.trap_irq);
1171 /* SDMA Privileged inst */
1172 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241,
1173 &adev->sdma.illegal_inst_irq);
1177 /* SDMA Privileged inst */
1178 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
1179 &adev->sdma.illegal_inst_irq);
1183 r = sdma_v3_0_init_microcode(adev);
1185 DRM_ERROR("Failed to load sdma firmware!\n");
1189 for (i = 0; i < adev->sdma.num_instances; i++) {
1190 ring = &adev->sdma.instance[i].ring;
1191 ring->ring_obj = NULL;
1192 if (!amdgpu_sriov_vf(adev)) {
1193 ring->use_doorbell = true;
1194 ring->doorbell_index = (i == 0) ?
1195 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1197 ring->use_pollmem = true;
1200 sprintf(ring->name, "sdma%d", i);
1201 r = amdgpu_ring_init(adev, ring, 1024,
1202 &adev->sdma.trap_irq,
1204 AMDGPU_SDMA_IRQ_TRAP0 :
1205 AMDGPU_SDMA_IRQ_TRAP1);
1213 static int sdma_v3_0_sw_fini(void *handle)
1215 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1218 for (i = 0; i < adev->sdma.num_instances; i++)
1219 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1221 sdma_v3_0_free_microcode(adev);
1225 static int sdma_v3_0_hw_init(void *handle)
1228 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1230 sdma_v3_0_init_golden_registers(adev);
1232 r = sdma_v3_0_start(adev);
1239 static int sdma_v3_0_hw_fini(void *handle)
1241 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1243 sdma_v3_0_ctx_switch_enable(adev, false);
1244 sdma_v3_0_enable(adev, false);
1249 static int sdma_v3_0_suspend(void *handle)
1251 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1253 return sdma_v3_0_hw_fini(adev);
1256 static int sdma_v3_0_resume(void *handle)
1258 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1260 return sdma_v3_0_hw_init(adev);
1263 static bool sdma_v3_0_is_idle(void *handle)
1265 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1266 u32 tmp = RREG32(mmSRBM_STATUS2);
1268 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1269 SRBM_STATUS2__SDMA1_BUSY_MASK))
1275 static int sdma_v3_0_wait_for_idle(void *handle)
1279 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1281 for (i = 0; i < adev->usec_timeout; i++) {
1282 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1283 SRBM_STATUS2__SDMA1_BUSY_MASK);
1292 static bool sdma_v3_0_check_soft_reset(void *handle)
1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1295 u32 srbm_soft_reset = 0;
1296 u32 tmp = RREG32(mmSRBM_STATUS2);
1298 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1299 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1300 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1301 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1304 if (srbm_soft_reset) {
1305 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1308 adev->sdma.srbm_soft_reset = 0;
1313 static int sdma_v3_0_pre_soft_reset(void *handle)
1315 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1316 u32 srbm_soft_reset = 0;
1318 if (!adev->sdma.srbm_soft_reset)
1321 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1323 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1324 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1325 sdma_v3_0_ctx_switch_enable(adev, false);
1326 sdma_v3_0_enable(adev, false);
1332 static int sdma_v3_0_post_soft_reset(void *handle)
1334 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1335 u32 srbm_soft_reset = 0;
1337 if (!adev->sdma.srbm_soft_reset)
1340 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1342 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1343 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1344 sdma_v3_0_gfx_resume(adev);
1345 sdma_v3_0_rlc_resume(adev);
1351 static int sdma_v3_0_soft_reset(void *handle)
1353 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1354 u32 srbm_soft_reset = 0;
1357 if (!adev->sdma.srbm_soft_reset)
1360 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1362 if (srbm_soft_reset) {
1363 tmp = RREG32(mmSRBM_SOFT_RESET);
1364 tmp |= srbm_soft_reset;
1365 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1366 WREG32(mmSRBM_SOFT_RESET, tmp);
1367 tmp = RREG32(mmSRBM_SOFT_RESET);
1371 tmp &= ~srbm_soft_reset;
1372 WREG32(mmSRBM_SOFT_RESET, tmp);
1373 tmp = RREG32(mmSRBM_SOFT_RESET);
1375 /* Wait a little for things to settle down */
1382 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1383 struct amdgpu_irq_src *source,
1385 enum amdgpu_interrupt_state state)
1390 case AMDGPU_SDMA_IRQ_TRAP0:
1392 case AMDGPU_IRQ_STATE_DISABLE:
1393 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1394 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1395 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1397 case AMDGPU_IRQ_STATE_ENABLE:
1398 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1399 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1400 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1406 case AMDGPU_SDMA_IRQ_TRAP1:
1408 case AMDGPU_IRQ_STATE_DISABLE:
1409 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1410 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1411 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1413 case AMDGPU_IRQ_STATE_ENABLE:
1414 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1415 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1416 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1428 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1429 struct amdgpu_irq_src *source,
1430 struct amdgpu_iv_entry *entry)
1432 u8 instance_id, queue_id;
1434 instance_id = (entry->ring_id & 0x3) >> 0;
1435 queue_id = (entry->ring_id & 0xc) >> 2;
1436 DRM_DEBUG("IH: SDMA trap\n");
1437 switch (instance_id) {
1441 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1454 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1468 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1469 struct amdgpu_irq_src *source,
1470 struct amdgpu_iv_entry *entry)
1472 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1473 schedule_work(&adev->reset_work);
1477 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1478 struct amdgpu_device *adev,
1481 uint32_t temp, data;
1484 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1485 for (i = 0; i < adev->sdma.num_instances; i++) {
1486 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1487 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1488 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1489 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1490 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1491 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1492 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1493 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1494 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1496 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1499 for (i = 0; i < adev->sdma.num_instances; i++) {
1500 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1501 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1502 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1503 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1504 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1505 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1506 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1507 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1508 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1511 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1516 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1517 struct amdgpu_device *adev,
1520 uint32_t temp, data;
1523 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1524 for (i = 0; i < adev->sdma.num_instances; i++) {
1525 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1526 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1529 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1532 for (i = 0; i < adev->sdma.num_instances; i++) {
1533 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1534 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1537 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1542 static int sdma_v3_0_set_clockgating_state(void *handle,
1543 enum amd_clockgating_state state)
1545 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1547 if (amdgpu_sriov_vf(adev))
1550 switch (adev->asic_type) {
1554 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1555 state == AMD_CG_STATE_GATE);
1556 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1557 state == AMD_CG_STATE_GATE);
1565 static int sdma_v3_0_set_powergating_state(void *handle,
1566 enum amd_powergating_state state)
1571 static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags)
1573 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1576 if (amdgpu_sriov_vf(adev))
1579 /* AMD_CG_SUPPORT_SDMA_MGCG */
1580 data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
1581 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
1582 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1584 /* AMD_CG_SUPPORT_SDMA_LS */
1585 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
1586 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1587 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1590 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1591 .name = "sdma_v3_0",
1592 .early_init = sdma_v3_0_early_init,
1594 .sw_init = sdma_v3_0_sw_init,
1595 .sw_fini = sdma_v3_0_sw_fini,
1596 .hw_init = sdma_v3_0_hw_init,
1597 .hw_fini = sdma_v3_0_hw_fini,
1598 .suspend = sdma_v3_0_suspend,
1599 .resume = sdma_v3_0_resume,
1600 .is_idle = sdma_v3_0_is_idle,
1601 .wait_for_idle = sdma_v3_0_wait_for_idle,
1602 .check_soft_reset = sdma_v3_0_check_soft_reset,
1603 .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1604 .post_soft_reset = sdma_v3_0_post_soft_reset,
1605 .soft_reset = sdma_v3_0_soft_reset,
1606 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1607 .set_powergating_state = sdma_v3_0_set_powergating_state,
1608 .get_clockgating_state = sdma_v3_0_get_clockgating_state,
1611 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1612 .type = AMDGPU_RING_TYPE_SDMA,
1614 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1615 .support_64bit_ptrs = false,
1616 .get_rptr = sdma_v3_0_ring_get_rptr,
1617 .get_wptr = sdma_v3_0_ring_get_wptr,
1618 .set_wptr = sdma_v3_0_ring_set_wptr,
1620 6 + /* sdma_v3_0_ring_emit_hdp_flush */
1621 3 + /* hdp invalidate */
1622 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1623 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */
1624 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1625 .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
1626 .emit_ib = sdma_v3_0_ring_emit_ib,
1627 .emit_fence = sdma_v3_0_ring_emit_fence,
1628 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1629 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1630 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1631 .test_ring = sdma_v3_0_ring_test_ring,
1632 .test_ib = sdma_v3_0_ring_test_ib,
1633 .insert_nop = sdma_v3_0_ring_insert_nop,
1634 .pad_ib = sdma_v3_0_ring_pad_ib,
1635 .emit_wreg = sdma_v3_0_ring_emit_wreg,
1638 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1642 for (i = 0; i < adev->sdma.num_instances; i++) {
1643 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1644 adev->sdma.instance[i].ring.me = i;
1648 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1649 .set = sdma_v3_0_set_trap_irq_state,
1650 .process = sdma_v3_0_process_trap_irq,
1653 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1654 .process = sdma_v3_0_process_illegal_inst_irq,
1657 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1659 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1660 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1661 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1665 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1667 * @ring: amdgpu_ring structure holding ring information
1668 * @src_offset: src GPU address
1669 * @dst_offset: dst GPU address
1670 * @byte_count: number of bytes to xfer
1672 * Copy GPU buffers using the DMA engine (VI).
1673 * Used by the amdgpu ttm implementation to move pages if
1674 * registered as the asic copy callback.
1676 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1677 uint64_t src_offset,
1678 uint64_t dst_offset,
1679 uint32_t byte_count)
1681 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1682 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1683 ib->ptr[ib->length_dw++] = byte_count;
1684 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1685 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1686 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1687 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1688 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1692 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1694 * @ring: amdgpu_ring structure holding ring information
1695 * @src_data: value to write to buffer
1696 * @dst_offset: dst GPU address
1697 * @byte_count: number of bytes to xfer
1699 * Fill GPU buffers using the DMA engine (VI).
1701 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1703 uint64_t dst_offset,
1704 uint32_t byte_count)
1706 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1707 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1708 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1709 ib->ptr[ib->length_dw++] = src_data;
1710 ib->ptr[ib->length_dw++] = byte_count;
1713 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1714 .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1716 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1718 .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1720 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1723 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1725 if (adev->mman.buffer_funcs == NULL) {
1726 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1727 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1731 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1732 .copy_pte_num_dw = 7,
1733 .copy_pte = sdma_v3_0_vm_copy_pte,
1735 .write_pte = sdma_v3_0_vm_write_pte,
1736 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1739 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1743 if (adev->vm_manager.vm_pte_funcs == NULL) {
1744 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1745 for (i = 0; i < adev->sdma.num_instances; i++)
1746 adev->vm_manager.vm_pte_rings[i] =
1747 &adev->sdma.instance[i].ring;
1749 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1753 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
1755 .type = AMD_IP_BLOCK_TYPE_SDMA,
1759 .funcs = &sdma_v3_0_ip_funcs,
1762 const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
1764 .type = AMD_IP_BLOCK_TYPE_SDMA,
1768 .funcs = &sdma_v3_0_ip_funcs,