drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_3_0_d.h"
  33 #include "oss/oss_3_0_sh_mask.h"
  34
  35 #include "gmc/gmc_8_1_d.h"
  36 #include "gmc/gmc_8_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "tonga_sdma_pkt_open.h"
  46
  47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  51
  52 /*(DEBLOBBED)*/
  53
  54 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  55 {
  56         SDMA0_REGISTER_OFFSET,
  57         SDMA1_REGISTER_OFFSET
  58 };
  59
  60 static const u32 golden_settings_tonga_a11[] =
  61 {
  62         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  63         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  64         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  65         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  66         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  67         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  68         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  69         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  70         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  71         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  72 };
  73
  74 static const u32 tonga_mgcg_cgcg_init[] =
  75 {
  76         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  77         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  78 };
  79
  80 static const u32 golden_settings_fiji_a10[] =
  81 {
  82         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  83         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  84         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  85         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  86         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  87         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  88         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  89         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  90 };
  91
  92 static const u32 fiji_mgcg_cgcg_init[] =
  93 {
  94         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  95         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  96 };
  97
  98 static const u32 cz_golden_settings_a11[] =
  99 {
 100         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 101         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 102         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 103         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 104         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 105         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 106         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 107         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 108         mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
 109         mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
 110         mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 111         mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 112 };
 113
 114 static const u32 cz_mgcg_cgcg_init[] =
 115 {
 116         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 117         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 118 };
 119
 120 static const u32 stoney_golden_settings_a11[] =
 121 {
 122         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 123         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 124         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 125         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 126 };
 127
 128 static const u32 stoney_mgcg_cgcg_init[] =
 129 {
 130         mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
 131 };
 132
 133 /*
 134  * sDMA - System DMA
 135  * Starting with CIK, the GPU has new asynchronous
 136  * DMA engines.  These engines are used for compute
 137  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
 138  * and each one supports 1 ring buffer used for gfx
 139  * and 2 queues used for compute.
 140  *
 141  * The programming model is very similar to the CP
 142  * (ring buffer, IBs, etc.), but sDMA has it's own
 143  * packet format that is different from the PM4 format
 144  * used by the CP. sDMA supports copying data, writing
 145  * embedded data, solid fills, and a number of other
 146  * things.  It also has support for tiling/detiling of
 147  * buffers.
 148  */
 149
 150 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 151 {
 152         switch (adev->asic_type) {
 153         case CHIP_FIJI:
 154                 amdgpu_program_register_sequence(adev,
 155                                                  fiji_mgcg_cgcg_init,
 156                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 157                 amdgpu_program_register_sequence(adev,
 158                                                  golden_settings_fiji_a10,
 159                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 160                 break;
 161         case CHIP_TONGA:
 162                 amdgpu_program_register_sequence(adev,
 163                                                  tonga_mgcg_cgcg_init,
 164                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 165                 amdgpu_program_register_sequence(adev,
 166                                                  golden_settings_tonga_a11,
 167                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 168                 break;
 169         case CHIP_CARRIZO:
 170                 amdgpu_program_register_sequence(adev,
 171                                                  cz_mgcg_cgcg_init,
 172                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 173                 amdgpu_program_register_sequence(adev,
 174                                                  cz_golden_settings_a11,
 175                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 176                 break;
 177         case CHIP_STONEY:
 178                 amdgpu_program_register_sequence(adev,
 179                                                  stoney_mgcg_cgcg_init,
 180                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 181                 amdgpu_program_register_sequence(adev,
 182                                                  stoney_golden_settings_a11,
 183                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 184                 break;
 185         default:
 186                 break;
 187         }
 188 }
 189
 190 /**
 191  * sdma_v3_0_init_microcode - load ucode images from disk
 192  *
 193  * @adev: amdgpu_device pointer
 194  *
 195  * Use the firmware interface to load the ucode images into
 196  * the driver (not loaded into hw).
 197  * Returns 0 on success, error on failure.
 198  */
 199 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 200 {
 201         const char *chip_name;
 202         char fw_name[30];
 203         int err = 0, i;
 204         struct amdgpu_firmware_info *info = NULL;
 205         const struct common_firmware_header *header = NULL;
 206         const struct sdma_firmware_header_v1_0 *hdr;
 207
 208         DRM_DEBUG("\n");
 209
 210         switch (adev->asic_type) {
 211         case CHIP_TONGA:
 212                 chip_name = "tonga";
 213                 break;
 214         case CHIP_FIJI:
 215                 chip_name = "fiji";
 216                 break;
 217         case CHIP_CARRIZO:
 218                 chip_name = "carrizo";
 219                 break;
 220         case CHIP_STONEY:
 221                 chip_name = "stoney";
 222                 break;
 223         default: BUG();
 224         }
 225
 226         for (i = 0; i < adev->sdma.num_instances; i++) {
 227                 if (i == 0)
 228                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 229                 else
 230                         snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
 231                 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 232                 if (err)
 233                         goto out;
 234                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 235                 if (err)
 236                         goto out;
 237                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 238                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 239                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 240                 if (adev->sdma.instance[i].feature_version >= 20)
 241                         adev->sdma.instance[i].burst_nop = true;
 242
 243                 if (adev->firmware.smu_load) {
 244                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 245                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 246                         info->fw = adev->sdma.instance[i].fw;
 247                         header = (const struct common_firmware_header *)info->fw->data;
 248                         adev->firmware.fw_size +=
 249                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 250                 }
 251         }
 252 out:
 253         if (err) {
 254                 printk(KERN_ERR
 255                        "sdma_v3_0: Failed to load firmware \"%s\"\n",
 256                        fw_name);
 257                 for (i = 0; i < adev->sdma.num_instances; i++) {
 258                         release_firmware(adev->sdma.instance[i].fw);
 259                         adev->sdma.instance[i].fw = NULL;
 260                 }
 261         }
 262         return err;
 263 }
 264
 265 /**
 266  * sdma_v3_0_ring_get_rptr - get the current read pointer
 267  *
 268  * @ring: amdgpu ring pointer
 269  *
 270  * Get the current rptr from the hardware (VI+).
 271  */
 272 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 273 {
 274         u32 rptr;
 275
 276         /* XXX check if swapping is necessary on BE */
 277         rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
 278
 279         return rptr;
 280 }
 281
 282 /**
 283  * sdma_v3_0_ring_get_wptr - get the current write pointer
 284  *
 285  * @ring: amdgpu ring pointer
 286  *
 287  * Get the current wptr from the hardware (VI+).
 288  */
 289 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 290 {
 291         struct amdgpu_device *adev = ring->adev;
 292         u32 wptr;
 293
 294         if (ring->use_doorbell) {
 295                 /* XXX check if swapping is necessary on BE */
 296                 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
 297         } else {
 298                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 299
 300                 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 301         }
 302
 303         return wptr;
 304 }
 305
 306 /**
 307  * sdma_v3_0_ring_set_wptr - commit the write pointer
 308  *
 309  * @ring: amdgpu ring pointer
 310  *
 311  * Write the wptr back to the hardware (VI+).
 312  */
 313 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 314 {
 315         struct amdgpu_device *adev = ring->adev;
 316
 317         if (ring->use_doorbell) {
 318                 /* XXX check if swapping is necessary on BE */
 319                 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
 320                 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
 321         } else {
 322                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 323
 324                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 325         }
 326 }
 327
 328 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 329 {
 330         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 331         int i;
 332
 333         for (i = 0; i < count; i++)
 334                 if (sdma && sdma->burst_nop && (i == 0))
 335                         amdgpu_ring_write(ring, ring->nop |
 336                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 337                 else
 338                         amdgpu_ring_write(ring, ring->nop);
 339 }
 340
 341 /**
 342  * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
 343  *
 344  * @ring: amdgpu ring pointer
 345  * @ib: IB object to schedule
 346  *
 347  * Schedule an IB in the DMA ring (VI).
 348  */
 349 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 350                                    struct amdgpu_ib *ib)
 351 {
 352         u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
 353         u32 next_rptr = ring->wptr + 5;
 354
 355         while ((next_rptr & 7) != 2)
 356                 next_rptr++;
 357         next_rptr += 6;
 358
 359         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 360                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 361         amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
 362         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
 363         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 364         amdgpu_ring_write(ring, next_rptr);
 365
 366         /* IB packet must end on a 8 DW boundary */
 367         sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
 368
 369         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 370                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
 371         /* base must be 32 byte aligned */
 372         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 373         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 374         amdgpu_ring_write(ring, ib->length_dw);
 375         amdgpu_ring_write(ring, 0);
 376         amdgpu_ring_write(ring, 0);
 377
 378 }
 379
 380 /**
 381  * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 382  *
 383  * @ring: amdgpu ring pointer
 384  *
 385  * Emit an hdp flush packet on the requested DMA ring.
 386  */
 387 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 388 {
 389         u32 ref_and_mask = 0;
 390
 391         if (ring == &ring->adev->sdma.instance[0].ring)
 392                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 393         else
 394                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 395
 396         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 397                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 398                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 399         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 400         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 401         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 402         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 403         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 404                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 405 }
 406
 407 /**
 408  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
 409  *
 410  * @ring: amdgpu ring pointer
 411  * @fence: amdgpu fence object
 412  *
 413  * Add a DMA fence packet to the ring to write
 414  * the fence seq number and DMA trap packet to generate
 415  * an interrupt if needed (VI).
 416  */
 417 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 418                                       unsigned flags)
 419 {
 420         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 421         /* write the fence */
 422         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 423         amdgpu_ring_write(ring, lower_32_bits(addr));
 424         amdgpu_ring_write(ring, upper_32_bits(addr));
 425         amdgpu_ring_write(ring, lower_32_bits(seq));
 426
 427         /* optionally write high bits as well */
 428         if (write64bit) {
 429                 addr += 4;
 430                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 431                 amdgpu_ring_write(ring, lower_32_bits(addr));
 432                 amdgpu_ring_write(ring, upper_32_bits(addr));
 433                 amdgpu_ring_write(ring, upper_32_bits(seq));
 434         }
 435
 436         /* generate an interrupt */
 437         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 438         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 439 }
 440
 441
 442 /**
 443  * sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring
 444  *
 445  * @ring: amdgpu_ring structure holding ring information
 446  * @semaphore: amdgpu semaphore object
 447  * @emit_wait: wait or signal semaphore
 448  *
 449  * Add a DMA semaphore packet to the ring wait on or signal
 450  * other rings (VI).
 451  */
 452 static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring,
 453                                           struct amdgpu_semaphore *semaphore,
 454                                           bool emit_wait)
 455 {
 456         u64 addr = semaphore->gpu_addr;
 457         u32 sig = emit_wait ? 0 : 1;
 458
 459         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
 460                           SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
 461         amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
 462         amdgpu_ring_write(ring, upper_32_bits(addr));
 463
 464         return true;
 465 }
 466
 467 /**
 468  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
 469  *
 470  * @adev: amdgpu_device pointer
 471  *
 472  * Stop the gfx async dma ring buffers (VI).
 473  */
 474 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 475 {
 476         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 477         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 478         u32 rb_cntl, ib_cntl;
 479         int i;
 480
 481         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 482             (adev->mman.buffer_funcs_ring == sdma1))
 483                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 484
 485         for (i = 0; i < adev->sdma.num_instances; i++) {
 486                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 487                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 488                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 489                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 490                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 491                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 492         }
 493         sdma0->ready = false;
 494         sdma1->ready = false;
 495 }
 496
 497 /**
 498  * sdma_v3_0_rlc_stop - stop the compute async dma engines
 499  *
 500  * @adev: amdgpu_device pointer
 501  *
 502  * Stop the compute async dma queues (VI).
 503  */
 504 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
 505 {
 506         /* XXX todo */
 507 }
 508
 509 /**
 510  * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
 511  *
 512  * @adev: amdgpu_device pointer
 513  * @enable: enable/disable the DMA MEs context switch.
 514  *
 515  * Halt or unhalt the async dma engines context switch (VI).
 516  */
 517 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 518 {
 519         u32 f32_cntl;
 520         int i;
 521
 522         for (i = 0; i < adev->sdma.num_instances; i++) {
 523                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 524                 if (enable)
 525                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 526                                         AUTO_CTXSW_ENABLE, 1);
 527                 else
 528                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 529                                         AUTO_CTXSW_ENABLE, 0);
 530                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 531         }
 532 }
 533
 534 /**
 535  * sdma_v3_0_enable - stop the async dma engines
 536  *
 537  * @adev: amdgpu_device pointer
 538  * @enable: enable/disable the DMA MEs.
 539  *
 540  * Halt or unhalt the async dma engines (VI).
 541  */
 542 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
 543 {
 544         u32 f32_cntl;
 545         int i;
 546
 547         if (enable == false) {
 548                 sdma_v3_0_gfx_stop(adev);
 549                 sdma_v3_0_rlc_stop(adev);
 550         }
 551
 552         for (i = 0; i < adev->sdma.num_instances; i++) {
 553                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 554                 if (enable)
 555                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 556                 else
 557                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 558                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 559         }
 560 }
 561
 562 /**
 563  * sdma_v3_0_gfx_resume - setup and start the async dma engines
 564  *
 565  * @adev: amdgpu_device pointer
 566  *
 567  * Set up the gfx DMA ring buffers and enable them (VI).
 568  * Returns 0 for success, error for failure.
 569  */
 570 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 571 {
 572         struct amdgpu_ring *ring;
 573         u32 rb_cntl, ib_cntl;
 574         u32 rb_bufsz;
 575         u32 wb_offset;
 576         u32 doorbell;
 577         int i, j, r;
 578
 579         for (i = 0; i < adev->sdma.num_instances; i++) {
 580                 ring = &adev->sdma.instance[i].ring;
 581                 wb_offset = (ring->rptr_offs * 4);
 582
 583                 mutex_lock(&adev->srbm_mutex);
 584                 for (j = 0; j < 16; j++) {
 585                         vi_srbm_select(adev, 0, 0, 0, j);
 586                         /* SDMA GFX */
 587                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 588                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 589                 }
 590                 vi_srbm_select(adev, 0, 0, 0, 0);
 591                 mutex_unlock(&adev->srbm_mutex);
 592
 593                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 594
 595                 /* Set ring buffer size in dwords */
 596                 rb_bufsz = order_base_2(ring->ring_size / 4);
 597                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 598                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 599 #ifdef __BIG_ENDIAN
 600                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 601                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 602                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 603 #endif
 604                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 605
 606                 /* Initialize the ring buffer's read and write pointers */
 607                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 608                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 609
 610                 /* set the wb address whether it's enabled or not */
 611                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 612                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 613                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 614                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 615
 616                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 617
 618                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 619                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 620
 621                 ring->wptr = 0;
 622                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
 623
 624                 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
 625
 626                 if (ring->use_doorbell) {
 627                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
 628                                                  OFFSET, ring->doorbell_index);
 629                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 630                 } else {
 631                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 632                 }
 633                 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
 634
 635                 /* enable DMA RB */
 636                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 637                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 638
 639                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 640                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 641 #ifdef __BIG_ENDIAN
 642                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 643 #endif
 644                 /* enable DMA IBs */
 645                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 646
 647                 ring->ready = true;
 648
 649                 r = amdgpu_ring_test_ring(ring);
 650                 if (r) {
 651                         ring->ready = false;
 652                         return r;
 653                 }
 654
 655                 if (adev->mman.buffer_funcs_ring == ring)
 656                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 657         }
 658
 659         return 0;
 660 }
 661
 662 /**
 663  * sdma_v3_0_rlc_resume - setup and start the async dma engines
 664  *
 665  * @adev: amdgpu_device pointer
 666  *
 667  * Set up the compute DMA queues and enable them (VI).
 668  * Returns 0 for success, error for failure.
 669  */
 670 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
 671 {
 672         /* XXX todo */
 673         return 0;
 674 }
 675
 676 /**
 677  * sdma_v3_0_load_microcode - load the sDMA ME ucode
 678  *
 679  * @adev: amdgpu_device pointer
 680  *
 681  * Loads the sDMA0/1 ucode.
 682  * Returns 0 for success, -EINVAL if the ucode is not available.
 683  */
 684 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
 685 {
 686         const struct sdma_firmware_header_v1_0 *hdr;
 687         const __le32 *fw_data;
 688         u32 fw_size;
 689         int i, j;
 690
 691         /* halt the MEs */
 692         sdma_v3_0_enable(adev, false);
 693
 694         for (i = 0; i < adev->sdma.num_instances; i++) {
 695                 if (!adev->sdma.instance[i].fw)
 696                         return -EINVAL;
 697                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 698                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 699                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 700                 fw_data = (const __le32 *)
 701                         (adev->sdma.instance[i].fw->data +
 702                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 703                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
 704                 for (j = 0; j < fw_size; j++)
 705                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
 706                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
 707         }
 708
 709         return 0;
 710 }
 711
 712 /**
 713  * sdma_v3_0_start - setup and start the async dma engines
 714  *
 715  * @adev: amdgpu_device pointer
 716  *
 717  * Set up the DMA engines and enable them (VI).
 718  * Returns 0 for success, error for failure.
 719  */
 720 static int sdma_v3_0_start(struct amdgpu_device *adev)
 721 {
 722         int r, i;
 723
 724         if (!adev->firmware.smu_load) {
 725                 r = sdma_v3_0_load_microcode(adev);
 726                 if (r)
 727                         return r;
 728         } else {
 729                 for (i = 0; i < adev->sdma.num_instances; i++) {
 730                         r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
 731                                                                          (i == 0) ?
 732                                                                          AMDGPU_UCODE_ID_SDMA0 :
 733                                                                          AMDGPU_UCODE_ID_SDMA1);
 734                         if (r)
 735                                 return -EINVAL;
 736                 }
 737         }
 738
 739         /* unhalt the MEs */
 740         sdma_v3_0_enable(adev, true);
 741         /* enable sdma ring preemption */
 742         sdma_v3_0_ctx_switch_enable(adev, true);
 743
 744         /* start the gfx rings and rlc compute queues */
 745         r = sdma_v3_0_gfx_resume(adev);
 746         if (r)
 747                 return r;
 748         r = sdma_v3_0_rlc_resume(adev);
 749         if (r)
 750                 return r;
 751
 752         return 0;
 753 }
 754
 755 /**
 756  * sdma_v3_0_ring_test_ring - simple async dma engine test
 757  *
 758  * @ring: amdgpu_ring structure holding ring information
 759  *
 760  * Test the DMA engine by writing using it to write an
 761  * value to memory. (VI).
 762  * Returns 0 for success, error for failure.
 763  */
 764 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
 765 {
 766         struct amdgpu_device *adev = ring->adev;
 767         unsigned i;
 768         unsigned index;
 769         int r;
 770         u32 tmp;
 771         u64 gpu_addr;
 772
 773         r = amdgpu_wb_get(adev, &index);
 774         if (r) {
 775                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 776                 return r;
 777         }
 778
 779         gpu_addr = adev->wb.gpu_addr + (index * 4);
 780         tmp = 0xCAFEDEAD;
 781         adev->wb.wb[index] = cpu_to_le32(tmp);
 782
 783         r = amdgpu_ring_lock(ring, 5);
 784         if (r) {
 785                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 786                 amdgpu_wb_free(adev, index);
 787                 return r;
 788         }
 789
 790         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 791                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 792         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 793         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 794         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 795         amdgpu_ring_write(ring, 0xDEADBEEF);
 796         amdgpu_ring_unlock_commit(ring);
 797
 798         for (i = 0; i < adev->usec_timeout; i++) {
 799                 tmp = le32_to_cpu(adev->wb.wb[index]);
 800                 if (tmp == 0xDEADBEEF)
 801                         break;
 802                 DRM_UDELAY(1);
 803         }
 804
 805         if (i < adev->usec_timeout) {
 806                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 807         } else {
 808                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 809                           ring->idx, tmp);
 810                 r = -EINVAL;
 811         }
 812         amdgpu_wb_free(adev, index);
 813
 814         return r;
 815 }
 816
 817 /**
 818  * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
 819  *
 820  * @ring: amdgpu_ring structure holding ring information
 821  *
 822  * Test a simple IB in the DMA ring (VI).
 823  * Returns 0 on success, error on failure.
 824  */
 825 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
 826 {
 827         struct amdgpu_device *adev = ring->adev;
 828         struct amdgpu_ib ib;
 829         struct fence *f = NULL;
 830         unsigned i;
 831         unsigned index;
 832         int r;
 833         u32 tmp = 0;
 834         u64 gpu_addr;
 835
 836         r = amdgpu_wb_get(adev, &index);
 837         if (r) {
 838                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 839                 return r;
 840         }
 841
 842         gpu_addr = adev->wb.gpu_addr + (index * 4);
 843         tmp = 0xCAFEDEAD;
 844         adev->wb.wb[index] = cpu_to_le32(tmp);
 845         memset(&ib, 0, sizeof(ib));
 846         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 847         if (r) {
 848                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 849                 goto err0;
 850         }
 851
 852         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 853                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 854         ib.ptr[1] = lower_32_bits(gpu_addr);
 855         ib.ptr[2] = upper_32_bits(gpu_addr);
 856         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 857         ib.ptr[4] = 0xDEADBEEF;
 858         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 859         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 860         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 861         ib.length_dw = 8;
 862
 863         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
 864                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 865                                                  &f);
 866         if (r)
 867                 goto err1;
 868
 869         r = fence_wait(f, false);
 870         if (r) {
 871                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 872                 goto err1;
 873         }
 874         for (i = 0; i < adev->usec_timeout; i++) {
 875                 tmp = le32_to_cpu(adev->wb.wb[index]);
 876                 if (tmp == 0xDEADBEEF)
 877                         break;
 878                 DRM_UDELAY(1);
 879         }
 880         if (i < adev->usec_timeout) {
 881                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 882                          ring->idx, i);
 883                 goto err1;
 884         } else {
 885                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 886                 r = -EINVAL;
 887         }
 888 err1:
 889         fence_put(f);
 890         amdgpu_ib_free(adev, &ib);
 891 err0:
 892         amdgpu_wb_free(adev, index);
 893         return r;
 894 }
 895
 896 /**
 897  * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
 898  *
 899  * @ib: indirect buffer to fill with commands
 900  * @pe: addr of the page entry
 901  * @src: src addr to copy from
 902  * @count: number of page entries to update
 903  *
 904  * Update PTEs by copying them from the GART using sDMA (CIK).
 905  */
 906 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
 907                                   uint64_t pe, uint64_t src,
 908                                   unsigned count)
 909 {
 910         while (count) {
 911                 unsigned bytes = count * 8;
 912                 if (bytes > 0x1FFFF8)
 913                         bytes = 0x1FFFF8;
 914
 915                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 916                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 917                 ib->ptr[ib->length_dw++] = bytes;
 918                 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 919                 ib->ptr[ib->length_dw++] = lower_32_bits(src);
 920                 ib->ptr[ib->length_dw++] = upper_32_bits(src);
 921                 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 922                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 923
 924                 pe += bytes;
 925                 src += bytes;
 926                 count -= bytes / 8;
 927         }
 928 }
 929
 930 /**
 931  * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
 932  *
 933  * @ib: indirect buffer to fill with commands
 934  * @pe: addr of the page entry
 935  * @addr: dst addr to write into pe
 936  * @count: number of page entries to update
 937  * @incr: increase next addr by incr bytes
 938  * @flags: access flags
 939  *
 940  * Update PTEs by writing them manually using sDMA (CIK).
 941  */
 942 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
 943                                    uint64_t pe,
 944                                    uint64_t addr, unsigned count,
 945                                    uint32_t incr, uint32_t flags)
 946 {
 947         uint64_t value;
 948         unsigned ndw;
 949
 950         while (count) {
 951                 ndw = count * 2;
 952                 if (ndw > 0xFFFFE)
 953                         ndw = 0xFFFFE;
 954
 955                 /* for non-physically contiguous pages (system) */
 956                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 957                         SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 958                 ib->ptr[ib->length_dw++] = pe;
 959                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 960                 ib->ptr[ib->length_dw++] = ndw;
 961                 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
 962                         if (flags & AMDGPU_PTE_SYSTEM) {
 963                                 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
 964                                 value &= 0xFFFFFFFFFFFFF000ULL;
 965                         } else if (flags & AMDGPU_PTE_VALID) {
 966                                 value = addr;
 967                         } else {
 968                                 value = 0;
 969                         }
 970                         addr += incr;
 971                         value |= flags;
 972                         ib->ptr[ib->length_dw++] = value;
 973                         ib->ptr[ib->length_dw++] = upper_32_bits(value);
 974                 }
 975         }
 976 }
 977
 978 /**
 979  * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
 980  *
 981  * @ib: indirect buffer to fill with commands
 982  * @pe: addr of the page entry
 983  * @addr: dst addr to write into pe
 984  * @count: number of page entries to update
 985  * @incr: increase next addr by incr bytes
 986  * @flags: access flags
 987  *
 988  * Update the page tables using sDMA (CIK).
 989  */
 990 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
 991                                      uint64_t pe,
 992                                      uint64_t addr, unsigned count,
 993                                      uint32_t incr, uint32_t flags)
 994 {
 995         uint64_t value;
 996         unsigned ndw;
 997
 998         while (count) {
 999                 ndw = count;
1000                 if (ndw > 0x7FFFF)
1001                         ndw = 0x7FFFF;
1002
1003                 if (flags & AMDGPU_PTE_VALID)
1004                         value = addr;
1005                 else
1006                         value = 0;
1007
1008                 /* for physically contiguous pages (vram) */
1009                 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1010                 ib->ptr[ib->length_dw++] = pe; /* dst addr */
1011                 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1012                 ib->ptr[ib->length_dw++] = flags; /* mask */
1013                 ib->ptr[ib->length_dw++] = 0;
1014                 ib->ptr[ib->length_dw++] = value; /* value */
1015                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1016                 ib->ptr[ib->length_dw++] = incr; /* increment size */
1017                 ib->ptr[ib->length_dw++] = 0;
1018                 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
1019
1020                 pe += ndw * 8;
1021                 addr += ndw * incr;
1022                 count -= ndw;
1023         }
1024 }
1025
1026 /**
1027  * sdma_v3_0_vm_pad_ib - pad the IB to the required number of dw
1028  *
1029  * @ib: indirect buffer to fill with padding
1030  *
1031  */
1032 static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib)
1033 {
1034         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);
1035         u32 pad_count;
1036         int i;
1037
1038         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1039         for (i = 0; i < pad_count; i++)
1040                 if (sdma && sdma->burst_nop && (i == 0))
1041                         ib->ptr[ib->length_dw++] =
1042                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1043                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1044                 else
1045                         ib->ptr[ib->length_dw++] =
1046                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1047 }
1048
1049 /**
1050  * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1051  *
1052  * @ring: amdgpu_ring pointer
1053  * @vm: amdgpu_vm pointer
1054  *
1055  * Update the page table base and flush the VM TLB
1056  * using sDMA (VI).
1057  */
1058 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1059                                          unsigned vm_id, uint64_t pd_addr)
1060 {
1061         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1062                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1063         if (vm_id < 8) {
1064                 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1065         } else {
1066                 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1067         }
1068         amdgpu_ring_write(ring, pd_addr >> 12);
1069
1070         /* flush TLB */
1071         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1072                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1073         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1074         amdgpu_ring_write(ring, 1 << vm_id);
1075
1076         /* wait for flush */
1077         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1078                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1079                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1080         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1081         amdgpu_ring_write(ring, 0);
1082         amdgpu_ring_write(ring, 0); /* reference */
1083         amdgpu_ring_write(ring, 0); /* mask */
1084         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1085                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1086 }
1087
1088 static int sdma_v3_0_early_init(void *handle)
1089 {
1090         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1091
1092         switch (adev->asic_type) {
1093         case CHIP_STONEY:
1094                 adev->sdma.num_instances = 1;
1095                 break;
1096         default:
1097                 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1098                 break;
1099         }
1100
1101         sdma_v3_0_set_ring_funcs(adev);
1102         sdma_v3_0_set_buffer_funcs(adev);
1103         sdma_v3_0_set_vm_pte_funcs(adev);
1104         sdma_v3_0_set_irq_funcs(adev);
1105
1106         return 0;
1107 }
1108
1109 static int sdma_v3_0_sw_init(void *handle)
1110 {
1111         struct amdgpu_ring *ring;
1112         int r, i;
1113         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1114
1115         /* SDMA trap event */
1116         r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
1117         if (r)
1118                 return r;
1119
1120         /* SDMA Privileged inst */
1121         r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
1122         if (r)
1123                 return r;
1124
1125         /* SDMA Privileged inst */
1126         r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
1127         if (r)
1128                 return r;
1129
1130         r = sdma_v3_0_init_microcode(adev);
1131         if (r) {
1132                 DRM_ERROR("Failed to load sdma firmware!\n");
1133                 return r;
1134         }
1135
1136         for (i = 0; i < adev->sdma.num_instances; i++) {
1137                 ring = &adev->sdma.instance[i].ring;
1138                 ring->ring_obj = NULL;
1139                 ring->use_doorbell = true;
1140                 ring->doorbell_index = (i == 0) ?
1141                         AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1142
1143                 sprintf(ring->name, "sdma%d", i);
1144                 r = amdgpu_ring_init(adev, ring, 256 * 1024,
1145                                      SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1146                                      &adev->sdma.trap_irq,
1147                                      (i == 0) ?
1148                                      AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
1149                                      AMDGPU_RING_TYPE_SDMA);
1150                 if (r)
1151                         return r;
1152         }
1153
1154         return r;
1155 }
1156
1157 static int sdma_v3_0_sw_fini(void *handle)
1158 {
1159         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1160         int i;
1161
1162         for (i = 0; i < adev->sdma.num_instances; i++)
1163                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1164
1165         return 0;
1166 }
1167
1168 static int sdma_v3_0_hw_init(void *handle)
1169 {
1170         int r;
1171         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1172
1173         sdma_v3_0_init_golden_registers(adev);
1174
1175         r = sdma_v3_0_start(adev);
1176         if (r)
1177                 return r;
1178
1179         return r;
1180 }
1181
1182 static int sdma_v3_0_hw_fini(void *handle)
1183 {
1184         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1185
1186         sdma_v3_0_ctx_switch_enable(adev, false);
1187         sdma_v3_0_enable(adev, false);
1188
1189         return 0;
1190 }
1191
1192 static int sdma_v3_0_suspend(void *handle)
1193 {
1194         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1195
1196         return sdma_v3_0_hw_fini(adev);
1197 }
1198
1199 static int sdma_v3_0_resume(void *handle)
1200 {
1201         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1202
1203         return sdma_v3_0_hw_init(adev);
1204 }
1205
1206 static bool sdma_v3_0_is_idle(void *handle)
1207 {
1208         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1209         u32 tmp = RREG32(mmSRBM_STATUS2);
1210
1211         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1212                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1213             return false;
1214
1215         return true;
1216 }
1217
1218 static int sdma_v3_0_wait_for_idle(void *handle)
1219 {
1220         unsigned i;
1221         u32 tmp;
1222         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1223
1224         for (i = 0; i < adev->usec_timeout; i++) {
1225                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1226                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1227
1228                 if (!tmp)
1229                         return 0;
1230                 udelay(1);
1231         }
1232         return -ETIMEDOUT;
1233 }
1234
1235 static void sdma_v3_0_print_status(void *handle)
1236 {
1237         int i, j;
1238         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1239
1240         dev_info(adev->dev, "VI SDMA registers\n");
1241         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
1242                  RREG32(mmSRBM_STATUS2));
1243         for (i = 0; i < adev->sdma.num_instances; i++) {
1244                 dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
1245                          i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1246                 dev_info(adev->dev, "  SDMA%d_F32_CNTL=0x%08X\n",
1247                          i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1248                 dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
1249                          i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1250                 dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1251                          i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1252                 dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
1253                          i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1254                 dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
1255                          i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1256                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
1257                          i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1258                 dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
1259                          i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1260                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1261                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1262                 dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1263                          i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1264                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
1265                          i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1266                 dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1267                          i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1268                 dev_info(adev->dev, "  SDMA%d_GFX_DOORBELL=0x%08X\n",
1269                          i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]));
1270                 mutex_lock(&adev->srbm_mutex);
1271                 for (j = 0; j < 16; j++) {
1272                         vi_srbm_select(adev, 0, 0, 0, j);
1273                         dev_info(adev->dev, "  VM %d:\n", j);
1274                         dev_info(adev->dev, "  SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1275                                  i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1276                         dev_info(adev->dev, "  SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1277                                  i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1278                 }
1279                 vi_srbm_select(adev, 0, 0, 0, 0);
1280                 mutex_unlock(&adev->srbm_mutex);
1281         }
1282 }
1283
1284 static int sdma_v3_0_soft_reset(void *handle)
1285 {
1286         u32 srbm_soft_reset = 0;
1287         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1288         u32 tmp = RREG32(mmSRBM_STATUS2);
1289
1290         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1291                 /* sdma0 */
1292                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1293                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1294                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1295                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1296         }
1297         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1298                 /* sdma1 */
1299                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1300                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1301                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1302                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1303         }
1304
1305         if (srbm_soft_reset) {
1306                 sdma_v3_0_print_status((void *)adev);
1307
1308                 tmp = RREG32(mmSRBM_SOFT_RESET);
1309                 tmp |= srbm_soft_reset;
1310                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1311                 WREG32(mmSRBM_SOFT_RESET, tmp);
1312                 tmp = RREG32(mmSRBM_SOFT_RESET);
1313
1314                 udelay(50);
1315
1316                 tmp &= ~srbm_soft_reset;
1317                 WREG32(mmSRBM_SOFT_RESET, tmp);
1318                 tmp = RREG32(mmSRBM_SOFT_RESET);
1319
1320                 /* Wait a little for things to settle down */
1321                 udelay(50);
1322
1323                 sdma_v3_0_print_status((void *)adev);
1324         }
1325
1326         return 0;
1327 }
1328
1329 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1330                                         struct amdgpu_irq_src *source,
1331                                         unsigned type,
1332                                         enum amdgpu_interrupt_state state)
1333 {
1334         u32 sdma_cntl;
1335
1336         switch (type) {
1337         case AMDGPU_SDMA_IRQ_TRAP0:
1338                 switch (state) {
1339                 case AMDGPU_IRQ_STATE_DISABLE:
1340                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1341                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1342                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1343                         break;
1344                 case AMDGPU_IRQ_STATE_ENABLE:
1345                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1346                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1347                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1348                         break;
1349                 default:
1350                         break;
1351                 }
1352                 break;
1353         case AMDGPU_SDMA_IRQ_TRAP1:
1354                 switch (state) {
1355                 case AMDGPU_IRQ_STATE_DISABLE:
1356                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1357                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1358                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1359                         break;
1360                 case AMDGPU_IRQ_STATE_ENABLE:
1361                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1362                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1363                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1364                         break;
1365                 default:
1366                         break;
1367                 }
1368                 break;
1369         default:
1370                 break;
1371         }
1372         return 0;
1373 }
1374
1375 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1376                                       struct amdgpu_irq_src *source,
1377                                       struct amdgpu_iv_entry *entry)
1378 {
1379         u8 instance_id, queue_id;
1380
1381         instance_id = (entry->ring_id & 0x3) >> 0;
1382         queue_id = (entry->ring_id & 0xc) >> 2;
1383         DRM_DEBUG("IH: SDMA trap\n");
1384         switch (instance_id) {
1385         case 0:
1386                 switch (queue_id) {
1387                 case 0:
1388                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1389                         break;
1390                 case 1:
1391                         /* XXX compute */
1392                         break;
1393                 case 2:
1394                         /* XXX compute */
1395                         break;
1396                 }
1397                 break;
1398         case 1:
1399                 switch (queue_id) {
1400                 case 0:
1401                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1402                         break;
1403                 case 1:
1404                         /* XXX compute */
1405                         break;
1406                 case 2:
1407                         /* XXX compute */
1408                         break;
1409                 }
1410                 break;
1411         }
1412         return 0;
1413 }
1414
1415 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1416                                               struct amdgpu_irq_src *source,
1417                                               struct amdgpu_iv_entry *entry)
1418 {
1419         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1420         schedule_work(&adev->reset_work);
1421         return 0;
1422 }
1423
1424 static int sdma_v3_0_set_clockgating_state(void *handle,
1425                                           enum amd_clockgating_state state)
1426 {
1427         return 0;
1428 }
1429
1430 static int sdma_v3_0_set_powergating_state(void *handle,
1431                                           enum amd_powergating_state state)
1432 {
1433         return 0;
1434 }
1435
1436 const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1437         .early_init = sdma_v3_0_early_init,
1438         .late_init = NULL,
1439         .sw_init = sdma_v3_0_sw_init,
1440         .sw_fini = sdma_v3_0_sw_fini,
1441         .hw_init = sdma_v3_0_hw_init,
1442         .hw_fini = sdma_v3_0_hw_fini,
1443         .suspend = sdma_v3_0_suspend,
1444         .resume = sdma_v3_0_resume,
1445         .is_idle = sdma_v3_0_is_idle,
1446         .wait_for_idle = sdma_v3_0_wait_for_idle,
1447         .soft_reset = sdma_v3_0_soft_reset,
1448         .print_status = sdma_v3_0_print_status,
1449         .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1450         .set_powergating_state = sdma_v3_0_set_powergating_state,
1451 };
1452
1453 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1454         .get_rptr = sdma_v3_0_ring_get_rptr,
1455         .get_wptr = sdma_v3_0_ring_get_wptr,
1456         .set_wptr = sdma_v3_0_ring_set_wptr,
1457         .parse_cs = NULL,
1458         .emit_ib = sdma_v3_0_ring_emit_ib,
1459         .emit_fence = sdma_v3_0_ring_emit_fence,
1460         .emit_semaphore = sdma_v3_0_ring_emit_semaphore,
1461         .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1462         .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1463         .test_ring = sdma_v3_0_ring_test_ring,
1464         .test_ib = sdma_v3_0_ring_test_ib,
1465         .insert_nop = sdma_v3_0_ring_insert_nop,
1466 };
1467
1468 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1469 {
1470         int i;
1471
1472         for (i = 0; i < adev->sdma.num_instances; i++)
1473                 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1474 }
1475
1476 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1477         .set = sdma_v3_0_set_trap_irq_state,
1478         .process = sdma_v3_0_process_trap_irq,
1479 };
1480
1481 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1482         .process = sdma_v3_0_process_illegal_inst_irq,
1483 };
1484
1485 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1486 {
1487         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1488         adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1489         adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1490 }
1491
1492 /**
1493  * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1494  *
1495  * @ring: amdgpu_ring structure holding ring information
1496  * @src_offset: src GPU address
1497  * @dst_offset: dst GPU address
1498  * @byte_count: number of bytes to xfer
1499  *
1500  * Copy GPU buffers using the DMA engine (VI).
1501  * Used by the amdgpu ttm implementation to move pages if
1502  * registered as the asic copy callback.
1503  */
1504 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1505                                        uint64_t src_offset,
1506                                        uint64_t dst_offset,
1507                                        uint32_t byte_count)
1508 {
1509         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1510                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1511         ib->ptr[ib->length_dw++] = byte_count;
1512         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1513         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1514         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1515         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1516         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1517 }
1518
1519 /**
1520  * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1521  *
1522  * @ring: amdgpu_ring structure holding ring information
1523  * @src_data: value to write to buffer
1524  * @dst_offset: dst GPU address
1525  * @byte_count: number of bytes to xfer
1526  *
1527  * Fill GPU buffers using the DMA engine (VI).
1528  */
1529 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1530                                        uint32_t src_data,
1531                                        uint64_t dst_offset,
1532                                        uint32_t byte_count)
1533 {
1534         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1535         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1536         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1537         ib->ptr[ib->length_dw++] = src_data;
1538         ib->ptr[ib->length_dw++] = byte_count;
1539 }
1540
1541 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1542         .copy_max_bytes = 0x1fffff,
1543         .copy_num_dw = 7,
1544         .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1545
1546         .fill_max_bytes = 0x1fffff,
1547         .fill_num_dw = 5,
1548         .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1549 };
1550
1551 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1552 {
1553         if (adev->mman.buffer_funcs == NULL) {
1554                 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1555                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1556         }
1557 }
1558
1559 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1560         .copy_pte = sdma_v3_0_vm_copy_pte,
1561         .write_pte = sdma_v3_0_vm_write_pte,
1562         .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1563         .pad_ib = sdma_v3_0_vm_pad_ib,
1564 };
1565
1566 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1567 {
1568         if (adev->vm_manager.vm_pte_funcs == NULL) {
1569                 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1570                 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
1571                 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
1572         }
1573 }