2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "oss/oss_3_0_d.h"
33 #include "oss/oss_3_0_sh_mask.h"
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "tonga_sdma_pkt_open.h"
47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
54 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
56 SDMA0_REGISTER_OFFSET,
60 static const u32 golden_settings_tonga_a11[] =
62 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
63 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
64 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
65 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
66 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
67 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
68 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
69 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
70 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
71 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
74 static const u32 tonga_mgcg_cgcg_init[] =
76 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
77 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
80 static const u32 golden_settings_fiji_a10[] =
82 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
83 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
84 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
85 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
86 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
87 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
88 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
89 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
92 static const u32 fiji_mgcg_cgcg_init[] =
94 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
95 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
98 static const u32 cz_golden_settings_a11[] =
100 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
101 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
102 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
103 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
104 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
105 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
106 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
107 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
108 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
109 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
110 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
111 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
114 static const u32 cz_mgcg_cgcg_init[] =
116 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
117 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
120 static const u32 stoney_golden_settings_a11[] =
122 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
123 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
124 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
125 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
128 static const u32 stoney_mgcg_cgcg_init[] =
130 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
135 * Starting with CIK, the GPU has new asynchronous
136 * DMA engines. These engines are used for compute
137 * and gfx. There are two DMA engines (SDMA0, SDMA1)
138 * and each one supports 1 ring buffer used for gfx
139 * and 2 queues used for compute.
141 * The programming model is very similar to the CP
142 * (ring buffer, IBs, etc.), but sDMA has it's own
143 * packet format that is different from the PM4 format
144 * used by the CP. sDMA supports copying data, writing
145 * embedded data, solid fills, and a number of other
146 * things. It also has support for tiling/detiling of
150 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
152 switch (adev->asic_type) {
154 amdgpu_program_register_sequence(adev,
156 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
157 amdgpu_program_register_sequence(adev,
158 golden_settings_fiji_a10,
159 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
162 amdgpu_program_register_sequence(adev,
163 tonga_mgcg_cgcg_init,
164 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
165 amdgpu_program_register_sequence(adev,
166 golden_settings_tonga_a11,
167 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
170 amdgpu_program_register_sequence(adev,
172 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
173 amdgpu_program_register_sequence(adev,
174 cz_golden_settings_a11,
175 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
178 amdgpu_program_register_sequence(adev,
179 stoney_mgcg_cgcg_init,
180 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
181 amdgpu_program_register_sequence(adev,
182 stoney_golden_settings_a11,
183 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
191 * sdma_v3_0_init_microcode - load ucode images from disk
193 * @adev: amdgpu_device pointer
195 * Use the firmware interface to load the ucode images into
196 * the driver (not loaded into hw).
197 * Returns 0 on success, error on failure.
199 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
201 const char *chip_name;
204 struct amdgpu_firmware_info *info = NULL;
205 const struct common_firmware_header *header = NULL;
206 const struct sdma_firmware_header_v1_0 *hdr;
210 switch (adev->asic_type) {
218 chip_name = "carrizo";
221 chip_name = "stoney";
226 for (i = 0; i < adev->sdma.num_instances; i++) {
228 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
230 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
231 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
234 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
237 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
238 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
239 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
240 if (adev->sdma.instance[i].feature_version >= 20)
241 adev->sdma.instance[i].burst_nop = true;
243 if (adev->firmware.smu_load) {
244 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
245 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
246 info->fw = adev->sdma.instance[i].fw;
247 header = (const struct common_firmware_header *)info->fw->data;
248 adev->firmware.fw_size +=
249 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
255 "sdma_v3_0: Failed to load firmware \"%s\"\n",
257 for (i = 0; i < adev->sdma.num_instances; i++) {
258 release_firmware(adev->sdma.instance[i].fw);
259 adev->sdma.instance[i].fw = NULL;
266 * sdma_v3_0_ring_get_rptr - get the current read pointer
268 * @ring: amdgpu ring pointer
270 * Get the current rptr from the hardware (VI+).
272 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
276 /* XXX check if swapping is necessary on BE */
277 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
283 * sdma_v3_0_ring_get_wptr - get the current write pointer
285 * @ring: amdgpu ring pointer
287 * Get the current wptr from the hardware (VI+).
289 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
291 struct amdgpu_device *adev = ring->adev;
294 if (ring->use_doorbell) {
295 /* XXX check if swapping is necessary on BE */
296 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
298 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
300 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
307 * sdma_v3_0_ring_set_wptr - commit the write pointer
309 * @ring: amdgpu ring pointer
311 * Write the wptr back to the hardware (VI+).
313 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
315 struct amdgpu_device *adev = ring->adev;
317 if (ring->use_doorbell) {
318 /* XXX check if swapping is necessary on BE */
319 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
320 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
322 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
324 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
328 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
330 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
333 for (i = 0; i < count; i++)
334 if (sdma && sdma->burst_nop && (i == 0))
335 amdgpu_ring_write(ring, ring->nop |
336 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
338 amdgpu_ring_write(ring, ring->nop);
342 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
344 * @ring: amdgpu ring pointer
345 * @ib: IB object to schedule
347 * Schedule an IB in the DMA ring (VI).
349 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
350 struct amdgpu_ib *ib)
352 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;
353 u32 next_rptr = ring->wptr + 5;
355 while ((next_rptr & 7) != 2)
359 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
360 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
361 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
362 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
363 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
364 amdgpu_ring_write(ring, next_rptr);
366 /* IB packet must end on a 8 DW boundary */
367 sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
369 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
370 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
371 /* base must be 32 byte aligned */
372 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
373 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
374 amdgpu_ring_write(ring, ib->length_dw);
375 amdgpu_ring_write(ring, 0);
376 amdgpu_ring_write(ring, 0);
381 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
383 * @ring: amdgpu ring pointer
385 * Emit an hdp flush packet on the requested DMA ring.
387 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
389 u32 ref_and_mask = 0;
391 if (ring == &ring->adev->sdma.instance[0].ring)
392 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
394 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
396 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
397 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
398 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
399 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
400 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
401 amdgpu_ring_write(ring, ref_and_mask); /* reference */
402 amdgpu_ring_write(ring, ref_and_mask); /* mask */
403 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
404 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
408 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
410 * @ring: amdgpu ring pointer
411 * @fence: amdgpu fence object
413 * Add a DMA fence packet to the ring to write
414 * the fence seq number and DMA trap packet to generate
415 * an interrupt if needed (VI).
417 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
420 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
421 /* write the fence */
422 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
423 amdgpu_ring_write(ring, lower_32_bits(addr));
424 amdgpu_ring_write(ring, upper_32_bits(addr));
425 amdgpu_ring_write(ring, lower_32_bits(seq));
427 /* optionally write high bits as well */
430 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
431 amdgpu_ring_write(ring, lower_32_bits(addr));
432 amdgpu_ring_write(ring, upper_32_bits(addr));
433 amdgpu_ring_write(ring, upper_32_bits(seq));
436 /* generate an interrupt */
437 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
438 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
443 * sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring
445 * @ring: amdgpu_ring structure holding ring information
446 * @semaphore: amdgpu semaphore object
447 * @emit_wait: wait or signal semaphore
449 * Add a DMA semaphore packet to the ring wait on or signal
452 static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring,
453 struct amdgpu_semaphore *semaphore,
456 u64 addr = semaphore->gpu_addr;
457 u32 sig = emit_wait ? 0 : 1;
459 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |
460 SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig));
461 amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);
462 amdgpu_ring_write(ring, upper_32_bits(addr));
468 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
470 * @adev: amdgpu_device pointer
472 * Stop the gfx async dma ring buffers (VI).
474 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
476 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
477 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
478 u32 rb_cntl, ib_cntl;
481 if ((adev->mman.buffer_funcs_ring == sdma0) ||
482 (adev->mman.buffer_funcs_ring == sdma1))
483 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
485 for (i = 0; i < adev->sdma.num_instances; i++) {
486 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
487 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
488 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
489 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
490 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
491 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
493 sdma0->ready = false;
494 sdma1->ready = false;
498 * sdma_v3_0_rlc_stop - stop the compute async dma engines
500 * @adev: amdgpu_device pointer
502 * Stop the compute async dma queues (VI).
504 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
510 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
512 * @adev: amdgpu_device pointer
513 * @enable: enable/disable the DMA MEs context switch.
515 * Halt or unhalt the async dma engines context switch (VI).
517 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
522 for (i = 0; i < adev->sdma.num_instances; i++) {
523 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
525 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
526 AUTO_CTXSW_ENABLE, 1);
528 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
529 AUTO_CTXSW_ENABLE, 0);
530 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
535 * sdma_v3_0_enable - stop the async dma engines
537 * @adev: amdgpu_device pointer
538 * @enable: enable/disable the DMA MEs.
540 * Halt or unhalt the async dma engines (VI).
542 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
547 if (enable == false) {
548 sdma_v3_0_gfx_stop(adev);
549 sdma_v3_0_rlc_stop(adev);
552 for (i = 0; i < adev->sdma.num_instances; i++) {
553 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
555 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
557 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
558 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
563 * sdma_v3_0_gfx_resume - setup and start the async dma engines
565 * @adev: amdgpu_device pointer
567 * Set up the gfx DMA ring buffers and enable them (VI).
568 * Returns 0 for success, error for failure.
570 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
572 struct amdgpu_ring *ring;
573 u32 rb_cntl, ib_cntl;
579 for (i = 0; i < adev->sdma.num_instances; i++) {
580 ring = &adev->sdma.instance[i].ring;
581 wb_offset = (ring->rptr_offs * 4);
583 mutex_lock(&adev->srbm_mutex);
584 for (j = 0; j < 16; j++) {
585 vi_srbm_select(adev, 0, 0, 0, j);
587 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
588 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
590 vi_srbm_select(adev, 0, 0, 0, 0);
591 mutex_unlock(&adev->srbm_mutex);
593 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
595 /* Set ring buffer size in dwords */
596 rb_bufsz = order_base_2(ring->ring_size / 4);
597 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
598 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
600 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
601 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
602 RPTR_WRITEBACK_SWAP_ENABLE, 1);
604 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
606 /* Initialize the ring buffer's read and write pointers */
607 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
608 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
610 /* set the wb address whether it's enabled or not */
611 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
612 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
613 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
614 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
616 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
618 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
619 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
622 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
624 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
626 if (ring->use_doorbell) {
627 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
628 OFFSET, ring->doorbell_index);
629 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
631 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
633 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
636 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
637 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
639 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
640 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
642 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
645 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
649 r = amdgpu_ring_test_ring(ring);
655 if (adev->mman.buffer_funcs_ring == ring)
656 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
663 * sdma_v3_0_rlc_resume - setup and start the async dma engines
665 * @adev: amdgpu_device pointer
667 * Set up the compute DMA queues and enable them (VI).
668 * Returns 0 for success, error for failure.
670 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
677 * sdma_v3_0_load_microcode - load the sDMA ME ucode
679 * @adev: amdgpu_device pointer
681 * Loads the sDMA0/1 ucode.
682 * Returns 0 for success, -EINVAL if the ucode is not available.
684 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
686 const struct sdma_firmware_header_v1_0 *hdr;
687 const __le32 *fw_data;
692 sdma_v3_0_enable(adev, false);
694 for (i = 0; i < adev->sdma.num_instances; i++) {
695 if (!adev->sdma.instance[i].fw)
697 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
698 amdgpu_ucode_print_sdma_hdr(&hdr->header);
699 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
700 fw_data = (const __le32 *)
701 (adev->sdma.instance[i].fw->data +
702 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
703 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
704 for (j = 0; j < fw_size; j++)
705 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
706 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
713 * sdma_v3_0_start - setup and start the async dma engines
715 * @adev: amdgpu_device pointer
717 * Set up the DMA engines and enable them (VI).
718 * Returns 0 for success, error for failure.
720 static int sdma_v3_0_start(struct amdgpu_device *adev)
724 if (!adev->firmware.smu_load) {
725 r = sdma_v3_0_load_microcode(adev);
729 for (i = 0; i < adev->sdma.num_instances; i++) {
730 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
732 AMDGPU_UCODE_ID_SDMA0 :
733 AMDGPU_UCODE_ID_SDMA1);
740 sdma_v3_0_enable(adev, true);
741 /* enable sdma ring preemption */
742 sdma_v3_0_ctx_switch_enable(adev, true);
744 /* start the gfx rings and rlc compute queues */
745 r = sdma_v3_0_gfx_resume(adev);
748 r = sdma_v3_0_rlc_resume(adev);
756 * sdma_v3_0_ring_test_ring - simple async dma engine test
758 * @ring: amdgpu_ring structure holding ring information
760 * Test the DMA engine by writing using it to write an
761 * value to memory. (VI).
762 * Returns 0 for success, error for failure.
764 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
766 struct amdgpu_device *adev = ring->adev;
773 r = amdgpu_wb_get(adev, &index);
775 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
779 gpu_addr = adev->wb.gpu_addr + (index * 4);
781 adev->wb.wb[index] = cpu_to_le32(tmp);
783 r = amdgpu_ring_lock(ring, 5);
785 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
786 amdgpu_wb_free(adev, index);
790 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
791 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
792 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
793 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
794 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
795 amdgpu_ring_write(ring, 0xDEADBEEF);
796 amdgpu_ring_unlock_commit(ring);
798 for (i = 0; i < adev->usec_timeout; i++) {
799 tmp = le32_to_cpu(adev->wb.wb[index]);
800 if (tmp == 0xDEADBEEF)
805 if (i < adev->usec_timeout) {
806 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
808 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
812 amdgpu_wb_free(adev, index);
818 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
820 * @ring: amdgpu_ring structure holding ring information
822 * Test a simple IB in the DMA ring (VI).
823 * Returns 0 on success, error on failure.
825 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring)
827 struct amdgpu_device *adev = ring->adev;
829 struct fence *f = NULL;
836 r = amdgpu_wb_get(adev, &index);
838 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
842 gpu_addr = adev->wb.gpu_addr + (index * 4);
844 adev->wb.wb[index] = cpu_to_le32(tmp);
845 memset(&ib, 0, sizeof(ib));
846 r = amdgpu_ib_get(ring, NULL, 256, &ib);
848 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
852 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
853 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
854 ib.ptr[1] = lower_32_bits(gpu_addr);
855 ib.ptr[2] = upper_32_bits(gpu_addr);
856 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
857 ib.ptr[4] = 0xDEADBEEF;
858 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
859 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
860 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
863 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
864 AMDGPU_FENCE_OWNER_UNDEFINED,
869 r = fence_wait(f, false);
871 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
874 for (i = 0; i < adev->usec_timeout; i++) {
875 tmp = le32_to_cpu(adev->wb.wb[index]);
876 if (tmp == 0xDEADBEEF)
880 if (i < adev->usec_timeout) {
881 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
885 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
890 amdgpu_ib_free(adev, &ib);
892 amdgpu_wb_free(adev, index);
897 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
899 * @ib: indirect buffer to fill with commands
900 * @pe: addr of the page entry
901 * @src: src addr to copy from
902 * @count: number of page entries to update
904 * Update PTEs by copying them from the GART using sDMA (CIK).
906 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
907 uint64_t pe, uint64_t src,
911 unsigned bytes = count * 8;
912 if (bytes > 0x1FFFF8)
915 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
916 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
917 ib->ptr[ib->length_dw++] = bytes;
918 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
919 ib->ptr[ib->length_dw++] = lower_32_bits(src);
920 ib->ptr[ib->length_dw++] = upper_32_bits(src);
921 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
922 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
931 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
933 * @ib: indirect buffer to fill with commands
934 * @pe: addr of the page entry
935 * @addr: dst addr to write into pe
936 * @count: number of page entries to update
937 * @incr: increase next addr by incr bytes
938 * @flags: access flags
940 * Update PTEs by writing them manually using sDMA (CIK).
942 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
944 uint64_t addr, unsigned count,
945 uint32_t incr, uint32_t flags)
955 /* for non-physically contiguous pages (system) */
956 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
957 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
958 ib->ptr[ib->length_dw++] = pe;
959 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
960 ib->ptr[ib->length_dw++] = ndw;
961 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
962 if (flags & AMDGPU_PTE_SYSTEM) {
963 value = amdgpu_vm_map_gart(ib->ring->adev, addr);
964 value &= 0xFFFFFFFFFFFFF000ULL;
965 } else if (flags & AMDGPU_PTE_VALID) {
972 ib->ptr[ib->length_dw++] = value;
973 ib->ptr[ib->length_dw++] = upper_32_bits(value);
979 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
981 * @ib: indirect buffer to fill with commands
982 * @pe: addr of the page entry
983 * @addr: dst addr to write into pe
984 * @count: number of page entries to update
985 * @incr: increase next addr by incr bytes
986 * @flags: access flags
988 * Update the page tables using sDMA (CIK).
990 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
992 uint64_t addr, unsigned count,
993 uint32_t incr, uint32_t flags)
1003 if (flags & AMDGPU_PTE_VALID)
1008 /* for physically contiguous pages (vram) */
1009 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
1010 ib->ptr[ib->length_dw++] = pe; /* dst addr */
1011 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1012 ib->ptr[ib->length_dw++] = flags; /* mask */
1013 ib->ptr[ib->length_dw++] = 0;
1014 ib->ptr[ib->length_dw++] = value; /* value */
1015 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1016 ib->ptr[ib->length_dw++] = incr; /* increment size */
1017 ib->ptr[ib->length_dw++] = 0;
1018 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
1027 * sdma_v3_0_vm_pad_ib - pad the IB to the required number of dw
1029 * @ib: indirect buffer to fill with padding
1032 static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib)
1034 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);
1038 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1039 for (i = 0; i < pad_count; i++)
1040 if (sdma && sdma->burst_nop && (i == 0))
1041 ib->ptr[ib->length_dw++] =
1042 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1043 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1045 ib->ptr[ib->length_dw++] =
1046 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1050 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1052 * @ring: amdgpu_ring pointer
1053 * @vm: amdgpu_vm pointer
1055 * Update the page table base and flush the VM TLB
1058 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1059 unsigned vm_id, uint64_t pd_addr)
1061 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1062 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1064 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1066 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1068 amdgpu_ring_write(ring, pd_addr >> 12);
1071 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1072 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1073 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1074 amdgpu_ring_write(ring, 1 << vm_id);
1076 /* wait for flush */
1077 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1078 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1079 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1080 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1081 amdgpu_ring_write(ring, 0);
1082 amdgpu_ring_write(ring, 0); /* reference */
1083 amdgpu_ring_write(ring, 0); /* mask */
1084 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1085 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1088 static int sdma_v3_0_early_init(void *handle)
1090 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1092 switch (adev->asic_type) {
1094 adev->sdma.num_instances = 1;
1097 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1101 sdma_v3_0_set_ring_funcs(adev);
1102 sdma_v3_0_set_buffer_funcs(adev);
1103 sdma_v3_0_set_vm_pte_funcs(adev);
1104 sdma_v3_0_set_irq_funcs(adev);
1109 static int sdma_v3_0_sw_init(void *handle)
1111 struct amdgpu_ring *ring;
1113 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1115 /* SDMA trap event */
1116 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
1120 /* SDMA Privileged inst */
1121 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
1125 /* SDMA Privileged inst */
1126 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
1130 r = sdma_v3_0_init_microcode(adev);
1132 DRM_ERROR("Failed to load sdma firmware!\n");
1136 for (i = 0; i < adev->sdma.num_instances; i++) {
1137 ring = &adev->sdma.instance[i].ring;
1138 ring->ring_obj = NULL;
1139 ring->use_doorbell = true;
1140 ring->doorbell_index = (i == 0) ?
1141 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1143 sprintf(ring->name, "sdma%d", i);
1144 r = amdgpu_ring_init(adev, ring, 256 * 1024,
1145 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1146 &adev->sdma.trap_irq,
1148 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
1149 AMDGPU_RING_TYPE_SDMA);
1157 static int sdma_v3_0_sw_fini(void *handle)
1159 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1162 for (i = 0; i < adev->sdma.num_instances; i++)
1163 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1168 static int sdma_v3_0_hw_init(void *handle)
1171 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1173 sdma_v3_0_init_golden_registers(adev);
1175 r = sdma_v3_0_start(adev);
1182 static int sdma_v3_0_hw_fini(void *handle)
1184 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1186 sdma_v3_0_ctx_switch_enable(adev, false);
1187 sdma_v3_0_enable(adev, false);
1192 static int sdma_v3_0_suspend(void *handle)
1194 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1196 return sdma_v3_0_hw_fini(adev);
1199 static int sdma_v3_0_resume(void *handle)
1201 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1203 return sdma_v3_0_hw_init(adev);
1206 static bool sdma_v3_0_is_idle(void *handle)
1208 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1209 u32 tmp = RREG32(mmSRBM_STATUS2);
1211 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1212 SRBM_STATUS2__SDMA1_BUSY_MASK))
1218 static int sdma_v3_0_wait_for_idle(void *handle)
1222 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1224 for (i = 0; i < adev->usec_timeout; i++) {
1225 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1226 SRBM_STATUS2__SDMA1_BUSY_MASK);
1235 static void sdma_v3_0_print_status(void *handle)
1238 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1240 dev_info(adev->dev, "VI SDMA registers\n");
1241 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1242 RREG32(mmSRBM_STATUS2));
1243 for (i = 0; i < adev->sdma.num_instances; i++) {
1244 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1245 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1246 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n",
1247 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1248 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1249 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1250 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1251 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1252 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1253 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1254 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1255 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1256 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1257 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1258 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1259 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1260 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1261 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1262 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1263 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1264 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1265 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1266 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1267 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1268 dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n",
1269 i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]));
1270 mutex_lock(&adev->srbm_mutex);
1271 for (j = 0; j < 16; j++) {
1272 vi_srbm_select(adev, 0, 0, 0, j);
1273 dev_info(adev->dev, " VM %d:\n", j);
1274 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1275 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1276 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1277 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1279 vi_srbm_select(adev, 0, 0, 0, 0);
1280 mutex_unlock(&adev->srbm_mutex);
1284 static int sdma_v3_0_soft_reset(void *handle)
1286 u32 srbm_soft_reset = 0;
1287 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1288 u32 tmp = RREG32(mmSRBM_STATUS2);
1290 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1292 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1293 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1294 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1295 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1297 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1299 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1300 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1301 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1302 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1305 if (srbm_soft_reset) {
1306 sdma_v3_0_print_status((void *)adev);
1308 tmp = RREG32(mmSRBM_SOFT_RESET);
1309 tmp |= srbm_soft_reset;
1310 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1311 WREG32(mmSRBM_SOFT_RESET, tmp);
1312 tmp = RREG32(mmSRBM_SOFT_RESET);
1316 tmp &= ~srbm_soft_reset;
1317 WREG32(mmSRBM_SOFT_RESET, tmp);
1318 tmp = RREG32(mmSRBM_SOFT_RESET);
1320 /* Wait a little for things to settle down */
1323 sdma_v3_0_print_status((void *)adev);
1329 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1330 struct amdgpu_irq_src *source,
1332 enum amdgpu_interrupt_state state)
1337 case AMDGPU_SDMA_IRQ_TRAP0:
1339 case AMDGPU_IRQ_STATE_DISABLE:
1340 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1341 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1342 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1344 case AMDGPU_IRQ_STATE_ENABLE:
1345 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1346 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1347 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1353 case AMDGPU_SDMA_IRQ_TRAP1:
1355 case AMDGPU_IRQ_STATE_DISABLE:
1356 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1357 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1358 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1360 case AMDGPU_IRQ_STATE_ENABLE:
1361 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1362 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1363 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1375 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1376 struct amdgpu_irq_src *source,
1377 struct amdgpu_iv_entry *entry)
1379 u8 instance_id, queue_id;
1381 instance_id = (entry->ring_id & 0x3) >> 0;
1382 queue_id = (entry->ring_id & 0xc) >> 2;
1383 DRM_DEBUG("IH: SDMA trap\n");
1384 switch (instance_id) {
1388 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1401 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1415 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1416 struct amdgpu_irq_src *source,
1417 struct amdgpu_iv_entry *entry)
1419 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1420 schedule_work(&adev->reset_work);
1424 static int sdma_v3_0_set_clockgating_state(void *handle,
1425 enum amd_clockgating_state state)
1430 static int sdma_v3_0_set_powergating_state(void *handle,
1431 enum amd_powergating_state state)
1436 const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1437 .early_init = sdma_v3_0_early_init,
1439 .sw_init = sdma_v3_0_sw_init,
1440 .sw_fini = sdma_v3_0_sw_fini,
1441 .hw_init = sdma_v3_0_hw_init,
1442 .hw_fini = sdma_v3_0_hw_fini,
1443 .suspend = sdma_v3_0_suspend,
1444 .resume = sdma_v3_0_resume,
1445 .is_idle = sdma_v3_0_is_idle,
1446 .wait_for_idle = sdma_v3_0_wait_for_idle,
1447 .soft_reset = sdma_v3_0_soft_reset,
1448 .print_status = sdma_v3_0_print_status,
1449 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1450 .set_powergating_state = sdma_v3_0_set_powergating_state,
1453 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1454 .get_rptr = sdma_v3_0_ring_get_rptr,
1455 .get_wptr = sdma_v3_0_ring_get_wptr,
1456 .set_wptr = sdma_v3_0_ring_set_wptr,
1458 .emit_ib = sdma_v3_0_ring_emit_ib,
1459 .emit_fence = sdma_v3_0_ring_emit_fence,
1460 .emit_semaphore = sdma_v3_0_ring_emit_semaphore,
1461 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1462 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1463 .test_ring = sdma_v3_0_ring_test_ring,
1464 .test_ib = sdma_v3_0_ring_test_ib,
1465 .insert_nop = sdma_v3_0_ring_insert_nop,
1468 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1472 for (i = 0; i < adev->sdma.num_instances; i++)
1473 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1476 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1477 .set = sdma_v3_0_set_trap_irq_state,
1478 .process = sdma_v3_0_process_trap_irq,
1481 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1482 .process = sdma_v3_0_process_illegal_inst_irq,
1485 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1487 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1488 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1489 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1493 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1495 * @ring: amdgpu_ring structure holding ring information
1496 * @src_offset: src GPU address
1497 * @dst_offset: dst GPU address
1498 * @byte_count: number of bytes to xfer
1500 * Copy GPU buffers using the DMA engine (VI).
1501 * Used by the amdgpu ttm implementation to move pages if
1502 * registered as the asic copy callback.
1504 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1505 uint64_t src_offset,
1506 uint64_t dst_offset,
1507 uint32_t byte_count)
1509 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1510 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1511 ib->ptr[ib->length_dw++] = byte_count;
1512 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1513 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1514 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1515 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1516 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1520 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1522 * @ring: amdgpu_ring structure holding ring information
1523 * @src_data: value to write to buffer
1524 * @dst_offset: dst GPU address
1525 * @byte_count: number of bytes to xfer
1527 * Fill GPU buffers using the DMA engine (VI).
1529 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1531 uint64_t dst_offset,
1532 uint32_t byte_count)
1534 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1535 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1536 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1537 ib->ptr[ib->length_dw++] = src_data;
1538 ib->ptr[ib->length_dw++] = byte_count;
1541 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1542 .copy_max_bytes = 0x1fffff,
1544 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1546 .fill_max_bytes = 0x1fffff,
1548 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1551 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1553 if (adev->mman.buffer_funcs == NULL) {
1554 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1555 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1559 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1560 .copy_pte = sdma_v3_0_vm_copy_pte,
1561 .write_pte = sdma_v3_0_vm_write_pte,
1562 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1563 .pad_ib = sdma_v3_0_vm_pad_ib,
1566 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1568 if (adev->vm_manager.vm_pte_funcs == NULL) {
1569 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1570 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
1571 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;