2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "oss/oss_3_0_d.h"
33 #include "oss/oss_3_0_sh_mask.h"
35 #include "gmc/gmc_8_1_d.h"
36 #include "gmc/gmc_8_1_sh_mask.h"
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "tonga_sdma_pkt_open.h"
47 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
48 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
49 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
50 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
57 SDMA0_REGISTER_OFFSET,
61 static const u32 golden_settings_tonga_a11[] =
63 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
64 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
65 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
66 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
67 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
68 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
69 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
70 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
71 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
72 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
75 static const u32 tonga_mgcg_cgcg_init[] =
77 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
78 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
81 static const u32 golden_settings_fiji_a10[] =
83 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
84 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
85 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
86 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
87 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
88 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
89 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
90 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
93 static const u32 fiji_mgcg_cgcg_init[] =
95 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
96 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
99 static const u32 golden_settings_polaris11_a11[] =
101 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
102 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
103 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
104 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
105 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
106 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
107 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
108 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
109 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
110 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
113 static const u32 golden_settings_polaris10_a11[] =
115 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
116 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
117 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
118 mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
119 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
120 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
121 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
122 mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
123 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
124 mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
127 static const u32 cz_golden_settings_a11[] =
129 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
130 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
131 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
132 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
133 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
134 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
135 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
136 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
137 mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
138 mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
139 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
140 mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
143 static const u32 cz_mgcg_cgcg_init[] =
145 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
146 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
149 static const u32 stoney_golden_settings_a11[] =
151 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
152 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
153 mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
154 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
157 static const u32 stoney_mgcg_cgcg_init[] =
159 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
164 * Starting with CIK, the GPU has new asynchronous
165 * DMA engines. These engines are used for compute
166 * and gfx. There are two DMA engines (SDMA0, SDMA1)
167 * and each one supports 1 ring buffer used for gfx
168 * and 2 queues used for compute.
170 * The programming model is very similar to the CP
171 * (ring buffer, IBs, etc.), but sDMA has it's own
172 * packet format that is different from the PM4 format
173 * used by the CP. sDMA supports copying data, writing
174 * embedded data, solid fills, and a number of other
175 * things. It also has support for tiling/detiling of
179 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
181 switch (adev->asic_type) {
183 amdgpu_program_register_sequence(adev,
185 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
186 amdgpu_program_register_sequence(adev,
187 golden_settings_fiji_a10,
188 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
191 amdgpu_program_register_sequence(adev,
192 tonga_mgcg_cgcg_init,
193 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
194 amdgpu_program_register_sequence(adev,
195 golden_settings_tonga_a11,
196 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
199 amdgpu_program_register_sequence(adev,
200 golden_settings_polaris11_a11,
201 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
204 amdgpu_program_register_sequence(adev,
205 golden_settings_polaris10_a11,
206 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
209 amdgpu_program_register_sequence(adev,
211 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
212 amdgpu_program_register_sequence(adev,
213 cz_golden_settings_a11,
214 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
217 amdgpu_program_register_sequence(adev,
218 stoney_mgcg_cgcg_init,
219 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
220 amdgpu_program_register_sequence(adev,
221 stoney_golden_settings_a11,
222 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
229 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
232 for (i = 0; i < adev->sdma.num_instances; i++) {
233 release_firmware(adev->sdma.instance[i].fw);
234 adev->sdma.instance[i].fw = NULL;
239 * sdma_v3_0_init_microcode - load ucode images from disk
241 * @adev: amdgpu_device pointer
243 * Use the firmware interface to load the ucode images into
244 * the driver (not loaded into hw).
245 * Returns 0 on success, error on failure.
247 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
249 const char *chip_name;
252 struct amdgpu_firmware_info *info = NULL;
253 const struct common_firmware_header *header = NULL;
254 const struct sdma_firmware_header_v1_0 *hdr;
258 switch (adev->asic_type) {
266 chip_name = "polaris11";
269 chip_name = "polaris10";
272 chip_name = "carrizo";
275 chip_name = "stoney";
280 for (i = 0; i < adev->sdma.num_instances; i++) {
282 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
284 snprintf(fw_name, sizeof(fw_name), "/*(DEBLOBBED)*/", chip_name);
285 err = reject_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
288 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
291 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
292 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
293 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
294 if (adev->sdma.instance[i].feature_version >= 20)
295 adev->sdma.instance[i].burst_nop = true;
297 if (adev->firmware.smu_load) {
298 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
299 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
300 info->fw = adev->sdma.instance[i].fw;
301 header = (const struct common_firmware_header *)info->fw->data;
302 adev->firmware.fw_size +=
303 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
309 "sdma_v3_0: Failed to load firmware \"%s\"\n",
311 for (i = 0; i < adev->sdma.num_instances; i++) {
312 release_firmware(adev->sdma.instance[i].fw);
313 adev->sdma.instance[i].fw = NULL;
320 * sdma_v3_0_ring_get_rptr - get the current read pointer
322 * @ring: amdgpu ring pointer
324 * Get the current rptr from the hardware (VI+).
326 static uint32_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
328 /* XXX check if swapping is necessary on BE */
329 return ring->adev->wb.wb[ring->rptr_offs] >> 2;
333 * sdma_v3_0_ring_get_wptr - get the current write pointer
335 * @ring: amdgpu ring pointer
337 * Get the current wptr from the hardware (VI+).
339 static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
341 struct amdgpu_device *adev = ring->adev;
344 if (ring->use_doorbell) {
345 /* XXX check if swapping is necessary on BE */
346 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
348 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
350 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
357 * sdma_v3_0_ring_set_wptr - commit the write pointer
359 * @ring: amdgpu ring pointer
361 * Write the wptr back to the hardware (VI+).
363 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
365 struct amdgpu_device *adev = ring->adev;
367 if (ring->use_doorbell) {
368 /* XXX check if swapping is necessary on BE */
369 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
370 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
372 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
374 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
378 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
380 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
383 for (i = 0; i < count; i++)
384 if (sdma && sdma->burst_nop && (i == 0))
385 amdgpu_ring_write(ring, ring->nop |
386 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
388 amdgpu_ring_write(ring, ring->nop);
392 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
394 * @ring: amdgpu ring pointer
395 * @ib: IB object to schedule
397 * Schedule an IB in the DMA ring (VI).
399 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
400 struct amdgpu_ib *ib,
401 unsigned vm_id, bool ctx_switch)
403 u32 vmid = vm_id & 0xf;
405 /* IB packet must end on a 8 DW boundary */
406 sdma_v3_0_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
408 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
409 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
410 /* base must be 32 byte aligned */
411 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
412 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
413 amdgpu_ring_write(ring, ib->length_dw);
414 amdgpu_ring_write(ring, 0);
415 amdgpu_ring_write(ring, 0);
420 * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
422 * @ring: amdgpu ring pointer
424 * Emit an hdp flush packet on the requested DMA ring.
426 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
428 u32 ref_and_mask = 0;
430 if (ring == &ring->adev->sdma.instance[0].ring)
431 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
433 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
435 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
436 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
437 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
438 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
439 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
440 amdgpu_ring_write(ring, ref_and_mask); /* reference */
441 amdgpu_ring_write(ring, ref_and_mask); /* mask */
442 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
443 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
446 static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
448 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
449 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
450 amdgpu_ring_write(ring, mmHDP_DEBUG0);
451 amdgpu_ring_write(ring, 1);
455 * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
457 * @ring: amdgpu ring pointer
458 * @fence: amdgpu fence object
460 * Add a DMA fence packet to the ring to write
461 * the fence seq number and DMA trap packet to generate
462 * an interrupt if needed (VI).
464 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
467 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
468 /* write the fence */
469 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
470 amdgpu_ring_write(ring, lower_32_bits(addr));
471 amdgpu_ring_write(ring, upper_32_bits(addr));
472 amdgpu_ring_write(ring, lower_32_bits(seq));
474 /* optionally write high bits as well */
477 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
478 amdgpu_ring_write(ring, lower_32_bits(addr));
479 amdgpu_ring_write(ring, upper_32_bits(addr));
480 amdgpu_ring_write(ring, upper_32_bits(seq));
483 /* generate an interrupt */
484 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
485 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
489 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
491 * @adev: amdgpu_device pointer
493 * Stop the gfx async dma ring buffers (VI).
495 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
497 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
498 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
499 u32 rb_cntl, ib_cntl;
502 if ((adev->mman.buffer_funcs_ring == sdma0) ||
503 (adev->mman.buffer_funcs_ring == sdma1))
504 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
506 for (i = 0; i < adev->sdma.num_instances; i++) {
507 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
508 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
509 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
510 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
511 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
512 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
514 sdma0->ready = false;
515 sdma1->ready = false;
519 * sdma_v3_0_rlc_stop - stop the compute async dma engines
521 * @adev: amdgpu_device pointer
523 * Stop the compute async dma queues (VI).
525 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
531 * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
533 * @adev: amdgpu_device pointer
534 * @enable: enable/disable the DMA MEs context switch.
536 * Halt or unhalt the async dma engines context switch (VI).
538 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
543 for (i = 0; i < adev->sdma.num_instances; i++) {
544 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
546 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
547 AUTO_CTXSW_ENABLE, 1);
549 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
550 AUTO_CTXSW_ENABLE, 0);
551 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
556 * sdma_v3_0_enable - stop the async dma engines
558 * @adev: amdgpu_device pointer
559 * @enable: enable/disable the DMA MEs.
561 * Halt or unhalt the async dma engines (VI).
563 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
569 sdma_v3_0_gfx_stop(adev);
570 sdma_v3_0_rlc_stop(adev);
573 for (i = 0; i < adev->sdma.num_instances; i++) {
574 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
576 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
578 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
579 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
584 * sdma_v3_0_gfx_resume - setup and start the async dma engines
586 * @adev: amdgpu_device pointer
588 * Set up the gfx DMA ring buffers and enable them (VI).
589 * Returns 0 for success, error for failure.
591 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
593 struct amdgpu_ring *ring;
594 u32 rb_cntl, ib_cntl;
600 for (i = 0; i < adev->sdma.num_instances; i++) {
601 ring = &adev->sdma.instance[i].ring;
602 wb_offset = (ring->rptr_offs * 4);
604 mutex_lock(&adev->srbm_mutex);
605 for (j = 0; j < 16; j++) {
606 vi_srbm_select(adev, 0, 0, 0, j);
608 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
609 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
611 vi_srbm_select(adev, 0, 0, 0, 0);
612 mutex_unlock(&adev->srbm_mutex);
614 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
615 adev->gfx.config.gb_addr_config & 0x70);
617 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
619 /* Set ring buffer size in dwords */
620 rb_bufsz = order_base_2(ring->ring_size / 4);
621 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
622 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
624 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
625 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
626 RPTR_WRITEBACK_SWAP_ENABLE, 1);
628 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
630 /* Initialize the ring buffer's read and write pointers */
631 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
632 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
633 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
634 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
636 /* set the wb address whether it's enabled or not */
637 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
638 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
639 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
640 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
642 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
644 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
645 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
648 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
650 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
652 if (ring->use_doorbell) {
653 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
654 OFFSET, ring->doorbell_index);
655 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
657 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
659 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
662 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
663 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
665 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
666 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
668 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
671 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
677 sdma_v3_0_enable(adev, true);
678 /* enable sdma ring preemption */
679 sdma_v3_0_ctx_switch_enable(adev, true);
681 for (i = 0; i < adev->sdma.num_instances; i++) {
682 ring = &adev->sdma.instance[i].ring;
683 r = amdgpu_ring_test_ring(ring);
689 if (adev->mman.buffer_funcs_ring == ring)
690 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
697 * sdma_v3_0_rlc_resume - setup and start the async dma engines
699 * @adev: amdgpu_device pointer
701 * Set up the compute DMA queues and enable them (VI).
702 * Returns 0 for success, error for failure.
704 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
711 * sdma_v3_0_load_microcode - load the sDMA ME ucode
713 * @adev: amdgpu_device pointer
715 * Loads the sDMA0/1 ucode.
716 * Returns 0 for success, -EINVAL if the ucode is not available.
718 static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
720 const struct sdma_firmware_header_v1_0 *hdr;
721 const __le32 *fw_data;
726 sdma_v3_0_enable(adev, false);
728 for (i = 0; i < adev->sdma.num_instances; i++) {
729 if (!adev->sdma.instance[i].fw)
731 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
732 amdgpu_ucode_print_sdma_hdr(&hdr->header);
733 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
734 fw_data = (const __le32 *)
735 (adev->sdma.instance[i].fw->data +
736 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
737 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
738 for (j = 0; j < fw_size; j++)
739 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
740 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
747 * sdma_v3_0_start - setup and start the async dma engines
749 * @adev: amdgpu_device pointer
751 * Set up the DMA engines and enable them (VI).
752 * Returns 0 for success, error for failure.
754 static int sdma_v3_0_start(struct amdgpu_device *adev)
758 if (!adev->pp_enabled) {
759 if (!adev->firmware.smu_load) {
760 r = sdma_v3_0_load_microcode(adev);
764 for (i = 0; i < adev->sdma.num_instances; i++) {
765 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
767 AMDGPU_UCODE_ID_SDMA0 :
768 AMDGPU_UCODE_ID_SDMA1);
775 /* disble sdma engine before programing it */
776 sdma_v3_0_ctx_switch_enable(adev, false);
777 sdma_v3_0_enable(adev, false);
779 /* start the gfx rings and rlc compute queues */
780 r = sdma_v3_0_gfx_resume(adev);
783 r = sdma_v3_0_rlc_resume(adev);
791 * sdma_v3_0_ring_test_ring - simple async dma engine test
793 * @ring: amdgpu_ring structure holding ring information
795 * Test the DMA engine by writing using it to write an
796 * value to memory. (VI).
797 * Returns 0 for success, error for failure.
799 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
801 struct amdgpu_device *adev = ring->adev;
808 r = amdgpu_wb_get(adev, &index);
810 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
814 gpu_addr = adev->wb.gpu_addr + (index * 4);
816 adev->wb.wb[index] = cpu_to_le32(tmp);
818 r = amdgpu_ring_alloc(ring, 5);
820 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
821 amdgpu_wb_free(adev, index);
825 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
826 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
827 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
828 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
829 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
830 amdgpu_ring_write(ring, 0xDEADBEEF);
831 amdgpu_ring_commit(ring);
833 for (i = 0; i < adev->usec_timeout; i++) {
834 tmp = le32_to_cpu(adev->wb.wb[index]);
835 if (tmp == 0xDEADBEEF)
840 if (i < adev->usec_timeout) {
841 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
843 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
847 amdgpu_wb_free(adev, index);
853 * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
855 * @ring: amdgpu_ring structure holding ring information
857 * Test a simple IB in the DMA ring (VI).
858 * Returns 0 on success, error on failure.
860 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
862 struct amdgpu_device *adev = ring->adev;
864 struct fence *f = NULL;
870 r = amdgpu_wb_get(adev, &index);
872 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
876 gpu_addr = adev->wb.gpu_addr + (index * 4);
878 adev->wb.wb[index] = cpu_to_le32(tmp);
879 memset(&ib, 0, sizeof(ib));
880 r = amdgpu_ib_get(adev, NULL, 256, &ib);
882 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
886 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
887 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
888 ib.ptr[1] = lower_32_bits(gpu_addr);
889 ib.ptr[2] = upper_32_bits(gpu_addr);
890 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
891 ib.ptr[4] = 0xDEADBEEF;
892 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
893 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
894 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
897 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
901 r = fence_wait_timeout(f, false, timeout);
903 DRM_ERROR("amdgpu: IB test timed out\n");
907 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
910 tmp = le32_to_cpu(adev->wb.wb[index]);
911 if (tmp == 0xDEADBEEF) {
912 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
915 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
919 amdgpu_ib_free(adev, &ib, NULL);
922 amdgpu_wb_free(adev, index);
927 * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
929 * @ib: indirect buffer to fill with commands
930 * @pe: addr of the page entry
931 * @src: src addr to copy from
932 * @count: number of page entries to update
934 * Update PTEs by copying them from the GART using sDMA (CIK).
936 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
937 uint64_t pe, uint64_t src,
940 unsigned bytes = count * 8;
942 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
943 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
944 ib->ptr[ib->length_dw++] = bytes;
945 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
946 ib->ptr[ib->length_dw++] = lower_32_bits(src);
947 ib->ptr[ib->length_dw++] = upper_32_bits(src);
948 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
949 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
953 * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
955 * @ib: indirect buffer to fill with commands
956 * @pe: addr of the page entry
957 * @value: dst addr to write into pe
958 * @count: number of page entries to update
959 * @incr: increase next addr by incr bytes
961 * Update PTEs by writing them manually using sDMA (CIK).
963 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
964 uint64_t value, unsigned count,
967 unsigned ndw = count * 2;
969 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
970 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
971 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
972 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
973 ib->ptr[ib->length_dw++] = ndw;
974 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
975 ib->ptr[ib->length_dw++] = lower_32_bits(value);
976 ib->ptr[ib->length_dw++] = upper_32_bits(value);
982 * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
984 * @ib: indirect buffer to fill with commands
985 * @pe: addr of the page entry
986 * @addr: dst addr to write into pe
987 * @count: number of page entries to update
988 * @incr: increase next addr by incr bytes
989 * @flags: access flags
991 * Update the page tables using sDMA (CIK).
993 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
994 uint64_t addr, unsigned count,
995 uint32_t incr, uint32_t flags)
997 /* for physically contiguous pages (vram) */
998 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
999 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1000 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1001 ib->ptr[ib->length_dw++] = flags; /* mask */
1002 ib->ptr[ib->length_dw++] = 0;
1003 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1004 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1005 ib->ptr[ib->length_dw++] = incr; /* increment size */
1006 ib->ptr[ib->length_dw++] = 0;
1007 ib->ptr[ib->length_dw++] = count; /* number of entries */
1011 * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1013 * @ib: indirect buffer to fill with padding
1016 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1018 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1022 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1023 for (i = 0; i < pad_count; i++)
1024 if (sdma && sdma->burst_nop && (i == 0))
1025 ib->ptr[ib->length_dw++] =
1026 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1027 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1029 ib->ptr[ib->length_dw++] =
1030 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1034 * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1036 * @ring: amdgpu_ring pointer
1038 * Make sure all previous operations are completed (CIK).
1040 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1042 uint32_t seq = ring->fence_drv.sync_seq;
1043 uint64_t addr = ring->fence_drv.gpu_addr;
1046 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1047 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1048 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1049 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1050 amdgpu_ring_write(ring, addr & 0xfffffffc);
1051 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1052 amdgpu_ring_write(ring, seq); /* reference */
1053 amdgpu_ring_write(ring, 0xfffffff); /* mask */
1054 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1055 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1059 * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1061 * @ring: amdgpu_ring pointer
1062 * @vm: amdgpu_vm pointer
1064 * Update the page table base and flush the VM TLB
1067 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1068 unsigned vm_id, uint64_t pd_addr)
1070 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1071 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1073 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
1075 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
1077 amdgpu_ring_write(ring, pd_addr >> 12);
1080 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1081 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1082 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
1083 amdgpu_ring_write(ring, 1 << vm_id);
1085 /* wait for flush */
1086 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1087 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1088 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1089 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1090 amdgpu_ring_write(ring, 0);
1091 amdgpu_ring_write(ring, 0); /* reference */
1092 amdgpu_ring_write(ring, 0); /* mask */
1093 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1094 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1097 static unsigned sdma_v3_0_ring_get_emit_ib_size(struct amdgpu_ring *ring)
1100 7 + 6; /* sdma_v3_0_ring_emit_ib */
1103 static unsigned sdma_v3_0_ring_get_dma_frame_size(struct amdgpu_ring *ring)
1106 6 + /* sdma_v3_0_ring_emit_hdp_flush */
1107 3 + /* sdma_v3_0_ring_emit_hdp_invalidate */
1108 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1109 12 + /* sdma_v3_0_ring_emit_vm_flush */
1110 10 + 10 + 10; /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1113 static int sdma_v3_0_early_init(void *handle)
1115 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1117 switch (adev->asic_type) {
1119 adev->sdma.num_instances = 1;
1122 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1126 sdma_v3_0_set_ring_funcs(adev);
1127 sdma_v3_0_set_buffer_funcs(adev);
1128 sdma_v3_0_set_vm_pte_funcs(adev);
1129 sdma_v3_0_set_irq_funcs(adev);
1134 static int sdma_v3_0_sw_init(void *handle)
1136 struct amdgpu_ring *ring;
1138 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1140 /* SDMA trap event */
1141 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
1145 /* SDMA Privileged inst */
1146 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
1150 /* SDMA Privileged inst */
1151 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
1155 r = sdma_v3_0_init_microcode(adev);
1157 DRM_ERROR("Failed to load sdma firmware!\n");
1161 for (i = 0; i < adev->sdma.num_instances; i++) {
1162 ring = &adev->sdma.instance[i].ring;
1163 ring->ring_obj = NULL;
1164 ring->use_doorbell = true;
1165 ring->doorbell_index = (i == 0) ?
1166 AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
1168 sprintf(ring->name, "sdma%d", i);
1169 r = amdgpu_ring_init(adev, ring, 1024,
1170 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
1171 &adev->sdma.trap_irq,
1173 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
1174 AMDGPU_RING_TYPE_SDMA);
1182 static int sdma_v3_0_sw_fini(void *handle)
1184 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1187 for (i = 0; i < adev->sdma.num_instances; i++)
1188 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1190 sdma_v3_0_free_microcode(adev);
1194 static int sdma_v3_0_hw_init(void *handle)
1197 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1199 sdma_v3_0_init_golden_registers(adev);
1201 r = sdma_v3_0_start(adev);
1208 static int sdma_v3_0_hw_fini(void *handle)
1210 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1212 sdma_v3_0_ctx_switch_enable(adev, false);
1213 sdma_v3_0_enable(adev, false);
1218 static int sdma_v3_0_suspend(void *handle)
1220 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1222 return sdma_v3_0_hw_fini(adev);
1225 static int sdma_v3_0_resume(void *handle)
1227 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1229 return sdma_v3_0_hw_init(adev);
1232 static bool sdma_v3_0_is_idle(void *handle)
1234 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1235 u32 tmp = RREG32(mmSRBM_STATUS2);
1237 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1238 SRBM_STATUS2__SDMA1_BUSY_MASK))
1244 static int sdma_v3_0_wait_for_idle(void *handle)
1248 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1250 for (i = 0; i < adev->usec_timeout; i++) {
1251 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1252 SRBM_STATUS2__SDMA1_BUSY_MASK);
1261 static bool sdma_v3_0_check_soft_reset(void *handle)
1263 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1264 u32 srbm_soft_reset = 0;
1265 u32 tmp = RREG32(mmSRBM_STATUS2);
1267 if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1268 (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1269 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1270 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1273 if (srbm_soft_reset) {
1274 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1277 adev->sdma.srbm_soft_reset = 0;
1282 static int sdma_v3_0_pre_soft_reset(void *handle)
1284 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1285 u32 srbm_soft_reset = 0;
1287 if (!adev->sdma.srbm_soft_reset)
1290 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1292 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1293 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1294 sdma_v3_0_ctx_switch_enable(adev, false);
1295 sdma_v3_0_enable(adev, false);
1301 static int sdma_v3_0_post_soft_reset(void *handle)
1303 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1304 u32 srbm_soft_reset = 0;
1306 if (!adev->sdma.srbm_soft_reset)
1309 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1311 if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1312 REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1313 sdma_v3_0_gfx_resume(adev);
1314 sdma_v3_0_rlc_resume(adev);
1320 static int sdma_v3_0_soft_reset(void *handle)
1322 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1323 u32 srbm_soft_reset = 0;
1326 if (!adev->sdma.srbm_soft_reset)
1329 srbm_soft_reset = adev->sdma.srbm_soft_reset;
1331 if (srbm_soft_reset) {
1332 tmp = RREG32(mmSRBM_SOFT_RESET);
1333 tmp |= srbm_soft_reset;
1334 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1335 WREG32(mmSRBM_SOFT_RESET, tmp);
1336 tmp = RREG32(mmSRBM_SOFT_RESET);
1340 tmp &= ~srbm_soft_reset;
1341 WREG32(mmSRBM_SOFT_RESET, tmp);
1342 tmp = RREG32(mmSRBM_SOFT_RESET);
1344 /* Wait a little for things to settle down */
1351 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1352 struct amdgpu_irq_src *source,
1354 enum amdgpu_interrupt_state state)
1359 case AMDGPU_SDMA_IRQ_TRAP0:
1361 case AMDGPU_IRQ_STATE_DISABLE:
1362 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1363 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1364 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1366 case AMDGPU_IRQ_STATE_ENABLE:
1367 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1368 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1369 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1375 case AMDGPU_SDMA_IRQ_TRAP1:
1377 case AMDGPU_IRQ_STATE_DISABLE:
1378 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1379 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1380 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1382 case AMDGPU_IRQ_STATE_ENABLE:
1383 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1384 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1385 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1397 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1398 struct amdgpu_irq_src *source,
1399 struct amdgpu_iv_entry *entry)
1401 u8 instance_id, queue_id;
1403 instance_id = (entry->ring_id & 0x3) >> 0;
1404 queue_id = (entry->ring_id & 0xc) >> 2;
1405 DRM_DEBUG("IH: SDMA trap\n");
1406 switch (instance_id) {
1410 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1423 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1437 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1438 struct amdgpu_irq_src *source,
1439 struct amdgpu_iv_entry *entry)
1441 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1442 schedule_work(&adev->reset_work);
1446 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1447 struct amdgpu_device *adev,
1450 uint32_t temp, data;
1453 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1454 for (i = 0; i < adev->sdma.num_instances; i++) {
1455 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1456 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1457 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1458 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1459 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1460 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1461 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1462 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1463 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1465 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1468 for (i = 0; i < adev->sdma.num_instances; i++) {
1469 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1470 data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1471 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1472 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1473 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1474 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1475 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1476 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1477 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1480 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1485 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1486 struct amdgpu_device *adev,
1489 uint32_t temp, data;
1492 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1493 for (i = 0; i < adev->sdma.num_instances; i++) {
1494 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1495 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1498 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1501 for (i = 0; i < adev->sdma.num_instances; i++) {
1502 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1503 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1506 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1511 static int sdma_v3_0_set_clockgating_state(void *handle,
1512 enum amd_clockgating_state state)
1514 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1516 switch (adev->asic_type) {
1520 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1521 state == AMD_CG_STATE_GATE ? true : false);
1522 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1523 state == AMD_CG_STATE_GATE ? true : false);
1531 static int sdma_v3_0_set_powergating_state(void *handle,
1532 enum amd_powergating_state state)
1537 const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1538 .name = "sdma_v3_0",
1539 .early_init = sdma_v3_0_early_init,
1541 .sw_init = sdma_v3_0_sw_init,
1542 .sw_fini = sdma_v3_0_sw_fini,
1543 .hw_init = sdma_v3_0_hw_init,
1544 .hw_fini = sdma_v3_0_hw_fini,
1545 .suspend = sdma_v3_0_suspend,
1546 .resume = sdma_v3_0_resume,
1547 .is_idle = sdma_v3_0_is_idle,
1548 .wait_for_idle = sdma_v3_0_wait_for_idle,
1549 .check_soft_reset = sdma_v3_0_check_soft_reset,
1550 .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1551 .post_soft_reset = sdma_v3_0_post_soft_reset,
1552 .soft_reset = sdma_v3_0_soft_reset,
1553 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1554 .set_powergating_state = sdma_v3_0_set_powergating_state,
1557 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1558 .get_rptr = sdma_v3_0_ring_get_rptr,
1559 .get_wptr = sdma_v3_0_ring_get_wptr,
1560 .set_wptr = sdma_v3_0_ring_set_wptr,
1562 .emit_ib = sdma_v3_0_ring_emit_ib,
1563 .emit_fence = sdma_v3_0_ring_emit_fence,
1564 .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1565 .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1566 .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1567 .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate,
1568 .test_ring = sdma_v3_0_ring_test_ring,
1569 .test_ib = sdma_v3_0_ring_test_ib,
1570 .insert_nop = sdma_v3_0_ring_insert_nop,
1571 .pad_ib = sdma_v3_0_ring_pad_ib,
1572 .get_emit_ib_size = sdma_v3_0_ring_get_emit_ib_size,
1573 .get_dma_frame_size = sdma_v3_0_ring_get_dma_frame_size,
1576 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1580 for (i = 0; i < adev->sdma.num_instances; i++)
1581 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1584 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1585 .set = sdma_v3_0_set_trap_irq_state,
1586 .process = sdma_v3_0_process_trap_irq,
1589 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1590 .process = sdma_v3_0_process_illegal_inst_irq,
1593 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1595 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1596 adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1597 adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1601 * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1603 * @ring: amdgpu_ring structure holding ring information
1604 * @src_offset: src GPU address
1605 * @dst_offset: dst GPU address
1606 * @byte_count: number of bytes to xfer
1608 * Copy GPU buffers using the DMA engine (VI).
1609 * Used by the amdgpu ttm implementation to move pages if
1610 * registered as the asic copy callback.
1612 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1613 uint64_t src_offset,
1614 uint64_t dst_offset,
1615 uint32_t byte_count)
1617 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1618 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1619 ib->ptr[ib->length_dw++] = byte_count;
1620 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1621 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1622 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1623 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1624 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1628 * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1630 * @ring: amdgpu_ring structure holding ring information
1631 * @src_data: value to write to buffer
1632 * @dst_offset: dst GPU address
1633 * @byte_count: number of bytes to xfer
1635 * Fill GPU buffers using the DMA engine (VI).
1637 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1639 uint64_t dst_offset,
1640 uint32_t byte_count)
1642 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1643 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1644 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1645 ib->ptr[ib->length_dw++] = src_data;
1646 ib->ptr[ib->length_dw++] = byte_count;
1649 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1650 .copy_max_bytes = 0x1fffff,
1652 .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1654 .fill_max_bytes = 0x1fffff,
1656 .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1659 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1661 if (adev->mman.buffer_funcs == NULL) {
1662 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1663 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1667 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1668 .copy_pte = sdma_v3_0_vm_copy_pte,
1669 .write_pte = sdma_v3_0_vm_write_pte,
1670 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1673 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1677 if (adev->vm_manager.vm_pte_funcs == NULL) {
1678 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1679 for (i = 0; i < adev->sdma.num_instances; i++)
1680 adev->vm_manager.vm_pte_rings[i] =
1681 &adev->sdma.instance[i].ring;
1683 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;